AsmWriterEmitter.cpp revision 314564
11590Srgrimes//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 21590Srgrimes// 31590Srgrimes// The LLVM Compiler Infrastructure 41590Srgrimes// 51590Srgrimes// This file is distributed under the University of Illinois Open Source 61590Srgrimes// License. See LICENSE.TXT for details. 71590Srgrimes// 81590Srgrimes//===----------------------------------------------------------------------===// 91590Srgrimes// 101590Srgrimes// This tablegen backend emits an assembly printer for the current target. 111590Srgrimes// Note that this is currently fairly skeletal, but will grow over time. 121590Srgrimes// 131590Srgrimes//===----------------------------------------------------------------------===// 141590Srgrimes 151590Srgrimes#include "AsmWriterInst.h" 161590Srgrimes#include "CodeGenInstruction.h" 171590Srgrimes#include "CodeGenRegisters.h" 181590Srgrimes#include "CodeGenTarget.h" 191590Srgrimes#include "SequenceToOffsetTable.h" 201590Srgrimes#include "Types.h" 211590Srgrimes#include "llvm/ADT/ArrayRef.h" 221590Srgrimes#include "llvm/ADT/DenseMap.h" 231590Srgrimes#include "llvm/ADT/SmallString.h" 241590Srgrimes#include "llvm/ADT/SmallVector.h" 251590Srgrimes#include "llvm/ADT/STLExtras.h" 261590Srgrimes#include "llvm/ADT/StringExtras.h" 271590Srgrimes#include "llvm/ADT/StringRef.h" 281590Srgrimes#include "llvm/ADT/Twine.h" 2950477Speter#include "llvm/Support/Casting.h" 301590Srgrimes#include "llvm/Support/Debug.h" 31240506Seadler#include "llvm/Support/ErrorHandling.h" 321590Srgrimes#include "llvm/Support/Format.h" 3379535Sru#include "llvm/Support/MathExtras.h" 341590Srgrimes#include "llvm/Support/raw_ostream.h" 351590Srgrimes#include "llvm/TableGen/Error.h" 3634781Ssteve#include "llvm/TableGen/Record.h" 371590Srgrimes#include "llvm/TableGen/TableGenBackend.h" 3868963Sru#include <algorithm> 3929311Sache#include <cassert> 401590Srgrimes#include <cstddef> 411590Srgrimes#include <cstdint> 4249177Sgreen#include <deque> 431590Srgrimes#include <iterator> 441590Srgrimes#include <map> 4528694Scharnier#include <set> 461590Srgrimes#include <string> 471590Srgrimes#include <tuple> 481590Srgrimes#include <utility> 491590Srgrimes#include <vector> 501590Srgrimes 511590Srgrimesusing namespace llvm; 521590Srgrimes 531590Srgrimes#define DEBUG_TYPE "asm-writer-emitter" 541590Srgrimes 551590Srgrimesnamespace { 561590Srgrimes 571590Srgrimesclass AsmWriterEmitter { 581590Srgrimes RecordKeeper &Records; 591590Srgrimes CodeGenTarget Target; 60165226Sru ArrayRef<const CodeGenInstruction *> NumberedInstructions; 6129311Sache std::vector<AsmWriterInst> Instructions; 6229311Sache 6329311Sachepublic: 641590Srgrimes AsmWriterEmitter(RecordKeeper &R); 651590Srgrimes 661590Srgrimes void run(raw_ostream &o); 671590Srgrimes 681590Srgrimesprivate: 691590Srgrimes void EmitPrintInstruction(raw_ostream &o); 701590Srgrimes void EmitGetRegisterName(raw_ostream &o); 71165226Sru void EmitPrintAliasInstruction(raw_ostream &O); 721590Srgrimes 731590Srgrimes void FindUniqueOperandCommands(std::vector<std::string> &UOC, 741590Srgrimes std::vector<std::vector<unsigned>> &InstIdxs, 75165226Sru std::vector<unsigned> &InstOpsUsed, 761590Srgrimes bool PassSubtarget) const; 77141846Sru}; 7828694Scharnier 7980407Sbrian} // end anonymous namespace 801590Srgrimes 811590Srgrimesstatic void PrintCases(std::vector<std::pair<std::string, 8249177Sgreen AsmWriterOperand>> &OpsToPrint, raw_ostream &O, 831590Srgrimes bool PassSubtarget) { 8449177Sgreen O << " case " << OpsToPrint.back().first << ":"; 851590Srgrimes AsmWriterOperand TheOp = OpsToPrint.back().second; 86202756Sed OpsToPrint.pop_back(); 87202756Sed 881590Srgrimes // Check to see if any other operands are identical in this list, and if so, 891590Srgrimes // emit a case label for them. 90140420Sru for (unsigned i = OpsToPrint.size(); i != 0; --i) 91140420Sru if (OpsToPrint[i-1].second == TheOp) { 92140420Sru O << "\n case " << OpsToPrint[i-1].first << ":"; 93140420Sru OpsToPrint.erase(OpsToPrint.begin()+i-1); 94140420Sru } 95140420Sru 96140420Sru // Finally, emit the code. 97140420Sru O << "\n " << TheOp.getCode(PassSubtarget); 981590Srgrimes O << "\n break;\n"; 991590Srgrimes} 1001590Srgrimes 10121748Swosch/// EmitInstructions - Emit the last instruction in the vector and any other 10221748Swosch/// instructions that are suitably similar to it. 103140420Srustatic void EmitInstructions(std::vector<AsmWriterInst> &Insts, 104140420Sru raw_ostream &O, bool PassSubtarget) { 105140420Sru AsmWriterInst FirstInst = Insts.back(); 106140420Sru Insts.pop_back(); 107140420Sru 1081590Srgrimes std::vector<AsmWriterInst> SimilarInsts; 1091590Srgrimes unsigned DifferingOperand = ~0; 1101590Srgrimes for (unsigned i = Insts.size(); i != 0; --i) { 1111590Srgrimes unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 112165226Sru if (DiffOp != ~1U) { 113165226Sru if (DifferingOperand == ~0U) // First match! 114165226Sru DifferingOperand = DiffOp; 1151590Srgrimes 116165226Sru // If this differs in the same operand as the rest of the instructions in 117165226Sru // this class, move it to the SimilarInsts list. 1181590Srgrimes if (DifferingOperand == DiffOp || DiffOp == ~0U) { 1191590Srgrimes SimilarInsts.push_back(Insts[i-1]); 1201590Srgrimes Insts.erase(Insts.begin()+i-1); 1211590Srgrimes } 12228694Scharnier } 1231590Srgrimes } 124165226Sru 1251590Srgrimes O << " case " << FirstInst.CGI->Namespace << "::" 1261590Srgrimes << FirstInst.CGI->TheDef->getName() << ":\n"; 1271590Srgrimes for (const AsmWriterInst &AWI : SimilarInsts) 1281590Srgrimes O << " case " << AWI.CGI->Namespace << "::" 1291590Srgrimes << AWI.CGI->TheDef->getName() << ":\n"; 1301590Srgrimes for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 1311590Srgrimes if (i != DifferingOperand) { 1321590Srgrimes // If the operand is the same for all instructions, just print it. 1331590Srgrimes O << " " << FirstInst.Operands[i].getCode(PassSubtarget); 1341590Srgrimes } else { 1351590Srgrimes // If this is the operand that varies between all of the instructions, 1361590Srgrimes // emit a switch for just this operand now. 1371590Srgrimes O << " switch (MI->getOpcode()) {\n"; 1381590Srgrimes O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; 1391590Srgrimes std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint; 14079755Sdd OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + 14128694Scharnier FirstInst.CGI->TheDef->getName().str(), 1421590Srgrimes FirstInst.Operands[i])); 1431590Srgrimes 1441590Srgrimes for (const AsmWriterInst &AWI : SimilarInsts) { 145 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::" + 146 AWI.CGI->TheDef->getName().str(), 147 AWI.Operands[i])); 148 } 149 std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 150 while (!OpsToPrint.empty()) 151 PrintCases(OpsToPrint, O, PassSubtarget); 152 O << " }"; 153 } 154 O << "\n"; 155 } 156 O << " break;\n"; 157} 158 159void AsmWriterEmitter:: 160FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 161 std::vector<std::vector<unsigned>> &InstIdxs, 162 std::vector<unsigned> &InstOpsUsed, 163 bool PassSubtarget) const { 164 // This vector parallels UniqueOperandCommands, keeping track of which 165 // instructions each case are used for. It is a comma separated string of 166 // enums. 167 std::vector<std::string> InstrsForCase; 168 InstrsForCase.resize(UniqueOperandCommands.size()); 169 InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 170 171 for (size_t i = 0, e = Instructions.size(); i != e; ++i) { 172 const AsmWriterInst &Inst = Instructions[i]; 173 if (Inst.Operands.empty()) 174 continue; // Instruction already done. 175 176 std::string Command = " "+Inst.Operands[0].getCode(PassSubtarget)+"\n"; 177 178 // Check to see if we already have 'Command' in UniqueOperandCommands. 179 // If not, add it. 180 auto I = llvm::find(UniqueOperandCommands, Command); 181 if (I != UniqueOperandCommands.end()) { 182 size_t idx = I - UniqueOperandCommands.begin(); 183 InstrsForCase[idx] += ", "; 184 InstrsForCase[idx] += Inst.CGI->TheDef->getName(); 185 InstIdxs[idx].push_back(i); 186 } else { 187 UniqueOperandCommands.push_back(std::move(Command)); 188 InstrsForCase.push_back(Inst.CGI->TheDef->getName()); 189 InstIdxs.emplace_back(); 190 InstIdxs.back().push_back(i); 191 192 // This command matches one operand so far. 193 InstOpsUsed.push_back(1); 194 } 195 } 196 197 // For each entry of UniqueOperandCommands, there is a set of instructions 198 // that uses it. If the next command of all instructions in the set are 199 // identical, fold it into the command. 200 for (size_t CommandIdx = 0, e = UniqueOperandCommands.size(); 201 CommandIdx != e; ++CommandIdx) { 202 203 const auto &Idxs = InstIdxs[CommandIdx]; 204 205 for (unsigned Op = 1; ; ++Op) { 206 // Find the first instruction in the set. 207 const AsmWriterInst &FirstInst = Instructions[Idxs.front()]; 208 // If this instruction has no more operands, we isn't anything to merge 209 // into this command. 210 if (FirstInst.Operands.size() == Op) 211 break; 212 213 // Otherwise, scan to see if all of the other instructions in this command 214 // set share the operand. 215 if (std::any_of(Idxs.begin()+1, Idxs.end(), 216 [&](unsigned Idx) { 217 const AsmWriterInst &OtherInst = Instructions[Idx]; 218 return OtherInst.Operands.size() == Op || 219 OtherInst.Operands[Op] != FirstInst.Operands[Op]; 220 })) 221 break; 222 223 // Okay, everything in this command set has the same next operand. Add it 224 // to UniqueOperandCommands and remember that it was consumed. 225 std::string Command = " " + 226 FirstInst.Operands[Op].getCode(PassSubtarget) + "\n"; 227 228 UniqueOperandCommands[CommandIdx] += Command; 229 InstOpsUsed[CommandIdx]++; 230 } 231 } 232 233 // Prepend some of the instructions each case is used for onto the case val. 234 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 235 std::string Instrs = InstrsForCase[i]; 236 if (Instrs.size() > 70) { 237 Instrs.erase(Instrs.begin()+70, Instrs.end()); 238 Instrs += "..."; 239 } 240 241 if (!Instrs.empty()) 242 UniqueOperandCommands[i] = " // " + Instrs + "\n" + 243 UniqueOperandCommands[i]; 244 } 245} 246 247static void UnescapeString(std::string &Str) { 248 for (unsigned i = 0; i != Str.size(); ++i) { 249 if (Str[i] == '\\' && i != Str.size()-1) { 250 switch (Str[i+1]) { 251 default: continue; // Don't execute the code after the switch. 252 case 'a': Str[i] = '\a'; break; 253 case 'b': Str[i] = '\b'; break; 254 case 'e': Str[i] = 27; break; 255 case 'f': Str[i] = '\f'; break; 256 case 'n': Str[i] = '\n'; break; 257 case 'r': Str[i] = '\r'; break; 258 case 't': Str[i] = '\t'; break; 259 case 'v': Str[i] = '\v'; break; 260 case '"': Str[i] = '\"'; break; 261 case '\'': Str[i] = '\''; break; 262 case '\\': Str[i] = '\\'; break; 263 } 264 // Nuke the second character. 265 Str.erase(Str.begin()+i+1); 266 } 267 } 268} 269 270/// EmitPrintInstruction - Generate the code for the "printInstruction" method 271/// implementation. Destroys all instances of AsmWriterInst information, by 272/// clearing the Instructions vector. 273void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 274 Record *AsmWriter = Target.getAsmWriter(); 275 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 276 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 277 278 O << 279 "/// printInstruction - This method is automatically generated by tablegen\n" 280 "/// from the instruction set description.\n" 281 "void " << Target.getName() << ClassName 282 << "::printInstruction(const MCInst *MI, " 283 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 284 << "raw_ostream &O) {\n"; 285 286 // Build an aggregate string, and build a table of offsets into it. 287 SequenceToOffsetTable<std::string> StringTable; 288 289 /// OpcodeInfo - This encodes the index of the string to use for the first 290 /// chunk of the output as well as indices used for operand printing. 291 std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size()); 292 const unsigned OpcodeInfoBits = 64; 293 294 // Add all strings to the string table upfront so it can generate an optimized 295 // representation. 296 for (AsmWriterInst &AWI : Instructions) { 297 if (AWI.Operands[0].OperandType == 298 AsmWriterOperand::isLiteralTextOperand && 299 !AWI.Operands[0].Str.empty()) { 300 std::string Str = AWI.Operands[0].Str; 301 UnescapeString(Str); 302 StringTable.add(Str); 303 } 304 } 305 306 StringTable.layout(); 307 308 unsigned MaxStringIdx = 0; 309 for (AsmWriterInst &AWI : Instructions) { 310 unsigned Idx; 311 if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand || 312 AWI.Operands[0].Str.empty()) { 313 // Something handled by the asmwriter printer, but with no leading string. 314 Idx = StringTable.get(""); 315 } else { 316 std::string Str = AWI.Operands[0].Str; 317 UnescapeString(Str); 318 Idx = StringTable.get(Str); 319 MaxStringIdx = std::max(MaxStringIdx, Idx); 320 321 // Nuke the string from the operand list. It is now handled! 322 AWI.Operands.erase(AWI.Operands.begin()); 323 } 324 325 // Bias offset by one since we want 0 as a sentinel. 326 OpcodeInfo[AWI.CGIIndex] = Idx+1; 327 } 328 329 // Figure out how many bits we used for the string index. 330 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); 331 332 // To reduce code size, we compactify common instructions into a few bits 333 // in the opcode-indexed table. 334 unsigned BitsLeft = OpcodeInfoBits-AsmStrBits; 335 336 std::vector<std::vector<std::string>> TableDrivenOperandPrinters; 337 338 while (true) { 339 std::vector<std::string> UniqueOperandCommands; 340 std::vector<std::vector<unsigned>> InstIdxs; 341 std::vector<unsigned> NumInstOpsHandled; 342 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 343 NumInstOpsHandled, PassSubtarget); 344 345 // If we ran out of operands to print, we're done. 346 if (UniqueOperandCommands.empty()) break; 347 348 // Compute the number of bits we need to represent these cases, this is 349 // ceil(log2(numentries)). 350 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 351 352 // If we don't have enough bits for this operand, don't include it. 353 if (NumBits > BitsLeft) { 354 DEBUG(errs() << "Not enough bits to densely encode " << NumBits 355 << " more bits\n"); 356 break; 357 } 358 359 // Otherwise, we can include this in the initial lookup table. Add it in. 360 for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) { 361 unsigned NumOps = NumInstOpsHandled[i]; 362 for (unsigned Idx : InstIdxs[i]) { 363 OpcodeInfo[Instructions[Idx].CGIIndex] |= 364 (uint64_t)i << (OpcodeInfoBits-BitsLeft); 365 // Remove the info about this operand from the instruction. 366 AsmWriterInst &Inst = Instructions[Idx]; 367 if (!Inst.Operands.empty()) { 368 assert(NumOps <= Inst.Operands.size() && 369 "Can't remove this many ops!"); 370 Inst.Operands.erase(Inst.Operands.begin(), 371 Inst.Operands.begin()+NumOps); 372 } 373 } 374 } 375 BitsLeft -= NumBits; 376 377 // Remember the handlers for this set of operands. 378 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); 379 } 380 381 // Emit the string table itself. 382 O << " static const char AsmStrs[] = {\n"; 383 StringTable.emit(O, printChar); 384 O << " };\n\n"; 385 386 // Emit the lookup tables in pieces to minimize wasted bytes. 387 unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8; 388 unsigned Table = 0, Shift = 0; 389 SmallString<128> BitsString; 390 raw_svector_ostream BitsOS(BitsString); 391 // If the total bits is more than 32-bits we need to use a 64-bit type. 392 BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32) 393 << "_t Bits = 0;\n"; 394 while (BytesNeeded != 0) { 395 // Figure out how big this table section needs to be, but no bigger than 4. 396 unsigned TableSize = std::min(1 << Log2_32(BytesNeeded), 4); 397 BytesNeeded -= TableSize; 398 TableSize *= 8; // Convert to bits; 399 uint64_t Mask = (1ULL << TableSize) - 1; 400 O << " static const uint" << TableSize << "_t OpInfo" << Table 401 << "[] = {\n"; 402 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 403 O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// " 404 << NumberedInstructions[i]->TheDef->getName() << "\n"; 405 } 406 O << " };\n\n"; 407 // Emit string to combine the individual table lookups. 408 BitsOS << " Bits |= "; 409 // If the total bits is more than 32-bits we need to use a 64-bit type. 410 if (BitsLeft < (OpcodeInfoBits - 32)) 411 BitsOS << "(uint64_t)"; 412 BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; 413 // Prepare the shift for the next iteration and increment the table count. 414 Shift += TableSize; 415 ++Table; 416 } 417 418 // Emit the initial tab character. 419 O << " O << \"\\t\";\n\n"; 420 421 O << " // Emit the opcode for the instruction.\n"; 422 O << BitsString; 423 424 // Emit the starting string. 425 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 426 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 427 428 // Output the table driven operand information. 429 BitsLeft = OpcodeInfoBits-AsmStrBits; 430 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 431 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 432 433 // Compute the number of bits we need to represent these cases, this is 434 // ceil(log2(numentries)). 435 unsigned NumBits = Log2_32_Ceil(Commands.size()); 436 assert(NumBits <= BitsLeft && "consistency error"); 437 438 // Emit code to extract this field from Bits. 439 O << "\n // Fragment " << i << " encoded into " << NumBits 440 << " bits for " << Commands.size() << " unique commands.\n"; 441 442 if (Commands.size() == 2) { 443 // Emit two possibilitys with if/else. 444 O << " if ((Bits >> " 445 << (OpcodeInfoBits-BitsLeft) << ") & " 446 << ((1 << NumBits)-1) << ") {\n" 447 << Commands[1] 448 << " } else {\n" 449 << Commands[0] 450 << " }\n\n"; 451 } else if (Commands.size() == 1) { 452 // Emit a single possibility. 453 O << Commands[0] << "\n\n"; 454 } else { 455 O << " switch ((Bits >> " 456 << (OpcodeInfoBits-BitsLeft) << ") & " 457 << ((1 << NumBits)-1) << ") {\n" 458 << " default: llvm_unreachable(\"Invalid command number.\");\n"; 459 460 // Print out all the cases. 461 for (unsigned j = 0, e = Commands.size(); j != e; ++j) { 462 O << " case " << j << ":\n"; 463 O << Commands[j]; 464 O << " break;\n"; 465 } 466 O << " }\n\n"; 467 } 468 BitsLeft -= NumBits; 469 } 470 471 // Okay, delete instructions with no operand info left. 472 auto I = llvm::remove_if(Instructions, 473 [](AsmWriterInst &Inst) { return Inst.Operands.empty(); }); 474 Instructions.erase(I, Instructions.end()); 475 476 477 // Because this is a vector, we want to emit from the end. Reverse all of the 478 // elements in the vector. 479 std::reverse(Instructions.begin(), Instructions.end()); 480 481 482 // Now that we've emitted all of the operand info that fit into 64 bits, emit 483 // information for those instructions that are left. This is a less dense 484 // encoding, but we expect the main 64-bit table to handle the majority of 485 // instructions. 486 if (!Instructions.empty()) { 487 // Find the opcode # of inline asm. 488 O << " switch (MI->getOpcode()) {\n"; 489 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; 490 while (!Instructions.empty()) 491 EmitInstructions(Instructions, O, PassSubtarget); 492 493 O << " }\n"; 494 } 495 496 O << "}\n"; 497} 498 499static void 500emitRegisterNameString(raw_ostream &O, StringRef AltName, 501 const std::deque<CodeGenRegister> &Registers) { 502 SequenceToOffsetTable<std::string> StringTable; 503 SmallVector<std::string, 4> AsmNames(Registers.size()); 504 unsigned i = 0; 505 for (const auto &Reg : Registers) { 506 std::string &AsmName = AsmNames[i++]; 507 508 // "NoRegAltName" is special. We don't need to do a lookup for that, 509 // as it's just a reference to the default register name. 510 if (AltName == "" || AltName == "NoRegAltName") { 511 AsmName = Reg.TheDef->getValueAsString("AsmName"); 512 if (AsmName.empty()) 513 AsmName = Reg.getName(); 514 } else { 515 // Make sure the register has an alternate name for this index. 516 std::vector<Record*> AltNameList = 517 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 518 unsigned Idx = 0, e; 519 for (e = AltNameList.size(); 520 Idx < e && (AltNameList[Idx]->getName() != AltName); 521 ++Idx) 522 ; 523 // If the register has an alternate name for this index, use it. 524 // Otherwise, leave it empty as an error flag. 525 if (Idx < e) { 526 std::vector<std::string> AltNames = 527 Reg.TheDef->getValueAsListOfStrings("AltNames"); 528 if (AltNames.size() <= Idx) 529 PrintFatalError(Reg.TheDef->getLoc(), 530 "Register definition missing alt name for '" + 531 AltName + "'."); 532 AsmName = AltNames[Idx]; 533 } 534 } 535 StringTable.add(AsmName); 536 } 537 538 StringTable.layout(); 539 O << " static const char AsmStrs" << AltName << "[] = {\n"; 540 StringTable.emit(O, printChar); 541 O << " };\n\n"; 542 543 O << " static const " << getMinimalTypeForRange(StringTable.size() - 1, 32) 544 << " RegAsmOffset" << AltName << "[] = {"; 545 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 546 if ((i % 14) == 0) 547 O << "\n "; 548 O << StringTable.get(AsmNames[i]) << ", "; 549 } 550 O << "\n };\n" 551 << "\n"; 552} 553 554void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 555 Record *AsmWriter = Target.getAsmWriter(); 556 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 557 const auto &Registers = Target.getRegBank().getRegisters(); 558 const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices(); 559 bool hasAltNames = AltNameIndices.size() > 1; 560 std::string Namespace = 561 Registers.front().TheDef->getValueAsString("Namespace"); 562 563 O << 564 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 565 "/// from the register set description. This returns the assembler name\n" 566 "/// for the specified register.\n" 567 "const char *" << Target.getName() << ClassName << "::"; 568 if (hasAltNames) 569 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 570 else 571 O << "getRegisterName(unsigned RegNo) {\n"; 572 O << " assert(RegNo && RegNo < " << (Registers.size()+1) 573 << " && \"Invalid register number!\");\n" 574 << "\n"; 575 576 if (hasAltNames) { 577 for (const Record *R : AltNameIndices) 578 emitRegisterNameString(O, R->getName(), Registers); 579 } else 580 emitRegisterNameString(O, "", Registers); 581 582 if (hasAltNames) { 583 O << " switch(AltIdx) {\n" 584 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; 585 for (const Record *R : AltNameIndices) { 586 const std::string &AltName = R->getName(); 587 std::string Prefix = !Namespace.empty() ? Namespace + "::" : ""; 588 O << " case " << Prefix << AltName << ":\n" 589 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" 590 << AltName << "[RegNo-1]) &&\n" 591 << " \"Invalid alt name index for register!\");\n" 592 << " return AsmStrs" << AltName << "+RegAsmOffset" 593 << AltName << "[RegNo-1];\n"; 594 } 595 O << " }\n"; 596 } else { 597 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 598 << " \"Invalid alt name index for register!\");\n" 599 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; 600 } 601 O << "}\n"; 602} 603 604namespace { 605 606// IAPrinter - Holds information about an InstAlias. Two InstAliases match if 607// they both have the same conditionals. In which case, we cannot print out the 608// alias for that pattern. 609class IAPrinter { 610 std::vector<std::string> Conds; 611 std::map<StringRef, std::pair<int, int>> OpMap; 612 613 std::string Result; 614 std::string AsmString; 615 616public: 617 IAPrinter(std::string R, std::string AS) 618 : Result(std::move(R)), AsmString(std::move(AS)) {} 619 620 void addCond(const std::string &C) { Conds.push_back(C); } 621 622 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { 623 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 624 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && 625 "Idx out of range"); 626 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 627 } 628 629 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } 630 int getOpIndex(StringRef Op) { return OpMap[Op].first; } 631 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; } 632 633 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start, 634 StringRef::iterator End) { 635 StringRef::iterator I = Start; 636 StringRef::iterator Next; 637 if (*I == '{') { 638 // ${some_name} 639 Start = ++I; 640 while (I != End && *I != '}') 641 ++I; 642 Next = I; 643 // eat the final '}' 644 if (Next != End) 645 ++Next; 646 } else { 647 // $name, just eat the usual suspects. 648 while (I != End && 649 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || 650 (*I >= '0' && *I <= '9') || *I == '_')) 651 ++I; 652 Next = I; 653 } 654 655 return std::make_pair(StringRef(Start, I - Start), Next); 656 } 657 658 void print(raw_ostream &O) { 659 if (Conds.empty()) { 660 O.indent(6) << "return true;\n"; 661 return; 662 } 663 664 O << "if ("; 665 666 for (std::vector<std::string>::iterator 667 I = Conds.begin(), E = Conds.end(); I != E; ++I) { 668 if (I != Conds.begin()) { 669 O << " &&\n"; 670 O.indent(8); 671 } 672 673 O << *I; 674 } 675 676 O << ") {\n"; 677 O.indent(6) << "// " << Result << "\n"; 678 679 // Directly mangle mapped operands into the string. Each operand is 680 // identified by a '$' sign followed by a byte identifying the number of the 681 // operand. We add one to the index to avoid zero bytes. 682 StringRef ASM(AsmString); 683 SmallString<128> OutString; 684 raw_svector_ostream OS(OutString); 685 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { 686 OS << *I; 687 if (*I == '$') { 688 StringRef Name; 689 std::tie(Name, I) = parseName(++I, E); 690 assert(isOpMapped(Name) && "Unmapped operand!"); 691 692 int OpIndex, PrintIndex; 693 std::tie(OpIndex, PrintIndex) = getOpData(Name); 694 if (PrintIndex == -1) { 695 // Can use the default printOperand route. 696 OS << format("\\x%02X", (unsigned char)OpIndex + 1); 697 } else 698 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand 699 // number, and which of our pre-detected Methods to call. 700 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); 701 } else { 702 ++I; 703 } 704 } 705 706 // Emit the string. 707 O.indent(6) << "AsmString = \"" << OutString << "\";\n"; 708 709 O.indent(6) << "break;\n"; 710 O.indent(4) << '}'; 711 } 712 713 bool operator==(const IAPrinter &RHS) const { 714 if (Conds.size() != RHS.Conds.size()) 715 return false; 716 717 unsigned Idx = 0; 718 for (const auto &str : Conds) 719 if (str != RHS.Conds[Idx++]) 720 return false; 721 722 return true; 723 } 724}; 725 726} // end anonymous namespace 727 728static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { 729 std::string FlatAsmString = 730 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant); 731 AsmString = FlatAsmString; 732 733 return AsmString.count(' ') + AsmString.count('\t'); 734} 735 736namespace { 737 738struct AliasPriorityComparator { 739 typedef std::pair<CodeGenInstAlias, int> ValueType; 740 bool operator()(const ValueType &LHS, const ValueType &RHS) const { 741 if (LHS.second == RHS.second) { 742 // We don't actually care about the order, but for consistency it 743 // shouldn't depend on pointer comparisons. 744 return LHS.first.TheDef->getName() < RHS.first.TheDef->getName(); 745 } 746 747 // Aliases with larger priorities should be considered first. 748 return LHS.second > RHS.second; 749 } 750}; 751 752} // end anonymous namespace 753 754void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { 755 Record *AsmWriter = Target.getAsmWriter(); 756 757 O << "\n#ifdef PRINT_ALIAS_INSTR\n"; 758 O << "#undef PRINT_ALIAS_INSTR\n\n"; 759 760 ////////////////////////////// 761 // Gather information about aliases we need to print 762 ////////////////////////////// 763 764 // Emit the method that prints the alias instruction. 765 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 766 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 767 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 768 769 std::vector<Record*> AllInstAliases = 770 Records.getAllDerivedDefinitions("InstAlias"); 771 772 // Create a map from the qualified name to a list of potential matches. 773 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator> 774 AliasWithPriority; 775 std::map<std::string, AliasWithPriority> AliasMap; 776 for (Record *R : AllInstAliases) { 777 int Priority = R->getValueAsInt("EmitPriority"); 778 if (Priority < 1) 779 continue; // Aliases with priority 0 are never emitted. 780 781 const DagInit *DI = R->getValueAsDag("ResultInst"); 782 const DefInit *Op = cast<DefInit>(DI->getOperator()); 783 AliasMap[getQualifiedName(Op->getDef())].insert( 784 std::make_pair(CodeGenInstAlias(R, Variant, Target), Priority)); 785 } 786 787 // A map of which conditions need to be met for each instruction operand 788 // before it can be matched to the mnemonic. 789 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap; 790 791 std::vector<std::string> PrintMethods; 792 793 // A list of MCOperandPredicates for all operands in use, and the reverse map 794 std::vector<const Record*> MCOpPredicates; 795 DenseMap<const Record*, unsigned> MCOpPredicateMap; 796 797 for (auto &Aliases : AliasMap) { 798 for (auto &Alias : Aliases.second) { 799 const CodeGenInstAlias &CGA = Alias.first; 800 unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); 801 unsigned NumResultOps = 802 CountNumOperands(CGA.ResultInst->AsmString, Variant); 803 804 // Don't emit the alias if it has more operands than what it's aliasing. 805 if (NumResultOps < CountNumOperands(CGA.AsmString, Variant)) 806 continue; 807 808 IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString); 809 810 std::string Namespace = Target.getName(); 811 std::vector<Record *> ReqFeatures; 812 if (PassSubtarget) { 813 // We only consider ReqFeatures predicates if PassSubtarget 814 std::vector<Record *> RF = 815 CGA.TheDef->getValueAsListOfDefs("Predicates"); 816 std::copy_if(RF.begin(), RF.end(), std::back_inserter(ReqFeatures), 817 [](Record *R) { 818 return R->getValueAsBit("AssemblerMatcherPredicate"); 819 }); 820 } 821 822 unsigned NumMIOps = 0; 823 for (auto &Operand : CGA.ResultOperands) 824 NumMIOps += Operand.getMINumOperands(); 825 826 std::string Cond; 827 Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps); 828 IAP.addCond(Cond); 829 830 bool CantHandle = false; 831 832 unsigned MIOpNum = 0; 833 for (unsigned i = 0, e = LastOpNo; i != e; ++i) { 834 std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")"; 835 836 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; 837 838 switch (RO.Kind) { 839 case CodeGenInstAlias::ResultOperand::K_Record: { 840 const Record *Rec = RO.getRecord(); 841 StringRef ROName = RO.getName(); 842 int PrintMethodIdx = -1; 843 844 // These two may have a PrintMethod, which we want to record (if it's 845 // the first time we've seen it) and provide an index for the aliasing 846 // code to use. 847 if (Rec->isSubClassOf("RegisterOperand") || 848 Rec->isSubClassOf("Operand")) { 849 std::string PrintMethod = Rec->getValueAsString("PrintMethod"); 850 if (PrintMethod != "" && PrintMethod != "printOperand") { 851 PrintMethodIdx = 852 llvm::find(PrintMethods, PrintMethod) - PrintMethods.begin(); 853 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size()) 854 PrintMethods.push_back(PrintMethod); 855 } 856 } 857 858 if (Rec->isSubClassOf("RegisterOperand")) 859 Rec = Rec->getValueAsDef("RegClass"); 860 if (Rec->isSubClassOf("RegisterClass")) { 861 IAP.addCond(Op + ".isReg()"); 862 863 if (!IAP.isOpMapped(ROName)) { 864 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 865 Record *R = CGA.ResultOperands[i].getRecord(); 866 if (R->isSubClassOf("RegisterOperand")) 867 R = R->getValueAsDef("RegClass"); 868 Cond = std::string("MRI.getRegClass(") + Target.getName().str() + 869 "::" + R->getName().str() + "RegClassID).contains(" + Op + 870 ".getReg())"; 871 } else { 872 Cond = Op + ".getReg() == MI->getOperand(" + 873 utostr(IAP.getOpIndex(ROName)) + ").getReg()"; 874 } 875 } else { 876 // Assume all printable operands are desired for now. This can be 877 // overridden in the InstAlias instantiation if necessary. 878 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 879 880 // There might be an additional predicate on the MCOperand 881 unsigned Entry = MCOpPredicateMap[Rec]; 882 if (!Entry) { 883 if (!Rec->isValueUnset("MCOperandPredicate")) { 884 MCOpPredicates.push_back(Rec); 885 Entry = MCOpPredicates.size(); 886 MCOpPredicateMap[Rec] = Entry; 887 } else 888 break; // No conditions on this operand at all 889 } 890 Cond = Target.getName().str() + ClassName + "ValidateMCOperand(" + 891 Op + ", STI, " + utostr(Entry) + ")"; 892 } 893 // for all subcases of ResultOperand::K_Record: 894 IAP.addCond(Cond); 895 break; 896 } 897 case CodeGenInstAlias::ResultOperand::K_Imm: { 898 // Just because the alias has an immediate result, doesn't mean the 899 // MCInst will. An MCExpr could be present, for example. 900 IAP.addCond(Op + ".isImm()"); 901 902 Cond = Op + ".getImm() == " + itostr(CGA.ResultOperands[i].getImm()); 903 IAP.addCond(Cond); 904 break; 905 } 906 case CodeGenInstAlias::ResultOperand::K_Reg: 907 // If this is zero_reg, something's playing tricks we're not 908 // equipped to handle. 909 if (!CGA.ResultOperands[i].getRegister()) { 910 CantHandle = true; 911 break; 912 } 913 914 Cond = Op + ".getReg() == " + Target.getName().str() + "::" + 915 CGA.ResultOperands[i].getRegister()->getName().str(); 916 IAP.addCond(Cond); 917 break; 918 } 919 920 MIOpNum += RO.getMINumOperands(); 921 } 922 923 if (CantHandle) continue; 924 925 for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) { 926 Record *R = *I; 927 std::string AsmCondString = R->getValueAsString("AssemblerCondString"); 928 929 // AsmCondString has syntax [!]F(,[!]F)* 930 SmallVector<StringRef, 4> Ops; 931 SplitString(AsmCondString, Ops, ","); 932 assert(!Ops.empty() && "AssemblerCondString cannot be empty"); 933 934 for (auto &Op : Ops) { 935 assert(!Op.empty() && "Empty operator"); 936 if (Op[0] == '!') 937 Cond = "!STI.getFeatureBits()[" + Namespace + "::" + 938 Op.substr(1).str() + "]"; 939 else 940 Cond = "STI.getFeatureBits()[" + Namespace + "::" + Op.str() + "]"; 941 IAP.addCond(Cond); 942 } 943 } 944 945 IAPrinterMap[Aliases.first].push_back(std::move(IAP)); 946 } 947 } 948 949 ////////////////////////////// 950 // Write out the printAliasInstr function 951 ////////////////////////////// 952 953 std::string Header; 954 raw_string_ostream HeaderO(Header); 955 956 HeaderO << "bool " << Target.getName() << ClassName 957 << "::printAliasInstr(const MCInst" 958 << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 959 << "raw_ostream &OS) {\n"; 960 961 std::string Cases; 962 raw_string_ostream CasesO(Cases); 963 964 for (auto &Entry : IAPrinterMap) { 965 std::vector<IAPrinter> &IAPs = Entry.second; 966 std::vector<IAPrinter*> UniqueIAPs; 967 968 for (auto &LHS : IAPs) { 969 bool IsDup = false; 970 for (const auto &RHS : IAPs) { 971 if (&LHS != &RHS && LHS == RHS) { 972 IsDup = true; 973 break; 974 } 975 } 976 977 if (!IsDup) 978 UniqueIAPs.push_back(&LHS); 979 } 980 981 if (UniqueIAPs.empty()) continue; 982 983 CasesO.indent(2) << "case " << Entry.first << ":\n"; 984 985 for (IAPrinter *IAP : UniqueIAPs) { 986 CasesO.indent(4); 987 IAP->print(CasesO); 988 CasesO << '\n'; 989 } 990 991 CasesO.indent(4) << "return false;\n"; 992 } 993 994 if (CasesO.str().empty()) { 995 O << HeaderO.str(); 996 O << " return false;\n"; 997 O << "}\n\n"; 998 O << "#endif // PRINT_ALIAS_INSTR\n"; 999 return; 1000 } 1001 1002 if (!MCOpPredicates.empty()) 1003 O << "static bool " << Target.getName() << ClassName 1004 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1005 << " const MCSubtargetInfo &STI,\n" 1006 << " unsigned PredicateIndex);\n"; 1007 1008 O << HeaderO.str(); 1009 O.indent(2) << "const char *AsmString;\n"; 1010 O.indent(2) << "switch (MI->getOpcode()) {\n"; 1011 O.indent(2) << "default: return false;\n"; 1012 O << CasesO.str(); 1013 O.indent(2) << "}\n\n"; 1014 1015 // Code that prints the alias, replacing the operands with the ones from the 1016 // MCInst. 1017 O << " unsigned I = 0;\n"; 1018 O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n"; 1019 O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n"; 1020 O << " ++I;\n"; 1021 O << " OS << '\\t' << StringRef(AsmString, I);\n"; 1022 1023 O << " if (AsmString[I] != '\\0') {\n"; 1024 O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t')"; 1025 O << " OS << '\\t';\n"; 1026 O << " do {\n"; 1027 O << " if (AsmString[I] == '$') {\n"; 1028 O << " ++I;\n"; 1029 O << " if (AsmString[I] == (char)0xff) {\n"; 1030 O << " ++I;\n"; 1031 O << " int OpIdx = AsmString[I++] - 1;\n"; 1032 O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; 1033 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; 1034 O << (PassSubtarget ? "STI, " : ""); 1035 O << "OS);\n"; 1036 O << " } else\n"; 1037 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; 1038 O << (PassSubtarget ? "STI, " : ""); 1039 O << "OS);\n"; 1040 O << " } else {\n"; 1041 O << " OS << AsmString[I++];\n"; 1042 O << " }\n"; 1043 O << " } while (AsmString[I] != '\\0');\n"; 1044 O << " }\n\n"; 1045 1046 O << " return true;\n"; 1047 O << "}\n\n"; 1048 1049 ////////////////////////////// 1050 // Write out the printCustomAliasOperand function 1051 ////////////////////////////// 1052 1053 O << "void " << Target.getName() << ClassName << "::" 1054 << "printCustomAliasOperand(\n" 1055 << " const MCInst *MI, unsigned OpIdx,\n" 1056 << " unsigned PrintMethodIdx,\n" 1057 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") 1058 << " raw_ostream &OS) {\n"; 1059 if (PrintMethods.empty()) 1060 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; 1061 else { 1062 O << " switch (PrintMethodIdx) {\n" 1063 << " default:\n" 1064 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" 1065 << " break;\n"; 1066 1067 for (unsigned i = 0; i < PrintMethods.size(); ++i) { 1068 O << " case " << i << ":\n" 1069 << " " << PrintMethods[i] << "(MI, OpIdx, " 1070 << (PassSubtarget ? "STI, " : "") << "OS);\n" 1071 << " break;\n"; 1072 } 1073 O << " }\n"; 1074 } 1075 O << "}\n\n"; 1076 1077 if (!MCOpPredicates.empty()) { 1078 O << "static bool " << Target.getName() << ClassName 1079 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1080 << " const MCSubtargetInfo &STI,\n" 1081 << " unsigned PredicateIndex) {\n" 1082 << " switch (PredicateIndex) {\n" 1083 << " default:\n" 1084 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n" 1085 << " break;\n"; 1086 1087 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) { 1088 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate"); 1089 if (CodeInit *SI = dyn_cast<CodeInit>(MCOpPred)) { 1090 O << " case " << i + 1 << ": {\n" 1091 << SI->getValue() << "\n" 1092 << " }\n"; 1093 } else 1094 llvm_unreachable("Unexpected MCOperandPredicate field!"); 1095 } 1096 O << " }\n" 1097 << "}\n\n"; 1098 } 1099 1100 O << "#endif // PRINT_ALIAS_INSTR\n"; 1101} 1102 1103AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1104 Record *AsmWriter = Target.getAsmWriter(); 1105 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 1106 1107 // Get the instruction numbering. 1108 NumberedInstructions = Target.getInstructionsByEnumValue(); 1109 1110 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 1111 const CodeGenInstruction *I = NumberedInstructions[i]; 1112 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") 1113 Instructions.emplace_back(*I, i, Variant); 1114 } 1115} 1116 1117void AsmWriterEmitter::run(raw_ostream &O) { 1118 EmitPrintInstruction(O); 1119 EmitGetRegisterName(O); 1120 EmitPrintAliasInstruction(O); 1121} 1122 1123namespace llvm { 1124 1125void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { 1126 emitSourceFileHeader("Assembly Writer Source Fragment", OS); 1127 AsmWriterEmitter(RK).run(OS); 1128} 1129 1130} // end namespace llvm 1131