1234353Sdim//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2193323Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed// 9193323Sed// This file describes the XCore instructions in TableGen format. 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13193323Sed// Uses of CP, DP are not currently reflected in the patterns, since 14193323Sed// having a physical register as an operand prevents loop hoisting and 15193323Sed// since the value of these registers never changes during the life of the 16193323Sed// function. 17193323Sed 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed// Instruction format superclass. 20193323Sed//===----------------------------------------------------------------------===// 21193323Sed 22193323Sedinclude "XCoreInstrFormats.td" 23193323Sed 24193323Sed//===----------------------------------------------------------------------===// 25193323Sed// XCore specific DAG Nodes. 26193323Sed// 27193323Sed 28193323Sed// Call 29193323Seddef SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 30193323Seddef XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 31218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 32205407Srdivacky SDNPVariadic]>; 33193323Sed 34249423Sdimdef XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 35249423Sdim [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 36193323Sed 37276479Sdimdef SDT_XCoreEhRet : SDTypeProfile<0, 2, 38276479Sdim [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 39276479Sdimdef XCoreEhRet : SDNode<"XCoreISD::EH_RETURN", SDT_XCoreEhRet, 40276479Sdim [SDNPHasChain, SDNPOptInGlue]>; 41276479Sdim 42204642Srdivackydef SDT_XCoreBR_JT : SDTypeProfile<0, 2, 43204642Srdivacky [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 44204642Srdivacky 45204642Srdivackydef XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 46204642Srdivacky [SDNPHasChain]>; 47204642Srdivacky 48204642Srdivackydef XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 49204642Srdivacky [SDNPHasChain]>; 50204642Srdivacky 51193323Seddef SDT_XCoreAddress : SDTypeProfile<1, 1, 52193323Sed [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 53193323Sed 54193323Seddef pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 55193323Sed []>; 56193323Sed 57193323Seddef dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 58193323Sed []>; 59193323Sed 60193323Seddef cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 61193323Sed []>; 62193323Sed 63276479Sdimdef frametoargsoffset : SDNode<"XCoreISD::FRAME_TO_ARGS_OFFSET", SDTIntLeaf, 64276479Sdim []>; 65276479Sdim 66193323Seddef SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 67193323Seddef XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 68243830Sdim [SDNPHasChain, SDNPMayStore]>; 69193323Sed 70276479Sdimdef SDT_XCoreLdwsp : SDTypeProfile<1, 1, [SDTCisInt<1>]>; 71276479Sdimdef XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp, 72276479Sdim [SDNPHasChain, SDNPMayLoad]>; 73276479Sdim 74193323Sed// These are target-independent nodes, but have target-specific formats. 75321369Sdimdef SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 76321369Sdim SDTCisVT<1, i32> ]>; 77193323Seddef SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 78321369Sdim SDTCisVT<1, i32> ]>; 79193323Sed 80193323Seddef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 81218893Sdim [SDNPHasChain, SDNPOutGlue]>; 82193323Seddef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 83218893Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 84193323Sed 85261991Sdimdef SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>; 86261991Sdim 87261991Sdimdef XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER, 88261991Sdim [SDNPHasChain]>; 89261991Sdim 90193323Sed//===----------------------------------------------------------------------===// 91193323Sed// Instruction Pattern Stuff 92193323Sed//===----------------------------------------------------------------------===// 93193323Sed 94193323Seddef div4_xform : SDNodeXForm<imm, [{ 95193323Sed // Transformation function: imm/4 96193323Sed assert(N->getZExtValue() % 4 == 0); 97288943Sdim return getI32Imm(N->getZExtValue()/4, SDLoc(N)); 98193323Sed}]>; 99193323Sed 100193323Seddef msksize_xform : SDNodeXForm<imm, [{ 101193323Sed // Transformation function: get the size of a mask 102193323Sed assert(isMask_32(N->getZExtValue())); 103193323Sed // look for the first non-zero bit 104288943Sdim return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()), 105288943Sdim SDLoc(N)); 106193323Sed}]>; 107193323Sed 108193323Seddef neg_xform : SDNodeXForm<imm, [{ 109193323Sed // Transformation function: -imm 110193323Sed uint32_t value = N->getZExtValue(); 111288943Sdim return getI32Imm(-value, SDLoc(N)); 112193323Sed}]>; 113193323Sed 114198090Srdivackydef bpwsub_xform : SDNodeXForm<imm, [{ 115198090Srdivacky // Transformation function: 32-imm 116198090Srdivacky uint32_t value = N->getZExtValue(); 117288943Sdim return getI32Imm(32 - value, SDLoc(N)); 118198090Srdivacky}]>; 119198090Srdivacky 120193323Seddef div4neg_xform : SDNodeXForm<imm, [{ 121193323Sed // Transformation function: -imm/4 122193323Sed uint32_t value = N->getZExtValue(); 123193323Sed assert(-value % 4 == 0); 124288943Sdim return getI32Imm(-value/4, SDLoc(N)); 125193323Sed}]>; 126193323Sed 127193323Seddef immUs4Neg : PatLeaf<(imm), [{ 128193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 129193323Sed return (-value)%4 == 0 && (-value)/4 <= 11; 130193323Sed}]>; 131193323Sed 132193323Seddef immUs4 : PatLeaf<(imm), [{ 133193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 134193323Sed return value%4 == 0 && value/4 <= 11; 135193323Sed}]>; 136193323Sed 137193323Seddef immUsNeg : PatLeaf<(imm), [{ 138193323Sed return -((uint32_t)N->getZExtValue()) <= 11; 139193323Sed}]>; 140193323Sed 141193323Seddef immUs : PatLeaf<(imm), [{ 142193323Sed return (uint32_t)N->getZExtValue() <= 11; 143193323Sed}]>; 144193323Sed 145193323Seddef immU6 : PatLeaf<(imm), [{ 146193323Sed return (uint32_t)N->getZExtValue() < (1 << 6); 147193323Sed}]>; 148193323Sed 149193323Seddef immU16 : PatLeaf<(imm), [{ 150193323Sed return (uint32_t)N->getZExtValue() < (1 << 16); 151193323Sed}]>; 152193323Sed 153212904Sdimdef immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 154193323Sed 155193323Seddef immBitp : PatLeaf<(imm), [{ 156193323Sed uint32_t value = (uint32_t)N->getZExtValue(); 157193323Sed return (value >= 1 && value <= 8) 158193323Sed || value == 16 159193323Sed || value == 24 160193323Sed || value == 32; 161193323Sed}]>; 162193323Sed 163198090Srdivackydef immBpwSubBitp : PatLeaf<(imm), [{ 164198090Srdivacky uint32_t value = (uint32_t)N->getZExtValue(); 165198090Srdivacky return (value >= 24 && value <= 31) 166198090Srdivacky || value == 16 167198090Srdivacky || value == 8 168198090Srdivacky || value == 0; 169198090Srdivacky}]>; 170198090Srdivacky 171193323Seddef lda16f : PatFrag<(ops node:$addr, node:$offset), 172193323Sed (add node:$addr, (shl node:$offset, 1))>; 173193323Seddef lda16b : PatFrag<(ops node:$addr, node:$offset), 174193323Sed (sub node:$addr, (shl node:$offset, 1))>; 175193323Seddef ldawf : PatFrag<(ops node:$addr, node:$offset), 176193323Sed (add node:$addr, (shl node:$offset, 2))>; 177193323Seddef ldawb : PatFrag<(ops node:$addr, node:$offset), 178193323Sed (sub node:$addr, (shl node:$offset, 2))>; 179193323Sed 180193323Sed// Instruction operand types 181251662Sdimdef pcrel_imm : Operand<i32>; 182251662Sdimdef pcrel_imm_neg : Operand<i32> { 183251662Sdim let DecoderMethod = "DecodeNegImmOperand"; 184251662Sdim} 185193323Seddef brtarget : Operand<OtherVT>; 186251662Sdimdef brtarget_neg : Operand<OtherVT> { 187251662Sdim let DecoderMethod = "DecodeNegImmOperand"; 188251662Sdim} 189193323Sed 190193323Sed// Addressing modes 191193323Seddef ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 192193323Sed 193193323Sed// Address operands 194193323Seddef MEMii : Operand<i32> { 195193323Sed let MIOperandInfo = (ops i32imm, i32imm); 196193323Sed} 197193323Sed 198204642Srdivacky// Jump tables. 199204642Srdivackydef InlineJT : Operand<i32> { 200204642Srdivacky let PrintMethod = "printInlineJT"; 201204642Srdivacky} 202204642Srdivacky 203204642Srdivackydef InlineJT32 : Operand<i32> { 204204642Srdivacky let PrintMethod = "printInlineJT32"; 205204642Srdivacky} 206204642Srdivacky 207193323Sed//===----------------------------------------------------------------------===// 208193323Sed// Instruction Class Templates 209193323Sed//===----------------------------------------------------------------------===// 210193323Sed 211193323Sed// Three operand short 212193323Sed 213249423Sdimmulticlass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 214249423Sdim def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 215249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 216249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 217249423Sdim def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 218249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 219249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 220193323Sed} 221193323Sed 222249423Sdimmulticlass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 223249423Sdim def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 224249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), []>; 225249423Sdim def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 226249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), []>; 227193323Sed} 228193323Sed 229249423Sdimmulticlass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 230249423Sdim SDNode OpNode> { 231249423Sdim def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 232249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 233249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 234249423Sdim def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 235249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 236249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 237193323Sed} 238193323Sed 239249423Sdimclass F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 240249423Sdim _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 241249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 242249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 243193323Sed 244249423Sdimclass F3R_np<bits<5> opc, string OpcStr> : 245249423Sdim _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 246249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), []>; 247193323Sed// Three operand long 248193323Sed 249193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 250249423Sdimmulticlass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 251249423Sdim SDNode OpNode> { 252249423Sdim def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 253249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 254249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 255249423Sdim def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 256249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 257249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 258193323Sed} 259193323Sed 260193323Sed/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 261249423Sdimmulticlass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 262249423Sdim SDNode OpNode> { 263249423Sdim def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 264249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 265249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 266249423Sdim def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 267249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 268249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 269193323Sed} 270193323Sed 271249423Sdimclass FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 272249423Sdim _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 273249423Sdim !strconcat(OpcStr, " $dst, $b, $c"), 274249423Sdim [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 275193323Sed 276193323Sed// Register - U6 277193323Sed// Operand register - U6 278249423Sdimmulticlass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 279249423Sdim def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 280249423Sdim !strconcat(OpcStr, " $a, $b"), []>; 281249423Sdim def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 282249423Sdim !strconcat(OpcStr, " $a, $b"), []>; 283193323Sed} 284193323Sed 285249423Sdimmulticlass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 286251662Sdim def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 287251662Sdim !strconcat(OpcStr, " $a, $b"), []>; 288251662Sdim def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 289251662Sdim !strconcat(OpcStr, " $a, $b"), []>; 290193323Sed} 291193323Sed 292249423Sdim 293193323Sed// U6 294249423Sdimmulticlass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 295249423Sdim def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 296249423Sdim [(OpNode immU6:$a)]>; 297249423Sdim def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 298249423Sdim [(OpNode immU16:$a)]>; 299193323Sed} 300193323Sed 301249423Sdimmulticlass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 302249423Sdim def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 303249423Sdim [(Int immU6:$a)]>; 304249423Sdim def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 305249423Sdim [(Int immU16:$a)]>; 306193323Sed} 307193323Sed 308249423Sdimmulticlass FU6_LU6_np<bits<10> opc, string OpcStr> { 309249423Sdim def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 310249423Sdim def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 311193323Sed} 312193323Sed 313193323Sed// Two operand short 314193323Sed 315249423Sdimclass F2R_np<bits<6> opc, string OpcStr> : 316249423Sdim _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 317249423Sdim !strconcat(OpcStr, " $dst, $b"), []>; 318193323Sed 319193323Sed// Two operand long 320193323Sed 321193323Sed//===----------------------------------------------------------------------===// 322193323Sed// Pseudo Instructions 323193323Sed//===----------------------------------------------------------------------===// 324193323Sed 325193323Sedlet Defs = [SP], Uses = [SP] in { 326321369Sdimdef ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2), 327321369Sdim "# ADJCALLSTACKDOWN $amt, $amt2", 328321369Sdim [(callseq_start timm:$amt, timm:$amt2)]>; 329193323Seddef ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 330249423Sdim "# ADJCALLSTACKUP $amt1", 331193323Sed [(callseq_end timm:$amt1, timm:$amt2)]>; 332193323Sed} 333193323Sed 334276479Sdimlet isReMaterializable = 1 in 335276479Sdimdef FRAME_TO_ARGS_OFFSET : PseudoInstXCore<(outs GRRegs:$dst), (ins), 336276479Sdim "# FRAME_TO_ARGS_OFFSET $dst", 337276479Sdim [(set GRRegs:$dst, (frametoargsoffset))]>; 338276479Sdim 339276479Sdimlet isReturn = 1, isTerminator = 1, isBarrier = 1 in 340276479Sdimdef EH_RETURN : PseudoInstXCore<(outs), (ins GRRegs:$s, GRRegs:$handler), 341276479Sdim "# EH_RETURN $s, $handler", 342276479Sdim [(XCoreEhRet GRRegs:$s, GRRegs:$handler)]>; 343276479Sdim 344193323Seddef LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 345249423Sdim "# LDWFI $dst, $addr", 346193323Sed [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 347193323Sed 348193323Seddef LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 349249423Sdim "# LDAWFI $dst, $addr", 350193323Sed [(set GRRegs:$dst, ADDRspii:$addr)]>; 351193323Sed 352193323Seddef STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 353249423Sdim "# STWFI $src, $addr", 354193323Sed [(store GRRegs:$src, ADDRspii:$addr)]>; 355193323Sed 356198892Srdivacky// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 357198892Srdivacky// instruction selection into a branch sequence. 358198892Srdivackylet usesCustomInserter = 1 in { 359193323Sed def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 360193323Sed (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 361249423Sdim "# SELECT_CC PSEUDO!", 362193323Sed [(set GRRegs:$dst, 363193323Sed (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 364193323Sed} 365193323Sed 366261991Sdimlet hasSideEffects = 1 in 367261991Sdimdef Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER", 368261991Sdim [(XCoreMemBarrier)]>; 369261991Sdim 370193323Sed//===----------------------------------------------------------------------===// 371193323Sed// Instructions 372193323Sed//===----------------------------------------------------------------------===// 373193323Sed 374193323Sed// Three operand short 375249423Sdimdefm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 376249423Sdimdefm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 377280031Sdimlet hasSideEffects = 0 in { 378249423Sdimdefm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 379249423Sdimdef LSS_3r : F3R_np<0b11000, "lss">; 380249423Sdimdef LSU_3r : F3R_np<0b11001, "lsu">; 381193323Sed} 382249423Sdimdef AND_3r : F3R<0b00111, "and", and>; 383249423Sdimdef OR_3r : F3R<0b01000, "or", or>; 384193323Sed 385193323Sedlet mayLoad=1 in { 386249423Sdimdef LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 387249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 388249423Sdim "ldw $dst, $addr[$offset]", []>; 389193323Sed 390249423Sdimdef LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 391249423Sdim (ins GRRegs:$addr, i32imm:$offset), 392249423Sdim "ldw $dst, $addr[$offset]", []>; 393193323Sed 394249423Sdimdef LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 395249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 396249423Sdim "ld16s $dst, $addr[$offset]", []>; 397193323Sed 398249423Sdimdef LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 399249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 400249423Sdim "ld8u $dst, $addr[$offset]", []>; 401193323Sed} 402193323Sed 403193323Sedlet mayStore=1 in { 404249423Sdimdef STW_l3r : _FL3R<0b000001100, (outs), 405249423Sdim (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 406249423Sdim "stw $val, $addr[$offset]", []>; 407193323Sed 408280031Sdimdef STW_2rus : _F2RUS<0b00000, (outs), 409249423Sdim (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 410249423Sdim "stw $val, $addr[$offset]", []>; 411193323Sed} 412193323Sed 413249423Sdimdefm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 414249423Sdimdefm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 415193323Sed 416249423Sdim// The first operand is treated as an immediate since it refers to a register 417249423Sdim// number in another thread. 418249423Sdimdef TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 419249423Sdim "set t[$c]:r$a, $b", []>; 420249423Sdim 421193323Sed// Three operand long 422249423Sdimdef LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 423249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 424249423Sdim "ldaw $dst, $addr[$offset]", 425249423Sdim [(set GRRegs:$dst, 426249423Sdim (ldawf GRRegs:$addr, GRRegs:$offset))]>; 427193323Sed 428280031Sdimlet hasSideEffects = 0 in 429249423Sdimdef LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 430249423Sdim (ins GRRegs:$addr, i32imm:$offset), 431249423Sdim "ldaw $dst, $addr[$offset]", []>; 432193323Sed 433249423Sdimdef LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 434249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 435249423Sdim "ldaw $dst, $addr[-$offset]", 436249423Sdim [(set GRRegs:$dst, 437249423Sdim (ldawb GRRegs:$addr, GRRegs:$offset))]>; 438193323Sed 439280031Sdimlet hasSideEffects = 0 in 440249423Sdimdef LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 441249423Sdim (ins GRRegs:$addr, i32imm:$offset), 442249423Sdim "ldaw $dst, $addr[-$offset]", []>; 443193323Sed 444249423Sdimdef LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 445249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 446249423Sdim "lda16 $dst, $addr[$offset]", 447249423Sdim [(set GRRegs:$dst, 448249423Sdim (lda16f GRRegs:$addr, GRRegs:$offset))]>; 449193323Sed 450249423Sdimdef LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 451249423Sdim (ins GRRegs:$addr, GRRegs:$offset), 452249423Sdim "lda16 $dst, $addr[-$offset]", 453249423Sdim [(set GRRegs:$dst, 454249423Sdim (lda16b GRRegs:$addr, GRRegs:$offset))]>; 455193323Sed 456249423Sdimdef MUL_l3r : FL3R<0b001111100, "mul", mul>; 457193323Sed// Instructions which may trap are marked as side effecting. 458193323Sedlet hasSideEffects = 1 in { 459249423Sdimdef DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 460249423Sdimdef DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 461249423Sdimdef REMS_l3r : FL3R<0b110001100, "rems", srem>; 462249423Sdimdef REMU_l3r : FL3R<0b110011100, "remu", urem>; 463193323Sed} 464249423Sdimdef XOR_l3r : FL3R<0b000011100, "xor", xor>; 465249423Sdimdefm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 466223017Sdim 467223017Sdimlet Constraints = "$src1 = $dst" in 468249423Sdimdef CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 469249423Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 470249423Sdim "crc32 $dst, $src2, $src3", 471249423Sdim [(set GRRegs:$dst, 472249423Sdim (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 473249423Sdim GRRegs:$src3))]>; 474223017Sdim 475193323Sedlet mayStore=1 in { 476249423Sdimdef ST16_l3r : _FL3R<0b100001100, (outs), 477249423Sdim (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 478249423Sdim "st16 $val, $addr[$offset]", []>; 479193323Sed 480249423Sdimdef ST8_l3r : _FL3R<0b100011100, (outs), 481249423Sdim (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 482249423Sdim "st8 $val, $addr[$offset]", []>; 483193323Sed} 484193323Sed 485249423Sdimdef INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 486249423Sdim (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 487249423Sdim []>; 488249423Sdim 489249423Sdimdef OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 490249423Sdim (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 491249423Sdim "outpw res[$b], $a, $c", []>; 492249423Sdim 493193323Sed// Four operand long 494249423Sdimlet Constraints = "$e = $a,$f = $b" in { 495249423Sdimdef MACCU_l4r : _FL4RSrcDstSrcDst< 496249423Sdim 0b000001, (outs GRRegs:$a, GRRegs:$b), 497249423Sdim (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 498193323Sed 499249423Sdimdef MACCS_l4r : _FL4RSrcDstSrcDst< 500249423Sdim 0b000010, (outs GRRegs:$a, GRRegs:$b), 501249423Sdim (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 502193323Sed} 503193323Sed 504249423Sdimlet Constraints = "$e = $b" in 505249423Sdimdef CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 506249423Sdim (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 507249423Sdim "crc8 $b, $a, $c, $d", []>; 508223017Sdim 509193323Sed// Five operand long 510193323Sed 511249423Sdimdef LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 512249423Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 513249423Sdim "ladd $dst2, $dst1, $src1, $src2, $src3", 514249423Sdim []>; 515193323Sed 516249423Sdimdef LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 517249423Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 518249423Sdim "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 519193323Sed 520249423Sdimdef LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 521249423Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 522249423Sdim "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 523193323Sed 524193323Sed// Six operand long 525193323Sed 526249423Sdimdef LMUL_l6r : _FL6R< 527249423Sdim 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 528249423Sdim (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 529249423Sdim "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 530193323Sed 531193323Sed// Register - U6 532193323Sed 533193323Sed//let Uses = [DP] in ... 534280031Sdimlet hasSideEffects = 0, isReMaterializable = 1 in 535251662Sdimdef LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 536249423Sdim "ldaw $a, dp[$b]", []>; 537193323Sed 538193323Sedlet isReMaterializable = 1 in 539251662Sdimdef LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 540249423Sdim "ldaw $a, dp[$b]", 541251662Sdim [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 542193323Sed 543193323Sedlet mayLoad=1 in 544251662Sdimdef LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 545249423Sdim "ldw $a, dp[$b]", []>; 546193323Sed 547251662Sdimdef LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 548249423Sdim "ldw $a, dp[$b]", 549251662Sdim [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>; 550249423Sdim 551193323Sedlet mayStore=1 in 552251662Sdimdef STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 553249423Sdim "stw $a, dp[$b]", []>; 554193323Sed 555251662Sdimdef STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 556249423Sdim "stw $a, dp[$b]", 557251662Sdim [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 558193323Sed 559193323Sed//let Uses = [CP] in .. 560280031Sdimlet mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in { 561261991Sdimdef LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 562261991Sdim "ldw $a, cp[$b]", []>; 563261991Sdimdef LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 564261991Sdim "ldw $a, cp[$b]", 565261991Sdim [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>; 566261991Sdim} 567193323Sed 568193323Sedlet Uses = [SP] in { 569193323Sedlet mayStore=1 in { 570249423Sdimdef STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 571249423Sdim "stw $a, sp[$b]", 572249423Sdim [(XCoreStwsp RRegs:$a, immU6:$b)]>; 573193323Sed 574249423Sdimdef STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 575249423Sdim "stw $a, sp[$b]", 576249423Sdim [(XCoreStwsp RRegs:$a, immU16:$b)]>; 577193323Sed} 578193323Sed 579193323Sedlet mayLoad=1 in { 580249423Sdimdef LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 581276479Sdim "ldw $a, sp[$b]", 582276479Sdim [(set RRegs:$a, (XCoreLdwsp immU6:$b))]>; 583193323Sed 584249423Sdimdef LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 585276479Sdim "ldw $a, sp[$b]", 586276479Sdim [(set RRegs:$a, (XCoreLdwsp immU16:$b))]>; 587193323Sed} 588193323Sed 589280031Sdimlet hasSideEffects = 0 in { 590249423Sdimdef LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 591249423Sdim "ldaw $a, sp[$b]", []>; 592193323Sed 593249423Sdimdef LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 594249423Sdim "ldaw $a, sp[$b]", []>; 595193323Sed} 596193323Sed} 597193323Sed 598193323Sedlet isReMaterializable = 1 in { 599249423Sdimdef LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 600249423Sdim "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; 601193323Sed 602249423Sdimdef LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 603249423Sdim "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; 604193323Sed} 605193323Sed 606249423Sdimdef SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 607249423Sdim "setc res[$a], $b", 608249423Sdim [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 609218893Sdim 610249423Sdimdef SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 611249423Sdim "setc res[$a], $b", 612249423Sdim [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 613218893Sdim 614193323Sed// Operand register - U6 615193323Sedlet isBranch = 1, isTerminator = 1 in { 616249423Sdimdefm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 617249423Sdimdefm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 618249423Sdimdefm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 619249423Sdimdefm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 620193323Sed} 621193323Sed 622193323Sed// U6 623193323Sedlet Defs = [SP], Uses = [SP] in { 624280031Sdimlet hasSideEffects = 0 in 625249423Sdimdefm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 626249423Sdim 627193323Sedlet mayStore = 1 in 628249423Sdimdefm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 629193323Sed 630199481Srdivackylet isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 631249423Sdimdefm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 632193323Sed} 633193323Sed} 634193323Sed 635280031Sdimlet hasSideEffects = 0 in 636249423Sdimdefm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 637249423Sdim 638249423Sdimlet Uses = [R11], isCall=1 in 639249423Sdimdefm BLAT : FU6_LU6_np<0b0111001101, "blat">; 640249423Sdim 641204642Srdivackylet isBranch = 1, isTerminator = 1, isBarrier = 1 in { 642251662Sdimdef BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 643193323Sed 644251662Sdimdef BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 645193323Sed 646249423Sdimdef BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 647193323Sed 648249423Sdimdef BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 649193323Sed} 650193323Sed 651193323Sed//let Uses = [CP] in ... 652280031Sdimlet Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in 653251662Sdimdef LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 654193323Sed []>; 655193323Sed 656198090Srdivackylet Defs = [R11], isReMaterializable = 1 in 657251662Sdimdef LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 658251662Sdim [(set R11, (cprelwrapper tglobaladdr:$a))]>; 659193323Sed 660249423Sdimlet Defs = [R11] in 661249423Sdimdefm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 662221345Sdim 663249423Sdimdefm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 664221345Sdim 665249423Sdimdefm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 666249423Sdim 667221345Sdim// setsr may cause a branch if it is used to enable events. clrsr may 668221345Sdim// branch if it is executed while events are enabled. 669249423Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 670249423Sdim isCodeGenOnly = 1 in { 671249423Sdimdefm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 672249423Sdimdefm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 673221345Sdim} 674221345Sdim 675249423Sdimdefm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 676249423Sdim 677249423Sdimlet Uses = [SP], Defs = [SP], mayStore = 1 in 678249423Sdimdefm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 679249423Sdim 680249423Sdimlet Uses = [SP], Defs = [SP], mayLoad = 1 in 681249423Sdimdefm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 682249423Sdim 683193323Sed// U10 684193323Sed 685251662Sdimlet Defs = [R11], isReMaterializable = 1 in { 686280031Sdimlet hasSideEffects = 0 in 687251662Sdimdef LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>; 688193323Sed 689251662Sdimdef LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 690249423Sdim [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 691193323Sed 692280031Sdimlet hasSideEffects = 0 in 693251662Sdimdef LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", 694251662Sdim []>; 695251662Sdim 696280031Sdimlet hasSideEffects = 0 in 697251662Sdimdef LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a), 698251662Sdim "ldap r11, $a", 699251662Sdim [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 700251662Sdim 701251662Sdimlet isCodeGenOnly = 1 in 702251662Sdimdef LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 703249423Sdim [(set R11, (pcrelwrapper tblockaddress:$a))]>; 704251662Sdim} 705199511Srdivacky 706193323Sedlet isCall=1, 707203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 708226633SdimDefs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 709249423Sdimdef BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 710193323Sed 711249423Sdimdef BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 712249423Sdim 713251662Sdimdef BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 714276479Sdim []>; 715249423Sdim 716251662Sdimdef BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 717276479Sdim [(XCoreBranchLink tglobaladdr:$a)]>; 718251662Sdim 719251662Sdimdef BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 720251662Sdim 721251662Sdimdef BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 722193323Sed} 723193323Sed 724249423Sdimlet Defs = [R11], mayLoad = 1, isReMaterializable = 1, 725280031Sdim hasSideEffects = 0 in { 726249423Sdimdef LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 727249423Sdim 728249423Sdimdef LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 729249423Sdim []>; 730249423Sdim} 731249423Sdim 732193323Sed// Two operand short 733249423Sdimdef NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 734249423Sdim "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 735193323Sed 736249423Sdimdef NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 737249423Sdim "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 738193323Sed 739210299Sedlet Constraints = "$src1 = $dst" in { 740249423Sdimdef SEXT_rus : 741249423Sdim _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 742249423Sdim "sext $dst, $src2", 743249423Sdim [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 744249423Sdim immBitp:$src2))]>; 745193323Sed 746249423Sdimdef SEXT_2r : 747249423Sdim _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 748249423Sdim "sext $dst, $src2", 749249423Sdim [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 750226633Sdim 751249423Sdimdef ZEXT_rus : 752249423Sdim _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 753249423Sdim "zext $dst, $src2", 754249423Sdim [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 755249423Sdim immBitp:$src2))]>; 756193323Sed 757249423Sdimdef ZEXT_2r : 758249423Sdim _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 759249423Sdim "zext $dst, $src2", 760249423Sdim [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 761226633Sdim 762249423Sdimdef ANDNOT_2r : 763249423Sdim _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 764249423Sdim "andnot $dst, $src2", 765249423Sdim [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 766193323Sed} 767193323Sed 768280031Sdimlet isReMaterializable = 1, hasSideEffects = 0 in 769249423Sdimdef MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 770249423Sdim "mkmsk $dst, $size", []>; 771193323Sed 772249423Sdimdef MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 773249423Sdim "mkmsk $dst, $size", 774249423Sdim [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 775193323Sed 776249423Sdimdef GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 777249423Sdim "getr $dst, $type", 778249423Sdim [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 779218893Sdim 780249423Sdimdef GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 781249423Sdim "getts $dst, res[$r]", 782249423Sdim [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 783219077Sdim 784249423Sdimdef SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 785249423Sdim "setpt res[$r], $val", 786249423Sdim [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 787219077Sdim 788249423Sdimdef OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 789249423Sdim "outct res[$r], $val", 790249423Sdim [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 791218893Sdim 792249423Sdimdef OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 793249423Sdim "outct res[$r], $val", 794249423Sdim [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 795218893Sdim 796249423Sdimdef OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 797249423Sdim "outt res[$r], $val", 798249423Sdim [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 799218893Sdim 800249423Sdimdef OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 801249423Sdim "out res[$r], $val", 802249423Sdim [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 803218893Sdim 804219077Sdimlet Constraints = "$src = $dst" in 805249423Sdimdef OUTSHR_2r : 806249423Sdim _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 807249423Sdim "outshr res[$r], $src", 808249423Sdim [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 809219077Sdim 810249423Sdimdef INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 811249423Sdim "inct $dst, res[$r]", 812249423Sdim [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 813218893Sdim 814249423Sdimdef INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 815249423Sdim "int $dst, res[$r]", 816249423Sdim [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 817218893Sdim 818249423Sdimdef IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 819218893Sdim "in $dst, res[$r]", 820218893Sdim [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 821218893Sdim 822219077Sdimlet Constraints = "$src = $dst" in 823249423Sdimdef INSHR_2r : 824249423Sdim _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 825249423Sdim "inshr $dst, res[$r]", 826249423Sdim [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 827219077Sdim 828249423Sdimdef CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 829249423Sdim "chkct res[$r], $val", 830249423Sdim [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 831218893Sdim 832249423Sdimdef CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 833249423Sdim "chkct res[$r], $val", 834249423Sdim [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 835218893Sdim 836249423Sdimdef TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 837226633Sdim "testct $dst, res[$src]", 838226633Sdim [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 839226633Sdim 840249423Sdimdef TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 841226633Sdim "testwct $dst, res[$src]", 842226633Sdim [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 843226633Sdim 844249423Sdimdef SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 845249423Sdim "setd res[$r], $val", 846249423Sdim [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 847218893Sdim 848249423Sdimdef SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 849249423Sdim "setpsc res[$src1], $src2", 850249423Sdim [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 851249423Sdim 852249423Sdimdef GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 853221345Sdim "getst $dst, res[$r]", 854221345Sdim [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 855221345Sdim 856249423Sdimdef INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 857221345Sdim "init t[$t]:sp, $src", 858221345Sdim [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 859221345Sdim 860249423Sdimdef INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 861221345Sdim "init t[$t]:pc, $src", 862221345Sdim [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 863221345Sdim 864249423Sdimdef INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 865221345Sdim "init t[$t]:cp, $src", 866221345Sdim [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 867221345Sdim 868249423Sdimdef INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 869221345Sdim "init t[$t]:dp, $src", 870221345Sdim [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 871221345Sdim 872249423Sdimdef PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 873249423Sdim "peek $dst, res[$src]", 874249423Sdim [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 875249423Sdim 876249423Sdimdef ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 877249423Sdim "endin $dst, res[$src]", 878249423Sdim [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 879249423Sdim 880249423Sdimdef EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 881249423Sdim "eef $a, res[$b]", []>; 882249423Sdim 883249423Sdimdef EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 884249423Sdim "eet $a, res[$b]", []>; 885249423Sdim 886249423Sdimdef TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 887249423Sdim "tsetmr r$a, $b", []>; 888249423Sdim 889193323Sed// Two operand long 890249423Sdimdef BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 891249423Sdim "bitrev $dst, $src", 892249423Sdim [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 893193323Sed 894249423Sdimdef BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 895249423Sdim "byterev $dst, $src", 896249423Sdim [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 897193323Sed 898280031Sdimdef CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 899249423Sdim "clz $dst, $src", 900249423Sdim [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 901193323Sed 902249423Sdimdef GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 903249423Sdim "getd $dst, res[$src]", []>; 904218893Sdim 905249423Sdimdef GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 906249423Sdim "getn $dst, res[$src]", []>; 907219077Sdim 908249423Sdimdef SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 909249423Sdim "setc res[$r], $val", 910249423Sdim [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 911221345Sdim 912249423Sdimdef SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 913249423Sdim "settw res[$r], $val", 914249423Sdim [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 915221345Sdim 916249423Sdimdef GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 917249423Sdim "get $dst, ps[$src]", 918249423Sdim [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 919249423Sdim 920249423Sdimdef SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 921249423Sdim "set ps[$src1], $src2", 922249423Sdim [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 923249423Sdim 924249423Sdimdef INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 925221345Sdim "init t[$t]:lr, $src", 926221345Sdim [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 927221345Sdim 928249423Sdimdef SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 929249423Sdim "setclk res[$src1], $src2", 930249423Sdim [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 931221345Sdim 932249423Sdimdef SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 933249423Sdim "setn res[$src1], $src2", []>; 934221345Sdim 935249423Sdimdef SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 936249423Sdim "setrdy res[$src1], $src2", 937249423Sdim [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 938221345Sdim 939249423Sdimdef TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 940249423Sdim "testlcl $dst, res[$src]", []>; 941226633Sdim 942193323Sed// One operand short 943249423Sdimdef MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 944249423Sdim "msync res[$a]", 945249423Sdim [(int_xcore_msync GRRegs:$a)]>; 946249423Sdimdef MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 947249423Sdim "mjoin res[$a]", 948249423Sdim [(int_xcore_mjoin GRRegs:$a)]>; 949221345Sdim 950204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 951249423Sdimdef BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 952249423Sdim "bau $a", 953249423Sdim [(brind GRRegs:$a)]>; 954193323Sed 955204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 956204642Srdivackydef BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 957204642Srdivacky "bru $i\n$t", 958204642Srdivacky [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 959204642Srdivacky 960204642Srdivackylet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 961204642Srdivackydef BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 962204642Srdivacky "bru $i\n$t", 963204642Srdivacky [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 964204642Srdivacky 965249423Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 966249423Sdimdef BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; 967249423Sdim 968280031Sdimlet Defs=[SP], hasSideEffects=0 in 969249423Sdimdef SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 970193323Sed 971280031Sdimlet hasSideEffects=0 in 972249423Sdimdef SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 973249423Sdim 974280031Sdimlet hasSideEffects=0 in 975249423Sdimdef SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 976249423Sdim 977204642Srdivackylet hasCtrlDep = 1 in 978249423Sdimdef ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 979249423Sdim "ecallt $a", 980193323Sed []>; 981193323Sed 982204642Srdivackylet hasCtrlDep = 1 in 983249423Sdimdef ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 984249423Sdim "ecallf $a", 985193323Sed []>; 986193323Sed 987193323Sedlet isCall=1, 988203954Srdivacky// All calls clobber the link register and the non-callee-saved registers: 989226633SdimDefs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 990249423Sdimdef BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 991249423Sdim "bla $a", 992249423Sdim [(XCoreBranchLink GRRegs:$a)]>; 993193323Sed} 994193323Sed 995249423Sdimdef SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 996249423Sdim "syncr res[$a]", 997249423Sdim [(int_xcore_syncr GRRegs:$a)]>; 998219077Sdim 999249423Sdimdef FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 1000249423Sdim "freer res[$a]", 1001249423Sdim [(int_xcore_freer GRRegs:$a)]>; 1002218893Sdim 1003226633Sdimlet Uses=[R11] in { 1004249423Sdimdef SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 1005249423Sdim "setv res[$a], r11", 1006249423Sdim [(int_xcore_setv GRRegs:$a, R11)]>; 1007219077Sdim 1008249423Sdimdef SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 1009249423Sdim "setev res[$a], r11", 1010249423Sdim [(int_xcore_setev GRRegs:$a, R11)]>; 1011226633Sdim} 1012226633Sdim 1013249423Sdimdef DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 1014219077Sdim 1015276479Sdimdef EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", 1016276479Sdim [(int_xcore_edu GRRegs:$a)]>; 1017249423Sdim 1018249423Sdimdef EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 1019249423Sdim "eeu res[$a]", 1020249423Sdim [(int_xcore_eeu GRRegs:$a)]>; 1021249423Sdim 1022249423Sdimdef KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 1023249423Sdim 1024249423Sdimdef WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 1025249423Sdim 1026249423Sdimdef WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 1027249423Sdim 1028249423Sdimdef TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 1029249423Sdim 1030276479Sdimdef CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", 1031276479Sdim [(int_xcore_clrpt GRRegs:$a)]>; 1032249423Sdim 1033193323Sed// Zero operand short 1034193323Sed 1035249423Sdimdef CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 1036219077Sdim 1037249423Sdimdef DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 1038249423Sdim 1039249423Sdimlet Defs = [SP], Uses = [SP] in 1040249423Sdimdef DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1041249423Sdim 1042249423Sdimlet Defs = [SP] in 1043249423Sdimdef DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1044249423Sdim 1045249423Sdimdef DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1046249423Sdim 1047249423Sdimdef FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1048249423Sdim 1049226633Sdimlet Defs = [R11] in { 1050249423Sdimdef GETID_0R : _F0R<0b0001001110, (outs), (ins), 1051226633Sdim "get r11, id", 1052226633Sdim [(set R11, (int_xcore_getid))]>; 1053193323Sed 1054249423Sdimdef GETED_0R : _F0R<0b0000111110, (outs), (ins), 1055226633Sdim "get r11, ed", 1056226633Sdim [(set R11, (int_xcore_geted))]>; 1057226633Sdim 1058249423Sdimdef GETET_0R : _F0R<0b0000111111, (outs), (ins), 1059226633Sdim "get r11, et", 1060226633Sdim [(set R11, (int_xcore_getet))]>; 1061249423Sdim 1062249423Sdimdef GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1063249423Sdim "get r11, kep", []>; 1064249423Sdim 1065249423Sdimdef GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1066249423Sdim "get r11, ksp", []>; 1067226633Sdim} 1068226633Sdim 1069249423Sdimlet Defs = [SP] in 1070249423Sdimdef KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1071249423Sdim 1072249423Sdimlet Uses = [SP], mayLoad = 1 in { 1073249423Sdimdef LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1074249423Sdim 1075249423Sdimdef LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1076249423Sdim 1077249423Sdimdef LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1078249423Sdim 1079249423Sdimdef LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1080249423Sdim} 1081249423Sdim 1082249423Sdimlet Uses=[R11] in 1083249423Sdimdef SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1084249423Sdim 1085249423Sdimdef SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1086221345Sdim "ssync", 1087239462Sdim [(int_xcore_ssync)]>; 1088221345Sdim 1089249423Sdimlet Uses = [SP], mayStore = 1 in { 1090249423Sdimdef STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1091249423Sdim 1092249423Sdimdef STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1093249423Sdim 1094249423Sdimdef STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1095249423Sdim 1096249423Sdimdef STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1097249423Sdim} 1098249423Sdim 1099219077Sdimlet isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1100219077Sdim hasSideEffects = 1 in 1101249423Sdimdef WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1102249423Sdim "waiteu", 1103249423Sdim [(brind (int_xcore_waitevent))]>; 1104219077Sdim 1105193323Sed//===----------------------------------------------------------------------===// 1106193323Sed// Non-Instruction Patterns 1107193323Sed//===----------------------------------------------------------------------===// 1108193323Sed 1109249423Sdimdef : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1110193323Sed 1111193323Sed/// sext_inreg 1112193323Seddef : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1113193323Seddef : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1114193323Seddef : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1115193323Sed 1116193323Sed/// loads 1117193323Seddef : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1118193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1119193323Seddef : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1120193323Sed 1121198090Srdivackydef : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1122193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1123193323Seddef : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1124193323Sed 1125193323Seddef : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1126193323Sed (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1127193323Seddef : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1128193323Sed (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1129193323Seddef : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1130193323Sed 1131193323Sed/// anyext 1132193323Seddef : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1133193323Sed (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1134193323Seddef : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1135193323Seddef : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1136193323Sed (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1137193323Seddef : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1138193323Sed 1139193323Sed/// stores 1140193323Seddef : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1141193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1142193323Seddef : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1143193323Sed (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1144193323Sed 1145193323Seddef : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1146193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1147193323Seddef : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1148193323Sed (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1149193323Sed 1150193323Seddef : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1151249423Sdim (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1152193323Seddef : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1153193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1154193323Seddef : Pat<(store GRRegs:$val, GRRegs:$addr), 1155193323Sed (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1156193323Sed 1157193323Sed/// cttz 1158193323Seddef : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1159193323Sed 1160193323Sed/// trap 1161193323Seddef : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1162193323Sed 1163193323Sed/// 1164193323Sed/// branch patterns 1165193323Sed/// 1166193323Sed 1167193323Sed// unconditional branch 1168193323Seddef : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1169193323Sed 1170193323Sed// direct match equal/notequal zero brcond 1171193323Seddef : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1172193323Sed (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1173193323Seddef : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1174193323Sed (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1175193323Sed 1176193323Seddef : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1177193323Sed (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1178193323Seddef : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1179193323Sed (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1180193323Seddef : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1181193323Sed (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1182193323Seddef : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1183193323Sed (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1184193323Seddef : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1185193323Sed (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1186193323Seddef : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1187193323Sed (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1188193323Sed 1189193323Sed// generic brcond pattern 1190193323Seddef : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1191193323Sed 1192193323Sed 1193193323Sed/// 1194193323Sed/// Select patterns 1195193323Sed/// 1196193323Sed 1197193323Sed// direct match equal/notequal zero select 1198193323Seddef : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1199193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1200193323Sed 1201193323Seddef : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1202193323Sed (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1203193323Sed 1204193323Seddef : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1205193323Sed (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1206193323Seddef : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1207193323Sed (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1208193323Seddef : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1209193323Sed (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1210193323Seddef : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1211193323Sed (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1212193323Seddef : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1213193323Sed (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1214193323Seddef : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1215193323Sed (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1216193323Sed 1217193323Sed/// 1218193323Sed/// setcc patterns, only matched when none of the above brcond 1219193323Sed/// patterns match 1220193323Sed/// 1221193323Sed 1222193323Sed// setcc 2 register operands 1223193323Seddef : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1224193323Sed (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1225193323Seddef : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1226193323Sed (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1227193323Sed 1228193323Seddef : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1229193323Sed (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1230193323Seddef : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1231193323Sed (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1232193323Sed 1233193323Seddef : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1234193323Sed (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1235193323Seddef : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1236193323Sed (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1237193323Sed 1238193323Seddef : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1239193323Sed (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1240193323Seddef : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1241193323Sed (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1242193323Sed 1243193323Seddef : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1244193323Sed (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1245193323Sed 1246193323Seddef : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1247193323Sed (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1248193323Sed 1249193323Sed// setcc reg/imm operands 1250193323Seddef : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1251193323Sed (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1252193323Seddef : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1253193323Sed (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1254193323Sed 1255193323Sed// misc 1256193323Seddef : Pat<(add GRRegs:$addr, immUs4:$offset), 1257193323Sed (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1258193323Sed 1259193323Seddef : Pat<(sub GRRegs:$addr, immUs4:$offset), 1260193323Sed (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1261193323Sed 1262193323Seddef : Pat<(and GRRegs:$val, immMskBitp:$mask), 1263193323Sed (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1264193323Sed 1265193323Sed// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1266193323Seddef : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1267193323Sed (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1268193323Sed 1269193323Seddef : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1270193323Sed (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1271193323Sed 1272193323Sed/// 1273193323Sed/// Some peepholes 1274193323Sed/// 1275193323Sed 1276193323Seddef : Pat<(mul GRRegs:$src, 3), 1277193323Sed (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1278193323Sed 1279193323Seddef : Pat<(mul GRRegs:$src, 5), 1280193323Sed (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1281193323Sed 1282193323Seddef : Pat<(mul GRRegs:$src, -3), 1283193323Sed (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1284193323Sed 1285193323Sed// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1286193323Seddef : Pat<(sra GRRegs:$src, 31), 1287193323Sed (ASHR_l2rus GRRegs:$src, 32)>; 1288193323Sed 1289198090Srdivackydef : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1290198090Srdivacky (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1291198090Srdivacky 1292198090Srdivacky// setge X, 0 is canonicalized to setgt X, -1 1293198090Srdivackydef : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1294198090Srdivacky (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1295198090Srdivacky 1296198090Srdivackydef : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1297198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1298198090Srdivacky 1299198090Srdivackydef : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1300198090Srdivacky (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1301198090Srdivacky 1302198090Srdivackydef : Pat<(setgt GRRegs:$lhs, -1), 1303198090Srdivacky (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1304198090Srdivacky 1305198090Srdivackydef : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1306198090Srdivacky (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1307276479Sdim 1308276479Sdimdef : Pat<(load (cprelwrapper tconstpool:$b)), 1309276479Sdim (LDWCP_lru6 tconstpool:$b)>; 1310276479Sdim 1311276479Sdimdef : Pat<(cprelwrapper tconstpool:$b), 1312276479Sdim (LDAWCP_lu6 tconstpool:$b)>; 1313