1234353Sdim//===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===// 2193323Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed 9193323Sed//===----------------------------------------------------------------------===// 10193323Sed// Instruction format superclass 11193323Sed//===----------------------------------------------------------------------===// 12249423Sdimclass InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern> 13193323Sed : Instruction { 14193323Sed field bits<32> Inst; 15193323Sed 16193323Sed let Namespace = "XCore"; 17193323Sed dag OutOperandList = outs; 18193323Sed dag InOperandList = ins; 19193323Sed let AsmString = asmstr; 20193323Sed let Pattern = pattern; 21249423Sdim let Size = sz; 22249423Sdim field bits<32> SoftFail = 0; 23193323Sed} 24193323Sed 25193323Sed// XCore pseudo instructions format 26193323Sedclass PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern> 27249423Sdim : InstXCore<0, outs, ins, asmstr, pattern> { 28249423Sdim let isPseudo = 1; 29249423Sdim} 30193323Sed 31193323Sed//===----------------------------------------------------------------------===// 32193323Sed// Instruction formats 33193323Sed//===----------------------------------------------------------------------===// 34193323Sed 35249423Sdimclass _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 36249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 37249423Sdim let Inst{15-11} = opc; 38249423Sdim let DecoderMethod = "Decode3RInstruction"; 39193323Sed} 40193323Sed 41249423Sdim// 3R with first operand as an immediate. Used for TSETR where the first 42249423Sdim// operand is treated as an immediate since it refers to a register number in 43249423Sdim// another thread. 44249423Sdimclass _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 45249423Sdim : _F3R<opc, outs, ins, asmstr, pattern> { 46249423Sdim let DecoderMethod = "Decode3RImmInstruction"; 47193323Sed} 48193323Sed 49249423Sdimclass _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 50249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 51249423Sdim let Inst{31-27} = opc{8-4}; 52249423Sdim let Inst{26-20} = 0b1111110; 53249423Sdim let Inst{19-16} = opc{3-0}; 54249423Sdim 55249423Sdim let Inst{15-11} = 0b11111; 56249423Sdim let DecoderMethod = "DecodeL3RInstruction"; 57193323Sed} 58193323Sed 59249423Sdim// L3R with first operand as both a source and a destination. 60249423Sdimclass _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr, 61249423Sdim list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> { 62249423Sdim let DecoderMethod = "DecodeL3RSrcDstInstruction"; 63193323Sed} 64193323Sed 65249423Sdimclass _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 66249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 67249423Sdim let Inst{15-11} = opc; 68249423Sdim let DecoderMethod = "Decode2RUSInstruction"; 69193323Sed} 70193323Sed 71249423Sdim// 2RUS with bitp operand 72249423Sdimclass _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr, 73249423Sdim list<dag> pattern> 74249423Sdim : _F2RUS<opc, outs, ins, asmstr, pattern> { 75249423Sdim let DecoderMethod = "Decode2RUSBitpInstruction"; 76193323Sed} 77193323Sed 78249423Sdimclass _FL2RUS<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 79249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 80249423Sdim let Inst{31-27} = opc{8-4}; 81249423Sdim let Inst{26-20} = 0b1111110; 82249423Sdim let Inst{19-16} = opc{3-0}; 83249423Sdim 84249423Sdim let Inst{15-11} = 0b11111; 85249423Sdim let DecoderMethod = "DecodeL2RUSInstruction"; 86193323Sed} 87193323Sed 88249423Sdim// L2RUS with bitp operand 89249423Sdimclass _FL2RUSBitp<bits<9> opc, dag outs, dag ins, string asmstr, 90249423Sdim list<dag> pattern> 91249423Sdim : _FL2RUS<opc, outs, ins, asmstr, pattern> { 92249423Sdim let DecoderMethod = "DecodeL2RUSBitpInstruction"; 93193323Sed} 94193323Sed 95249423Sdimclass _FRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 96249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 97249423Sdim bits<4> a; 98249423Sdim bits<6> b; 99249423Sdim 100249423Sdim let Inst{15-10} = opc; 101249423Sdim let Inst{9-6} = a; 102249423Sdim let Inst{5-0} = b; 103193323Sed} 104193323Sed 105249423Sdimclass _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 106249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 107249423Sdim bits<4> a; 108249423Sdim bits<16> b; 109249423Sdim 110249423Sdim let Inst{31-26} = opc; 111249423Sdim let Inst{25-22} = a; 112249423Sdim let Inst{21-16} = b{5-0}; 113249423Sdim let Inst{15-10} = 0b111100; 114249423Sdim let Inst{9-0} = b{15-6}; 115193323Sed} 116193323Sed 117249423Sdimclass _FU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 118249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 119249423Sdim bits<6> a; 120249423Sdim 121249423Sdim let Inst{15-6} = opc; 122249423Sdim let Inst{5-0} = a; 123193323Sed} 124193323Sed 125249423Sdimclass _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 126249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 127249423Sdim bits<16> a; 128249423Sdim 129249423Sdim let Inst{31-22} = opc; 130249423Sdim let Inst{21-16} = a{5-0}; 131249423Sdim let Inst{15-10} = 0b111100; 132249423Sdim let Inst{9-0} = a{15-6}; 133193323Sed} 134193323Sed 135249423Sdimclass _FU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 136249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 137249423Sdim bits<10> a; 138249423Sdim 139249423Sdim let Inst{15-10} = opc; 140249423Sdim let Inst{9-0} = a; 141193323Sed} 142193323Sed 143249423Sdimclass _FLU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 144249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 145249423Sdim bits<20> a; 146249423Sdim 147249423Sdim let Inst{31-26} = opc; 148249423Sdim let Inst{25-16} = a{9-0}; 149249423Sdim let Inst{15-10} = 0b111100; 150249423Sdim let Inst{9-0} = a{19-10}; 151193323Sed} 152193323Sed 153249423Sdimclass _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 154249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 155249423Sdim let Inst{15-11} = opc{5-1}; 156249423Sdim let Inst{4} = opc{0}; 157249423Sdim let DecoderMethod = "Decode2RInstruction"; 158193323Sed} 159193323Sed 160249423Sdim// 2R with first operand as an immediate. Used for TSETMR where the first 161249423Sdim// operand is treated as an immediate since it refers to a register number in 162249423Sdim// another thread. 163249423Sdimclass _F2RImm<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 164249423Sdim : _F2R<opc, outs, ins, asmstr, pattern> { 165249423Sdim let DecoderMethod = "Decode2RImmInstruction"; 166193323Sed} 167193323Sed 168249423Sdim// 2R with first operand as both a source and a destination. 169249423Sdimclass _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr, 170249423Sdim list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> { 171249423Sdim let DecoderMethod = "Decode2RSrcDstInstruction"; 172193323Sed} 173193323Sed 174249423Sdim// Same as 2R with last two operands swapped 175249423Sdimclass _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 176249423Sdim : _F2R<opc, outs, ins, asmstr, pattern> { 177249423Sdim let DecoderMethod = "DecodeR2RInstruction"; 178193323Sed} 179249423Sdim 180249423Sdimclass _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 181249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 182249423Sdim let Inst{15-11} = opc{5-1}; 183249423Sdim let Inst{4} = opc{0}; 184249423Sdim let DecoderMethod = "DecodeRUSInstruction"; 185249423Sdim} 186249423Sdim 187249423Sdim// RUS with bitp operand 188249423Sdimclass _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr, 189249423Sdim list<dag> pattern> 190249423Sdim : _FRUS<opc, outs, ins, asmstr, pattern> { 191249423Sdim let DecoderMethod = "DecodeRUSBitpInstruction"; 192249423Sdim} 193249423Sdim 194249423Sdim// RUS with first operand as both a source and a destination and a bitp second 195249423Sdim// operand 196249423Sdimclass _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr, 197249423Sdim list<dag> pattern> 198249423Sdim : _FRUS<opc, outs, ins, asmstr, pattern> { 199249423Sdim let DecoderMethod = "DecodeRUSSrcDstBitpInstruction"; 200249423Sdim} 201249423Sdim 202249423Sdimclass _FL2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 203249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 204249423Sdim let Inst{31-27} = opc{9-5}; 205249423Sdim let Inst{26-20} = 0b1111110; 206249423Sdim let Inst{19-16} = opc{4-1}; 207249423Sdim 208249423Sdim let Inst{15-11} = 0b11111; 209249423Sdim let Inst{4} = opc{0}; 210249423Sdim let DecoderMethod = "DecodeL2RInstruction"; 211249423Sdim} 212249423Sdim 213249423Sdim// Same as L2R with last two operands swapped 214249423Sdimclass _FLR2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 215249423Sdim : _FL2R<opc, outs, ins, asmstr, pattern> { 216249423Sdim let DecoderMethod = "DecodeLR2RInstruction"; 217249423Sdim} 218249423Sdim 219249423Sdimclass _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 220249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 221249423Sdim bits<4> a; 222249423Sdim 223249423Sdim let Inst{15-11} = opc{5-1}; 224249423Sdim let Inst{10-5} = 0b111111; 225249423Sdim let Inst{4} = opc{0}; 226249423Sdim let Inst{3-0} = a; 227249423Sdim} 228249423Sdim 229249423Sdimclass _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 230249423Sdim : InstXCore<2, outs, ins, asmstr, pattern> { 231249423Sdim let Inst{15-11} = opc{9-5}; 232249423Sdim let Inst{10-5} = 0b111111; 233249423Sdim let Inst{4-0} = opc{4-0}; 234249423Sdim} 235249423Sdim 236249423Sdimclass _FL4R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 237249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 238249423Sdim bits<4> d; 239249423Sdim 240249423Sdim let Inst{31-27} = opc{5-1}; 241249423Sdim let Inst{26-21} = 0b111111; 242249423Sdim let Inst{20} = opc{0}; 243249423Sdim let Inst{19-16} = d; 244249423Sdim let Inst{15-11} = 0b11111; 245249423Sdim} 246249423Sdim 247249423Sdim// L4R with 4th operand as both a source and a destination. 248249423Sdimclass _FL4RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr, 249249423Sdim list<dag> pattern> 250249423Sdim : _FL4R<opc, outs, ins, asmstr, pattern> { 251249423Sdim let DecoderMethod = "DecodeL4RSrcDstInstruction"; 252249423Sdim} 253249423Sdim 254249423Sdim// L4R with 1st and 4th operand as both a source and a destination. 255249423Sdimclass _FL4RSrcDstSrcDst<bits<6> opc, dag outs, dag ins, string asmstr, 256249423Sdim list<dag> pattern> 257249423Sdim : _FL4R<opc, outs, ins, asmstr, pattern> { 258249423Sdim let DecoderMethod = "DecodeL4RSrcDstSrcDstInstruction"; 259249423Sdim} 260249423Sdim 261249423Sdimclass _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 262249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 263249423Sdim let Inst{31-27} = opc{5-1}; 264249423Sdim let Inst{20} = opc{0}; 265249423Sdim let Inst{15-11} = 0b11111; 266249423Sdim 267249423Sdim let DecoderMethod = "DecodeL5RInstruction"; 268249423Sdim} 269249423Sdim 270249423Sdimclass _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> 271249423Sdim : InstXCore<4, outs, ins, asmstr, pattern> { 272249423Sdim let Inst{31-27} = opc; 273249423Sdim let Inst{15-11} = 0b11111; 274249423Sdim 275249423Sdim let DecoderMethod = "DecodeL6RInstruction"; 276249423Sdim} 277