X86Subtarget.h revision 327952 
1//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15#define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16
17#include "X86FrameLowering.h"
18#include "X86ISelLowering.h"
19#include "X86InstrInfo.h"
20#include "X86SelectionDAGInfo.h"
21#include "llvm/ADT/StringRef.h"
22#include "llvm/ADT/Triple.h"
23#include "llvm/CodeGen/GlobalISel/CallLowering.h"
24#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
25#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
27#include "llvm/CodeGen/TargetSubtargetInfo.h"
28#include "llvm/IR/CallingConv.h"
29#include "llvm/MC/MCInstrItineraries.h"
30#include "llvm/Target/TargetMachine.h"
31#include <memory>
32
33#define GET_SUBTARGETINFO_HEADER
34#include "X86GenSubtargetInfo.inc"
35
36namespace llvm {
37
38class GlobalValue;
39
40/// The X86 backend supports a number of different styles of PIC.
41///
42namespace PICStyles {
43
44enum Style {
45  StubPIC,          // Used on i386-darwin in pic mode.
46  GOT,              // Used on 32 bit elf on when in pic mode.
47  RIPRel,           // Used on X86-64 when in pic mode.
48  None              // Set when not in pic mode.
49};
50
51} // end namespace PICStyles
52
53class X86Subtarget final : public X86GenSubtargetInfo {
54public:
55  enum X86ProcFamilyEnum {
56    Others,
57    IntelAtom,
58    IntelSLM,
59    IntelGLM,
60    IntelHaswell,
61    IntelBroadwell,
62    IntelSkylake,
63    IntelKNL,
64    IntelSKX,
65    IntelCannonlake,
66    IntelIcelake,
67  };
68
69protected:
70  enum X86SSEEnum {
71    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
72  };
73
74  enum X863DNowEnum {
75    NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
76  };
77
78  /// X86 processor family: Intel Atom, and others
79  X86ProcFamilyEnum X86ProcFamily;
80
81  /// Which PIC style to use
82  PICStyles::Style PICStyle;
83
84  const TargetMachine &TM;
85
86  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
87  X86SSEEnum X86SSELevel;
88
89  /// MMX, 3DNow, 3DNow Athlon, or none supported.
90  X863DNowEnum X863DNowLevel;
91
92  /// True if the processor supports X87 instructions.
93  bool HasX87;
94
95  /// True if this processor has conditional move instructions
96  /// (generally pentium pro+).
97  bool HasCMov;
98
99  /// True if the processor supports X86-64 instructions.
100  bool HasX86_64;
101
102  /// True if the processor supports POPCNT.
103  bool HasPOPCNT;
104
105  /// True if the processor supports SSE4A instructions.
106  bool HasSSE4A;
107
108  /// Target has AES instructions
109  bool HasAES;
110  bool HasVAES;
111
112  /// Target has FXSAVE/FXRESTOR instructions
113  bool HasFXSR;
114
115  /// Target has XSAVE instructions
116  bool HasXSAVE;
117
118  /// Target has XSAVEOPT instructions
119  bool HasXSAVEOPT;
120
121  /// Target has XSAVEC instructions
122  bool HasXSAVEC;
123
124  /// Target has XSAVES instructions
125  bool HasXSAVES;
126
127  /// Target has carry-less multiplication
128  bool HasPCLMUL;
129  bool HasVPCLMULQDQ;
130
131  /// Target has Galois Field Arithmetic instructions
132  bool HasGFNI;
133
134  /// Target has 3-operand fused multiply-add
135  bool HasFMA;
136
137  /// Target has 4-operand fused multiply-add
138  bool HasFMA4;
139
140  /// Target has XOP instructions
141  bool HasXOP;
142
143  /// Target has TBM instructions.
144  bool HasTBM;
145
146  /// Target has LWP instructions
147  bool HasLWP;
148
149  /// True if the processor has the MOVBE instruction.
150  bool HasMOVBE;
151
152  /// True if the processor has the RDRAND instruction.
153  bool HasRDRAND;
154
155  /// Processor has 16-bit floating point conversion instructions.
156  bool HasF16C;
157
158  /// Processor has FS/GS base insturctions.
159  bool HasFSGSBase;
160
161  /// Processor has LZCNT instruction.
162  bool HasLZCNT;
163
164  /// Processor has BMI1 instructions.
165  bool HasBMI;
166
167  /// Processor has BMI2 instructions.
168  bool HasBMI2;
169
170  /// Processor has VBMI instructions.
171  bool HasVBMI;
172
173  /// Processor has VBMI2 instructions.
174  bool HasVBMI2;
175
176  /// Processor has Integer Fused Multiply Add
177  bool HasIFMA;
178
179  /// Processor has RTM instructions.
180  bool HasRTM;
181
182  /// Processor has ADX instructions.
183  bool HasADX;
184
185  /// Processor has SHA instructions.
186  bool HasSHA;
187
188  /// Processor has PRFCHW instructions.
189  bool HasPRFCHW;
190
191  /// Processor has RDSEED instructions.
192  bool HasRDSEED;
193
194  /// Processor has LAHF/SAHF instructions.
195  bool HasLAHFSAHF;
196
197  /// Processor has MONITORX/MWAITX instructions.
198  bool HasMWAITX;
199
200  /// Processor has Cache Line Zero instruction
201  bool HasCLZERO;
202
203  /// Processor has Prefetch with intent to Write instruction
204  bool HasPREFETCHWT1;
205
206  /// True if SHLD instructions are slow.
207  bool IsSHLDSlow;
208
209  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
210  //  PMULUDQ.
211  bool IsPMULLDSlow;
212
213  /// True if unaligned memory accesses of 16-bytes are slow.
214  bool IsUAMem16Slow;
215
216  /// True if unaligned memory accesses of 32-bytes are slow.
217  bool IsUAMem32Slow;
218
219  /// True if SSE operations can have unaligned memory operands.
220  /// This may require setting a configuration bit in the processor.
221  bool HasSSEUnalignedMem;
222
223  /// True if this processor has the CMPXCHG16B instruction;
224  /// this is true for most x86-64 chips, but not the first AMD chips.
225  bool HasCmpxchg16b;
226
227  /// True if the LEA instruction should be used for adjusting
228  /// the stack pointer. This is an optimization for Intel Atom processors.
229  bool UseLeaForSP;
230
231  /// True if its preferable to combine to a single shuffle using a variable
232  /// mask over multiple fixed shuffles.
233  bool HasFastVariableShuffle;
234
235  /// True if there is no performance penalty to writing only the lower parts
236  /// of a YMM or ZMM register without clearing the upper part.
237  bool HasFastPartialYMMorZMMWrite;
238
239  /// True if gather is reasonably fast. This is true for Skylake client and
240  /// all AVX-512 CPUs.
241  bool HasFastGather;
242
243  /// True if hardware SQRTSS instruction is at least as fast (latency) as
244  /// RSQRTSS followed by a Newton-Raphson iteration.
245  bool HasFastScalarFSQRT;
246
247  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
248  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
249  bool HasFastVectorFSQRT;
250
251  /// True if 8-bit divisions are significantly faster than
252  /// 32-bit divisions and should be used when possible.
253  bool HasSlowDivide32;
254
255  /// True if 32-bit divides are significantly faster than
256  /// 64-bit divisions and should be used when possible.
257  bool HasSlowDivide64;
258
259  /// True if LZCNT instruction is fast.
260  bool HasFastLZCNT;
261
262  /// True if SHLD based rotate is fast.
263  bool HasFastSHLDRotate;
264
265  /// True if the processor supports macrofusion.
266  bool HasMacroFusion;
267
268  /// True if the processor has enhanced REP MOVSB/STOSB.
269  bool HasERMSB;
270
271  /// True if the short functions should be padded to prevent
272  /// a stall when returning too early.
273  bool PadShortFunctions;
274
275  /// True if two memory operand instructions should use a temporary register
276  /// instead.
277  bool SlowTwoMemOps;
278
279  /// True if the LEA instruction inputs have to be ready at address generation
280  /// (AG) time.
281  bool LEAUsesAG;
282
283  /// True if the LEA instruction with certain arguments is slow
284  bool SlowLEA;
285
286  /// True if the LEA instruction has all three source operands: base, index,
287  /// and offset or if the LEA instruction uses base and index registers where
288  /// the base is EBP, RBP,or R13
289  bool Slow3OpsLEA;
290
291  /// True if INC and DEC instructions are slow when writing to flags
292  bool SlowIncDec;
293
294  /// Processor has AVX-512 PreFetch Instructions
295  bool HasPFI;
296
297  /// Processor has AVX-512 Exponential and Reciprocal Instructions
298  bool HasERI;
299
300  /// Processor has AVX-512 Conflict Detection Instructions
301  bool HasCDI;
302
303  /// Processor has AVX-512 population count Instructions
304  bool HasVPOPCNTDQ;
305
306  /// Processor has AVX-512 Doubleword and Quadword instructions
307  bool HasDQI;
308
309  /// Processor has AVX-512 Byte and Word instructions
310  bool HasBWI;
311
312  /// Processor has AVX-512 Vector Length eXtenstions
313  bool HasVLX;
314
315  /// Processor has PKU extenstions
316  bool HasPKU;
317
318  /// Processor has AVX-512 Vector Neural Network Instructions
319  bool HasVNNI;
320
321  /// Processor has AVX-512 Bit Algorithms instructions
322  bool HasBITALG;
323
324  /// Processor supports MPX - Memory Protection Extensions
325  bool HasMPX;
326
327  /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
328  /// using Shadow Stack
329  bool HasSHSTK;
330
331  /// Processor supports CET IBT - Control-Flow Enforcement Technology
332  /// using Indirect Branch Tracking
333  bool HasIBT;
334
335  /// Processor has Software Guard Extensions
336  bool HasSGX;
337
338  /// Processor supports Flush Cache Line instruction
339  bool HasCLFLUSHOPT;
340
341  /// Processor supports Cache Line Write Back instruction
342  bool HasCLWB;
343
344  /// Use software floating point for code generation.
345  bool UseSoftFloat;
346
347  /// The minimum alignment known to hold of the stack frame on
348  /// entry to the function and which must be maintained by every function.
349  unsigned stackAlignment;
350
351  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
352  ///
353  unsigned MaxInlineSizeThreshold;
354
355  /// What processor and OS we're targeting.
356  Triple TargetTriple;
357
358  /// Instruction itineraries for scheduling
359  InstrItineraryData InstrItins;
360
361  /// GlobalISel related APIs.
362  std::unique_ptr<CallLowering> CallLoweringInfo;
363  std::unique_ptr<LegalizerInfo> Legalizer;
364  std::unique_ptr<RegisterBankInfo> RegBankInfo;
365  std::unique_ptr<InstructionSelector> InstSelector;
366
367private:
368  /// Override the stack alignment.
369  unsigned StackAlignOverride;
370
371  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
372  bool In64BitMode;
373
374  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
375  bool In32BitMode;
376
377  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
378  bool In16BitMode;
379
380  /// Contains the Overhead of gather\scatter instructions
381  int GatherOverhead;
382  int ScatterOverhead;
383
384  X86SelectionDAGInfo TSInfo;
385  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
386  // X86TargetLowering needs.
387  X86InstrInfo InstrInfo;
388  X86TargetLowering TLInfo;
389  X86FrameLowering FrameLowering;
390
391public:
392  /// This constructor initializes the data members to match that
393  /// of the specified triple.
394  ///
395  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
396               const X86TargetMachine &TM, unsigned StackAlignOverride);
397
398  const X86TargetLowering *getTargetLowering() const override {
399    return &TLInfo;
400  }
401
402  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
403
404  const X86FrameLowering *getFrameLowering() const override {
405    return &FrameLowering;
406  }
407
408  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
409    return &TSInfo;
410  }
411
412  const X86RegisterInfo *getRegisterInfo() const override {
413    return &getInstrInfo()->getRegisterInfo();
414  }
415
416  /// Returns the minimum alignment known to hold of the
417  /// stack frame on entry to the function and which must be maintained by every
418  /// function for this subtarget.
419  unsigned getStackAlignment() const { return stackAlignment; }
420
421  /// Returns the maximum memset / memcpy size
422  /// that still makes it profitable to inline the call.
423  unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
424
425  /// ParseSubtargetFeatures - Parses features string setting specified
426  /// subtarget options.  Definition of function is auto generated by tblgen.
427  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
428
429  /// Methods used by Global ISel
430  const CallLowering *getCallLowering() const override;
431  const InstructionSelector *getInstructionSelector() const override;
432  const LegalizerInfo *getLegalizerInfo() const override;
433  const RegisterBankInfo *getRegBankInfo() const override;
434
435private:
436  /// Initialize the full set of dependencies so we can use an initializer
437  /// list for X86Subtarget.
438  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
439  void initializeEnvironment();
440  void initSubtargetFeatures(StringRef CPU, StringRef FS);
441
442public:
443  /// Is this x86_64? (disregarding specific ABI / programming model)
444  bool is64Bit() const {
445    return In64BitMode;
446  }
447
448  bool is32Bit() const {
449    return In32BitMode;
450  }
451
452  bool is16Bit() const {
453    return In16BitMode;
454  }
455
456  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
457  bool isTarget64BitILP32() const {
458    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
459                           TargetTriple.isOSNaCl());
460  }
461
462  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
463  bool isTarget64BitLP64() const {
464    return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
465                           !TargetTriple.isOSNaCl());
466  }
467
468  PICStyles::Style getPICStyle() const { return PICStyle; }
469  void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
470
471  bool hasX87() const { return HasX87; }
472  bool hasCMov() const { return HasCMov; }
473  bool hasSSE1() const { return X86SSELevel >= SSE1; }
474  bool hasSSE2() const { return X86SSELevel >= SSE2; }
475  bool hasSSE3() const { return X86SSELevel >= SSE3; }
476  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
477  bool hasSSE41() const { return X86SSELevel >= SSE41; }
478  bool hasSSE42() const { return X86SSELevel >= SSE42; }
479  bool hasAVX() const { return X86SSELevel >= AVX; }
480  bool hasAVX2() const { return X86SSELevel >= AVX2; }
481  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
482  bool hasFp256() const { return hasAVX(); }
483  bool hasInt256() const { return hasAVX2(); }
484  bool hasSSE4A() const { return HasSSE4A; }
485  bool hasMMX() const { return X863DNowLevel >= MMX; }
486  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
487  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
488  bool hasPOPCNT() const { return HasPOPCNT; }
489  bool hasAES() const { return HasAES; }
490  bool hasVAES() const { return HasVAES; }
491  bool hasFXSR() const { return HasFXSR; }
492  bool hasXSAVE() const { return HasXSAVE; }
493  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
494  bool hasXSAVEC() const { return HasXSAVEC; }
495  bool hasXSAVES() const { return HasXSAVES; }
496  bool hasPCLMUL() const { return HasPCLMUL; }
497  bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
498  bool hasGFNI() const { return HasGFNI; }
499  // Prefer FMA4 to FMA - its better for commutation/memory folding and
500  // has equal or better performance on all supported targets.
501  bool hasFMA() const { return HasFMA; }
502  bool hasFMA4() const { return HasFMA4; }
503  bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
504  bool hasXOP() const { return HasXOP; }
505  bool hasTBM() const { return HasTBM; }
506  bool hasLWP() const { return HasLWP; }
507  bool hasMOVBE() const { return HasMOVBE; }
508  bool hasRDRAND() const { return HasRDRAND; }
509  bool hasF16C() const { return HasF16C; }
510  bool hasFSGSBase() const { return HasFSGSBase; }
511  bool hasLZCNT() const { return HasLZCNT; }
512  bool hasBMI() const { return HasBMI; }
513  bool hasBMI2() const { return HasBMI2; }
514  bool hasVBMI() const { return HasVBMI; }
515  bool hasVBMI2() const { return HasVBMI2; }
516  bool hasIFMA() const { return HasIFMA; }
517  bool hasRTM() const { return HasRTM; }
518  bool hasADX() const { return HasADX; }
519  bool hasSHA() const { return HasSHA; }
520  bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
521  bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
522  bool hasSSEPrefetch() const {
523    // We implicitly enable these when we have a write prefix supporting cache
524    // level OR if we have prfchw, but don't already have a read prefetch from
525    // 3dnow.
526    return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
527  }
528  bool hasRDSEED() const { return HasRDSEED; }
529  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
530  bool hasMWAITX() const { return HasMWAITX; }
531  bool hasCLZERO() const { return HasCLZERO; }
532  bool isSHLDSlow() const { return IsSHLDSlow; }
533  bool isPMULLDSlow() const { return IsPMULLDSlow; }
534  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
535  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
536  int getGatherOverhead() const { return GatherOverhead; }
537  int getScatterOverhead() const { return ScatterOverhead; }
538  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
539  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
540  bool useLeaForSP() const { return UseLeaForSP; }
541  bool hasFastVariableShuffle() const {
542    return HasFastVariableShuffle;
543  }
544  bool hasFastPartialYMMorZMMWrite() const {
545    return HasFastPartialYMMorZMMWrite;
546  }
547  bool hasFastGather() const { return HasFastGather; }
548  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
549  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
550  bool hasFastLZCNT() const { return HasFastLZCNT; }
551  bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
552  bool hasMacroFusion() const { return HasMacroFusion; }
553  bool hasERMSB() const { return HasERMSB; }
554  bool hasSlowDivide32() const { return HasSlowDivide32; }
555  bool hasSlowDivide64() const { return HasSlowDivide64; }
556  bool padShortFunctions() const { return PadShortFunctions; }
557  bool slowTwoMemOps() const { return SlowTwoMemOps; }
558  bool LEAusesAG() const { return LEAUsesAG; }
559  bool slowLEA() const { return SlowLEA; }
560  bool slow3OpsLEA() const { return Slow3OpsLEA; }
561  bool slowIncDec() const { return SlowIncDec; }
562  bool hasCDI() const { return HasCDI; }
563  bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
564  bool hasPFI() const { return HasPFI; }
565  bool hasERI() const { return HasERI; }
566  bool hasDQI() const { return HasDQI; }
567  bool hasBWI() const { return HasBWI; }
568  bool hasVLX() const { return HasVLX; }
569  bool hasPKU() const { return HasPKU; }
570  bool hasVNNI() const { return HasVNNI; }
571  bool hasBITALG() const { return HasBITALG; }
572  bool hasMPX() const { return HasMPX; }
573  bool hasSHSTK() const { return HasSHSTK; }
574  bool hasIBT() const { return HasIBT; }
575  bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
576  bool hasCLWB() const { return HasCLWB; }
577
578  bool isXRaySupported() const override { return is64Bit(); }
579
580  X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
581
582  /// TODO: to be removed later and replaced with suitable properties
583  bool isAtom() const { return X86ProcFamily == IntelAtom; }
584  bool isSLM() const { return X86ProcFamily == IntelSLM; }
585  bool useSoftFloat() const { return UseSoftFloat; }
586
587  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
588  /// no-sse2). There isn't any reason to disable it if the target processor
589  /// supports it.
590  bool hasMFence() const { return hasSSE2() || is64Bit(); }
591
592  const Triple &getTargetTriple() const { return TargetTriple; }
593
594  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
595  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
596  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
597  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
598  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
599
600  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
601  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
602  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
603
604  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
605  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
606  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
607  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
608  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
609  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
610  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
611  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
612  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
613
614  bool isTargetWindowsMSVC() const {
615    return TargetTriple.isWindowsMSVCEnvironment();
616  }
617
618  bool isTargetKnownWindowsMSVC() const {
619    return TargetTriple.isKnownWindowsMSVCEnvironment();
620  }
621
622  bool isTargetWindowsCoreCLR() const {
623    return TargetTriple.isWindowsCoreCLREnvironment();
624  }
625
626  bool isTargetWindowsCygwin() const {
627    return TargetTriple.isWindowsCygwinEnvironment();
628  }
629
630  bool isTargetWindowsGNU() const {
631    return TargetTriple.isWindowsGNUEnvironment();
632  }
633
634  bool isTargetWindowsItanium() const {
635    return TargetTriple.isWindowsItaniumEnvironment();
636  }
637
638  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
639
640  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
641
642  bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
643
644  bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
645
646  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
647  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
648
649  bool isPICStyleStubPIC() const {
650    return PICStyle == PICStyles::StubPIC;
651  }
652
653  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
654
655  bool isCallingConvWin64(CallingConv::ID CC) const {
656    switch (CC) {
657    // On Win64, all these conventions just use the default convention.
658    case CallingConv::C:
659    case CallingConv::Fast:
660    case CallingConv::Swift:
661    case CallingConv::X86_FastCall:
662    case CallingConv::X86_StdCall:
663    case CallingConv::X86_ThisCall:
664    case CallingConv::X86_VectorCall:
665    case CallingConv::Intel_OCL_BI:
666      return isTargetWin64();
667    // This convention allows using the Win64 convention on other targets.
668    case CallingConv::Win64:
669      return true;
670    // This convention allows using the SysV convention on Windows targets.
671    case CallingConv::X86_64_SysV:
672      return false;
673    // Otherwise, who knows what this is.
674    default:
675      return false;
676    }
677  }
678
679  /// Classify a global variable reference for the current subtarget according
680  /// to how we should reference it in a non-pcrel context.
681  unsigned char classifyLocalReference(const GlobalValue *GV) const;
682
683  unsigned char classifyGlobalReference(const GlobalValue *GV,
684                                        const Module &M) const;
685  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
686
687  /// Classify a global function reference for the current subtarget.
688  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
689                                                const Module &M) const;
690  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
691
692  /// Classify a blockaddress reference for the current subtarget according to
693  /// how we should reference it in a non-pcrel context.
694  unsigned char classifyBlockAddressReference() const;
695
696  /// Return true if the subtarget allows calls to immediate address.
697  bool isLegalToCallImmediateAddr() const;
698
699  /// Enable the MachineScheduler pass for all X86 subtargets.
700  bool enableMachineScheduler() const override { return true; }
701
702  // TODO: Update the regression tests and return true.
703  bool supportPrintSchedInfo() const override { return false; }
704
705  bool enableEarlyIfConversion() const override;
706
707  /// Return the instruction itineraries based on the subtarget selection.
708  const InstrItineraryData *getInstrItineraryData() const override {
709    return &InstrItins;
710  }
711
712  AntiDepBreakMode getAntiDepBreakMode() const override {
713    return TargetSubtargetInfo::ANTIDEP_CRITICAL;
714  }
715
716  bool enableAdvancedRASplitCost() const override { return true; }
717};
718
719} // end namespace llvm
720
721#endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
722