X86Subtarget.h revision 234353
1234353Sdim//===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10224145Sdim// This file declares the X86 specific subclass of TargetSubtargetInfo. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#ifndef X86SUBTARGET_H 15193323Sed#define X86SUBTARGET_H 16193323Sed 17234353Sdim#include "llvm/CallingConv.h" 18210299Sed#include "llvm/ADT/Triple.h" 19224145Sdim#include "llvm/Target/TargetSubtargetInfo.h" 20193323Sed#include <string> 21193323Sed 22224145Sdim#define GET_SUBTARGETINFO_HEADER 23224145Sdim#include "X86GenSubtargetInfo.inc" 24224145Sdim 25193323Sednamespace llvm { 26193323Sedclass GlobalValue; 27224145Sdimclass StringRef; 28193323Sedclass TargetMachine; 29204642Srdivacky 30198090Srdivacky/// PICStyles - The X86 backend supports a number of different styles of PIC. 31204642Srdivacky/// 32193323Sednamespace PICStyles { 33193323Sedenum Style { 34198090Srdivacky StubPIC, // Used on i386-darwin in -fPIC mode. 35198090Srdivacky StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode. 36198090Srdivacky GOT, // Used on many 32-bit unices in -fPIC mode. 37198090Srdivacky RIPRel, // Used on X86-64 when not in -static mode. 38198090Srdivacky None // Set when in -static mode (not PIC or DynamicNoPIC mode). 39193323Sed}; 40193323Sed} 41193323Sed 42224145Sdimclass X86Subtarget : public X86GenSubtargetInfo { 43193323Sedprotected: 44193323Sed enum X86SSEEnum { 45234353Sdim NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 46193323Sed }; 47193323Sed 48193323Sed enum X863DNowEnum { 49193323Sed NoThreeDNow, ThreeDNow, ThreeDNowA 50193323Sed }; 51193323Sed 52234353Sdim enum X86ProcFamilyEnum { 53234353Sdim Others, IntelAtom 54234353Sdim }; 55234353Sdim 56234353Sdim /// X86ProcFamily - X86 processor family: Intel Atom, and others 57234353Sdim X86ProcFamilyEnum X86ProcFamily; 58234353Sdim 59193323Sed /// PICStyle - Which PIC style to use 60193323Sed /// 61193323Sed PICStyles::Style PICStyle; 62204642Srdivacky 63193323Sed /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or 64193323Sed /// none supported. 65193323Sed X86SSEEnum X86SSELevel; 66193323Sed 67193323Sed /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported. 68193323Sed /// 69193323Sed X863DNowEnum X863DNowLevel; 70193323Sed 71198090Srdivacky /// HasCMov - True if this processor has conditional move instructions 72198090Srdivacky /// (generally pentium pro+). 73198090Srdivacky bool HasCMov; 74204642Srdivacky 75193323Sed /// HasX86_64 - True if the processor supports X86-64 instructions. 76193323Sed /// 77193323Sed bool HasX86_64; 78193323Sed 79218893Sdim /// HasPOPCNT - True if the processor supports POPCNT. 80218893Sdim bool HasPOPCNT; 81218893Sdim 82195098Sed /// HasSSE4A - True if the processor supports SSE4A instructions. 83195098Sed bool HasSSE4A; 84195098Sed 85206124Srdivacky /// HasAES - Target has AES instructions 86206124Srdivacky bool HasAES; 87206124Srdivacky 88212904Sdim /// HasCLMUL - Target has carry-less multiplication 89212904Sdim bool HasCLMUL; 90212904Sdim 91195098Sed /// HasFMA3 - Target has 3-operand fused multiply-add 92195098Sed bool HasFMA3; 93195098Sed 94195098Sed /// HasFMA4 - Target has 4-operand fused multiply-add 95195098Sed bool HasFMA4; 96195098Sed 97234353Sdim /// HasXOP - Target has XOP instructions 98234353Sdim bool HasXOP; 99234353Sdim 100226633Sdim /// HasMOVBE - True if the processor has the MOVBE instruction. 101226633Sdim bool HasMOVBE; 102226633Sdim 103226633Sdim /// HasRDRAND - True if the processor has the RDRAND instruction. 104226633Sdim bool HasRDRAND; 105226633Sdim 106226633Sdim /// HasF16C - Processor has 16-bit floating point conversion instructions. 107226633Sdim bool HasF16C; 108226633Sdim 109234353Sdim /// HasFSGSBase - Processor has FS/GS base insturctions. 110234353Sdim bool HasFSGSBase; 111234353Sdim 112226633Sdim /// HasLZCNT - Processor has LZCNT instruction. 113226633Sdim bool HasLZCNT; 114226633Sdim 115226633Sdim /// HasBMI - Processor has BMI1 instructions. 116226633Sdim bool HasBMI; 117226633Sdim 118234353Sdim /// HasBMI2 - Processor has BMI2 instructions. 119234353Sdim bool HasBMI2; 120234353Sdim 121193323Sed /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. 122193323Sed bool IsBTMemSlow; 123201360Srdivacky 124206083Srdivacky /// IsUAMemFast - True if unaligned memory access is fast. 125206083Srdivacky bool IsUAMemFast; 126206083Srdivacky 127204642Srdivacky /// HasVectorUAMem - True if SIMD operations can have unaligned memory 128207618Srdivacky /// operands. This may require setting a feature bit in the processor. 129202375Srdivacky bool HasVectorUAMem; 130202375Srdivacky 131226633Sdim /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction; 132226633Sdim /// this is true for most x86-64 chips, but not the first AMD chips. 133226633Sdim bool HasCmpxchg16b; 134226633Sdim 135234353Sdim /// UseLeaForSP - True if the LEA instruction should be used for adjusting 136234353Sdim /// the stack pointer. This is an optimization for Intel Atom processors. 137234353Sdim bool UseLeaForSP; 138234353Sdim 139234353Sdim /// PostRAScheduler - True if using post-register-allocation scheduler. 140234353Sdim bool PostRAScheduler; 141234353Sdim 142193323Sed /// stackAlignment - The minimum alignment known to hold of the stack frame on 143193323Sed /// entry to the function and which must be maintained by every function. 144193323Sed unsigned stackAlignment; 145193323Sed 146193323Sed /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 147193323Sed /// 148193323Sed unsigned MaxInlineSizeThreshold; 149218893Sdim 150210299Sed /// TargetTriple - What processor and OS we're targeting. 151210299Sed Triple TargetTriple; 152234353Sdim 153234353Sdim /// Instruction itineraries for scheduling 154234353Sdim InstrItineraryData InstrItins; 155193323Sed 156193323Sedprivate: 157224145Sdim /// In64BitMode - True if compiling for 64-bit, false for 32-bit. 158224145Sdim bool In64BitMode; 159193323Sed 160193323Sedpublic: 161193323Sed 162193323Sed /// This constructor initializes the data members to match that 163198090Srdivacky /// of the specified triple. 164193323Sed /// 165224145Sdim X86Subtarget(const std::string &TT, const std::string &CPU, 166224145Sdim const std::string &FS, 167224145Sdim unsigned StackAlignOverride, bool is64Bit); 168193323Sed 169193323Sed /// getStackAlignment - Returns the minimum alignment known to hold of the 170193323Sed /// stack frame on entry to the function and which must be maintained by every 171193323Sed /// function for this subtarget. 172193323Sed unsigned getStackAlignment() const { return stackAlignment; } 173193323Sed 174193323Sed /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 175193323Sed /// that still makes it profitable to inline the call. 176193323Sed unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 177193323Sed 178193323Sed /// ParseSubtargetFeatures - Parses features string setting specified 179193323Sed /// subtarget options. Definition of function is auto generated by tblgen. 180224145Sdim void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 181193323Sed 182193323Sed /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID 183193323Sed /// instruction. 184193323Sed void AutoDetectSubtargetFeatures(); 185193323Sed 186224145Sdim bool is64Bit() const { return In64BitMode; } 187193323Sed 188193323Sed PICStyles::Style getPICStyle() const { return PICStyle; } 189193323Sed void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 190193323Sed 191205218Srdivacky bool hasCMov() const { return HasCMov; } 192193323Sed bool hasMMX() const { return X86SSELevel >= MMX; } 193193323Sed bool hasSSE1() const { return X86SSELevel >= SSE1; } 194193323Sed bool hasSSE2() const { return X86SSELevel >= SSE2; } 195193323Sed bool hasSSE3() const { return X86SSELevel >= SSE3; } 196193323Sed bool hasSSSE3() const { return X86SSELevel >= SSSE3; } 197193323Sed bool hasSSE41() const { return X86SSELevel >= SSE41; } 198193323Sed bool hasSSE42() const { return X86SSELevel >= SSE42; } 199234353Sdim bool hasAVX() const { return X86SSELevel >= AVX; } 200234353Sdim bool hasAVX2() const { return X86SSELevel >= AVX2; } 201193323Sed bool hasSSE4A() const { return HasSSE4A; } 202193323Sed bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } 203193323Sed bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } 204218893Sdim bool hasPOPCNT() const { return HasPOPCNT; } 205206124Srdivacky bool hasAES() const { return HasAES; } 206212904Sdim bool hasCLMUL() const { return HasCLMUL; } 207195098Sed bool hasFMA3() const { return HasFMA3; } 208195098Sed bool hasFMA4() const { return HasFMA4; } 209234353Sdim bool hasXOP() const { return HasXOP; } 210226633Sdim bool hasMOVBE() const { return HasMOVBE; } 211226633Sdim bool hasRDRAND() const { return HasRDRAND; } 212226633Sdim bool hasF16C() const { return HasF16C; } 213234353Sdim bool hasFSGSBase() const { return HasFSGSBase; } 214226633Sdim bool hasLZCNT() const { return HasLZCNT; } 215226633Sdim bool hasBMI() const { return HasBMI; } 216234353Sdim bool hasBMI2() const { return HasBMI2; } 217193323Sed bool isBTMemSlow() const { return IsBTMemSlow; } 218206083Srdivacky bool isUnalignedMemAccessFast() const { return IsUAMemFast; } 219202375Srdivacky bool hasVectorUAMem() const { return HasVectorUAMem; } 220226633Sdim bool hasCmpxchg16b() const { return HasCmpxchg16b; } 221234353Sdim bool useLeaForSP() const { return UseLeaForSP; } 222193323Sed 223234353Sdim bool isAtom() const { return X86ProcFamily == IntelAtom; } 224234353Sdim 225221345Sdim const Triple &getTargetTriple() const { return TargetTriple; } 226218893Sdim 227221345Sdim bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 228221345Sdim bool isTargetFreeBSD() const { 229221345Sdim return TargetTriple.getOS() == Triple::FreeBSD; 230221345Sdim } 231221345Sdim bool isTargetSolaris() const { 232221345Sdim return TargetTriple.getOS() == Triple::Solaris; 233221345Sdim } 234221345Sdim 235210299Sed // ELF is a reasonably sane default and the only other X86 targets we 236210299Sed // support are Darwin and Windows. Just use "not those". 237234353Sdim bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 238210299Sed bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; } 239226633Sdim bool isTargetNaCl() const { 240226633Sdim return TargetTriple.getOS() == Triple::NativeClient; 241226633Sdim } 242226633Sdim bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } 243226633Sdim bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } 244210299Sed bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; } 245218893Sdim bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; } 246210299Sed bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; } 247234353Sdim bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 248234353Sdim bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 249234353Sdim bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); } 250218893Sdim 251193323Sed bool isTargetWin64() const { 252226633Sdim // FIXME: x86_64-cygwin has not been released yet. 253234353Sdim return In64BitMode && TargetTriple.isOSWindows(); 254193323Sed } 255193323Sed 256212904Sdim bool isTargetWin32() const { 257234353Sdim // FIXME: Cygwin is included for isTargetWin64 -- should it be included 258234353Sdim // here too? 259224145Sdim return !In64BitMode && (isTargetMingw() || isTargetWindows()); 260212904Sdim } 261212904Sdim 262193323Sed bool isPICStyleSet() const { return PICStyle != PICStyles::None; } 263193323Sed bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; } 264193323Sed bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; } 265198090Srdivacky 266198090Srdivacky bool isPICStyleStubPIC() const { 267198090Srdivacky return PICStyle == PICStyles::StubPIC; 268198090Srdivacky } 269198090Srdivacky 270198090Srdivacky bool isPICStyleStubNoDynamic() const { 271198090Srdivacky return PICStyle == PICStyles::StubDynamicNoPIC; 272198090Srdivacky } 273198090Srdivacky bool isPICStyleStubAny() const { 274198090Srdivacky return PICStyle == PICStyles::StubDynamicNoPIC || 275198090Srdivacky PICStyle == PICStyles::StubPIC; } 276204642Srdivacky 277198090Srdivacky /// ClassifyGlobalReference - Classify a global variable reference for the 278198090Srdivacky /// current subtarget according to how we should reference it in a non-pcrel 279198090Srdivacky /// context. 280198090Srdivacky unsigned char ClassifyGlobalReference(const GlobalValue *GV, 281198090Srdivacky const TargetMachine &TM)const; 282193323Sed 283199989Srdivacky /// ClassifyBlockAddressReference - Classify a blockaddress reference for the 284199989Srdivacky /// current subtarget according to how we should reference it in a non-pcrel 285199989Srdivacky /// context. 286199989Srdivacky unsigned char ClassifyBlockAddressReference() const; 287199989Srdivacky 288193323Sed /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls 289193323Sed /// to immediate address. 290193323Sed bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const; 291193323Sed 292193323Sed /// This function returns the name of a function which has an interface 293193323Sed /// like the non-standard bzero function, if such a function exists on 294193323Sed /// the current subtarget and it is considered prefereable over 295193323Sed /// memset with zero passed as the second argument. Otherwise it 296193323Sed /// returns null. 297193323Sed const char *getBZeroEntry() const; 298193323Sed 299193323Sed /// getSpecialAddressLatency - For targets where it is beneficial to 300193323Sed /// backschedule instructions that compute addresses, return a value 301193323Sed /// indicating the number of scheduling cycles of backscheduling that 302193323Sed /// should be attempted. 303193323Sed unsigned getSpecialAddressLatency() const; 304234353Sdim 305234353Sdim /// enablePostRAScheduler - run for Atom optimization. 306234353Sdim bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 307234353Sdim TargetSubtargetInfo::AntiDepBreakMode& Mode, 308234353Sdim RegClassVector& CriticalPathRCs) const; 309234353Sdim 310234353Sdim /// getInstrItins = Return the instruction itineraries based on the 311234353Sdim /// subtarget selection. 312234353Sdim const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 313193323Sed}; 314193323Sed 315193323Sed} // End llvm namespace 316193323Sed 317193323Sed#endif 318