1249259Sdim//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2249259Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6249259Sdim// 7249259Sdim//===----------------------------------------------------------------------===// 8249259Sdim// 9249259Sdim// This file defines the machine model for Sandy Bridge to support instruction 10249259Sdim// scheduling and other instruction cost heuristics. 11249259Sdim// 12341825Sdim// Note that we define some instructions here that are not supported by SNB, 13341825Sdim// but we still have to define them because SNB is the default subtarget for 14341825Sdim// X86. These instructions are tagged with a comment `Unsupported = 1`. 15341825Sdim// 16249259Sdim//===----------------------------------------------------------------------===// 17249259Sdim 18249259Sdimdef SandyBridgeModel : SchedMachineModel { 19249259Sdim // All x86 instructions are modeled as a single micro-op, and SB can decode 4 20249259Sdim // instructions per cycle. 21249259Sdim // FIXME: Identify instructions that aren't a single fused micro-op. 22249259Sdim let IssueWidth = 4; 23261991Sdim let MicroOpBufferSize = 168; // Based on the reorder buffer. 24341825Sdim let LoadLatency = 5; 25249259Sdim let MispredictPenalty = 16; 26261991Sdim 27276479Sdim // Based on the LSD (loop-stream detector) queue size. 28276479Sdim let LoopMicroOpBufferSize = 28; 29276479Sdim 30327952Sdim // This flag is set to allow the scheduler to assign 31327952Sdim // a default model to unrecognized opcodes. 32261991Sdim let CompleteModel = 0; 33249259Sdim} 34249259Sdim 35249259Sdimlet SchedModel = SandyBridgeModel in { 36249259Sdim 37249259Sdim// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 38249259Sdim 39249259Sdim// Ports 0, 1, and 5 handle all computation. 40249259Sdimdef SBPort0 : ProcResource<1>; 41249259Sdimdef SBPort1 : ProcResource<1>; 42249259Sdimdef SBPort5 : ProcResource<1>; 43249259Sdim 44249259Sdim// Ports 2 and 3 are identical. They handle loads and the address half of 45249259Sdim// stores. 46249259Sdimdef SBPort23 : ProcResource<2>; 47249259Sdim 48249259Sdim// Port 4 gets the data half of stores. Store data can be available later than 49249259Sdim// the store address, but since we don't model the latency of stores, we can 50249259Sdim// ignore that. 51249259Sdimdef SBPort4 : ProcResource<1>; 52249259Sdim 53249259Sdim// Many micro-ops are capable of issuing on multiple ports. 54327952Sdimdef SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; 55249259Sdimdef SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 56249259Sdimdef SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 57249259Sdimdef SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 58249259Sdim 59261991Sdim// 54 Entry Unified Scheduler 60261991Sdimdef SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 61261991Sdim let BufferSize=54; 62261991Sdim} 63261991Sdim 64249259Sdim// Integer division issued on port 0. 65249259Sdimdef SBDivider : ProcResource<1>; 66341825Sdim// FP division and sqrt on port 0. 67341825Sdimdef SBFPDivider : ProcResource<1>; 68249259Sdim 69344779Sdim// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 70249259Sdim// cycles after the memory operand. 71341825Sdimdef : ReadAdvance<ReadAfterLd, 5>; 72249259Sdim 73344779Sdim// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 74344779Sdim// until 5/6/7 cycles after the memory operand. 75344779Sdimdef : ReadAdvance<ReadAfterVecLd, 5>; 76344779Sdimdef : ReadAdvance<ReadAfterVecXLd, 6>; 77344779Sdimdef : ReadAdvance<ReadAfterVecYLd, 7>; 78344779Sdim 79353358Sdimdef : ReadAdvance<ReadInt2Fpu, 0>; 80353358Sdim 81249259Sdim// Many SchedWrites are defined in pairs with and without a folded load. 82249259Sdim// Instructions with folded loads are usually micro-fused, so they only appear 83249259Sdim// as two micro-ops when queued in the reservation station. 84249259Sdim// This multiclass defines the resource usage for variants with and without 85249259Sdim// folded loads. 86249259Sdimmulticlass SBWriteResPair<X86FoldableSchedWrite SchedRW, 87341825Sdim list<ProcResourceKind> ExePorts, 88341825Sdim int Lat, list<int> Res = [1], int UOps = 1, 89341825Sdim int LoadLat = 5> { 90249259Sdim // Register variant is using a single cycle on ExePort. 91341825Sdim def : WriteRes<SchedRW, ExePorts> { 92341825Sdim let Latency = Lat; 93341825Sdim let ResourceCycles = Res; 94341825Sdim let NumMicroOps = UOps; 95341825Sdim } 96249259Sdim 97341825Sdim // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 98341825Sdim // the latency (default = 5). 99341825Sdim def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> { 100341825Sdim let Latency = !add(Lat, LoadLat); 101341825Sdim let ResourceCycles = !listconcat([1], Res); 102341825Sdim let NumMicroOps = !add(UOps, 1); 103249259Sdim } 104249259Sdim} 105249259Sdim 106341825Sdim// A folded store needs a cycle on port 4 for the store data, and an extra port 107341825Sdim// 2/3 cycle to recompute the address. 108341825Sdimdef : WriteRes<WriteRMW, [SBPort23,SBPort4]>; 109249259Sdim 110341825Sdimdef : WriteRes<WriteStore, [SBPort23, SBPort4]>; 111341825Sdimdef : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>; 112341825Sdimdef : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; } 113341825Sdimdef : WriteRes<WriteMove, [SBPort015]>; 114341825Sdimdef : WriteRes<WriteZero, []>; 115249259Sdim 116341825Sdim// Arithmetic. 117341825Sdimdefm : SBWriteResPair<WriteALU, [SBPort015], 1>; 118341825Sdimdefm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>; 119341825Sdim 120344779Sdimdefm : SBWriteResPair<WriteIMul8, [SBPort1], 3>; 121344779Sdimdefm : SBWriteResPair<WriteIMul16, [SBPort1,SBPort05,SBPort015], 4, [1,1,2], 4>; 122344779Sdimdefm : X86WriteRes<WriteIMul16Imm, [SBPort1,SBPort015], 4, [1,1], 2>; 123344779Sdimdefm : X86WriteRes<WriteIMul16ImmLd, [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>; 124344779Sdimdefm : SBWriteResPair<WriteIMul16Reg, [SBPort1], 3>; 125344779Sdimdefm : SBWriteResPair<WriteIMul32, [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>; 126344779Sdimdefm : SBWriteResPair<WriteIMul32Imm, [SBPort1], 3>; 127344779Sdimdefm : SBWriteResPair<WriteIMul32Reg, [SBPort1], 3>; 128344779Sdimdefm : SBWriteResPair<WriteIMul64, [SBPort1,SBPort0], 4, [1,1], 2>; 129344779Sdimdefm : SBWriteResPair<WriteIMul64Imm, [SBPort1], 3>; 130344779Sdimdefm : SBWriteResPair<WriteIMul64Reg, [SBPort1], 3>; 131344779Sdimdef : WriteRes<WriteIMulH, []> { let Latency = 3; } 132344779Sdim 133344779Sdimdefm : X86WriteRes<WriteXCHG, [SBPort015], 2, [3], 3>; 134341825Sdimdefm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>; 135344779Sdimdefm : X86WriteRes<WriteBSWAP64, [SBPort1, SBPort05], 2, [1,1], 2>; 136344779Sdimdefm : X86WriteRes<WriteCMPXCHG, [SBPort05, SBPort015], 5, [1,3], 4>; 137344779Sdimdefm : X86WriteRes<WriteCMPXCHGRMW,[SBPort015, SBPort5, SBPort23, SBPort4], 8, [1, 2, 2, 1], 6>; 138341825Sdim 139341825Sdimdefm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 140341825Sdimdefm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 141341825Sdimdefm : SBWriteResPair<WriteDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 142341825Sdimdefm : SBWriteResPair<WriteDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 143341825Sdimdefm : SBWriteResPair<WriteIDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 144341825Sdimdefm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 145341825Sdimdefm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 146341825Sdimdefm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 147341825Sdim 148341825Sdim// SHLD/SHRD. 149341825Sdimdefm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>; 150341825Sdimdefm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>; 151341825Sdimdefm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>; 152341825Sdimdefm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>; 153341825Sdim 154344779Sdimdefm : SBWriteResPair<WriteShift, [SBPort05], 1>; 155344779Sdimdefm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3>; 156344779Sdimdefm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>; 157344779Sdimdefm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3>; 158344779Sdim 159341825Sdimdefm : SBWriteResPair<WriteJump, [SBPort5], 1>; 160341825Sdimdefm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>; 161341825Sdim 162341825Sdimdefm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move. 163341825Sdimdefm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move. 164341825Sdimdef : WriteRes<WriteSETCC, [SBPort05]>; // Setcc. 165341825Sdimdef : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { 166341825Sdim let Latency = 2; 167341825Sdim let NumMicroOps = 3; 168341825Sdim} 169341825Sdim 170344779Sdimdefm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>; 171344779Sdimdefm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>; 172344779Sdimdefm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>; 173344779Sdim//defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>; 174344779Sdimdefm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>; 175344779Sdimdefm : X86WriteRes<WriteBitTestSetImmLd, [SBPort05,SBPort23], 6, [1,1], 3>; 176344779Sdimdefm : X86WriteRes<WriteBitTestSetRegLd, [SBPort05,SBPort23,SBPort5,SBPort015], 8, [1,1,1,1], 5>; 177344779Sdim 178249259Sdim// This is for simple LEAs with one or two input operands. 179249259Sdim// The complex ones can only execute on port 1, and they require two cycles on 180249259Sdim// the port to read all inputs. We don't model that. 181341825Sdimdef : WriteRes<WriteLEA, [SBPort01]>; 182249259Sdim 183341825Sdim// Bit counts. 184341825Sdimdefm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>; 185341825Sdimdefm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>; 186341825Sdimdefm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>; 187341825Sdimdefm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>; 188341825Sdimdefm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>; 189249259Sdim 190344779Sdim// BMI1 BEXTR/BLS, BMI2 BZHI 191341825Sdim// NOTE: These don't exist on Sandy Bridge. Ports are guesses. 192341825Sdimdefm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>; 193344779Sdimdefm : SBWriteResPair<WriteBLS, [SBPort015], 1>; 194344779Sdimdefm : SBWriteResPair<WriteBZHI, [SBPort1], 1>; 195341825Sdim 196249259Sdim// Scalar and vector floating point. 197341825Sdimdefm : X86WriteRes<WriteFLD0, [SBPort5], 1, [1], 1>; 198341825Sdimdefm : X86WriteRes<WriteFLD1, [SBPort0,SBPort5], 1, [1,1], 2>; 199341825Sdimdefm : X86WriteRes<WriteFLDC, [SBPort0,SBPort1], 1, [1,1], 2>; 200341825Sdimdefm : X86WriteRes<WriteFLoad, [SBPort23], 5, [1], 1>; 201341825Sdimdefm : X86WriteRes<WriteFLoadX, [SBPort23], 6, [1], 1>; 202341825Sdimdefm : X86WriteRes<WriteFLoadY, [SBPort23], 7, [1], 1>; 203341825Sdimdefm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 204341825Sdimdefm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 205341825Sdimdefm : X86WriteRes<WriteFStore, [SBPort23,SBPort4], 1, [1,1], 1>; 206341825Sdimdefm : X86WriteRes<WriteFStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 207341825Sdimdefm : X86WriteRes<WriteFStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 208341825Sdimdefm : X86WriteRes<WriteFStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 209341825Sdimdefm : X86WriteRes<WriteFStoreNTX, [SBPort23,SBPort4], 1, [1,1], 1>; 210341825Sdimdefm : X86WriteRes<WriteFStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 211360784Sdim 212360784Sdimdefm : X86WriteRes<WriteFMaskedStore32, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 213360784Sdimdefm : X86WriteRes<WriteFMaskedStore32Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 214360784Sdimdefm : X86WriteRes<WriteFMaskedStore64, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 215360784Sdimdefm : X86WriteRes<WriteFMaskedStore64Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 216360784Sdim 217341825Sdimdefm : X86WriteRes<WriteFMove, [SBPort5], 1, [1], 1>; 218341825Sdimdefm : X86WriteRes<WriteFMoveX, [SBPort5], 1, [1], 1>; 219341825Sdimdefm : X86WriteRes<WriteFMoveY, [SBPort5], 1, [1], 1>; 220341825Sdimdefm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>; 221341825Sdim 222341825Sdimdefm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>; 223341825Sdimdefm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>; 224341825Sdimdefm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>; 225341825Sdimdefm : SBWriteResPair<WriteFAddZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 226341825Sdimdefm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>; 227341825Sdimdefm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>; 228341825Sdimdefm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>; 229341825Sdimdefm : SBWriteResPair<WriteFAdd64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 230341825Sdim 231341825Sdimdefm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>; 232341825Sdimdefm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>; 233341825Sdimdefm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>; 234341825Sdimdefm : SBWriteResPair<WriteFCmpZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 235341825Sdimdefm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>; 236341825Sdimdefm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>; 237341825Sdimdefm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>; 238341825Sdimdefm : SBWriteResPair<WriteFCmp64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 239341825Sdim 240341825Sdimdefm : SBWriteResPair<WriteFCom, [SBPort1], 3>; 241341825Sdim 242341825Sdimdefm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>; 243341825Sdimdefm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>; 244341825Sdimdefm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>; 245341825Sdimdefm : SBWriteResPair<WriteFMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 246341825Sdimdefm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>; 247341825Sdimdefm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>; 248341825Sdimdefm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>; 249341825Sdimdefm : SBWriteResPair<WriteFMul64Z, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 250341825Sdim 251341825Sdimdefm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 252341825Sdimdefm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 253341825Sdimdefm : SBWriteResPair<WriteFDivY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 254341825Sdimdefm : SBWriteResPair<WriteFDivZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 255341825Sdimdefm : SBWriteResPair<WriteFDiv64, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 256341825Sdimdefm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 257341825Sdimdefm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 258341825Sdimdefm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 259341825Sdim 260341825Sdimdefm : SBWriteResPair<WriteFRcp, [SBPort0], 5, [1], 1, 6>; 261341825Sdimdefm : SBWriteResPair<WriteFRcpX, [SBPort0], 5, [1], 1, 6>; 262341825Sdimdefm : SBWriteResPair<WriteFRcpY, [SBPort0,SBPort05], 7, [2,1], 3, 7>; 263341825Sdimdefm : SBWriteResPair<WriteFRcpZ, [SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 264341825Sdim 265341825Sdimdefm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5, [1], 1, 6>; 266341825Sdimdefm : SBWriteResPair<WriteFRsqrtX,[SBPort0], 5, [1], 1, 6>; 267341825Sdimdefm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05], 7, [2,1], 3, 7>; 268341825Sdimdefm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 269341825Sdim 270341825Sdimdefm : SBWriteResPair<WriteFSqrt, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 271341825Sdimdefm : SBWriteResPair<WriteFSqrtX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 272341825Sdimdefm : SBWriteResPair<WriteFSqrtY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 273341825Sdimdefm : SBWriteResPair<WriteFSqrtZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 274341825Sdimdefm : SBWriteResPair<WriteFSqrt64, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 275341825Sdimdefm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 276341825Sdimdefm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 277341825Sdimdefm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 278341825Sdimdefm : SBWriteResPair<WriteFSqrt80, [SBPort0,SBFPDivider], 24, [1,24], 1, 6>; 279341825Sdim 280341825Sdimdefm : SBWriteResPair<WriteDPPD, [SBPort0,SBPort1,SBPort5], 9, [1,1,1], 3, 6>; 281341825Sdimdefm : SBWriteResPair<WriteDPPS, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>; 282341825Sdimdefm : SBWriteResPair<WriteDPPSY, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; 283341825Sdimdefm : SBWriteResPair<WriteDPPSZ, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1 284341825Sdimdefm : SBWriteResPair<WriteFSign, [SBPort5], 1>; 285341825Sdimdefm : SBWriteResPair<WriteFRnd, [SBPort1], 3, [1], 1, 6>; 286341825Sdimdefm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>; 287341825Sdimdefm : SBWriteResPair<WriteFRndZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 288341825Sdimdefm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>; 289341825Sdimdefm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>; 290341825Sdimdefm : SBWriteResPair<WriteFLogicZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 291341825Sdimdefm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>; 292341825Sdimdefm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>; 293341825Sdimdefm : SBWriteResPair<WriteFTestZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 294341825Sdimdefm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>; 295341825Sdimdefm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>; 296341825Sdimdefm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 297341825Sdimdefm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>; 298341825Sdimdefm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>; 299341825Sdimdefm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 300341825Sdimdefm : SBWriteResPair<WriteFBlend, [SBPort05], 1, [1], 1, 6>; 301341825Sdimdefm : SBWriteResPair<WriteFBlendY, [SBPort05], 1, [1], 1, 7>; 302341825Sdimdefm : SBWriteResPair<WriteFBlendZ, [SBPort05], 1, [1], 1, 7>; // Unsupported = 1 303341825Sdimdefm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>; 304341825Sdimdefm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>; 305341825Sdimdefm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1 306341825Sdim 307341825Sdim// Conversion between integer and float. 308341825Sdimdefm : SBWriteResPair<WriteCvtSS2I, [SBPort0,SBPort1], 5, [1,1], 2>; 309341825Sdimdefm : SBWriteResPair<WriteCvtPS2I, [SBPort1], 3, [1], 1, 6>; 310341825Sdimdefm : SBWriteResPair<WriteCvtPS2IY, [SBPort1], 3, [1], 1, 7>; 311341825Sdimdefm : SBWriteResPair<WriteCvtPS2IZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 312341825Sdimdefm : SBWriteResPair<WriteCvtSD2I, [SBPort0,SBPort1], 5, [1,1], 2>; 313341825Sdimdefm : SBWriteResPair<WriteCvtPD2I, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 314341825Sdimdefm : X86WriteRes<WriteCvtPD2IY, [SBPort1,SBPort5], 4, [1,1], 2>; 315341825Sdimdefm : X86WriteRes<WriteCvtPD2IZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 316341825Sdimdefm : X86WriteRes<WriteCvtPD2IYLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; 317341825Sdimdefm : X86WriteRes<WriteCvtPD2IZLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1 318341825Sdim 319341825Sdimdefm : X86WriteRes<WriteCvtI2SS, [SBPort1,SBPort5], 5, [1,2], 3>; 320341825Sdimdefm : X86WriteRes<WriteCvtI2SSLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 321341825Sdimdefm : SBWriteResPair<WriteCvtI2PS, [SBPort1], 3, [1], 1, 6>; 322341825Sdimdefm : SBWriteResPair<WriteCvtI2PSY, [SBPort1], 3, [1], 1, 7>; 323341825Sdimdefm : SBWriteResPair<WriteCvtI2PSZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 324341825Sdimdefm : X86WriteRes<WriteCvtI2SD, [SBPort1,SBPort5], 4, [1,1], 2>; 325341825Sdimdefm : X86WriteRes<WriteCvtI2PD, [SBPort1,SBPort5], 4, [1,1], 2>; 326341825Sdimdefm : X86WriteRes<WriteCvtI2PDY, [SBPort1,SBPort5], 4, [1,1], 2>; 327341825Sdimdefm : X86WriteRes<WriteCvtI2PDZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 328341825Sdimdefm : X86WriteRes<WriteCvtI2SDLd, [SBPort1,SBPort23], 9, [1,1], 2>; 329341825Sdimdefm : X86WriteRes<WriteCvtI2PDLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 330341825Sdimdefm : X86WriteRes<WriteCvtI2PDYLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 331341825Sdimdefm : X86WriteRes<WriteCvtI2PDZLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1 332341825Sdim 333341825Sdimdefm : SBWriteResPair<WriteCvtSS2SD, [SBPort0], 1, [1], 1, 6>; 334341825Sdimdefm : X86WriteRes<WriteCvtPS2PD, [SBPort0,SBPort5], 2, [1,1], 2>; 335341825Sdimdefm : X86WriteRes<WriteCvtPS2PDY, [SBPort0,SBPort5], 2, [1,1], 2>; 336341825Sdimdefm : X86WriteRes<WriteCvtPS2PDZ, [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1 337341825Sdimdefm : X86WriteRes<WriteCvtPS2PDLd, [SBPort0,SBPort23], 7, [1,1], 2>; 338341825Sdimdefm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>; 339341825Sdimdefm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1 340341825Sdimdefm : SBWriteResPair<WriteCvtSD2SS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 341341825Sdimdefm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 342341825Sdimdefm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>; 343341825Sdimdefm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1 344341825Sdim 345341825Sdimdefm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>; 346341825Sdimdefm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>; 347341825Sdimdefm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1 348341825Sdim 349341825Sdimdefm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>; 350341825Sdimdefm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>; 351341825Sdimdefm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1 352341825Sdimdefm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 353341825Sdimdefm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 354341825Sdimdefm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1 355341825Sdim 356341825Sdim// Vector integer operations. 357341825Sdimdefm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>; 358341825Sdimdefm : X86WriteRes<WriteVecLoadX, [SBPort23], 6, [1], 1>; 359341825Sdimdefm : X86WriteRes<WriteVecLoadY, [SBPort23], 7, [1], 1>; 360341825Sdimdefm : X86WriteRes<WriteVecLoadNT, [SBPort23], 6, [1], 1>; 361341825Sdimdefm : X86WriteRes<WriteVecLoadNTY, [SBPort23], 7, [1], 1>; 362341825Sdimdefm : X86WriteRes<WriteVecMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 363341825Sdimdefm : X86WriteRes<WriteVecMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 364341825Sdimdefm : X86WriteRes<WriteVecStore, [SBPort23,SBPort4], 1, [1,1], 1>; 365341825Sdimdefm : X86WriteRes<WriteVecStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 366341825Sdimdefm : X86WriteRes<WriteVecStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 367341825Sdimdefm : X86WriteRes<WriteVecStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 368341825Sdimdefm : X86WriteRes<WriteVecStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 369341825Sdimdefm : X86WriteRes<WriteVecMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 370341825Sdimdefm : X86WriteRes<WriteVecMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 371341825Sdimdefm : X86WriteRes<WriteVecMove, [SBPort05], 1, [1], 1>; 372341825Sdimdefm : X86WriteRes<WriteVecMoveX, [SBPort015], 1, [1], 1>; 373341825Sdimdefm : X86WriteRes<WriteVecMoveY, [SBPort05], 1, [1], 1>; 374341825Sdimdefm : X86WriteRes<WriteVecMoveToGpr, [SBPort0], 2, [1], 1>; 375341825Sdimdefm : X86WriteRes<WriteVecMoveFromGpr, [SBPort5], 1, [1], 1>; 376341825Sdim 377341825Sdimdefm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>; 378341825Sdimdefm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>; 379341825Sdimdefm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>; 380341825Sdimdefm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1 381341825Sdimdefm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>; 382341825Sdimdefm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>; 383341825Sdimdefm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1 384341825Sdimdefm : SBWriteResPair<WriteVecALU, [SBPort1], 3, [1], 1, 5>; 385341825Sdimdefm : SBWriteResPair<WriteVecALUX, [SBPort15], 1, [1], 1, 6>; 386341825Sdimdefm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>; 387341825Sdimdefm : SBWriteResPair<WriteVecALUZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 388341825Sdimdefm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>; 389341825Sdimdefm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>; 390341825Sdimdefm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>; 391341825Sdimdefm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 392341825Sdimdefm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; 393341825Sdimdefm : SBWriteResPair<WritePMULLDY, [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model 394341825Sdimdefm : SBWriteResPair<WritePMULLDZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 395341825Sdimdefm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>; 396341825Sdimdefm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>; 397341825Sdimdefm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>; 398341825Sdimdefm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 399341825Sdimdefm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>; 400341825Sdimdefm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>; 401341825Sdimdefm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>; 402341825Sdimdefm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 403341825Sdimdefm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>; 404341825Sdimdefm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>; 405341825Sdimdefm : SBWriteResPair<WriteBlendZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 406341825Sdimdefm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>; 407341825Sdimdefm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>; 408341825Sdimdefm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1 409341825Sdimdefm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>; 410341825Sdimdefm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>; 411341825Sdimdefm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1 412341825Sdimdefm : SBWriteResPair<WritePSADBW, [SBPort0], 5, [1], 1, 5>; 413341825Sdimdefm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>; 414341825Sdimdefm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>; 415341825Sdimdefm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 416341825Sdimdefm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>; 417341825Sdim 418341825Sdim// Vector integer shifts. 419341825Sdimdefm : SBWriteResPair<WriteVecShift, [SBPort5], 1, [1], 1, 5>; 420341825Sdimdefm : SBWriteResPair<WriteVecShiftX, [SBPort0,SBPort15], 2, [1,1], 2, 6>; 421341825Sdimdefm : SBWriteResPair<WriteVecShiftY, [SBPort0,SBPort15], 4, [1,1], 2, 7>; 422341825Sdimdefm : SBWriteResPair<WriteVecShiftZ, [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1 423341825Sdimdefm : SBWriteResPair<WriteVecShiftImm, [SBPort5], 1, [1], 1, 5>; 424341825Sdimdefm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>; 425341825Sdimdefm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>; 426341825Sdimdefm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 427341825Sdimdefm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1, [1], 1, 6>; 428341825Sdimdefm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>; 429341825Sdimdefm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 430341825Sdim 431341825Sdim// Vector insert/extract operations. 432341825Sdimdef : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> { 433276479Sdim let Latency = 2; 434341825Sdim let NumMicroOps = 2; 435276479Sdim} 436341825Sdimdef : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> { 437341825Sdim let Latency = 7; 438341825Sdim let NumMicroOps = 2; 439276479Sdim} 440249259Sdim 441341825Sdimdef : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> { 442341825Sdim let Latency = 3; 443341825Sdim let NumMicroOps = 2; 444276479Sdim} 445341825Sdimdef : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> { 446327952Sdim let Latency = 5; 447327952Sdim let NumMicroOps = 3; 448276479Sdim} 449249259Sdim 450321369Sdim//////////////////////////////////////////////////////////////////////////////// 451321369Sdim// Horizontal add/sub instructions. 452321369Sdim//////////////////////////////////////////////////////////////////////////////// 453321369Sdim 454341825Sdimdefm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>; 455341825Sdimdefm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>; 456341825Sdimdefm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1 457341825Sdimdefm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 5>; 458341825Sdimdefm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>; 459341825Sdimdefm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>; 460341825Sdimdefm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1 461321369Sdim 462341825Sdim//////////////////////////////////////////////////////////////////////////////// 463341825Sdim// String instructions. 464341825Sdim//////////////////////////////////////////////////////////////////////////////// 465321369Sdim 466276479Sdim// Packed Compare Implicit Length Strings, Return Mask 467341825Sdimdef : WriteRes<WritePCmpIStrM, [SBPort0]> { 468276479Sdim let Latency = 11; 469341825Sdim let NumMicroOps = 3; 470276479Sdim let ResourceCycles = [3]; 471276479Sdim} 472341825Sdimdef : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> { 473341825Sdim let Latency = 17; 474341825Sdim let NumMicroOps = 4; 475341825Sdim let ResourceCycles = [3,1]; 476276479Sdim} 477276479Sdim 478276479Sdim// Packed Compare Explicit Length Strings, Return Mask 479276479Sdimdef : WriteRes<WritePCmpEStrM, [SBPort015]> { 480276479Sdim let Latency = 11; 481276479Sdim let ResourceCycles = [8]; 482276479Sdim} 483276479Sdimdef : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> { 484276479Sdim let Latency = 11; 485276479Sdim let ResourceCycles = [7, 1]; 486276479Sdim} 487276479Sdim 488276479Sdim// Packed Compare Implicit Length Strings, Return Index 489327952Sdimdef : WriteRes<WritePCmpIStrI, [SBPort0]> { 490327952Sdim let Latency = 11; 491327952Sdim let NumMicroOps = 3; 492276479Sdim let ResourceCycles = [3]; 493276479Sdim} 494327952Sdimdef : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> { 495327952Sdim let Latency = 17; 496327952Sdim let NumMicroOps = 4; 497327952Sdim let ResourceCycles = [3,1]; 498276479Sdim} 499276479Sdim 500276479Sdim// Packed Compare Explicit Length Strings, Return Index 501276479Sdimdef : WriteRes<WritePCmpEStrI, [SBPort015]> { 502276479Sdim let Latency = 4; 503276479Sdim let ResourceCycles = [8]; 504276479Sdim} 505276479Sdimdef : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> { 506276479Sdim let Latency = 4; 507276479Sdim let ResourceCycles = [7, 1]; 508276479Sdim} 509276479Sdim 510341825Sdim// MOVMSK Instructions. 511341825Sdimdef : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; } 512341825Sdimdef : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; } 513341825Sdimdef : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; } 514341825Sdimdef : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; } 515341825Sdim 516276479Sdim// AES Instructions. 517327952Sdimdef : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> { 518327952Sdim let Latency = 7; 519327952Sdim let NumMicroOps = 2; 520327952Sdim let ResourceCycles = [1,1]; 521276479Sdim} 522327952Sdimdef : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> { 523327952Sdim let Latency = 13; 524327952Sdim let NumMicroOps = 3; 525327952Sdim let ResourceCycles = [1,1,1]; 526276479Sdim} 527276479Sdim 528327952Sdimdef : WriteRes<WriteAESIMC, [SBPort5]> { 529327952Sdim let Latency = 12; 530327952Sdim let NumMicroOps = 2; 531276479Sdim let ResourceCycles = [2]; 532276479Sdim} 533327952Sdimdef : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> { 534327952Sdim let Latency = 18; 535327952Sdim let NumMicroOps = 3; 536327952Sdim let ResourceCycles = [2,1]; 537276479Sdim} 538276479Sdim 539276479Sdimdef : WriteRes<WriteAESKeyGen, [SBPort015]> { 540276479Sdim let Latency = 8; 541276479Sdim let ResourceCycles = [11]; 542276479Sdim} 543276479Sdimdef : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> { 544276479Sdim let Latency = 8; 545276479Sdim let ResourceCycles = [10, 1]; 546276479Sdim} 547276479Sdim 548276479Sdim// Carry-less multiplication instructions. 549276479Sdimdef : WriteRes<WriteCLMul, [SBPort015]> { 550276479Sdim let Latency = 14; 551276479Sdim let ResourceCycles = [18]; 552276479Sdim} 553276479Sdimdef : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> { 554276479Sdim let Latency = 14; 555276479Sdim let ResourceCycles = [17, 1]; 556276479Sdim} 557276479Sdim 558341825Sdim// Load/store MXCSR. 559341825Sdim// FIXME: This is probably wrong. Only STMXCSR should require Port4. 560341825Sdimdef : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 561341825Sdimdef : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 562276479Sdim 563249259Sdimdef : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 564249259Sdimdef : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 565276479Sdimdef : WriteRes<WriteFence, [SBPort23, SBPort4]>; 566276479Sdimdef : WriteRes<WriteNop, []>; 567276479Sdim 568327952Sdim// AVX2/FMA is not supported on that architecture, but we should define the basic 569276479Sdim// scheduling resources anyway. 570341825Sdimdefm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>; 571341825Sdimdefm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>; 572341825Sdimdefm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>; 573341825Sdimdefm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>; 574341825Sdimdefm : SBWriteResPair<WriteFMA, [SBPort01], 5>; 575341825Sdimdefm : SBWriteResPair<WriteFMAX, [SBPort01], 5>; 576341825Sdimdefm : SBWriteResPair<WriteFMAY, [SBPort01], 5>; 577341825Sdimdefm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1 578327952Sdim 579327952Sdim// Remaining SNB instrs. 580327952Sdim 581327952Sdimdef SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { 582327952Sdim let Latency = 1; 583327952Sdim let NumMicroOps = 1; 584327952Sdim let ResourceCycles = [1]; 585327952Sdim} 586341825Sdimdef: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, 587341825Sdim COM_FST0r, 588341825Sdim UCOM_FPr, 589341825Sdim UCOM_Fr)>; 590327952Sdim 591327952Sdimdef SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { 592327952Sdim let Latency = 1; 593327952Sdim let NumMicroOps = 1; 594327952Sdim let ResourceCycles = [1]; 595327952Sdim} 596341825Sdimdef: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, 597341825Sdim LD_Frr, ST_Frr, ST_FPrr)>; 598341825Sdimdef: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. 599341825Sdimdef: InstRW<[SBWriteResGroup2], (instrs RETQ)>; 600327952Sdim 601327952Sdimdef SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { 602327952Sdim let Latency = 1; 603327952Sdim let NumMicroOps = 1; 604327952Sdim let ResourceCycles = [1]; 605327952Sdim} 606341825Sdimdef: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; 607327952Sdim 608327952Sdimdef SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { 609327952Sdim let Latency = 1; 610327952Sdim let NumMicroOps = 1; 611327952Sdim let ResourceCycles = [1]; 612327952Sdim} 613344779Sdimdef: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr, 614344779Sdim MMX_PABSDrr, 615344779Sdim MMX_PABSWrr, 616344779Sdim MMX_PADDQirr, 617344779Sdim MMX_PALIGNRrri, 618344779Sdim MMX_PSIGNBrr, 619344779Sdim MMX_PSIGNDrr, 620344779Sdim MMX_PSIGNWrr)>; 621327952Sdim 622327952Sdimdef SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { 623327952Sdim let Latency = 2; 624327952Sdim let NumMicroOps = 2; 625327952Sdim let ResourceCycles = [2]; 626327952Sdim} 627341825Sdimdef: InstRW<[SBWriteResGroup11], (instrs SCASB, 628341825Sdim SCASL, 629341825Sdim SCASQ, 630341825Sdim SCASW)>; 631327952Sdim 632327952Sdimdef SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { 633327952Sdim let Latency = 2; 634327952Sdim let NumMicroOps = 2; 635327952Sdim let ResourceCycles = [1,1]; 636327952Sdim} 637344779Sdimdef: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>; 638327952Sdim 639327952Sdimdef SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { 640327952Sdim let Latency = 2; 641327952Sdim let NumMicroOps = 2; 642327952Sdim let ResourceCycles = [1,1]; 643327952Sdim} 644341825Sdimdef: InstRW<[SBWriteResGroup15], (instrs CWD, 645341825Sdim FNSTSW16r)>; 646327952Sdim 647327952Sdimdef SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { 648327952Sdim let Latency = 2; 649327952Sdim let NumMicroOps = 2; 650327952Sdim let ResourceCycles = [1,1]; 651327952Sdim} 652344779Sdimdef: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ, 653344779Sdim MMX_MOVDQ2Qrr)>; 654327952Sdim 655327952Sdimdef SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { 656327952Sdim let Latency = 3; 657327952Sdim let NumMicroOps = 1; 658327952Sdim let ResourceCycles = [1]; 659327952Sdim} 660344779Sdimdef: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>; 661327952Sdim 662341825Sdimdef SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { 663327952Sdim let Latency = 3; 664327952Sdim let NumMicroOps = 2; 665327952Sdim let ResourceCycles = [1,1]; 666327952Sdim} 667341825Sdimdef: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; 668327952Sdim 669344779Sdimdef SBWriteResGroup23 : SchedWriteRes<[SBPort05]> { 670341825Sdim let Latency = 2; 671327952Sdim let NumMicroOps = 3; 672327952Sdim let ResourceCycles = [3]; 673327952Sdim} 674344779Sdimdef: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1", 675344779Sdim "RCR(8|16|32|64)r1")>; 676327952Sdim 677341825Sdimdef SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { 678341825Sdim let Latency = 7; 679327952Sdim let NumMicroOps = 3; 680341825Sdim let ResourceCycles = [1,2]; 681327952Sdim} 682341825Sdimdef: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; 683327952Sdim 684327952Sdimdef SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { 685327952Sdim let Latency = 3; 686327952Sdim let NumMicroOps = 3; 687327952Sdim let ResourceCycles = [1,1,1]; 688327952Sdim} 689341825Sdimdef: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 690327952Sdim 691327952Sdimdef SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { 692327952Sdim let Latency = 4; 693327952Sdim let NumMicroOps = 2; 694327952Sdim let ResourceCycles = [1,1]; 695327952Sdim} 696344779Sdimdef: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>; 697327952Sdim 698327952Sdimdef SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { 699327952Sdim let Latency = 4; 700327952Sdim let NumMicroOps = 4; 701327952Sdim let ResourceCycles = [1,3]; 702327952Sdim} 703341825Sdimdef: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; 704327952Sdim 705327952Sdimdef SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { 706327952Sdim let Latency = 5; 707327952Sdim let NumMicroOps = 1; 708327952Sdim let ResourceCycles = [1]; 709327952Sdim} 710341825Sdimdef: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", 711341825Sdim "MOVZX(16|32|64)rm(8|16)")>; 712327952Sdim 713344779Sdimdef SBWriteResGroup76 : SchedWriteRes<[SBPort05]> { 714344779Sdim let Latency = 5; 715344779Sdim let NumMicroOps = 8; 716344779Sdim let ResourceCycles = [8]; 717344779Sdim} 718344779Sdimdef: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)r(i|CL)", 719344779Sdim "RCR(8|16|32|64)r(i|CL)")>; 720344779Sdim 721327952Sdimdef SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { 722327952Sdim let Latency = 5; 723327952Sdim let NumMicroOps = 2; 724327952Sdim let ResourceCycles = [1,1]; 725327952Sdim} 726341825Sdimdef: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; 727327952Sdim 728327952Sdimdef SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { 729327952Sdim let Latency = 5; 730327952Sdim let NumMicroOps = 3; 731327952Sdim let ResourceCycles = [1,2]; 732327952Sdim} 733341825Sdimdef: InstRW<[SBWriteResGroup35], (instrs CLI)>; 734327952Sdim 735327952Sdimdef SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 736327952Sdim let Latency = 5; 737327952Sdim let NumMicroOps = 3; 738327952Sdim let ResourceCycles = [1,1,1]; 739327952Sdim} 740344779Sdimdef: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>; 741344779Sdimdef: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>; 742327952Sdim 743327952Sdimdef SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 744327952Sdim let Latency = 5; 745327952Sdim let NumMicroOps = 3; 746327952Sdim let ResourceCycles = [1,1,1]; 747327952Sdim} 748341825Sdimdef: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; 749341825Sdimdef: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", 750341825Sdim "(V?)EXTRACTPSmr")>; 751327952Sdim 752327952Sdimdef SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 753327952Sdim let Latency = 5; 754327952Sdim let NumMicroOps = 3; 755327952Sdim let ResourceCycles = [1,1,1]; 756327952Sdim} 757341825Sdimdef: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; 758327952Sdim 759327952Sdimdef SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { 760327952Sdim let Latency = 5; 761327952Sdim let NumMicroOps = 4; 762327952Sdim let ResourceCycles = [1,3]; 763327952Sdim} 764341825Sdimdef: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; 765327952Sdim 766327952Sdimdef SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { 767327952Sdim let Latency = 5; 768327952Sdim let NumMicroOps = 4; 769327952Sdim let ResourceCycles = [1,1,1,1]; 770327952Sdim} 771341825Sdimdef: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", 772341825Sdim "PUSHF(16|64)")>; 773327952Sdim 774327952Sdimdef SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 775327952Sdim let Latency = 5; 776327952Sdim let NumMicroOps = 4; 777327952Sdim let ResourceCycles = [1,1,1,1]; 778327952Sdim} 779327952Sdimdef: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; 780327952Sdim 781327952Sdimdef SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 782327952Sdim let Latency = 5; 783327952Sdim let NumMicroOps = 5; 784327952Sdim let ResourceCycles = [1,2,1,1]; 785327952Sdim} 786327952Sdimdef: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; 787327952Sdim 788327952Sdimdef SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { 789327952Sdim let Latency = 6; 790327952Sdim let NumMicroOps = 1; 791327952Sdim let ResourceCycles = [1]; 792327952Sdim} 793344779Sdimdef: InstRW<[SBWriteResGroup48], (instrs MMX_MOVD64from64rm, 794344779Sdim VBROADCASTSSrm)>; 795344779Sdimdef: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r", 796341825Sdim "(V?)MOV64toPQIrm", 797341825Sdim "(V?)MOVDDUPrm", 798341825Sdim "(V?)MOVDI2PDIrm", 799341825Sdim "(V?)MOVQI2PQIrm", 800341825Sdim "(V?)MOVSDrm", 801341825Sdim "(V?)MOVSHDUPrm", 802341825Sdim "(V?)MOVSLDUPrm", 803341825Sdim "(V?)MOVSSrm")>; 804327952Sdim 805327952Sdimdef SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { 806327952Sdim let Latency = 6; 807327952Sdim let NumMicroOps = 2; 808327952Sdim let ResourceCycles = [1,1]; 809327952Sdim} 810344779Sdimdef: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>; 811327952Sdim 812327952Sdimdef SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { 813327952Sdim let Latency = 6; 814327952Sdim let NumMicroOps = 2; 815327952Sdim let ResourceCycles = [1,1]; 816327952Sdim} 817344779Sdimdef: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm, 818344779Sdim MMX_PABSDrm, 819344779Sdim MMX_PABSWrm, 820344779Sdim MMX_PALIGNRrmi, 821344779Sdim MMX_PSIGNBrm, 822344779Sdim MMX_PSIGNDrm, 823344779Sdim MMX_PSIGNWrm)>; 824327952Sdim 825327952Sdimdef SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { 826327952Sdim let Latency = 6; 827327952Sdim let NumMicroOps = 2; 828327952Sdim let ResourceCycles = [1,1]; 829327952Sdim} 830341825Sdimdef: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; 831327952Sdim 832327952Sdimdef SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { 833327952Sdim let Latency = 6; 834327952Sdim let NumMicroOps = 3; 835327952Sdim let ResourceCycles = [1,2]; 836327952Sdim} 837341825Sdimdef: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", 838341825Sdim "ST_FP(32|64|80)m")>; 839327952Sdim 840327952Sdimdef SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { 841327952Sdim let Latency = 7; 842327952Sdim let NumMicroOps = 1; 843327952Sdim let ResourceCycles = [1]; 844327952Sdim} 845344779Sdimdef: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm, 846344779Sdim VBROADCASTSSYrm, 847344779Sdim VMOVDDUPYrm, 848344779Sdim VMOVSHDUPYrm, 849344779Sdim VMOVSLDUPYrm)>; 850327952Sdim 851327952Sdimdef SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { 852327952Sdim let Latency = 7; 853327952Sdim let NumMicroOps = 2; 854327952Sdim let ResourceCycles = [1,1]; 855327952Sdim} 856341825Sdimdef: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; 857327952Sdim 858327952Sdimdef SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { 859327952Sdim let Latency = 7; 860327952Sdim let NumMicroOps = 2; 861327952Sdim let ResourceCycles = [1,1]; 862327952Sdim} 863344779Sdimdef: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQirm)>; 864327952Sdim 865327952Sdimdef SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { 866327952Sdim let Latency = 7; 867327952Sdim let NumMicroOps = 3; 868327952Sdim let ResourceCycles = [2,1]; 869327952Sdim} 870344779Sdimdef: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>; 871327952Sdim 872327952Sdimdef SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { 873327952Sdim let Latency = 7; 874327952Sdim let NumMicroOps = 3; 875327952Sdim let ResourceCycles = [1,2]; 876327952Sdim} 877341825Sdimdef: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; 878327952Sdim 879327952Sdimdef SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 880327952Sdim let Latency = 7; 881327952Sdim let NumMicroOps = 3; 882327952Sdim let ResourceCycles = [1,1,1]; 883327952Sdim} 884341825Sdimdef: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>; 885327952Sdim 886327952Sdimdef SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { 887327952Sdim let Latency = 7; 888327952Sdim let NumMicroOps = 4; 889327952Sdim let ResourceCycles = [1,1,2]; 890327952Sdim} 891341825Sdimdef: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; 892327952Sdim 893327952Sdimdef SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { 894327952Sdim let Latency = 7; 895327952Sdim let NumMicroOps = 4; 896327952Sdim let ResourceCycles = [1,2,1]; 897327952Sdim} 898341825Sdimdef: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", 899341825Sdim "STR(16|32|64)r")>; 900327952Sdim 901327952Sdimdef SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 902327952Sdim let Latency = 7; 903327952Sdim let NumMicroOps = 4; 904327952Sdim let ResourceCycles = [1,1,2]; 905327952Sdim} 906341825Sdimdef: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; 907327952Sdimdef: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; 908327952Sdim 909327952Sdimdef SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 910327952Sdim let Latency = 7; 911327952Sdim let NumMicroOps = 4; 912327952Sdim let ResourceCycles = [1,2,1]; 913327952Sdim} 914344779Sdimdef: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 915344779Sdim "SHL(8|16|32|64)m(1|i)", 916344779Sdim "SHR(8|16|32|64)m(1|i)")>; 917327952Sdim 918327952Sdimdef SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 919327952Sdim let Latency = 8; 920327952Sdim let NumMicroOps = 3; 921327952Sdim let ResourceCycles = [1,1,1]; 922327952Sdim} 923341825Sdimdef: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; 924327952Sdim 925344779Sdimdef SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> { 926344779Sdim let Latency = 6; 927344779Sdim let NumMicroOps = 3; 928344779Sdim let ResourceCycles = [1, 2, 1]; 929327952Sdim} 930344779Sdimdef: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>; 931327952Sdim 932327952Sdimdef SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { 933327952Sdim let Latency = 8; 934327952Sdim let NumMicroOps = 5; 935327952Sdim let ResourceCycles = [2,3]; 936327952Sdim} 937341825Sdimdef: InstRW<[SBWriteResGroup83], (instrs CMPSB, 938341825Sdim CMPSL, 939341825Sdim CMPSQ, 940341825Sdim CMPSW)>; 941327952Sdim 942327952Sdimdef SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 943327952Sdim let Latency = 8; 944327952Sdim let NumMicroOps = 5; 945327952Sdim let ResourceCycles = [1,2,2]; 946327952Sdim} 947341825Sdimdef: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; 948327952Sdim 949327952Sdimdef SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 950327952Sdim let Latency = 8; 951327952Sdim let NumMicroOps = 5; 952327952Sdim let ResourceCycles = [1,2,2]; 953327952Sdim} 954344779Sdimdef: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)", 955344779Sdim "ROR(8|16|32|64)m(1|i)")>; 956327952Sdim 957327952Sdimdef SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 958327952Sdim let Latency = 8; 959327952Sdim let NumMicroOps = 5; 960327952Sdim let ResourceCycles = [1,2,2]; 961327952Sdim} 962341825Sdimdef: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 963341825Sdimdef: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; 964327952Sdim 965327952Sdimdef SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 966327952Sdim let Latency = 8; 967327952Sdim let NumMicroOps = 5; 968327952Sdim let ResourceCycles = [1,1,1,2]; 969327952Sdim} 970341825Sdimdef: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>; 971327952Sdim 972341825Sdimdef SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 973327952Sdim let Latency = 9; 974341825Sdim let NumMicroOps = 3; 975341825Sdim let ResourceCycles = [1,1,1]; 976327952Sdim} 977344779Sdimdef: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)(SD|SS)2SI(64)?rm")>; 978327952Sdim 979327952Sdimdef SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 980327952Sdim let Latency = 9; 981327952Sdim let NumMicroOps = 3; 982327952Sdim let ResourceCycles = [1,1,1]; 983327952Sdim} 984341825Sdimdef: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; 985327952Sdim 986327952Sdimdef SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 987327952Sdim let Latency = 9; 988327952Sdim let NumMicroOps = 4; 989327952Sdim let ResourceCycles = [1,1,2]; 990327952Sdim} 991341825Sdimdef: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", 992341825Sdim "IST_FP(16|32|64)m")>; 993327952Sdim 994327952Sdimdef SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 995327952Sdim let Latency = 9; 996327952Sdim let NumMicroOps = 6; 997327952Sdim let ResourceCycles = [1,2,3]; 998327952Sdim} 999341825Sdimdef: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", 1000341825Sdim "ROR(8|16|32|64)mCL", 1001341825Sdim "SAR(8|16|32|64)mCL", 1002341825Sdim "SHL(8|16|32|64)mCL", 1003341825Sdim "SHR(8|16|32|64)mCL")>; 1004327952Sdim 1005327952Sdimdef SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 1006327952Sdim let Latency = 9; 1007327952Sdim let NumMicroOps = 6; 1008327952Sdim let ResourceCycles = [1,2,3]; 1009327952Sdim} 1010341825Sdimdef: SchedAlias<WriteADCRMW, SBWriteResGroup98>; 1011327952Sdim 1012327952Sdimdef SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { 1013327952Sdim let Latency = 9; 1014327952Sdim let NumMicroOps = 6; 1015327952Sdim let ResourceCycles = [1,2,2,1]; 1016327952Sdim} 1017341825Sdimdef: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, 1018341825Sdim SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; 1019327952Sdim 1020327952Sdimdef SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { 1021327952Sdim let Latency = 9; 1022327952Sdim let NumMicroOps = 6; 1023327952Sdim let ResourceCycles = [1,1,2,1,1]; 1024327952Sdim} 1025344779Sdimdef : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW 1026327952Sdim 1027327952Sdimdef SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { 1028327952Sdim let Latency = 10; 1029327952Sdim let NumMicroOps = 2; 1030327952Sdim let ResourceCycles = [1,1]; 1031327952Sdim} 1032341825Sdimdef: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1033341825Sdim "ILD_F(16|32|64)m")>; 1034327952Sdim 1035327952Sdimdef SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { 1036327952Sdim let Latency = 11; 1037327952Sdim let NumMicroOps = 2; 1038327952Sdim let ResourceCycles = [1,1]; 1039327952Sdim} 1040341825Sdimdef: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; 1041327952Sdim 1042327952Sdimdef SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { 1043327952Sdim let Latency = 11; 1044327952Sdim let NumMicroOps = 3; 1045327952Sdim let ResourceCycles = [2,1]; 1046327952Sdim} 1047341825Sdimdef: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; 1048327952Sdim 1049344779Sdimdef SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> { 1050344779Sdim let Latency = 11; 1051344779Sdim let NumMicroOps = 11; 1052344779Sdim let ResourceCycles = [7,4]; 1053344779Sdim} 1054344779Sdimdef: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m", 1055344779Sdim "RCR(8|16|32|64)m")>; 1056344779Sdim 1057327952Sdimdef SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { 1058327952Sdim let Latency = 12; 1059327952Sdim let NumMicroOps = 2; 1060327952Sdim let ResourceCycles = [1,1]; 1061327952Sdim} 1062341825Sdimdef: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; 1063327952Sdim 1064327952Sdimdef SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { 1065327952Sdim let Latency = 13; 1066327952Sdim let NumMicroOps = 3; 1067327952Sdim let ResourceCycles = [2,1]; 1068327952Sdim} 1069341825Sdimdef: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1070327952Sdim 1071327952Sdimdef SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1072327952Sdim let Latency = 15; 1073327952Sdim let NumMicroOps = 3; 1074327952Sdim let ResourceCycles = [1,1,1]; 1075327952Sdim} 1076341825Sdimdef: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; 1077327952Sdim 1078327952Sdimdef SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { 1079327952Sdim let Latency = 31; 1080327952Sdim let NumMicroOps = 2; 1081327952Sdim let ResourceCycles = [1,1]; 1082327952Sdim} 1083341825Sdimdef: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; 1084327952Sdim 1085327952Sdimdef SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1086327952Sdim let Latency = 34; 1087327952Sdim let NumMicroOps = 3; 1088327952Sdim let ResourceCycles = [1,1,1]; 1089327952Sdim} 1090341825Sdimdef: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; 1091327952Sdim 1092344779Sdimdef SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> { 1093344779Sdim let Latency = 9; 1094344779Sdim let NumMicroOps = 20; 1095344779Sdim let ResourceCycles = [2]; 1096344779Sdim} 1097344779Sdimdef: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>; 1098344779Sdim 1099344779Sdimdef SBWriteResGroupVzeroupper : SchedWriteRes<[]> { 1100344779Sdim let Latency = 1; 1101344779Sdim let NumMicroOps = 4; 1102344779Sdim let ResourceCycles = []; 1103344779Sdim} 1104344779Sdimdef: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>; 1105344779Sdim 1106341825Sdimdef: InstRW<[WriteZero], (instrs CLC)>; 1107327952Sdim 1108344779Sdim// Intruction variants handled by the renamer. These might not need execution 1109344779Sdim// ports in certain conditions. 1110344779Sdim// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1111344779Sdim// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and 1112344779Sdim// renaming". 1113344779Sdim// These can be investigated with llvm-exegesis, e.g. 1114344779Sdim// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1115344779Sdim// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1116344779Sdim 1117344779Sdimdef SBWriteZeroLatency : SchedWriteRes<[]> { 1118344779Sdim let Latency = 0; 1119344779Sdim} 1120344779Sdim 1121344779Sdimdef SBWriteZeroIdiom : SchedWriteVariant<[ 1122344779Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1123344779Sdim SchedVar<NoSchedPred, [WriteALU]> 1124344779Sdim]>; 1125344779Sdimdef : InstRW<[SBWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1126344779Sdim XOR32rr, XOR64rr)>; 1127344779Sdim 1128344779Sdimdef SBWriteFZeroIdiom : SchedWriteVariant<[ 1129344779Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1130344779Sdim SchedVar<NoSchedPred, [WriteFLogic]> 1131344779Sdim]>; 1132344779Sdimdef : InstRW<[SBWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1133344779Sdim VXORPDrr)>; 1134344779Sdim 1135353358Sdimdef SBWriteFZeroIdiomY : SchedWriteVariant<[ 1136353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1137353358Sdim SchedVar<NoSchedPred, [WriteFLogicY]> 1138353358Sdim]>; 1139353358Sdimdef : InstRW<[SBWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1140353358Sdim 1141344779Sdimdef SBWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1142344779Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1143344779Sdim SchedVar<NoSchedPred, [WriteVecLogicX]> 1144344779Sdim]>; 1145344779Sdimdef : InstRW<[SBWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1146344779Sdim 1147344779Sdimdef SBWriteVZeroIdiomALUX : SchedWriteVariant<[ 1148344779Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1149344779Sdim SchedVar<NoSchedPred, [WriteVecALUX]> 1150344779Sdim]>; 1151344779Sdimdef : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1152344779Sdim PSUBDrr, VPSUBDrr, 1153344779Sdim PSUBQrr, VPSUBQrr, 1154344779Sdim PSUBWrr, VPSUBWrr, 1155344779Sdim PCMPGTBrr, VPCMPGTBrr, 1156344779Sdim PCMPGTDrr, VPCMPGTDrr, 1157344779Sdim PCMPGTWrr, VPCMPGTWrr)>; 1158344779Sdim 1159353358Sdimdef SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> { 1160353358Sdim let Latency = 5; 1161353358Sdim let NumMicroOps = 1; 1162353358Sdim let ResourceCycles = [1]; 1163353358Sdim} 1164353358Sdim 1165344779Sdimdef SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1166344779Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1167353358Sdim SchedVar<NoSchedPred, [SBWritePCMPGTQ]> 1168344779Sdim]>; 1169344779Sdimdef : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>; 1170344779Sdim 1171353358Sdim// CMOVs that use both Z and C flag require an extra uop. 1172353358Sdimdef SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> { 1173353358Sdim let Latency = 3; 1174353358Sdim let ResourceCycles = [2,1]; 1175353358Sdim let NumMicroOps = 3; 1176353358Sdim} 1177353358Sdim 1178353358Sdimdef SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> { 1179353358Sdim let Latency = 8; 1180353358Sdim let ResourceCycles = [1,2,1]; 1181353358Sdim let NumMicroOps = 4; 1182353358Sdim} 1183353358Sdim 1184353358Sdimdef SBCMOVA_CMOVBErr : SchedWriteVariant<[ 1185353358Sdim SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SBWriteCMOVA_CMOVBErr]>, 1186353358Sdim SchedVar<NoSchedPred, [WriteCMOV]> 1187353358Sdim]>; 1188353358Sdim 1189353358Sdimdef SBCMOVA_CMOVBErm : SchedWriteVariant<[ 1190353358Sdim SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>, 1191353358Sdim SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1192353358Sdim]>; 1193353358Sdim 1194353358Sdimdef : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1195353358Sdimdef : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1196353358Sdim 1197353358Sdim// SETCCs that use both Z and C flag require an extra uop. 1198353358Sdimdef SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> { 1199353358Sdim let Latency = 2; 1200353358Sdim let ResourceCycles = [2]; 1201353358Sdim let NumMicroOps = 2; 1202353358Sdim} 1203353358Sdim 1204353358Sdimdef SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 1205353358Sdim let Latency = 3; 1206353358Sdim let ResourceCycles = [1,1,2]; 1207353358Sdim let NumMicroOps = 4; 1208353358Sdim} 1209353358Sdim 1210353358Sdimdef SBSETA_SETBErr : SchedWriteVariant<[ 1211353358Sdim SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>, 1212353358Sdim SchedVar<NoSchedPred, [WriteSETCC]> 1213353358Sdim]>; 1214353358Sdim 1215353358Sdimdef SBSETA_SETBErm : SchedWriteVariant<[ 1216353358Sdim SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SBWriteSETA_SETBEm]>, 1217353358Sdim SchedVar<NoSchedPred, [WriteSETCCStore]> 1218353358Sdim]>; 1219353358Sdim 1220353358Sdimdef : InstRW<[SBSETA_SETBErr], (instrs SETCCr)>; 1221353358Sdimdef : InstRW<[SBSETA_SETBErm], (instrs SETCCm)>; 1222353358Sdim 1223249259Sdim} // SchedModel 1224