1249259Sdim//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 2249259Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6249259Sdim// 7249259Sdim//===----------------------------------------------------------------------===// 8249259Sdim// 9249259Sdim// This file defines the machine model for Haswell to support instruction 10249259Sdim// scheduling and other instruction cost heuristics. 11249259Sdim// 12341825Sdim// Note that we define some instructions here that are not supported by haswell, 13341825Sdim// but we still have to define them because KNL uses the HSW model. 14341825Sdim// They are currently tagged with a comment `Unsupported = 1`. 15341825Sdim// FIXME: Use Unsupported = 1 once KNL has its own model. 16341825Sdim// 17249259Sdim//===----------------------------------------------------------------------===// 18249259Sdim 19249259Sdimdef HaswellModel : SchedMachineModel { 20249259Sdim // All x86 instructions are modeled as a single micro-op, and HW can decode 4 21249259Sdim // instructions per cycle. 22249259Sdim let IssueWidth = 4; 23261991Sdim let MicroOpBufferSize = 192; // Based on the reorder buffer. 24327952Sdim let LoadLatency = 5; 25249259Sdim let MispredictPenalty = 16; 26261991Sdim 27276479Sdim // Based on the LSD (loop-stream detector) queue size and benchmarking data. 28276479Sdim let LoopMicroOpBufferSize = 50; 29276479Sdim 30341825Sdim // This flag is set to allow the scheduler to assign a default model to 31327952Sdim // unrecognized opcodes. 32261991Sdim let CompleteModel = 0; 33249259Sdim} 34249259Sdim 35249259Sdimlet SchedModel = HaswellModel in { 36249259Sdim 37249259Sdim// Haswell can issue micro-ops to 8 different ports in one cycle. 38249259Sdim 39276479Sdim// Ports 0, 1, 5, and 6 handle all computation. 40249259Sdim// Port 4 gets the data half of stores. Store data can be available later than 41249259Sdim// the store address, but since we don't model the latency of stores, we can 42249259Sdim// ignore that. 43249259Sdim// Ports 2 and 3 are identical. They handle loads and the address half of 44249259Sdim// stores. Port 7 can handle address calculations. 45249259Sdimdef HWPort0 : ProcResource<1>; 46249259Sdimdef HWPort1 : ProcResource<1>; 47249259Sdimdef HWPort2 : ProcResource<1>; 48249259Sdimdef HWPort3 : ProcResource<1>; 49249259Sdimdef HWPort4 : ProcResource<1>; 50249259Sdimdef HWPort5 : ProcResource<1>; 51249259Sdimdef HWPort6 : ProcResource<1>; 52249259Sdimdef HWPort7 : ProcResource<1>; 53249259Sdim 54249259Sdim// Many micro-ops are capable of issuing on multiple ports. 55280031Sdimdef HWPort01 : ProcResGroup<[HWPort0, HWPort1]>; 56249259Sdimdef HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 57249259Sdimdef HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 58280031Sdimdef HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; 59249259Sdimdef HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 60280031Sdimdef HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; 61249259Sdimdef HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 62276479Sdimdef HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; 63280031Sdimdef HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; 64249259Sdimdef HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 65280031Sdimdef HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; 66249259Sdimdef HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 67249259Sdim 68261991Sdim// 60 Entry Unified Scheduler 69261991Sdimdef HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 70261991Sdim HWPort5, HWPort6, HWPort7]> { 71261991Sdim let BufferSize=60; 72261991Sdim} 73261991Sdim 74249259Sdim// Integer division issued on port 0. 75249259Sdimdef HWDivider : ProcResource<1>; 76341825Sdim// FP division and sqrt on port 0. 77341825Sdimdef HWFPDivider : ProcResource<1>; 78249259Sdim 79344779Sdim// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 80249259Sdim// cycles after the memory operand. 81327952Sdimdef : ReadAdvance<ReadAfterLd, 5>; 82249259Sdim 83344779Sdim// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 84344779Sdim// until 5/6/7 cycles after the memory operand. 85344779Sdimdef : ReadAdvance<ReadAfterVecLd, 5>; 86344779Sdimdef : ReadAdvance<ReadAfterVecXLd, 6>; 87344779Sdimdef : ReadAdvance<ReadAfterVecYLd, 7>; 88344779Sdim 89353358Sdimdef : ReadAdvance<ReadInt2Fpu, 0>; 90353358Sdim 91249259Sdim// Many SchedWrites are defined in pairs with and without a folded load. 92249259Sdim// Instructions with folded loads are usually micro-fused, so they only appear 93249259Sdim// as two micro-ops when queued in the reservation station. 94249259Sdim// This multiclass defines the resource usage for variants with and without 95249259Sdim// folded loads. 96249259Sdimmulticlass HWWriteResPair<X86FoldableSchedWrite SchedRW, 97341825Sdim list<ProcResourceKind> ExePorts, 98341825Sdim int Lat, list<int> Res = [1], int UOps = 1, 99341825Sdim int LoadLat = 5> { 100249259Sdim // Register variant is using a single cycle on ExePort. 101341825Sdim def : WriteRes<SchedRW, ExePorts> { 102341825Sdim let Latency = Lat; 103341825Sdim let ResourceCycles = Res; 104341825Sdim let NumMicroOps = UOps; 105341825Sdim } 106249259Sdim 107341825Sdim // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 108341825Sdim // the latency (default = 5). 109341825Sdim def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> { 110341825Sdim let Latency = !add(Lat, LoadLat); 111341825Sdim let ResourceCycles = !listconcat([1], Res); 112341825Sdim let NumMicroOps = !add(UOps, 1); 113249259Sdim } 114249259Sdim} 115249259Sdim 116341825Sdim// A folded store needs a cycle on port 4 for the store data, and an extra port 117341825Sdim// 2/3/7 cycle to recompute the address. 118341825Sdimdef : WriteRes<WriteRMW, [HWPort237,HWPort4]>; 119249259Sdim 120276479Sdim// Store_addr on 237. 121276479Sdim// Store_data on 4. 122341825Sdimdefm : X86WriteRes<WriteStore, [HWPort237, HWPort4], 1, [1,1], 1>; 123341825Sdimdefm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>; 124341825Sdimdefm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>; 125341825Sdimdefm : X86WriteRes<WriteMove, [HWPort0156], 1, [1], 1>; 126341825Sdimdef : WriteRes<WriteZero, []>; 127249259Sdim 128341825Sdim// Arithmetic. 129341825Sdimdefm : HWWriteResPair<WriteALU, [HWPort0156], 1>; 130341825Sdimdefm : HWWriteResPair<WriteADC, [HWPort06, HWPort0156], 2, [1,1], 2>; 131341825Sdim 132344779Sdim// Integer multiplication. 133344779Sdimdefm : HWWriteResPair<WriteIMul8, [HWPort1], 3>; 134344779Sdimdefm : HWWriteResPair<WriteIMul16, [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>; 135344779Sdimdefm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>; 136344779Sdimdefm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>; 137344779Sdimdefm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>; 138344779Sdimdefm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>; 139344779Sdimdefm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>; 140344779Sdimdefm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>; 141344779Sdimdefm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>; 142344779Sdimdefm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>; 143344779Sdimdefm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>; 144344779Sdimdef : WriteRes<WriteIMulH, []> { let Latency = 3; } 145344779Sdim 146341825Sdimdefm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>; 147341825Sdimdefm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>; 148344779Sdimdefm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>; 149344779Sdimdefm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>; 150344779Sdimdefm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>; 151341825Sdim 152341825Sdim// Integer shifts and rotates. 153344779Sdimdefm : HWWriteResPair<WriteShift, [HWPort06], 1>; 154344779Sdimdefm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 155353358Sdimdefm : HWWriteResPair<WriteRotate, [HWPort06], 1, [1], 1>; 156344779Sdimdefm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 157341825Sdim 158341825Sdim// SHLD/SHRD. 159341825Sdimdefm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>; 160341825Sdimdefm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>; 161341825Sdimdefm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>; 162341825Sdimdefm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>; 163341825Sdim 164341825Sdimdefm : HWWriteResPair<WriteJump, [HWPort06], 1>; 165341825Sdimdefm : HWWriteResPair<WriteCRC32, [HWPort1], 3>; 166341825Sdim 167341825Sdimdefm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move. 168341825Sdimdefm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move. 169341825Sdimdef : WriteRes<WriteSETCC, [HWPort06]>; // Setcc. 170341825Sdimdef : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> { 171341825Sdim let Latency = 2; 172341825Sdim let NumMicroOps = 3; 173341825Sdim} 174341825Sdim 175344779Sdimdefm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>; 176344779Sdimdefm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>; 177344779Sdimdefm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>; 178344779Sdimdefm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>; 179344779Sdimdefm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>; 180344779Sdimdefm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>; 181344779Sdim//defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>; 182344779Sdim 183249259Sdim// This is for simple LEAs with one or two input operands. 184249259Sdim// The complex ones can only execute on port 1, and they require two cycles on 185249259Sdim// the port to read all inputs. We don't model that. 186249259Sdimdef : WriteRes<WriteLEA, [HWPort15]>; 187249259Sdim 188341825Sdim// Bit counts. 189341825Sdimdefm : HWWriteResPair<WriteBSF, [HWPort1], 3>; 190341825Sdimdefm : HWWriteResPair<WriteBSR, [HWPort1], 3>; 191341825Sdimdefm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>; 192341825Sdimdefm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>; 193341825Sdimdefm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>; 194249259Sdim 195344779Sdim// BMI1 BEXTR/BLS, BMI2 BZHI 196341825Sdimdefm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>; 197344779Sdimdefm : HWWriteResPair<WriteBLS, [HWPort15], 1>; 198344779Sdimdefm : HWWriteResPair<WriteBZHI, [HWPort15], 1>; 199341825Sdim 200344779Sdim// TODO: Why isn't the HWDivider used? 201344779Sdimdefm : X86WriteRes<WriteDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>; 202344779Sdimdefm : X86WriteRes<WriteDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 203344779Sdimdefm : X86WriteRes<WriteDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 204344779Sdimdefm : X86WriteRes<WriteDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 205344779Sdimdefm : X86WriteRes<WriteDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 206344779Sdimdefm : X86WriteRes<WriteDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 207344779Sdimdefm : X86WriteRes<WriteDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 208344779Sdimdefm : X86WriteRes<WriteDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 209341825Sdim 210344779Sdimdefm : X86WriteRes<WriteIDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>; 211344779Sdimdefm : X86WriteRes<WriteIDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 212344779Sdimdefm : X86WriteRes<WriteIDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 213344779Sdimdefm : X86WriteRes<WriteIDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 214344779Sdimdefm : X86WriteRes<WriteIDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 215344779Sdimdefm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 216344779Sdimdefm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 217344779Sdimdefm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 218344779Sdim 219249259Sdim// Scalar and vector floating point. 220341825Sdimdefm : X86WriteRes<WriteFLD0, [HWPort01], 1, [1], 1>; 221341825Sdimdefm : X86WriteRes<WriteFLD1, [HWPort01], 1, [2], 2>; 222341825Sdimdefm : X86WriteRes<WriteFLDC, [HWPort01], 1, [2], 2>; 223341825Sdimdefm : X86WriteRes<WriteFLoad, [HWPort23], 5, [1], 1>; 224341825Sdimdefm : X86WriteRes<WriteFLoadX, [HWPort23], 6, [1], 1>; 225341825Sdimdefm : X86WriteRes<WriteFLoadY, [HWPort23], 7, [1], 1>; 226341825Sdimdefm : X86WriteRes<WriteFMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 227341825Sdimdefm : X86WriteRes<WriteFMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 228341825Sdimdefm : X86WriteRes<WriteFStore, [HWPort237,HWPort4], 1, [1,1], 2>; 229341825Sdimdefm : X86WriteRes<WriteFStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 230341825Sdimdefm : X86WriteRes<WriteFStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 231341825Sdimdefm : X86WriteRes<WriteFStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 232341825Sdimdefm : X86WriteRes<WriteFStoreNTX, [HWPort237,HWPort4], 1, [1,1], 2>; 233341825Sdimdefm : X86WriteRes<WriteFStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 234360784Sdim 235360784Sdimdefm : X86WriteRes<WriteFMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 236360784Sdimdefm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 237360784Sdimdefm : X86WriteRes<WriteFMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 238360784Sdimdefm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 239360784Sdim 240341825Sdimdefm : X86WriteRes<WriteFMove, [HWPort5], 1, [1], 1>; 241341825Sdimdefm : X86WriteRes<WriteFMoveX, [HWPort5], 1, [1], 1>; 242341825Sdimdefm : X86WriteRes<WriteFMoveY, [HWPort5], 1, [1], 1>; 243341825Sdimdefm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>; 244249259Sdim 245341825Sdimdefm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>; 246341825Sdimdefm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>; 247341825Sdimdefm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>; 248341825Sdimdefm : HWWriteResPair<WriteFAddZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 249341825Sdimdefm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>; 250341825Sdimdefm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>; 251341825Sdimdefm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>; 252341825Sdimdefm : HWWriteResPair<WriteFAdd64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 253276479Sdim 254341825Sdimdefm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>; 255341825Sdimdefm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>; 256341825Sdimdefm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>; 257341825Sdimdefm : HWWriteResPair<WriteFCmpZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 258341825Sdimdefm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>; 259341825Sdimdefm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>; 260341825Sdimdefm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>; 261341825Sdimdefm : HWWriteResPair<WriteFCmp64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 262341825Sdim 263341825Sdimdefm : HWWriteResPair<WriteFCom, [HWPort1], 3>; 264341825Sdim 265341825Sdimdefm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>; 266341825Sdimdefm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>; 267341825Sdimdefm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>; 268341825Sdimdefm : HWWriteResPair<WriteFMulZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 269341825Sdimdefm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>; 270341825Sdimdefm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>; 271341825Sdimdefm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>; 272341825Sdimdefm : HWWriteResPair<WriteFMul64Z, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 273341825Sdim 274341825Sdimdefm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>; 275341825Sdimdefm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>; 276341825Sdimdefm : HWWriteResPair<WriteFDivY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 277341825Sdimdefm : HWWriteResPair<WriteFDivZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 278341825Sdimdefm : HWWriteResPair<WriteFDiv64, [HWPort0,HWFPDivider], 20, [1,14], 1, 5>; 279341825Sdimdefm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>; 280341825Sdimdefm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 281341825Sdimdefm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 282341825Sdim 283341825Sdimdefm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>; 284341825Sdimdefm : HWWriteResPair<WriteFRcpX, [HWPort0], 5, [1], 1, 6>; 285341825Sdimdefm : HWWriteResPair<WriteFRcpY, [HWPort0,HWPort015], 11, [2,1], 3, 7>; 286341825Sdimdefm : HWWriteResPair<WriteFRcpZ, [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 287341825Sdim 288341825Sdimdefm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5, [1], 1, 5>; 289341825Sdimdefm : HWWriteResPair<WriteFRsqrtX,[HWPort0], 5, [1], 1, 6>; 290341825Sdimdefm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>; 291341825Sdimdefm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 292341825Sdim 293341825Sdimdefm : HWWriteResPair<WriteFSqrt, [HWPort0,HWFPDivider], 11, [1,7], 1, 5>; 294341825Sdimdefm : HWWriteResPair<WriteFSqrtX, [HWPort0,HWFPDivider], 11, [1,7], 1, 6>; 295341825Sdimdefm : HWWriteResPair<WriteFSqrtY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 296341825Sdimdefm : HWWriteResPair<WriteFSqrtZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 297341825Sdimdefm : HWWriteResPair<WriteFSqrt64, [HWPort0,HWFPDivider], 16, [1,14], 1, 5>; 298341825Sdimdefm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>; 299341825Sdimdefm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 300341825Sdimdefm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 301341825Sdimdefm : HWWriteResPair<WriteFSqrt80, [HWPort0,HWFPDivider], 23, [1,17]>; 302341825Sdim 303341825Sdimdefm : HWWriteResPair<WriteFMA, [HWPort01], 5, [1], 1, 5>; 304341825Sdimdefm : HWWriteResPair<WriteFMAX, [HWPort01], 5, [1], 1, 6>; 305341825Sdimdefm : HWWriteResPair<WriteFMAY, [HWPort01], 5, [1], 1, 7>; 306341825Sdimdefm : HWWriteResPair<WriteFMAZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 307341825Sdimdefm : HWWriteResPair<WriteDPPD, [HWPort0,HWPort1,HWPort5], 9, [1,1,1], 3, 6>; 308341825Sdimdefm : HWWriteResPair<WriteDPPS, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>; 309341825Sdimdefm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; 310341825Sdimdefm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1 311341825Sdimdefm : HWWriteResPair<WriteFSign, [HWPort0], 1>; 312341825Sdimdefm : X86WriteRes<WriteFRnd, [HWPort23], 6, [1], 1>; 313341825Sdimdefm : X86WriteRes<WriteFRndY, [HWPort23], 6, [1], 1>; 314341825Sdimdefm : X86WriteRes<WriteFRndZ, [HWPort23], 6, [1], 1>; // Unsupported = 1 315341825Sdimdefm : X86WriteRes<WriteFRndLd, [HWPort1,HWPort23], 12, [2,1], 3>; 316341825Sdimdefm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>; 317341825Sdimdefm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1 318341825Sdimdefm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>; 319341825Sdimdefm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>; 320341825Sdimdefm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 321341825Sdimdefm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>; 322341825Sdimdefm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>; 323341825Sdimdefm : HWWriteResPair<WriteFTestZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 324341825Sdimdefm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>; 325341825Sdimdefm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>; 326341825Sdimdefm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 327341825Sdimdefm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>; 328341825Sdimdefm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>; 329341825Sdimdefm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 330341825Sdimdefm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>; 331341825Sdimdefm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>; 332341825Sdimdefm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1 333341825Sdimdefm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>; 334341825Sdimdefm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>; 335341825Sdimdefm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>; 336341825Sdimdefm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>; 337341825Sdimdefm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 338341825Sdim 339341825Sdim// Conversion between integer and float. 340341825Sdimdefm : HWWriteResPair<WriteCvtSD2I, [HWPort1], 3>; 341341825Sdimdefm : HWWriteResPair<WriteCvtPD2I, [HWPort1], 3>; 342341825Sdimdefm : HWWriteResPair<WriteCvtPD2IY, [HWPort1], 3>; 343341825Sdimdefm : HWWriteResPair<WriteCvtPD2IZ, [HWPort1], 3>; // Unsupported = 1 344341825Sdimdefm : HWWriteResPair<WriteCvtSS2I, [HWPort1], 3>; 345341825Sdimdefm : HWWriteResPair<WriteCvtPS2I, [HWPort1], 3>; 346341825Sdimdefm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3>; 347341825Sdimdefm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3>; // Unsupported = 1 348341825Sdim 349341825Sdimdefm : HWWriteResPair<WriteCvtI2SD, [HWPort1], 4>; 350341825Sdimdefm : HWWriteResPair<WriteCvtI2PD, [HWPort1], 4>; 351341825Sdimdefm : HWWriteResPair<WriteCvtI2PDY, [HWPort1], 4>; 352341825Sdimdefm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1], 4>; // Unsupported = 1 353341825Sdimdefm : HWWriteResPair<WriteCvtI2SS, [HWPort1], 4>; 354341825Sdimdefm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 4>; 355341825Sdimdefm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 4>; 356341825Sdimdefm : HWWriteResPair<WriteCvtI2PSZ, [HWPort1], 4>; // Unsupported = 1 357341825Sdim 358341825Sdimdefm : HWWriteResPair<WriteCvtSS2SD, [HWPort1], 3>; 359341825Sdimdefm : HWWriteResPair<WriteCvtPS2PD, [HWPort1], 3>; 360341825Sdimdefm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>; 361341825Sdimdefm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1 362341825Sdimdefm : HWWriteResPair<WriteCvtSD2SS, [HWPort1], 3>; 363341825Sdimdefm : HWWriteResPair<WriteCvtPD2PS, [HWPort1], 3>; 364341825Sdimdefm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>; 365341825Sdimdefm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1 366341825Sdim 367341825Sdimdefm : X86WriteRes<WriteCvtPH2PS, [HWPort0,HWPort5], 2, [1,1], 2>; 368341825Sdimdefm : X86WriteRes<WriteCvtPH2PSY, [HWPort0,HWPort5], 2, [1,1], 2>; 369341825Sdimdefm : X86WriteRes<WriteCvtPH2PSZ, [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1 370341825Sdimdefm : X86WriteRes<WriteCvtPH2PSLd, [HWPort0,HWPort23], 6, [1,1], 2>; 371341825Sdimdefm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>; 372341825Sdimdefm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1 373341825Sdim 374341825Sdimdefm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>; 375341825Sdimdefm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>; 376341825Sdimdefm : X86WriteRes<WriteCvtPS2PHZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1 377341825Sdimdefm : X86WriteRes<WriteCvtPS2PHSt, [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>; 378341825Sdimdefm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; 379341825Sdimdefm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1 380341825Sdim 381249259Sdim// Vector integer operations. 382341825Sdimdefm : X86WriteRes<WriteVecLoad, [HWPort23], 5, [1], 1>; 383341825Sdimdefm : X86WriteRes<WriteVecLoadX, [HWPort23], 6, [1], 1>; 384341825Sdimdefm : X86WriteRes<WriteVecLoadY, [HWPort23], 7, [1], 1>; 385341825Sdimdefm : X86WriteRes<WriteVecLoadNT, [HWPort23], 6, [1], 1>; 386341825Sdimdefm : X86WriteRes<WriteVecLoadNTY, [HWPort23], 7, [1], 1>; 387341825Sdimdefm : X86WriteRes<WriteVecMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 388341825Sdimdefm : X86WriteRes<WriteVecMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 389341825Sdimdefm : X86WriteRes<WriteVecStore, [HWPort237,HWPort4], 1, [1,1], 2>; 390341825Sdimdefm : X86WriteRes<WriteVecStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 391341825Sdimdefm : X86WriteRes<WriteVecStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 392341825Sdimdefm : X86WriteRes<WriteVecStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 393341825Sdimdefm : X86WriteRes<WriteVecStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 394341825Sdimdefm : X86WriteRes<WriteVecMaskedStore, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 395341825Sdimdefm : X86WriteRes<WriteVecMaskedStoreY, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 396341825Sdimdefm : X86WriteRes<WriteVecMove, [HWPort015], 1, [1], 1>; 397341825Sdimdefm : X86WriteRes<WriteVecMoveX, [HWPort015], 1, [1], 1>; 398341825Sdimdefm : X86WriteRes<WriteVecMoveY, [HWPort015], 1, [1], 1>; 399341825Sdimdefm : X86WriteRes<WriteVecMoveToGpr, [HWPort0], 1, [1], 1>; 400341825Sdimdefm : X86WriteRes<WriteVecMoveFromGpr, [HWPort5], 1, [1], 1>; 401249259Sdim 402341825Sdimdefm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>; 403341825Sdimdefm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>; 404341825Sdimdefm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>; 405341825Sdimdefm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1 406341825Sdimdefm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 407341825Sdimdefm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>; 408341825Sdimdefm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1 409341825Sdimdefm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 5>; 410341825Sdimdefm : HWWriteResPair<WriteVecALUX, [HWPort15], 1, [1], 1, 6>; 411341825Sdimdefm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>; 412341825Sdimdefm : HWWriteResPair<WriteVecALUZ, [HWPort15], 1, [1], 1, 7>; // Unsupported = 1 413341825Sdimdefm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>; 414341825Sdimdefm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>; 415341825Sdimdefm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>; 416341825Sdimdefm : HWWriteResPair<WriteVecIMulZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 417341825Sdimdefm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; 418341825Sdimdefm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>; 419341825Sdimdefm : HWWriteResPair<WritePMULLDZ, [HWPort0], 10, [2], 2, 7>; // Unsupported = 1 420341825Sdimdefm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>; 421341825Sdimdefm : HWWriteResPair<WriteShuffleX, [HWPort5], 1, [1], 1, 6>; 422341825Sdimdefm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>; 423341825Sdimdefm : HWWriteResPair<WriteShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 424341825Sdimdefm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>; 425341825Sdimdefm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>; 426341825Sdimdefm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>; 427341825Sdimdefm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1 428341825Sdimdefm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>; 429341825Sdimdefm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>; 430341825Sdimdefm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 431341825Sdimdefm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>; 432341825Sdimdefm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>; 433341825Sdimdefm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>; 434341825Sdimdefm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>; 435341825Sdimdefm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 436341825Sdimdefm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>; 437341825Sdimdefm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; 438341825Sdimdefm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1 439341825Sdimdefm : HWWriteResPair<WritePSADBW, [HWPort0], 5, [1], 1, 5>; 440341825Sdimdefm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>; 441341825Sdimdefm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>; 442341825Sdimdefm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 443341825Sdimdefm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>; 444341825Sdim 445341825Sdim// Vector integer shifts. 446341825Sdimdefm : HWWriteResPair<WriteVecShift, [HWPort0], 1, [1], 1, 5>; 447341825Sdimdefm : HWWriteResPair<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 448341825Sdimdefm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>; 449341825Sdimdefm : X86WriteRes<WriteVecShiftZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1 450341825Sdimdefm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>; 451341825Sdimdefm : X86WriteRes<WriteVecShiftZLd, [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1 452341825Sdim 453341825Sdimdefm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>; 454341825Sdimdefm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>; 455341825Sdimdefm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>; 456341825Sdimdefm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 457341825Sdimdefm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>; 458341825Sdimdefm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>; 459341825Sdimdefm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1 460341825Sdim 461341825Sdim// Vector insert/extract operations. 462341825Sdimdef : WriteRes<WriteVecInsert, [HWPort5]> { 463276479Sdim let Latency = 2; 464341825Sdim let NumMicroOps = 2; 465276479Sdim let ResourceCycles = [2]; 466276479Sdim} 467341825Sdimdef : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> { 468276479Sdim let Latency = 6; 469341825Sdim let NumMicroOps = 2; 470276479Sdim} 471341825Sdimdef: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 472276479Sdim 473341825Sdimdef : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> { 474276479Sdim let Latency = 2; 475341825Sdim let NumMicroOps = 2; 476276479Sdim} 477341825Sdimdef : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> { 478341825Sdim let Latency = 2; 479341825Sdim let NumMicroOps = 3; 480276479Sdim} 481276479Sdim 482341825Sdim// String instructions. 483276479Sdim 484276479Sdim// Packed Compare Implicit Length Strings, Return Mask 485276479Sdimdef : WriteRes<WritePCmpIStrM, [HWPort0]> { 486341825Sdim let Latency = 11; 487341825Sdim let NumMicroOps = 3; 488276479Sdim let ResourceCycles = [3]; 489276479Sdim} 490276479Sdimdef : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> { 491341825Sdim let Latency = 17; 492341825Sdim let NumMicroOps = 4; 493341825Sdim let ResourceCycles = [3,1]; 494276479Sdim} 495276479Sdim 496276479Sdim// Packed Compare Explicit Length Strings, Return Mask 497341825Sdimdef : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> { 498341825Sdim let Latency = 19; 499341825Sdim let NumMicroOps = 9; 500341825Sdim let ResourceCycles = [4,3,1,1]; 501276479Sdim} 502341825Sdimdef : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> { 503341825Sdim let Latency = 25; 504341825Sdim let NumMicroOps = 10; 505341825Sdim let ResourceCycles = [4,3,1,1,1]; 506276479Sdim} 507276479Sdim 508276479Sdim// Packed Compare Implicit Length Strings, Return Index 509276479Sdimdef : WriteRes<WritePCmpIStrI, [HWPort0]> { 510276479Sdim let Latency = 11; 511341825Sdim let NumMicroOps = 3; 512276479Sdim let ResourceCycles = [3]; 513276479Sdim} 514276479Sdimdef : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> { 515341825Sdim let Latency = 17; 516341825Sdim let NumMicroOps = 4; 517341825Sdim let ResourceCycles = [3,1]; 518276479Sdim} 519276479Sdim 520276479Sdim// Packed Compare Explicit Length Strings, Return Index 521341825Sdimdef : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> { 522341825Sdim let Latency = 18; 523341825Sdim let NumMicroOps = 8; 524341825Sdim let ResourceCycles = [4,3,1]; 525276479Sdim} 526341825Sdimdef : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> { 527341825Sdim let Latency = 24; 528341825Sdim let NumMicroOps = 9; 529341825Sdim let ResourceCycles = [4,3,1,1]; 530276479Sdim} 531276479Sdim 532341825Sdim// MOVMSK Instructions. 533341825Sdimdef : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; } 534341825Sdimdef : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; } 535341825Sdimdef : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; } 536341825Sdimdef : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; } 537341825Sdim 538276479Sdim// AES Instructions. 539276479Sdimdef : WriteRes<WriteAESDecEnc, [HWPort5]> { 540276479Sdim let Latency = 7; 541341825Sdim let NumMicroOps = 1; 542276479Sdim let ResourceCycles = [1]; 543276479Sdim} 544276479Sdimdef : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> { 545341825Sdim let Latency = 13; 546341825Sdim let NumMicroOps = 2; 547341825Sdim let ResourceCycles = [1,1]; 548276479Sdim} 549276479Sdim 550276479Sdimdef : WriteRes<WriteAESIMC, [HWPort5]> { 551276479Sdim let Latency = 14; 552341825Sdim let NumMicroOps = 2; 553276479Sdim let ResourceCycles = [2]; 554276479Sdim} 555276479Sdimdef : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> { 556341825Sdim let Latency = 20; 557341825Sdim let NumMicroOps = 3; 558341825Sdim let ResourceCycles = [2,1]; 559276479Sdim} 560276479Sdim 561341825Sdimdef : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> { 562341825Sdim let Latency = 29; 563341825Sdim let NumMicroOps = 11; 564341825Sdim let ResourceCycles = [2,7,2]; 565276479Sdim} 566341825Sdimdef : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> { 567341825Sdim let Latency = 34; 568341825Sdim let NumMicroOps = 11; 569341825Sdim let ResourceCycles = [2,7,1,1]; 570276479Sdim} 571276479Sdim 572276479Sdim// Carry-less multiplication instructions. 573276479Sdimdef : WriteRes<WriteCLMul, [HWPort0, HWPort5]> { 574341825Sdim let Latency = 11; 575341825Sdim let NumMicroOps = 3; 576341825Sdim let ResourceCycles = [2,1]; 577276479Sdim} 578276479Sdimdef : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> { 579341825Sdim let Latency = 17; 580341825Sdim let NumMicroOps = 4; 581341825Sdim let ResourceCycles = [2,1,1]; 582276479Sdim} 583276479Sdim 584341825Sdim// Load/store MXCSR. 585341825Sdimdef : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 586341825Sdimdef : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 587341825Sdim 588249259Sdimdef : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 589249259Sdimdef : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 590276479Sdimdef : WriteRes<WriteFence, [HWPort23, HWPort4]>; 591276479Sdimdef : WriteRes<WriteNop, []>; 592280031Sdim 593280031Sdim//================ Exceptions ================// 594280031Sdim 595280031Sdim//-- Specific Scheduling Models --// 596280031Sdim 597280031Sdim// Starting with P0. 598341825Sdimdef HWWriteP0 : SchedWriteRes<[HWPort0]>; 599280031Sdim 600341825Sdimdef HWWriteP01 : SchedWriteRes<[HWPort01]>; 601280031Sdim 602341825Sdimdef HWWrite2P01 : SchedWriteRes<[HWPort01]> { 603280031Sdim let NumMicroOps = 2; 604280031Sdim} 605341825Sdimdef HWWrite3P01 : SchedWriteRes<[HWPort01]> { 606280031Sdim let NumMicroOps = 3; 607280031Sdim} 608280031Sdim 609341825Sdimdef HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 610280031Sdim let NumMicroOps = 2; 611280031Sdim} 612280031Sdim 613341825Sdimdef HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 614280031Sdim let NumMicroOps = 3; 615280031Sdim let ResourceCycles = [2, 1]; 616280031Sdim} 617280031Sdim 618280031Sdim// Starting with P1. 619341825Sdimdef HWWriteP1 : SchedWriteRes<[HWPort1]>; 620280031Sdim 621280031Sdim 622341825Sdimdef HWWrite2P1 : SchedWriteRes<[HWPort1]> { 623280031Sdim let NumMicroOps = 2; 624280031Sdim let ResourceCycles = [2]; 625280031Sdim} 626280031Sdim 627280031Sdim// Notation: 628280031Sdim// - r: register. 629280031Sdim// - mm: 64 bit mmx register. 630280031Sdim// - x = 128 bit xmm register. 631280031Sdim// - (x)mm = mmx or xmm register. 632280031Sdim// - y = 256 bit ymm register. 633280031Sdim// - v = any vector register. 634280031Sdim// - m = memory. 635280031Sdim 636280031Sdim//=== Integer Instructions ===// 637280031Sdim//-- Move instructions --// 638280031Sdim 639280031Sdim// XLAT. 640341825Sdimdef HWWriteXLAT : SchedWriteRes<[]> { 641280031Sdim let Latency = 7; 642280031Sdim let NumMicroOps = 3; 643280031Sdim} 644341825Sdimdef : InstRW<[HWWriteXLAT], (instrs XLAT)>; 645280031Sdim 646280031Sdim// PUSHA. 647341825Sdimdef HWWritePushA : SchedWriteRes<[]> { 648280031Sdim let NumMicroOps = 19; 649280031Sdim} 650341825Sdimdef : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; 651280031Sdim 652280031Sdim// POPA. 653341825Sdimdef HWWritePopA : SchedWriteRes<[]> { 654280031Sdim let NumMicroOps = 18; 655280031Sdim} 656341825Sdimdef : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; 657280031Sdim 658280031Sdim//-- Arithmetic instructions --// 659280031Sdim 660280031Sdim// BTR BTS BTC. 661280031Sdim// m,r. 662341825Sdimdef HWWriteBTRSCmr : SchedWriteRes<[]> { 663280031Sdim let NumMicroOps = 11; 664280031Sdim} 665344779Sdimdef : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>; 666280031Sdim 667280031Sdim//-- Control transfer instructions --// 668280031Sdim 669280031Sdim// CALL. 670280031Sdim// i. 671341825Sdimdef HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { 672280031Sdim let NumMicroOps = 4; 673280031Sdim let ResourceCycles = [1, 2, 1]; 674280031Sdim} 675341825Sdimdef : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; 676280031Sdim 677280031Sdim// BOUND. 678280031Sdim// r,m. 679341825Sdimdef HWWriteBOUND : SchedWriteRes<[]> { 680280031Sdim let NumMicroOps = 15; 681280031Sdim} 682341825Sdimdef : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; 683280031Sdim 684280031Sdim// INTO. 685341825Sdimdef HWWriteINTO : SchedWriteRes<[]> { 686280031Sdim let NumMicroOps = 4; 687280031Sdim} 688341825Sdimdef : InstRW<[HWWriteINTO], (instrs INTO)>; 689280031Sdim 690280031Sdim//-- String instructions --// 691280031Sdim 692280031Sdim// LODSB/W. 693341825Sdimdef : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; 694280031Sdim 695280031Sdim// LODSD/Q. 696341825Sdimdef : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; 697280031Sdim 698280031Sdim// MOVS. 699341825Sdimdef HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { 700280031Sdim let Latency = 4; 701280031Sdim let NumMicroOps = 5; 702280031Sdim let ResourceCycles = [2, 1, 2]; 703280031Sdim} 704341825Sdimdef : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 705280031Sdim 706280031Sdim// CMPS. 707341825Sdimdef HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { 708280031Sdim let Latency = 4; 709280031Sdim let NumMicroOps = 5; 710280031Sdim let ResourceCycles = [2, 3]; 711280031Sdim} 712341825Sdimdef : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; 713280031Sdim 714280031Sdim//-- Other --// 715280031Sdim 716327952Sdim// RDPMC.f 717341825Sdimdef HWWriteRDPMC : SchedWriteRes<[]> { 718280031Sdim let NumMicroOps = 34; 719280031Sdim} 720341825Sdimdef : InstRW<[HWWriteRDPMC], (instrs RDPMC)>; 721280031Sdim 722280031Sdim// RDRAND. 723341825Sdimdef HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { 724280031Sdim let NumMicroOps = 17; 725280031Sdim let ResourceCycles = [1, 16]; 726280031Sdim} 727344779Sdimdef : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 728280031Sdim 729280031Sdim//=== Floating Point x87 Instructions ===// 730280031Sdim//-- Move instructions --// 731280031Sdim 732280031Sdim// FLD. 733280031Sdim// m80. 734344779Sdimdef : InstRW<[HWWriteP01], (instrs LD_Frr)>; 735280031Sdim 736280031Sdim// FBLD. 737280031Sdim// m80. 738341825Sdimdef HWWriteFBLD : SchedWriteRes<[]> { 739280031Sdim let Latency = 47; 740280031Sdim let NumMicroOps = 43; 741280031Sdim} 742344779Sdimdef : InstRW<[HWWriteFBLD], (instrs FBLDm)>; 743280031Sdim 744280031Sdim// FST(P). 745280031Sdim// r. 746341825Sdimdef : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; 747280031Sdim 748280031Sdim// FFREE. 749341825Sdimdef : InstRW<[HWWriteP01], (instregex "FFREE")>; 750280031Sdim 751280031Sdim// FNSAVE. 752341825Sdimdef HWWriteFNSAVE : SchedWriteRes<[]> { 753280031Sdim let NumMicroOps = 147; 754280031Sdim} 755344779Sdimdef : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>; 756280031Sdim 757280031Sdim// FRSTOR. 758341825Sdimdef HWWriteFRSTOR : SchedWriteRes<[]> { 759280031Sdim let NumMicroOps = 90; 760280031Sdim} 761344779Sdimdef : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>; 762280031Sdim 763280031Sdim//-- Arithmetic instructions --// 764280031Sdim 765280031Sdim// FCOMPP FUCOMPP. 766280031Sdim// r. 767341825Sdimdef : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>; 768280031Sdim 769280031Sdim// FCOMI(P) FUCOMI(P). 770280031Sdim// m. 771341825Sdimdef : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 772280031Sdim 773280031Sdim// FTST. 774341825Sdimdef : InstRW<[HWWriteP1], (instregex "TST_F")>; 775280031Sdim 776280031Sdim// FXAM. 777341825Sdimdef : InstRW<[HWWrite2P1], (instrs FXAM)>; 778280031Sdim 779280031Sdim// FPREM. 780341825Sdimdef HWWriteFPREM : SchedWriteRes<[]> { 781280031Sdim let Latency = 19; 782280031Sdim let NumMicroOps = 28; 783280031Sdim} 784341825Sdimdef : InstRW<[HWWriteFPREM], (instrs FPREM)>; 785280031Sdim 786280031Sdim// FPREM1. 787341825Sdimdef HWWriteFPREM1 : SchedWriteRes<[]> { 788280031Sdim let Latency = 27; 789280031Sdim let NumMicroOps = 41; 790280031Sdim} 791341825Sdimdef : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; 792280031Sdim 793280031Sdim// FRNDINT. 794341825Sdimdef HWWriteFRNDINT : SchedWriteRes<[]> { 795280031Sdim let Latency = 11; 796280031Sdim let NumMicroOps = 17; 797280031Sdim} 798341825Sdimdef : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>; 799280031Sdim 800280031Sdim//-- Math instructions --// 801280031Sdim 802280031Sdim// FSCALE. 803341825Sdimdef HWWriteFSCALE : SchedWriteRes<[]> { 804280031Sdim let Latency = 75; // 49-125 805280031Sdim let NumMicroOps = 50; // 25-75 806280031Sdim} 807341825Sdimdef : InstRW<[HWWriteFSCALE], (instrs FSCALE)>; 808280031Sdim 809280031Sdim// FXTRACT. 810341825Sdimdef HWWriteFXTRACT : SchedWriteRes<[]> { 811280031Sdim let Latency = 15; 812280031Sdim let NumMicroOps = 17; 813280031Sdim} 814341825Sdimdef : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>; 815280031Sdim 816327952Sdim//////////////////////////////////////////////////////////////////////////////// 817327952Sdim// Horizontal add/sub instructions. 818327952Sdim//////////////////////////////////////////////////////////////////////////////// 819280031Sdim 820341825Sdimdefm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>; 821341825Sdimdefm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>; 822341825Sdimdefm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 5>; 823341825Sdimdefm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>; 824341825Sdimdefm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>; 825280031Sdim 826327952Sdim//=== Floating Point XMM and YMM Instructions ===// 827280031Sdim 828327952Sdim// Remaining instrs. 829280031Sdim 830327952Sdimdef HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { 831327952Sdim let Latency = 6; 832327952Sdim let NumMicroOps = 1; 833327952Sdim let ResourceCycles = [1]; 834327952Sdim} 835344779Sdimdef: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>; 836344779Sdimdef: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm", 837341825Sdim "(V?)MOVSLDUPrm", 838341825Sdim "VPBROADCAST(D|Q)rm")>; 839280031Sdim 840327952Sdimdef HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> { 841327952Sdim let Latency = 7; 842327952Sdim let NumMicroOps = 1; 843327952Sdim let ResourceCycles = [1]; 844327952Sdim} 845344779Sdimdef: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128, 846344779Sdim VBROADCASTI128, 847344779Sdim VBROADCASTSDYrm, 848344779Sdim VBROADCASTSSYrm, 849344779Sdim VMOVDDUPYrm, 850344779Sdim VMOVSHDUPYrm, 851344779Sdim VMOVSLDUPYrm)>; 852341825Sdimdef: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m", 853341825Sdim "VPBROADCAST(D|Q)Yrm")>; 854280031Sdim 855327952Sdimdef HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> { 856327952Sdim let Latency = 5; 857327952Sdim let NumMicroOps = 1; 858327952Sdim let ResourceCycles = [1]; 859327952Sdim} 860344779Sdimdef: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm(8|16|32)", 861344779Sdim "MOVZX(16|32|64)rm(8|16)", 862341825Sdim "(V?)MOVDDUPrm")>; 863280031Sdim 864327952Sdimdef HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { 865327952Sdim let Latency = 1; 866327952Sdim let NumMicroOps = 2; 867327952Sdim let ResourceCycles = [1,1]; 868327952Sdim} 869344779Sdimdef: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>; 870344779Sdimdef: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>; 871280031Sdim 872327952Sdimdef HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { 873327952Sdim let Latency = 1; 874327952Sdim let NumMicroOps = 1; 875327952Sdim let ResourceCycles = [1]; 876280031Sdim} 877341825Sdimdef: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr", 878341825Sdim "VPSRLVQ(Y?)rr")>; 879280031Sdim 880327952Sdimdef HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { 881327952Sdim let Latency = 1; 882327952Sdim let NumMicroOps = 1; 883327952Sdim let ResourceCycles = [1]; 884280031Sdim} 885341825Sdimdef: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r", 886341825Sdim "UCOM_F(P?)r")>; 887280031Sdim 888327952Sdimdef HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { 889327952Sdim let Latency = 1; 890280031Sdim let NumMicroOps = 1; 891327952Sdim let ResourceCycles = [1]; 892280031Sdim} 893344779Sdimdef: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>; 894280031Sdim 895327952Sdimdef HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { 896327952Sdim let Latency = 1; 897327952Sdim let NumMicroOps = 1; 898327952Sdim let ResourceCycles = [1]; 899327952Sdim} 900327952Sdimdef: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>; 901280031Sdim 902327952Sdimdef HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { 903327952Sdim let Latency = 1; 904327952Sdim let NumMicroOps = 1; 905327952Sdim let ResourceCycles = [1]; 906327952Sdim} 907341825Sdimdef: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>; 908327952Sdim 909327952Sdimdef HWWriteResGroup7 : SchedWriteRes<[HWPort06]> { 910327952Sdim let Latency = 1; 911327952Sdim let NumMicroOps = 1; 912327952Sdim let ResourceCycles = [1]; 913327952Sdim} 914341825Sdimdef: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>; 915327952Sdim 916327952Sdimdef HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { 917327952Sdim let Latency = 1; 918327952Sdim let NumMicroOps = 1; 919327952Sdim let ResourceCycles = [1]; 920327952Sdim} 921344779Sdimdef: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>; 922327952Sdim 923327952Sdimdef HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { 924327952Sdim let Latency = 1; 925327952Sdim let NumMicroOps = 1; 926327952Sdim let ResourceCycles = [1]; 927327952Sdim} 928341825Sdimdef: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>; 929327952Sdim 930327952Sdimdef HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { 931327952Sdim let Latency = 1; 932327952Sdim let NumMicroOps = 1; 933327952Sdim let ResourceCycles = [1]; 934327952Sdim} 935341825Sdimdef: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE, 936344779Sdim CMC, STC, 937344779Sdim SGDT64m, 938344779Sdim SIDT64m, 939344779Sdim SMSW16m, 940344779Sdim STRm, 941344779Sdim SYSCALL)>; 942327952Sdim 943327952Sdimdef HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> { 944327952Sdim let Latency = 6; 945280031Sdim let NumMicroOps = 2; 946327952Sdim let ResourceCycles = [1,1]; 947280031Sdim} 948341825Sdimdef: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>; 949280031Sdim 950327952Sdimdef HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> { 951327952Sdim let Latency = 7; 952327952Sdim let NumMicroOps = 2; 953327952Sdim let ResourceCycles = [1,1]; 954327952Sdim} 955344779Sdimdef: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>; 956344779Sdimdef: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>; 957280031Sdim 958327952Sdimdef HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> { 959327952Sdim let Latency = 8; 960280031Sdim let NumMicroOps = 2; 961327952Sdim let ResourceCycles = [1,1]; 962280031Sdim} 963344779Sdimdef: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>; 964280031Sdim 965327952Sdimdef HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> { 966327952Sdim let Latency = 8; 967327952Sdim let NumMicroOps = 2; 968327952Sdim let ResourceCycles = [1,1]; 969280031Sdim} 970344779Sdimdef: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>; 971344779Sdimdef: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>; 972280031Sdim 973327952Sdimdef HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> { 974341825Sdim let Latency = 6; 975327952Sdim let NumMicroOps = 2; 976327952Sdim let ResourceCycles = [1,1]; 977280031Sdim} 978341825Sdimdef: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm", 979341825Sdim "(V?)PMOV(SX|ZX)BQrm", 980341825Sdim "(V?)PMOV(SX|ZX)BWrm", 981341825Sdim "(V?)PMOV(SX|ZX)DQrm", 982341825Sdim "(V?)PMOV(SX|ZX)WDrm", 983341825Sdim "(V?)PMOV(SX|ZX)WQrm")>; 984280031Sdim 985327952Sdimdef HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> { 986327952Sdim let Latency = 8; 987327952Sdim let NumMicroOps = 2; 988327952Sdim let ResourceCycles = [1,1]; 989280031Sdim} 990344779Sdimdef: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm, 991344779Sdim VPMOVSXBQYrm, 992344779Sdim VPMOVSXWQYrm)>; 993280031Sdim 994327952Sdimdef HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> { 995327952Sdim let Latency = 6; 996327952Sdim let NumMicroOps = 2; 997327952Sdim let ResourceCycles = [1,1]; 998280031Sdim} 999344779Sdimdef: InstRW<[HWWriteResGroup14], (instrs FARJMP64)>; 1000344779Sdimdef: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>; 1001280031Sdim 1002327952Sdimdef HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { 1003327952Sdim let Latency = 6; 1004327952Sdim let NumMicroOps = 2; 1005327952Sdim let ResourceCycles = [1,1]; 1006327952Sdim} 1007341825Sdimdef: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm", 1008341825Sdim "MOVBE(16|32|64)rm")>; 1009327952Sdim 1010327952Sdimdef HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { 1011327952Sdim let Latency = 7; 1012327952Sdim let NumMicroOps = 2; 1013327952Sdim let ResourceCycles = [1,1]; 1014327952Sdim} 1015344779Sdimdef: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm, 1016344779Sdim VINSERTI128rm, 1017344779Sdim VPBLENDDrmi)>; 1018327952Sdim 1019327952Sdimdef HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> { 1020327952Sdim let Latency = 8; 1021327952Sdim let NumMicroOps = 2; 1022327952Sdim let ResourceCycles = [1,1]; 1023327952Sdim} 1024344779Sdimdef: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>; 1025327952Sdim 1026327952Sdimdef HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> { 1027327952Sdim let Latency = 6; 1028327952Sdim let NumMicroOps = 2; 1029327952Sdim let ResourceCycles = [1,1]; 1030327952Sdim} 1031341825Sdimdef: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>; 1032341825Sdimdef: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>; 1033327952Sdim 1034327952Sdimdef HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> { 1035280031Sdim let Latency = 2; 1036280031Sdim let NumMicroOps = 2; 1037327952Sdim let ResourceCycles = [1,1]; 1038280031Sdim} 1039341825Sdimdef: InstRW<[HWWriteResGroup19], (instrs SFENCE)>; 1040280031Sdim 1041327952Sdimdef HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { 1042327952Sdim let Latency = 2; 1043280031Sdim let NumMicroOps = 3; 1044327952Sdim let ResourceCycles = [1,1,1]; 1045280031Sdim} 1046341825Sdimdef: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>; 1047280031Sdim 1048327952Sdimdef HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { 1049327952Sdim let Latency = 2; 1050327952Sdim let NumMicroOps = 3; 1051327952Sdim let ResourceCycles = [1,1,1]; 1052280031Sdim} 1053327952Sdimdef: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>; 1054280031Sdim 1055327952Sdimdef HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { 1056327952Sdim let Latency = 2; 1057327952Sdim let NumMicroOps = 3; 1058327952Sdim let ResourceCycles = [1,1,1]; 1059280031Sdim} 1060341825Sdimdef: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>; 1061280031Sdim 1062327952Sdimdef HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 1063327952Sdim let Latency = 2; 1064327952Sdim let NumMicroOps = 3; 1065327952Sdim let ResourceCycles = [1,1,1]; 1066280031Sdim} 1067344779Sdimdef: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 1068341825Sdim STOSB, STOSL, STOSQ, STOSW)>; 1069344779Sdimdef: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>; 1070280031Sdim 1071327952Sdimdef HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 1072327952Sdim let Latency = 7; 1073327952Sdim let NumMicroOps = 4; 1074327952Sdim let ResourceCycles = [1,1,1,1]; 1075280031Sdim} 1076344779Sdimdef: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)", 1077344779Sdim "SHL(8|16|32|64)m(1|i)", 1078344779Sdim "SHR(8|16|32|64)m(1|i)")>; 1079280031Sdim 1080327952Sdimdef HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1081327952Sdim let Latency = 7; 1082327952Sdim let NumMicroOps = 4; 1083327952Sdim let ResourceCycles = [1,1,1,1]; 1084280031Sdim} 1085341825Sdimdef: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm", 1086341825Sdim "PUSH(16|32|64)rmm")>; 1087280031Sdim 1088327952Sdimdef HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { 1089327952Sdim let Latency = 2; 1090327952Sdim let NumMicroOps = 2; 1091327952Sdim let ResourceCycles = [2]; 1092280031Sdim} 1093341825Sdimdef: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; 1094280031Sdim 1095327952Sdimdef HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { 1096327952Sdim let Latency = 2; 1097327952Sdim let NumMicroOps = 2; 1098327952Sdim let ResourceCycles = [2]; 1099327952Sdim} 1100341825Sdimdef: InstRW<[HWWriteResGroup30], (instrs LFENCE, 1101341825Sdim MFENCE, 1102341825Sdim WAIT, 1103341825Sdim XGETBV)>; 1104280031Sdim 1105327952Sdimdef HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> { 1106327952Sdim let Latency = 2; 1107327952Sdim let NumMicroOps = 2; 1108327952Sdim let ResourceCycles = [1,1]; 1109327952Sdim} 1110341825Sdimdef: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr", 1111341825Sdim "(V?)CVTSS2SDrr")>; 1112321369Sdim 1113327952Sdimdef HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> { 1114327952Sdim let Latency = 2; 1115327952Sdim let NumMicroOps = 2; 1116327952Sdim let ResourceCycles = [1,1]; 1117327952Sdim} 1118327952Sdimdef: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>; 1119327952Sdim 1120327952Sdimdef HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> { 1121327952Sdim let Latency = 2; 1122327952Sdim let NumMicroOps = 2; 1123327952Sdim let ResourceCycles = [1,1]; 1124327952Sdim} 1125344779Sdimdef: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>; 1126327952Sdim 1127327952Sdimdef HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> { 1128327952Sdim let Latency = 2; 1129327952Sdim let NumMicroOps = 2; 1130327952Sdim let ResourceCycles = [1,1]; 1131327952Sdim} 1132341825Sdimdef: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; 1133327952Sdim 1134327952Sdimdef HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> { 1135327952Sdim let Latency = 7; 1136321369Sdim let NumMicroOps = 3; 1137327952Sdim let ResourceCycles = [2,1]; 1138321369Sdim} 1139344779Sdimdef: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm, 1140344779Sdim MMX_PACKSSWBirm, 1141344779Sdim MMX_PACKUSWBirm)>; 1142327952Sdim 1143327952Sdimdef HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> { 1144327952Sdim let Latency = 7; 1145321369Sdim let NumMicroOps = 3; 1146327952Sdim let ResourceCycles = [1,2]; 1147321369Sdim} 1148341825Sdimdef: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64, 1149341825Sdim SCASB, SCASL, SCASQ, SCASW)>; 1150321369Sdim 1151327952Sdimdef HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { 1152327952Sdim let Latency = 7; 1153280031Sdim let NumMicroOps = 3; 1154327952Sdim let ResourceCycles = [1,1,1]; 1155280031Sdim} 1156341825Sdimdef: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; 1157280031Sdim 1158327952Sdimdef HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 1159327952Sdim let Latency = 7; 1160327952Sdim let NumMicroOps = 3; 1161327952Sdim let ResourceCycles = [1,1,1]; 1162327952Sdim} 1163341825Sdimdef: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>; 1164327952Sdim 1165327952Sdimdef HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { 1166327952Sdim let Latency = 3; 1167327952Sdim let NumMicroOps = 4; 1168327952Sdim let ResourceCycles = [1,1,1,1]; 1169327952Sdim} 1170327952Sdimdef: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; 1171327952Sdim 1172327952Sdimdef HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 1173327952Sdim let Latency = 3; 1174327952Sdim let NumMicroOps = 4; 1175327952Sdim let ResourceCycles = [1,1,1,1]; 1176327952Sdim} 1177341825Sdimdef: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>; 1178327952Sdim 1179327952Sdimdef HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 1180327952Sdim let Latency = 8; 1181327952Sdim let NumMicroOps = 5; 1182327952Sdim let ResourceCycles = [1,1,1,2]; 1183327952Sdim} 1184344779Sdimdef: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)", 1185344779Sdim "ROR(8|16|32|64)m(1|i)")>; 1186327952Sdim 1187353358Sdimdef HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> { 1188353358Sdim let Latency = 2; 1189353358Sdim let NumMicroOps = 2; 1190353358Sdim let ResourceCycles = [2]; 1191353358Sdim} 1192353358Sdimdef: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1193353358Sdim ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1194353358Sdim 1195327952Sdimdef HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1196327952Sdim let Latency = 8; 1197327952Sdim let NumMicroOps = 5; 1198327952Sdim let ResourceCycles = [1,1,1,2]; 1199327952Sdim} 1200341825Sdimdef: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>; 1201327952Sdim 1202327952Sdimdef HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1203327952Sdim let Latency = 8; 1204327952Sdim let NumMicroOps = 5; 1205327952Sdim let ResourceCycles = [1,1,1,1,1]; 1206327952Sdim} 1207344779Sdimdef: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>; 1208344779Sdimdef: InstRW<[HWWriteResGroup48], (instrs FARCALL64)>; 1209327952Sdim 1210327952Sdimdef HWWriteResGroup50 : SchedWriteRes<[HWPort1]> { 1211327952Sdim let Latency = 3; 1212327952Sdim let NumMicroOps = 1; 1213327952Sdim let ResourceCycles = [1]; 1214327952Sdim} 1215344779Sdimdef: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>; 1216344779Sdimdef: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr", 1217341825Sdim "(V?)CVTDQ2PS(Y?)rr")>; 1218327952Sdim 1219327952Sdimdef HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { 1220327952Sdim let Latency = 3; 1221327952Sdim let NumMicroOps = 1; 1222327952Sdim let ResourceCycles = [1]; 1223327952Sdim} 1224341825Sdimdef: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>; 1225327952Sdim 1226327952Sdimdef HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> { 1227327952Sdim let Latency = 9; 1228280031Sdim let NumMicroOps = 2; 1229327952Sdim let ResourceCycles = [1,1]; 1230280031Sdim} 1231341825Sdimdef: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm", 1232341825Sdim "(V?)CVTTPS2DQrm")>; 1233280031Sdim 1234327952Sdimdef HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> { 1235280031Sdim let Latency = 10; 1236280031Sdim let NumMicroOps = 2; 1237327952Sdim let ResourceCycles = [1,1]; 1238280031Sdim} 1239341825Sdimdef: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1240344779Sdim "ILD_F(16|32|64)m")>; 1241344779Sdimdef: InstRW<[HWWriteResGroup52_1], (instrs VCVTDQ2PSYrm, 1242344779Sdim VCVTPS2DQYrm, 1243344779Sdim VCVTTPS2DQYrm)>; 1244280031Sdim 1245327952Sdimdef HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> { 1246327952Sdim let Latency = 9; 1247280031Sdim let NumMicroOps = 2; 1248327952Sdim let ResourceCycles = [1,1]; 1249280031Sdim} 1250344779Sdimdef: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm, 1251344779Sdim VPMOVSXDQYrm, 1252344779Sdim VPMOVSXWDYrm, 1253344779Sdim VPMOVZXWDYrm)>; 1254280031Sdim 1255327952Sdimdef HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> { 1256327952Sdim let Latency = 3; 1257327952Sdim let NumMicroOps = 3; 1258327952Sdim let ResourceCycles = [2,1]; 1259327952Sdim} 1260344779Sdimdef: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr, 1261344779Sdim MMX_PACKSSWBirr, 1262344779Sdim MMX_PACKUSWBirr)>; 1263280031Sdim 1264327952Sdimdef HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> { 1265327952Sdim let Latency = 3; 1266327952Sdim let NumMicroOps = 3; 1267327952Sdim let ResourceCycles = [1,2]; 1268280031Sdim} 1269327952Sdimdef: InstRW<[HWWriteResGroup58], (instregex "CLD")>; 1270280031Sdim 1271327952Sdimdef HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { 1272327952Sdim let Latency = 3; 1273327952Sdim let NumMicroOps = 3; 1274327952Sdim let ResourceCycles = [1,2]; 1275327952Sdim} 1276344779Sdimdef: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)", 1277344779Sdim "RCR(8|16|32|64)r(1|i)")>; 1278280031Sdim 1279327952Sdimdef HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { 1280327952Sdim let Latency = 4; 1281327952Sdim let NumMicroOps = 3; 1282327952Sdim let ResourceCycles = [1,1,1]; 1283280031Sdim} 1284341825Sdimdef: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>; 1285280031Sdim 1286327952Sdimdef HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { 1287327952Sdim let Latency = 4; 1288327952Sdim let NumMicroOps = 3; 1289327952Sdim let ResourceCycles = [1,1,1]; 1290327952Sdim} 1291341825Sdimdef: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", 1292341825Sdim "IST_F(16|32)m")>; 1293280031Sdim 1294327952Sdimdef HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { 1295327952Sdim let Latency = 9; 1296327952Sdim let NumMicroOps = 5; 1297327952Sdim let ResourceCycles = [1,1,1,2]; 1298327952Sdim} 1299344779Sdimdef: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)", 1300344779Sdim "RCR(8|16|32|64)m(1|i)")>; 1301327952Sdim 1302327952Sdimdef HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1303327952Sdim let Latency = 9; 1304327952Sdim let NumMicroOps = 6; 1305327952Sdim let ResourceCycles = [1,1,1,3]; 1306327952Sdim} 1307341825Sdimdef: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>; 1308327952Sdim 1309327952Sdimdef HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1310327952Sdim let Latency = 9; 1311327952Sdim let NumMicroOps = 6; 1312327952Sdim let ResourceCycles = [1,1,1,2,1]; 1313327952Sdim} 1314344779Sdimdef: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL", 1315344779Sdim "ROR(8|16|32|64)mCL", 1316341825Sdim "SAR(8|16|32|64)mCL", 1317341825Sdim "SHL(8|16|32|64)mCL", 1318341825Sdim "SHR(8|16|32|64)mCL")>; 1319341825Sdimdef: SchedAlias<WriteADCRMW, HWWriteResGroup69>; 1320327952Sdim 1321327952Sdimdef HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { 1322280031Sdim let Latency = 4; 1323280031Sdim let NumMicroOps = 2; 1324327952Sdim let ResourceCycles = [1,1]; 1325280031Sdim} 1326341825Sdimdef: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr", 1327341825Sdim "(V?)CVT(T?)SS2SI(64)?rr")>; 1328280031Sdim 1329327952Sdimdef HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { 1330327952Sdim let Latency = 4; 1331327952Sdim let NumMicroOps = 2; 1332327952Sdim let ResourceCycles = [1,1]; 1333327952Sdim} 1334344779Sdimdef: InstRW<[HWWriteResGroup71], (instrs VCVTPS2PDYrr)>; 1335280031Sdim 1336327952Sdimdef HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> { 1337280031Sdim let Latency = 4; 1338280031Sdim let NumMicroOps = 2; 1339327952Sdim let ResourceCycles = [1,1]; 1340280031Sdim} 1341341825Sdimdef: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>; 1342280031Sdim 1343327952Sdimdef HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { 1344280031Sdim let Latency = 4; 1345327952Sdim let NumMicroOps = 2; 1346327952Sdim let ResourceCycles = [1,1]; 1347280031Sdim} 1348344779Sdimdef: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr, 1349344779Sdim MMX_CVTPD2PIirr, 1350344779Sdim MMX_CVTPS2PIirr, 1351344779Sdim MMX_CVTTPD2PIirr, 1352344779Sdim MMX_CVTTPS2PIirr)>; 1353344779Sdimdef: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr", 1354341825Sdim "(V?)CVTPD2PSrr", 1355341825Sdim "(V?)CVTSD2SSrr", 1356341825Sdim "(V?)CVTSI(64)?2SDrr", 1357341825Sdim "(V?)CVTSI2SSrr", 1358341825Sdim "(V?)CVT(T?)PD2DQrr")>; 1359280031Sdim 1360327952Sdimdef HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { 1361327952Sdim let Latency = 11; 1362327952Sdim let NumMicroOps = 3; 1363327952Sdim let ResourceCycles = [2,1]; 1364280031Sdim} 1365341825Sdimdef: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>; 1366280031Sdim 1367327952Sdimdef HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1368327952Sdim let Latency = 9; 1369327952Sdim let NumMicroOps = 3; 1370327952Sdim let ResourceCycles = [1,1,1]; 1371280031Sdim} 1372341825Sdimdef: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm", 1373341825Sdim "(V?)CVTSS2SI(64)?rm", 1374341825Sdim "(V?)CVTTSD2SI(64)?rm", 1375341825Sdim "VCVTTSS2SI64rm", 1376341825Sdim "(V?)CVTTSS2SIrm")>; 1377280031Sdim 1378327952Sdimdef HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { 1379327952Sdim let Latency = 10; 1380327952Sdim let NumMicroOps = 3; 1381327952Sdim let ResourceCycles = [1,1,1]; 1382280031Sdim} 1383344779Sdimdef: InstRW<[HWWriteResGroup77], (instrs VCVTPS2PDYrm)>; 1384280031Sdim 1385327952Sdimdef HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1386327952Sdim let Latency = 10; 1387327952Sdim let NumMicroOps = 3; 1388327952Sdim let ResourceCycles = [1,1,1]; 1389280031Sdim} 1390344779Sdimdef: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm, 1391344779Sdim CVTPD2DQrm, 1392344779Sdim CVTTPD2DQrm, 1393344779Sdim MMX_CVTPD2PIirm, 1394344779Sdim MMX_CVTTPD2PIirm, 1395344779Sdim CVTDQ2PDrm, 1396344779Sdim VCVTDQ2PDrm)>; 1397280031Sdim 1398327952Sdimdef HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1399327952Sdim let Latency = 9; 1400327952Sdim let NumMicroOps = 3; 1401327952Sdim let ResourceCycles = [1,1,1]; 1402280031Sdim} 1403344779Sdimdef: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm, 1404353358Sdim CVTSD2SSrm, CVTSD2SSrm_Int, 1405353358Sdim VCVTSD2SSrm, VCVTSD2SSrm_Int)>; 1406280031Sdim 1407327952Sdimdef HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { 1408327952Sdim let Latency = 9; 1409327952Sdim let NumMicroOps = 3; 1410327952Sdim let ResourceCycles = [1,1,1]; 1411327952Sdim} 1412341825Sdimdef: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>; 1413280031Sdim 1414327952Sdimdef HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> { 1415327952Sdim let Latency = 4; 1416327952Sdim let NumMicroOps = 4; 1417327952Sdim let ResourceCycles = [4]; 1418327952Sdim} 1419341825Sdimdef: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>; 1420280031Sdim 1421344779Sdimdef HWWriteResGroup82 : SchedWriteRes<[]> { 1422344779Sdim let Latency = 0; 1423327952Sdim let NumMicroOps = 4; 1424344779Sdim let ResourceCycles = []; 1425327952Sdim} 1426341825Sdimdef: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; 1427280031Sdim 1428327952Sdimdef HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { 1429327952Sdim let Latency = 4; 1430327952Sdim let NumMicroOps = 4; 1431327952Sdim let ResourceCycles = [1,1,2]; 1432327952Sdim} 1433327952Sdimdef: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>; 1434327952Sdim 1435327952Sdimdef HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { 1436327952Sdim let Latency = 9; 1437327952Sdim let NumMicroOps = 5; 1438327952Sdim let ResourceCycles = [1,2,1,1]; 1439327952Sdim} 1440341825Sdimdef: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm", 1441341825Sdim "LSL(16|32|64)rm")>; 1442280031Sdim 1443327952Sdimdef HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 1444327952Sdim let Latency = 5; 1445327952Sdim let NumMicroOps = 6; 1446327952Sdim let ResourceCycles = [1,1,4]; 1447280031Sdim} 1448341825Sdimdef: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>; 1449280031Sdim 1450327952Sdimdef HWWriteResGroup89 : SchedWriteRes<[HWPort0]> { 1451280031Sdim let Latency = 5; 1452327952Sdim let NumMicroOps = 1; 1453327952Sdim let ResourceCycles = [1]; 1454280031Sdim} 1455353358Sdimdef: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 1456280031Sdim 1457327952Sdimdef HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> { 1458327952Sdim let Latency = 11; 1459280031Sdim let NumMicroOps = 2; 1460327952Sdim let ResourceCycles = [1,1]; 1461280031Sdim} 1462341825Sdimdef: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>; 1463280031Sdim 1464327952Sdimdef HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> { 1465327952Sdim let Latency = 12; 1466327952Sdim let NumMicroOps = 2; 1467327952Sdim let ResourceCycles = [1,1]; 1468327952Sdim} 1469344779Sdimdef: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>; 1470344779Sdimdef: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>; 1471280031Sdim 1472327952Sdimdef HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> { 1473327952Sdim let Latency = 5; 1474327952Sdim let NumMicroOps = 3; 1475327952Sdim let ResourceCycles = [1,2]; 1476327952Sdim} 1477341825Sdimdef: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>; 1478280031Sdim 1479327952Sdimdef HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> { 1480327952Sdim let Latency = 5; 1481327952Sdim let NumMicroOps = 3; 1482327952Sdim let ResourceCycles = [1,1,1]; 1483327952Sdim} 1484327952Sdimdef: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>; 1485280031Sdim 1486327952Sdimdef HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { 1487327952Sdim let Latency = 10; 1488327952Sdim let NumMicroOps = 4; 1489327952Sdim let ResourceCycles = [1,1,1,1]; 1490327952Sdim} 1491327952Sdimdef: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>; 1492280031Sdim 1493327952Sdimdef HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { 1494280031Sdim let Latency = 5; 1495327952Sdim let NumMicroOps = 5; 1496327952Sdim let ResourceCycles = [1,4]; 1497280031Sdim} 1498341825Sdimdef: InstRW<[HWWriteResGroup99], (instrs PAUSE)>; 1499280031Sdim 1500327952Sdimdef HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { 1501327952Sdim let Latency = 5; 1502327952Sdim let NumMicroOps = 5; 1503327952Sdim let ResourceCycles = [1,4]; 1504280031Sdim} 1505341825Sdimdef: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; 1506280031Sdim 1507327952Sdimdef HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { 1508327952Sdim let Latency = 6; 1509280031Sdim let NumMicroOps = 2; 1510327952Sdim let ResourceCycles = [1,1]; 1511280031Sdim} 1512344779Sdimdef: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr, 1513344779Sdim VCVTPD2PSYrr, 1514344779Sdim VCVTPD2DQYrr, 1515344779Sdim VCVTTPD2DQYrr)>; 1516280031Sdim 1517327952Sdimdef HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { 1518327952Sdim let Latency = 13; 1519280031Sdim let NumMicroOps = 3; 1520327952Sdim let ResourceCycles = [2,1]; 1521280031Sdim} 1522341825Sdimdef: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1523280031Sdim 1524327952Sdimdef HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1525327952Sdim let Latency = 12; 1526280031Sdim let NumMicroOps = 3; 1527327952Sdim let ResourceCycles = [1,1,1]; 1528280031Sdim} 1529344779Sdimdef: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>; 1530280031Sdim 1531327952Sdimdef HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> { 1532327952Sdim let Latency = 6; 1533280031Sdim let NumMicroOps = 4; 1534327952Sdim let ResourceCycles = [1,1,1,1]; 1535280031Sdim} 1536327952Sdimdef: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>; 1537280031Sdim 1538327952Sdimdef HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> { 1539280031Sdim let Latency = 6; 1540327952Sdim let NumMicroOps = 6; 1541327952Sdim let ResourceCycles = [1,5]; 1542327952Sdim} 1543341825Sdimdef: InstRW<[HWWriteResGroup108], (instrs STD)>; 1544327952Sdim 1545327952Sdimdef HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> { 1546327952Sdim let Latency = 7; 1547327952Sdim let NumMicroOps = 7; 1548327952Sdim let ResourceCycles = [2,2,1,2]; 1549280031Sdim} 1550341825Sdimdef: InstRW<[HWWriteResGroup114], (instrs LOOP)>; 1551280031Sdim 1552327952Sdimdef HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1553327952Sdim let Latency = 15; 1554327952Sdim let NumMicroOps = 3; 1555327952Sdim let ResourceCycles = [1,1,1]; 1556327952Sdim} 1557341825Sdimdef: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>; 1558327952Sdim 1559327952Sdimdef HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1560327952Sdim let Latency = 16; 1561327952Sdim let NumMicroOps = 10; 1562327952Sdim let ResourceCycles = [1,1,1,4,1,2]; 1563327952Sdim} 1564341825Sdimdef: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>; 1565327952Sdim 1566327952Sdimdef HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { 1567327952Sdim let Latency = 11; 1568327952Sdim let NumMicroOps = 7; 1569327952Sdim let ResourceCycles = [2,2,3]; 1570327952Sdim} 1571341825Sdimdef: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL", 1572341825Sdim "RCR(16|32|64)rCL")>; 1573327952Sdim 1574327952Sdimdef HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 1575327952Sdim let Latency = 11; 1576327952Sdim let NumMicroOps = 9; 1577327952Sdim let ResourceCycles = [1,4,1,3]; 1578327952Sdim} 1579344779Sdimdef: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>; 1580327952Sdim 1581327952Sdimdef HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> { 1582327952Sdim let Latency = 11; 1583327952Sdim let NumMicroOps = 11; 1584327952Sdim let ResourceCycles = [2,9]; 1585327952Sdim} 1586341825Sdimdef: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>; 1587327952Sdim 1588327952Sdimdef HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1589327952Sdim let Latency = 17; 1590327952Sdim let NumMicroOps = 14; 1591327952Sdim let ResourceCycles = [1,1,1,4,2,5]; 1592327952Sdim} 1593341825Sdimdef: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>; 1594327952Sdim 1595327952Sdimdef HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1596327952Sdim let Latency = 19; 1597327952Sdim let NumMicroOps = 11; 1598327952Sdim let ResourceCycles = [2,1,1,3,1,3]; 1599327952Sdim} 1600341825Sdimdef: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>; 1601327952Sdim 1602327952Sdimdef HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 1603327952Sdim let Latency = 14; 1604327952Sdim let NumMicroOps = 10; 1605327952Sdim let ResourceCycles = [2,3,1,4]; 1606327952Sdim} 1607344779Sdimdef: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>; 1608280031Sdim 1609327952Sdimdef HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> { 1610327952Sdim let Latency = 19; 1611327952Sdim let NumMicroOps = 15; 1612327952Sdim let ResourceCycles = [1,14]; 1613327952Sdim} 1614344779Sdimdef: InstRW<[HWWriteResGroup143], (instrs POPF16)>; 1615327952Sdim 1616327952Sdimdef HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1617327952Sdim let Latency = 21; 1618327952Sdim let NumMicroOps = 8; 1619327952Sdim let ResourceCycles = [1,1,1,1,1,1,2]; 1620327952Sdim} 1621341825Sdimdef: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; 1622327952Sdim 1623344779Sdimdef HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> { 1624344779Sdim let Latency = 8; 1625344779Sdim let NumMicroOps = 20; 1626344779Sdim let ResourceCycles = [1,1]; 1627327952Sdim} 1628341825Sdimdef: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; 1629327952Sdim 1630327952Sdimdef HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1631327952Sdim let Latency = 22; 1632327952Sdim let NumMicroOps = 19; 1633327952Sdim let ResourceCycles = [2,1,4,1,1,4,6]; 1634327952Sdim} 1635341825Sdimdef: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>; 1636327952Sdim 1637327952Sdimdef HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { 1638327952Sdim let Latency = 17; 1639327952Sdim let NumMicroOps = 15; 1640327952Sdim let ResourceCycles = [2,1,2,4,2,4]; 1641327952Sdim} 1642341825Sdimdef: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; 1643327952Sdim 1644327952Sdimdef HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { 1645327952Sdim let Latency = 18; 1646327952Sdim let NumMicroOps = 8; 1647327952Sdim let ResourceCycles = [1,1,1,5]; 1648327952Sdim} 1649341825Sdimdef: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>; 1650327952Sdim 1651327952Sdimdef HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 1652327952Sdim let Latency = 23; 1653327952Sdim let NumMicroOps = 19; 1654327952Sdim let ResourceCycles = [3,1,15]; 1655327952Sdim} 1656327952Sdimdef: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>; 1657327952Sdim 1658327952Sdimdef HWWriteResGroup154 : SchedWriteRes<[HWPort0]> { 1659327952Sdim let Latency = 20; 1660327952Sdim let NumMicroOps = 1; 1661327952Sdim let ResourceCycles = [1]; 1662327952Sdim} 1663341825Sdimdef: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1664327952Sdim 1665327952Sdimdef HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> { 1666327952Sdim let Latency = 27; 1667327952Sdim let NumMicroOps = 2; 1668327952Sdim let ResourceCycles = [1,1]; 1669327952Sdim} 1670341825Sdimdef: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>; 1671327952Sdim 1672327952Sdimdef HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { 1673327952Sdim let Latency = 20; 1674327952Sdim let NumMicroOps = 10; 1675327952Sdim let ResourceCycles = [1,2,7]; 1676327952Sdim} 1677341825Sdimdef: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>; 1678327952Sdim 1679327952Sdimdef HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1680327952Sdim let Latency = 30; 1681327952Sdim let NumMicroOps = 3; 1682327952Sdim let ResourceCycles = [1,1,1]; 1683280031Sdim} 1684341825Sdimdef: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>; 1685280031Sdim 1686327952Sdimdef HWWriteResGroup162 : SchedWriteRes<[HWPort0]> { 1687327952Sdim let Latency = 24; 1688327952Sdim let NumMicroOps = 1; 1689327952Sdim let ResourceCycles = [1]; 1690327952Sdim} 1691341825Sdimdef: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1692327952Sdim 1693327952Sdimdef HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> { 1694327952Sdim let Latency = 31; 1695327952Sdim let NumMicroOps = 2; 1696327952Sdim let ResourceCycles = [1,1]; 1697327952Sdim} 1698341825Sdimdef: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>; 1699327952Sdim 1700327952Sdimdef HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1701327952Sdim let Latency = 30; 1702327952Sdim let NumMicroOps = 27; 1703327952Sdim let ResourceCycles = [1,5,1,1,19]; 1704327952Sdim} 1705341825Sdimdef: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>; 1706327952Sdim 1707327952Sdimdef HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1708327952Sdim let Latency = 31; 1709327952Sdim let NumMicroOps = 28; 1710327952Sdim let ResourceCycles = [1,6,1,1,19]; 1711327952Sdim} 1712341825Sdimdef: InstRW<[HWWriteResGroup165], (instrs XSAVE)>; 1713341825Sdimdef: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1714327952Sdim 1715327952Sdimdef HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1716327952Sdim let Latency = 34; 1717280031Sdim let NumMicroOps = 3; 1718327952Sdim let ResourceCycles = [1,1,1]; 1719280031Sdim} 1720341825Sdimdef: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>; 1721280031Sdim 1722327952Sdimdef HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { 1723327952Sdim let Latency = 35; 1724327952Sdim let NumMicroOps = 23; 1725327952Sdim let ResourceCycles = [1,5,3,4,10]; 1726327952Sdim} 1727341825Sdimdef: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri", 1728341825Sdim "IN(8|16|32)rr")>; 1729327952Sdim 1730327952Sdimdef HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1731327952Sdim let Latency = 36; 1732327952Sdim let NumMicroOps = 23; 1733327952Sdim let ResourceCycles = [1,5,2,1,4,10]; 1734327952Sdim} 1735341825Sdimdef: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir", 1736341825Sdim "OUT(8|16|32)rr")>; 1737327952Sdim 1738327952Sdimdef HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { 1739327952Sdim let Latency = 41; 1740327952Sdim let NumMicroOps = 18; 1741327952Sdim let ResourceCycles = [1,1,2,3,1,1,1,8]; 1742327952Sdim} 1743341825Sdimdef: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>; 1744327952Sdim 1745327952Sdimdef HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> { 1746327952Sdim let Latency = 42; 1747327952Sdim let NumMicroOps = 22; 1748327952Sdim let ResourceCycles = [2,20]; 1749327952Sdim} 1750341825Sdimdef: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>; 1751327952Sdim 1752327952Sdimdef HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> { 1753327952Sdim let Latency = 61; 1754327952Sdim let NumMicroOps = 64; 1755327952Sdim let ResourceCycles = [2,2,8,1,10,2,39]; 1756327952Sdim} 1757341825Sdimdef: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>; 1758327952Sdim 1759327952Sdimdef HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 1760327952Sdim let Latency = 64; 1761327952Sdim let NumMicroOps = 88; 1762327952Sdim let ResourceCycles = [4,4,31,1,2,1,45]; 1763327952Sdim} 1764341825Sdimdef: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>; 1765327952Sdim 1766327952Sdimdef HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 1767327952Sdim let Latency = 64; 1768327952Sdim let NumMicroOps = 90; 1769327952Sdim let ResourceCycles = [4,2,33,1,2,1,47]; 1770327952Sdim} 1771341825Sdimdef: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>; 1772327952Sdim 1773327952Sdimdef HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { 1774327952Sdim let Latency = 75; 1775327952Sdim let NumMicroOps = 15; 1776327952Sdim let ResourceCycles = [6,3,6]; 1777327952Sdim} 1778341825Sdimdef: InstRW<[HWWriteResGroup180], (instrs FNINIT)>; 1779327952Sdim 1780327952Sdimdef HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> { 1781327952Sdim let Latency = 115; 1782327952Sdim let NumMicroOps = 100; 1783327952Sdim let ResourceCycles = [9,9,11,8,1,11,21,30]; 1784327952Sdim} 1785341825Sdimdef: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>; 1786327952Sdim 1787327952Sdimdef HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> { 1788327952Sdim let Latency = 26; 1789327952Sdim let NumMicroOps = 12; 1790327952Sdim let ResourceCycles = [2,2,1,3,2,2]; 1791327952Sdim} 1792327952Sdimdef: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, 1793327952Sdim VPGATHERDQrm, 1794327952Sdim VPGATHERDDrm)>; 1795327952Sdim 1796327952Sdimdef HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1797327952Sdim let Latency = 24; 1798327952Sdim let NumMicroOps = 22; 1799327952Sdim let ResourceCycles = [5,3,4,1,5,4]; 1800327952Sdim} 1801327952Sdimdef: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm, 1802327952Sdim VPGATHERQQYrm)>; 1803327952Sdim 1804327952Sdimdef HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1805327952Sdim let Latency = 28; 1806327952Sdim let NumMicroOps = 22; 1807327952Sdim let ResourceCycles = [5,3,4,1,5,4]; 1808327952Sdim} 1809327952Sdimdef: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>; 1810327952Sdim 1811327952Sdimdef HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1812327952Sdim let Latency = 25; 1813327952Sdim let NumMicroOps = 22; 1814327952Sdim let ResourceCycles = [5,3,4,1,5,4]; 1815327952Sdim} 1816327952Sdimdef: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>; 1817327952Sdim 1818327952Sdimdef HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1819327952Sdim let Latency = 27; 1820327952Sdim let NumMicroOps = 20; 1821327952Sdim let ResourceCycles = [3,3,4,1,5,4]; 1822327952Sdim} 1823327952Sdimdef: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm, 1824327952Sdim VPGATHERDQYrm)>; 1825327952Sdim 1826327952Sdimdef HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1827327952Sdim let Latency = 27; 1828327952Sdim let NumMicroOps = 34; 1829327952Sdim let ResourceCycles = [5,3,8,1,9,8]; 1830327952Sdim} 1831327952Sdimdef: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm, 1832327952Sdim VPGATHERDDYrm)>; 1833327952Sdim 1834327952Sdimdef HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1835327952Sdim let Latency = 23; 1836327952Sdim let NumMicroOps = 14; 1837327952Sdim let ResourceCycles = [3,3,2,1,3,2]; 1838327952Sdim} 1839327952Sdimdef: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm, 1840327952Sdim VPGATHERQQrm)>; 1841327952Sdim 1842327952Sdimdef HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1843327952Sdim let Latency = 28; 1844327952Sdim let NumMicroOps = 15; 1845327952Sdim let ResourceCycles = [3,3,2,1,4,2]; 1846327952Sdim} 1847327952Sdimdef: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>; 1848327952Sdim 1849327952Sdimdef HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1850327952Sdim let Latency = 25; 1851327952Sdim let NumMicroOps = 15; 1852327952Sdim let ResourceCycles = [3,3,2,1,4,2]; 1853327952Sdim} 1854327952Sdimdef: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm, 1855327952Sdim VGATHERDPSrm)>; 1856327952Sdim 1857341825Sdimdef: InstRW<[WriteZero], (instrs CLC)>; 1858341825Sdim 1859353358Sdim 1860353358Sdim// Intruction variants handled by the renamer. These might not need execution 1861353358Sdim// ports in certain conditions. 1862353358Sdim// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1863353358Sdim// section "Haswell and Broadwell Pipeline" > "Register allocation and 1864353358Sdim// renaming". 1865353358Sdim// These can be investigated with llvm-exegesis, e.g. 1866353358Sdim// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1867353358Sdim// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1868353358Sdim 1869353358Sdimdef HWWriteZeroLatency : SchedWriteRes<[]> { 1870353358Sdim let Latency = 0; 1871353358Sdim} 1872353358Sdim 1873353358Sdimdef HWWriteZeroIdiom : SchedWriteVariant<[ 1874353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1875353358Sdim SchedVar<NoSchedPred, [WriteALU]> 1876353358Sdim]>; 1877353358Sdimdef : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1878353358Sdim XOR32rr, XOR64rr)>; 1879353358Sdim 1880353358Sdimdef HWWriteFZeroIdiom : SchedWriteVariant<[ 1881353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1882353358Sdim SchedVar<NoSchedPred, [WriteFLogic]> 1883353358Sdim]>; 1884353358Sdimdef : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1885353358Sdim VXORPDrr)>; 1886353358Sdim 1887353358Sdimdef HWWriteFZeroIdiomY : SchedWriteVariant<[ 1888353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1889353358Sdim SchedVar<NoSchedPred, [WriteFLogicY]> 1890353358Sdim]>; 1891353358Sdimdef : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1892353358Sdim 1893353358Sdimdef HWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1894353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1895353358Sdim SchedVar<NoSchedPred, [WriteVecLogicX]> 1896353358Sdim]>; 1897353358Sdimdef : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1898353358Sdim 1899353358Sdimdef HWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1900353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1901353358Sdim SchedVar<NoSchedPred, [WriteVecLogicY]> 1902353358Sdim]>; 1903353358Sdimdef : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1904353358Sdim 1905353358Sdimdef HWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1906353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1907353358Sdim SchedVar<NoSchedPred, [WriteVecALUX]> 1908353358Sdim]>; 1909353358Sdimdef : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1910353358Sdim PSUBDrr, VPSUBDrr, 1911353358Sdim PSUBQrr, VPSUBQrr, 1912353358Sdim PSUBWrr, VPSUBWrr, 1913353358Sdim PCMPGTBrr, VPCMPGTBrr, 1914353358Sdim PCMPGTDrr, VPCMPGTDrr, 1915353358Sdim PCMPGTWrr, VPCMPGTWrr)>; 1916353358Sdim 1917353358Sdimdef HWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1918353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1919353358Sdim SchedVar<NoSchedPred, [WriteVecALUY]> 1920353358Sdim]>; 1921353358Sdimdef : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1922353358Sdim VPSUBDYrr, 1923353358Sdim VPSUBQYrr, 1924353358Sdim VPSUBWYrr, 1925353358Sdim VPCMPGTBYrr, 1926353358Sdim VPCMPGTDYrr, 1927353358Sdim VPCMPGTWYrr)>; 1928353358Sdim 1929353358Sdimdef HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> { 1930353358Sdim let Latency = 5; 1931353358Sdim let NumMicroOps = 1; 1932353358Sdim let ResourceCycles = [1]; 1933353358Sdim} 1934353358Sdim 1935353358Sdimdef HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1936353358Sdim SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1937353358Sdim SchedVar<NoSchedPred, [HWWritePCMPGTQ]> 1938353358Sdim]>; 1939353358Sdimdef : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1940353358Sdim VPCMPGTQYrr)>; 1941353358Sdim 1942353358Sdim 1943353358Sdim// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require 1944353358Sdim// a single uop. It does not apply to the GR8 encoding. And only applies to the 1945353358Sdim// 8-bit immediate since using larger immediate for 0 would be silly. 1946353358Sdim// Unfortunately, this optimization does not apply to the AX/EAX/RAX short 1947353358Sdim// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since 1948353358Sdim// we schedule before that point. 1949353358Sdim// TODO: Should we disable using the short encodings on these CPUs? 1950353358Sdimdef HWFastADC0 : MCSchedPredicate< 1951353358Sdim CheckAll<[ 1952353358Sdim CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0. 1953353358Sdim CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX 1954353358Sdim CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX 1955353358Sdim CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX 1956353358Sdim ]> 1957353358Sdim>; 1958353358Sdim 1959353358Sdimdef HWWriteADC0 : SchedWriteRes<[HWPort06]> { 1960353358Sdim let Latency = 1; 1961353358Sdim let NumMicroOps = 1; 1962353358Sdim let ResourceCycles = [1]; 1963353358Sdim} 1964353358Sdim 1965353358Sdimdef HWWriteADC : SchedWriteVariant<[ 1966353358Sdim SchedVar<HWFastADC0, [HWWriteADC0]>, 1967353358Sdim SchedVar<NoSchedPred, [WriteADC]> 1968353358Sdim]>; 1969353358Sdim 1970353358Sdimdef : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8, 1971353358Sdim SBB16ri8, SBB32ri8, SBB64ri8)>; 1972353358Sdim 1973353358Sdim// CMOVs that use both Z and C flag require an extra uop. 1974353358Sdimdef HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> { 1975353358Sdim let Latency = 3; 1976353358Sdim let ResourceCycles = [1,2]; 1977353358Sdim let NumMicroOps = 3; 1978353358Sdim} 1979353358Sdim 1980353358Sdimdef HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> { 1981353358Sdim let Latency = 8; 1982353358Sdim let ResourceCycles = [1,1,2]; 1983353358Sdim let NumMicroOps = 4; 1984353358Sdim} 1985353358Sdim 1986353358Sdimdef HWCMOVA_CMOVBErr : SchedWriteVariant<[ 1987353358Sdim SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>, 1988353358Sdim SchedVar<NoSchedPred, [WriteCMOV]> 1989353358Sdim]>; 1990353358Sdim 1991353358Sdimdef HWCMOVA_CMOVBErm : SchedWriteVariant<[ 1992353358Sdim SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>, 1993353358Sdim SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1994353358Sdim]>; 1995353358Sdim 1996353358Sdimdef : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1997353358Sdimdef : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1998353358Sdim 1999353358Sdim// SETCCs that use both Z and C flag require an extra uop. 2000353358Sdimdef HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> { 2001353358Sdim let Latency = 2; 2002353358Sdim let ResourceCycles = [1,1]; 2003353358Sdim let NumMicroOps = 2; 2004353358Sdim} 2005353358Sdim 2006353358Sdimdef HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 2007353358Sdim let Latency = 3; 2008353358Sdim let ResourceCycles = [1,1,1,1]; 2009353358Sdim let NumMicroOps = 4; 2010353358Sdim} 2011353358Sdim 2012353358Sdimdef HWSETA_SETBErr : SchedWriteVariant<[ 2013353358Sdim SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>, 2014353358Sdim SchedVar<NoSchedPred, [WriteSETCC]> 2015353358Sdim]>; 2016353358Sdim 2017353358Sdimdef HWSETA_SETBErm : SchedWriteVariant<[ 2018353358Sdim SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>, 2019353358Sdim SchedVar<NoSchedPred, [WriteSETCCStore]> 2020353358Sdim]>; 2021353358Sdim 2022353358Sdimdef : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>; 2023353358Sdimdef : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>; 2024353358Sdim 2025249259Sdim} // SchedModel 2026