X86InstrInfo.td revision 363496 
1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instruction set, defining the instructions, and
10// properties of the instructions which are needed for code generation, machine
11// code emission, and analysis.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// X86 specific DAG Nodes.
17//
18
19def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
20
21def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
22//def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
23
24def SDTX86Cmov    : SDTypeProfile<1, 4,
25                                  [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
26                                   SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
27
28// Unary and binary operator instructions that set EFLAGS as a side-effect.
29def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
30                                           [SDTCisSameAs<0, 2>,
31                                            SDTCisInt<0>, SDTCisVT<1, i32>]>;
32
33def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
34                                            [SDTCisSameAs<0, 2>,
35                                             SDTCisSameAs<0, 3>,
36                                             SDTCisInt<0>, SDTCisVT<1, i32>]>;
37
38// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
39def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
40                                            [SDTCisSameAs<0, 2>,
41                                             SDTCisSameAs<0, 3>,
42                                             SDTCisInt<0>,
43                                             SDTCisVT<1, i32>,
44                                             SDTCisVT<4, i32>]>;
45// RES1, RES2, FLAGS = op LHS, RHS
46def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
47                                            [SDTCisSameAs<0, 1>,
48                                             SDTCisSameAs<0, 2>,
49                                             SDTCisSameAs<0, 3>,
50                                             SDTCisInt<0>, SDTCisVT<1, i32>]>;
51def SDTX86BrCond  : SDTypeProfile<0, 3,
52                                  [SDTCisVT<0, OtherVT>,
53                                   SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
54
55def SDTX86SetCC   : SDTypeProfile<1, 2,
56                                  [SDTCisVT<0, i8>,
57                                   SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
58def SDTX86SetCC_C : SDTypeProfile<1, 2,
59                                  [SDTCisInt<0>,
60                                   SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
61
62def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
63
64def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
65
66def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
67def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68                                        SDTCisVT<2, i32>]>;
69
70def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
71                                     SDTCisVT<2, i8>]>;
72def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
73def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3,
74                                          [SDTCisVT<0, i32>, SDTCisPtrTy<1>,
75                                          SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
76def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3,
77                                           [SDTCisVT<0, i64>, SDTCisPtrTy<1>,
78                                           SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
79
80def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
81                                                       SDTCisPtrTy<1>,
82                                                       SDTCisInt<2>]>;
83
84def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
85                                                      SDTCisPtrTy<1>]>;
86
87def SDTX86Ret     : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
88
89def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
90                                          SDTCisVT<1, i32>]>;
91def SDT_X86CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>,
92                                        SDTCisVT<1, i32>]>;
93
94def SDT_X86Call   : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
95
96def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
97
98def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
99                                                         SDTCisVT<1, iPTR>,
100                                                         SDTCisVT<2, iPTR>]>;
101
102def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
103                                            SDTCisPtrTy<1>,
104                                            SDTCisVT<2, i32>,
105                                            SDTCisVT<3, i8>,
106                                            SDTCisVT<4, i32>]>;
107
108def SDTX86RepStr  : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
109
110def SDTX86Void    : SDTypeProfile<0, 0, []>;
111
112def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
113
114def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
115
116def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
117
118def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
119
120def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
121
122def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
123
124def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
125
126def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
127
128def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
129
130def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
131                                         SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>;
132
133def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
134                            [SDNPHasChain,SDNPSideEffect]>;
135def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
136                        [SDNPHasChain]>;
137
138
139def X86bsf     : SDNode<"X86ISD::BSF",      SDTUnaryArithWithFlags>;
140def X86bsr     : SDNode<"X86ISD::BSR",      SDTUnaryArithWithFlags>;
141def X86shld    : SDNode<"X86ISD::SHLD",     SDTIntShiftDOp>;
142def X86shrd    : SDNode<"X86ISD::SHRD",     SDTIntShiftDOp>;
143
144def X86cmp     : SDNode<"X86ISD::CMP" ,     SDTX86CmpTest>;
145def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86CmpTest, [SDNPHasChain]>;
146def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86CmpTest, [SDNPHasChain]>;
147def X86bt      : SDNode<"X86ISD::BT",       SDTX86CmpTest>;
148
149def X86cmov    : SDNode<"X86ISD::CMOV",     SDTX86Cmov>;
150def X86brcond  : SDNode<"X86ISD::BRCOND",   SDTX86BrCond,
151                        [SDNPHasChain]>;
152def X86setcc   : SDNode<"X86ISD::SETCC",    SDTX86SetCC>;
153def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
154
155def X86sahf    : SDNode<"X86ISD::SAHF",     SDTX86sahf>;
156
157def X86rdrand  : SDNode<"X86ISD::RDRAND",   SDTX86rdrand,
158                        [SDNPHasChain, SDNPSideEffect]>;
159
160def X86rdseed  : SDNode<"X86ISD::RDSEED",   SDTX86rdrand,
161                        [SDNPHasChain, SDNPSideEffect]>;
162
163def X86rdpkru : SDNode<"X86ISD::RDPKRU",    SDTX86rdpkru,
164                       [SDNPHasChain, SDNPSideEffect]>;
165def X86wrpkru : SDNode<"X86ISD::WRPKRU",    SDTX86wrpkru,
166                       [SDNPHasChain, SDNPSideEffect]>;
167
168def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
169                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
170                         SDNPMayLoad, SDNPMemOperand]>;
171def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
172                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
173                         SDNPMayLoad, SDNPMemOperand]>;
174def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
175                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
176                         SDNPMayLoad, SDNPMemOperand]>;
177def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG",
178                                SDTX86caspairSaveEbx8,
179                                [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
180                                SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
181def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG",
182                                SDTX86caspairSaveRbx16,
183                                [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
184                                SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
185
186def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
187                        [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
188def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret,
189                        [SDNPHasChain, SDNPOptInGlue]>;
190
191def X86vastart_save_xmm_regs :
192                 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
193                        SDT_X86VASTART_SAVE_XMM_REGS,
194                        [SDNPHasChain, SDNPVariadic]>;
195def X86vaarg64 :
196                 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
197                        [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
198                         SDNPMemOperand]>;
199def X86callseq_start :
200                 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
201                        [SDNPHasChain, SDNPOutGlue]>;
202def X86callseq_end :
203                 SDNode<"ISD::CALLSEQ_END",   SDT_X86CallSeqEnd,
204                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
205
206def X86call    : SDNode<"X86ISD::CALL",     SDT_X86Call,
207                        [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
208                         SDNPVariadic]>;
209
210def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call,
211                            [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
212                             SDNPVariadic]>;
213def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind,
214                             [SDNPHasChain]>;
215
216def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
217                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
218def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
219                        [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
220                         SDNPMayLoad]>;
221
222def X86Wrapper    : SDNode<"X86ISD::Wrapper",     SDTX86Wrapper>;
223def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP",  SDTX86Wrapper>;
224
225def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER",
226                                  SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
227                                                       SDTCisInt<1>]>>;
228
229def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
230                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
231
232def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
233                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
234
235def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
236                        [SDNPHasChain]>;
237
238def X86eh_sjlj_setjmp  : SDNode<"X86ISD::EH_SJLJ_SETJMP",
239                                SDTypeProfile<1, 1, [SDTCisInt<0>,
240                                                     SDTCisPtrTy<1>]>,
241                                [SDNPHasChain, SDNPSideEffect]>;
242def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
243                                SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
244                                [SDNPHasChain, SDNPSideEffect]>;
245def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH",
246                                       SDTypeProfile<0, 0, []>,
247                                       [SDNPHasChain, SDNPSideEffect]>;
248
249def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
250                        [SDNPHasChain,  SDNPOptInGlue, SDNPVariadic]>;
251
252def X86add_flag  : SDNode<"X86ISD::ADD",  SDTBinaryArithWithFlags,
253                          [SDNPCommutative]>;
254def X86sub_flag  : SDNode<"X86ISD::SUB",  SDTBinaryArithWithFlags>;
255def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
256                          [SDNPCommutative]>;
257def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
258                          [SDNPCommutative]>;
259def X86adc_flag  : SDNode<"X86ISD::ADC",  SDTBinaryArithWithFlagsInOut>;
260def X86sbb_flag  : SDNode<"X86ISD::SBB",  SDTBinaryArithWithFlagsInOut>;
261
262def X86or_flag   : SDNode<"X86ISD::OR",   SDTBinaryArithWithFlags,
263                          [SDNPCommutative]>;
264def X86xor_flag  : SDNode<"X86ISD::XOR",  SDTBinaryArithWithFlags,
265                          [SDNPCommutative]>;
266def X86and_flag  : SDNode<"X86ISD::AND",  SDTBinaryArithWithFlags,
267                          [SDNPCommutative]>;
268
269def X86lock_add  : SDNode<"X86ISD::LADD",  SDTLockBinaryArithWithFlags,
270                          [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
271                           SDNPMemOperand]>;
272def X86lock_sub  : SDNode<"X86ISD::LSUB",  SDTLockBinaryArithWithFlags,
273                          [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
274                           SDNPMemOperand]>;
275def X86lock_or  : SDNode<"X86ISD::LOR",  SDTLockBinaryArithWithFlags,
276                         [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
277                          SDNPMemOperand]>;
278def X86lock_xor  : SDNode<"X86ISD::LXOR",  SDTLockBinaryArithWithFlags,
279                          [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
280                           SDNPMemOperand]>;
281def X86lock_and  : SDNode<"X86ISD::LAND",  SDTLockBinaryArithWithFlags,
282                          [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
283                           SDNPMemOperand]>;
284
285def X86bextr  : SDNode<"X86ISD::BEXTR",  SDTIntBinOp>;
286
287def X86bzhi   : SDNode<"X86ISD::BZHI",   SDTIntBinOp>;
288
289def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
290
291def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA,
292                          [SDNPHasChain, SDNPOutGlue]>;
293
294def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
295                          [SDNPHasChain]>;
296
297def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
298                        [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
299
300def X86lwpins : SDNode<"X86ISD::LWPINS",
301                       SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
302                                            SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
303                       [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>;
304
305def X86umwait : SDNode<"X86ISD::UMWAIT",
306                       SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
307                                            SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
308                       [SDNPHasChain, SDNPSideEffect]>;
309
310def X86tpause : SDNode<"X86ISD::TPAUSE",
311                       SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
312                                            SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
313                       [SDNPHasChain, SDNPSideEffect]>;
314
315def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD,
316                       [SDNPHasChain, SDNPSideEffect]>;
317def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD,
318                       [SDNPHasChain, SDNPSideEffect]>;
319
320//===----------------------------------------------------------------------===//
321// X86 Operand Definitions.
322//
323
324// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
325// the index operand of an address, to conform to x86 encoding restrictions.
326def ptr_rc_nosp : PointerLikeRegClass<1>;
327
328// *mem - Operand definitions for the funky X86 addressing mode operands.
329//
330def X86MemAsmOperand : AsmOperandClass {
331 let Name = "Mem";
332}
333let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in {
334  def X86Mem8AsmOperand   : AsmOperandClass { let Name = "Mem8"; }
335  def X86Mem16AsmOperand  : AsmOperandClass { let Name = "Mem16"; }
336  def X86Mem32AsmOperand  : AsmOperandClass { let Name = "Mem32"; }
337  def X86Mem64AsmOperand  : AsmOperandClass { let Name = "Mem64"; }
338  def X86Mem80AsmOperand  : AsmOperandClass { let Name = "Mem80"; }
339  def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; }
340  def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; }
341  def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; }
342  // Gather mem operands
343  def X86Mem64_RC128Operand  : AsmOperandClass { let Name = "Mem64_RC128"; }
344  def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; }
345  def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; }
346  def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; }
347  def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; }
348
349  def X86Mem64_RC128XOperand  : AsmOperandClass { let Name = "Mem64_RC128X"; }
350  def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; }
351  def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; }
352  def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; }
353  def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; }
354  def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; }
355  def X86Mem256_RC512Operand  : AsmOperandClass { let Name = "Mem256_RC512"; }
356  def X86Mem512_RC512Operand  : AsmOperandClass { let Name = "Mem512_RC512"; }
357}
358
359def X86AbsMemAsmOperand : AsmOperandClass {
360  let Name = "AbsMem";
361  let SuperClasses = [X86MemAsmOperand];
362}
363
364class X86MemOperand<string printMethod,
365          AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> {
366  let PrintMethod = printMethod;
367  let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
368  let ParserMatchClass = parserMatchClass;
369  let OperandType = "OPERAND_MEMORY";
370}
371
372// Gather mem operands
373class X86VMemOperand<RegisterClass RC, string printMethod,
374                     AsmOperandClass parserMatchClass>
375    : X86MemOperand<printMethod, parserMatchClass> {
376  let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG);
377}
378
379def anymem : X86MemOperand<"printanymem">;
380def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
381                          [(X86strict_fcmp node:$lhs, node:$rhs),
382                           (X86cmp node:$lhs, node:$rhs)]>;
383
384// FIXME: Right now we allow any size during parsing, but we might want to
385// restrict to only unsized memory.
386def opaquemem : X86MemOperand<"printopaquemem">;
387
388def i8mem   : X86MemOperand<"printbytemem",   X86Mem8AsmOperand>;
389def i16mem  : X86MemOperand<"printwordmem",  X86Mem16AsmOperand>;
390def i32mem  : X86MemOperand<"printdwordmem",  X86Mem32AsmOperand>;
391def i64mem  : X86MemOperand<"printqwordmem",  X86Mem64AsmOperand>;
392def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand>;
393def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand>;
394def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand>;
395def f32mem  : X86MemOperand<"printdwordmem",  X86Mem32AsmOperand>;
396def f64mem  : X86MemOperand<"printqwordmem",  X86Mem64AsmOperand>;
397def f80mem  : X86MemOperand<"printtbytemem",  X86Mem80AsmOperand>;
398def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand>;
399def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand>;
400def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand>;
401
402// Gather mem operands
403def vx64mem  : X86VMemOperand<VR128,  "printqwordmem",  X86Mem64_RC128Operand>;
404def vx128mem : X86VMemOperand<VR128,  "printxmmwordmem", X86Mem128_RC128Operand>;
405def vx256mem : X86VMemOperand<VR128,  "printymmwordmem", X86Mem256_RC128Operand>;
406def vy128mem : X86VMemOperand<VR256,  "printxmmwordmem", X86Mem128_RC256Operand>;
407def vy256mem : X86VMemOperand<VR256,  "printymmwordmem", X86Mem256_RC256Operand>;
408
409def vx64xmem  : X86VMemOperand<VR128X, "printqwordmem",  X86Mem64_RC128XOperand>;
410def vx128xmem : X86VMemOperand<VR128X, "printxmmwordmem", X86Mem128_RC128XOperand>;
411def vx256xmem : X86VMemOperand<VR128X, "printymmwordmem", X86Mem256_RC128XOperand>;
412def vy128xmem : X86VMemOperand<VR256X, "printxmmwordmem", X86Mem128_RC256XOperand>;
413def vy256xmem : X86VMemOperand<VR256X, "printymmwordmem", X86Mem256_RC256XOperand>;
414def vy512xmem : X86VMemOperand<VR256X, "printzmmwordmem", X86Mem512_RC256XOperand>;
415def vz256mem  : X86VMemOperand<VR512,  "printymmwordmem", X86Mem256_RC512Operand>;
416def vz512mem  : X86VMemOperand<VR512,  "printzmmwordmem", X86Mem512_RC512Operand>;
417
418// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead
419// of a plain GPR, so that it doesn't potentially require a REX prefix.
420def ptr_rc_norex : PointerLikeRegClass<2>;
421def ptr_rc_norex_nosp : PointerLikeRegClass<3>;
422
423def i8mem_NOREX : Operand<iPTR> {
424  let PrintMethod = "printbytemem";
425  let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm,
426                       SEGMENT_REG);
427  let ParserMatchClass = X86Mem8AsmOperand;
428  let OperandType = "OPERAND_MEMORY";
429}
430
431// GPRs available for tailcall.
432// It represents GR32_TC, GR64_TC or GR64_TCW64.
433def ptr_rc_tailcall : PointerLikeRegClass<4>;
434
435// Special i32mem for addresses of load folding tail calls. These are not
436// allowed to use callee-saved registers since they must be scheduled
437// after callee-saved register are popped.
438def i32mem_TC : Operand<i32> {
439  let PrintMethod = "printdwordmem";
440  let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
441                       i32imm, SEGMENT_REG);
442  let ParserMatchClass = X86Mem32AsmOperand;
443  let OperandType = "OPERAND_MEMORY";
444}
445
446// Special i64mem for addresses of load folding tail calls. These are not
447// allowed to use callee-saved registers since they must be scheduled
448// after callee-saved register are popped.
449def i64mem_TC : Operand<i64> {
450  let PrintMethod = "printqwordmem";
451  let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
452                       ptr_rc_tailcall, i32imm, SEGMENT_REG);
453  let ParserMatchClass = X86Mem64AsmOperand;
454  let OperandType = "OPERAND_MEMORY";
455}
456
457// Special parser to detect 16-bit mode to select 16-bit displacement.
458def X86AbsMem16AsmOperand : AsmOperandClass {
459  let Name = "AbsMem16";
460  let RenderMethod = "addAbsMemOperands";
461  let SuperClasses = [X86AbsMemAsmOperand];
462}
463
464// Branch targets print as pc-relative values.
465class BranchTargetOperand<ValueType ty> : Operand<ty> {
466  let OperandType = "OPERAND_PCREL";
467  let PrintMethod = "printPCRelImm";
468  let ParserMatchClass = X86AbsMemAsmOperand;
469}
470
471def i32imm_brtarget : BranchTargetOperand<i32>;
472def i16imm_brtarget : BranchTargetOperand<i16>;
473
474// 64-bits but only 32 bits are significant, and those bits are treated as being
475// pc relative.
476def i64i32imm_brtarget : BranchTargetOperand<i64>;
477
478def brtarget : BranchTargetOperand<OtherVT>;
479def brtarget8 : BranchTargetOperand<OtherVT>;
480def brtarget16 : BranchTargetOperand<OtherVT> {
481  let ParserMatchClass = X86AbsMem16AsmOperand;
482}
483def brtarget32 : BranchTargetOperand<OtherVT>;
484
485let RenderMethod = "addSrcIdxOperands" in {
486  def X86SrcIdx8Operand : AsmOperandClass {
487    let Name = "SrcIdx8";
488    let SuperClasses = [X86Mem8AsmOperand];
489  }
490  def X86SrcIdx16Operand : AsmOperandClass {
491    let Name = "SrcIdx16";
492    let SuperClasses = [X86Mem16AsmOperand];
493  }
494  def X86SrcIdx32Operand : AsmOperandClass {
495    let Name = "SrcIdx32";
496    let SuperClasses = [X86Mem32AsmOperand];
497  }
498  def X86SrcIdx64Operand : AsmOperandClass {
499    let Name = "SrcIdx64";
500    let SuperClasses = [X86Mem64AsmOperand];
501  }
502} // RenderMethod = "addSrcIdxOperands"
503
504let RenderMethod = "addDstIdxOperands" in {
505 def X86DstIdx8Operand : AsmOperandClass {
506   let Name = "DstIdx8";
507   let SuperClasses = [X86Mem8AsmOperand];
508 }
509 def X86DstIdx16Operand : AsmOperandClass {
510   let Name = "DstIdx16";
511   let SuperClasses = [X86Mem16AsmOperand];
512 }
513 def X86DstIdx32Operand : AsmOperandClass {
514   let Name = "DstIdx32";
515   let SuperClasses = [X86Mem32AsmOperand];
516 }
517 def X86DstIdx64Operand : AsmOperandClass {
518   let Name = "DstIdx64";
519   let SuperClasses = [X86Mem64AsmOperand];
520 }
521} // RenderMethod = "addDstIdxOperands"
522
523let RenderMethod = "addMemOffsOperands" in {
524  def X86MemOffs16_8AsmOperand : AsmOperandClass {
525    let Name = "MemOffs16_8";
526    let SuperClasses = [X86Mem8AsmOperand];
527  }
528  def X86MemOffs16_16AsmOperand : AsmOperandClass {
529    let Name = "MemOffs16_16";
530    let SuperClasses = [X86Mem16AsmOperand];
531  }
532  def X86MemOffs16_32AsmOperand : AsmOperandClass {
533    let Name = "MemOffs16_32";
534    let SuperClasses = [X86Mem32AsmOperand];
535  }
536  def X86MemOffs32_8AsmOperand : AsmOperandClass {
537    let Name = "MemOffs32_8";
538    let SuperClasses = [X86Mem8AsmOperand];
539  }
540  def X86MemOffs32_16AsmOperand : AsmOperandClass {
541    let Name = "MemOffs32_16";
542    let SuperClasses = [X86Mem16AsmOperand];
543  }
544  def X86MemOffs32_32AsmOperand : AsmOperandClass {
545    let Name = "MemOffs32_32";
546    let SuperClasses = [X86Mem32AsmOperand];
547  }
548  def X86MemOffs32_64AsmOperand : AsmOperandClass {
549    let Name = "MemOffs32_64";
550    let SuperClasses = [X86Mem64AsmOperand];
551  }
552  def X86MemOffs64_8AsmOperand : AsmOperandClass {
553    let Name = "MemOffs64_8";
554    let SuperClasses = [X86Mem8AsmOperand];
555  }
556  def X86MemOffs64_16AsmOperand : AsmOperandClass {
557    let Name = "MemOffs64_16";
558    let SuperClasses = [X86Mem16AsmOperand];
559  }
560  def X86MemOffs64_32AsmOperand : AsmOperandClass {
561    let Name = "MemOffs64_32";
562    let SuperClasses = [X86Mem32AsmOperand];
563  }
564  def X86MemOffs64_64AsmOperand : AsmOperandClass {
565    let Name = "MemOffs64_64";
566    let SuperClasses = [X86Mem64AsmOperand];
567  }
568} // RenderMethod = "addMemOffsOperands"
569
570class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
571    : X86MemOperand<printMethod, parserMatchClass> {
572  let MIOperandInfo = (ops ptr_rc, SEGMENT_REG);
573}
574
575class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass>
576    : X86MemOperand<printMethod, parserMatchClass> {
577  let MIOperandInfo = (ops ptr_rc);
578}
579
580def srcidx8  : X86SrcIdxOperand<"printSrcIdx8",  X86SrcIdx8Operand>;
581def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>;
582def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>;
583def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>;
584def dstidx8  : X86DstIdxOperand<"printDstIdx8",  X86DstIdx8Operand>;
585def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>;
586def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>;
587def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>;
588
589class X86MemOffsOperand<Operand immOperand, string printMethod,
590                        AsmOperandClass parserMatchClass>
591    : X86MemOperand<printMethod, parserMatchClass> {
592  let MIOperandInfo = (ops immOperand, SEGMENT_REG);
593}
594
595def offset16_8  : X86MemOffsOperand<i16imm, "printMemOffs8",
596                                    X86MemOffs16_8AsmOperand>;
597def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16",
598                                    X86MemOffs16_16AsmOperand>;
599def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32",
600                                    X86MemOffs16_32AsmOperand>;
601def offset32_8  : X86MemOffsOperand<i32imm, "printMemOffs8",
602                                    X86MemOffs32_8AsmOperand>;
603def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16",
604                                    X86MemOffs32_16AsmOperand>;
605def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32",
606                                    X86MemOffs32_32AsmOperand>;
607def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64",
608                                    X86MemOffs32_64AsmOperand>;
609def offset64_8  : X86MemOffsOperand<i64imm, "printMemOffs8",
610                                    X86MemOffs64_8AsmOperand>;
611def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16",
612                                    X86MemOffs64_16AsmOperand>;
613def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32",
614                                    X86MemOffs64_32AsmOperand>;
615def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64",
616                                    X86MemOffs64_64AsmOperand>;
617
618def ccode : Operand<i8> {
619  let PrintMethod = "printCondCode";
620  let OperandNamespace = "X86";
621  let OperandType = "OPERAND_COND_CODE";
622}
623
624class ImmSExtAsmOperandClass : AsmOperandClass {
625  let SuperClasses = [ImmAsmOperand];
626  let RenderMethod = "addImmOperands";
627}
628
629def X86GR32orGR64AsmOperand : AsmOperandClass {
630  let Name = "GR32orGR64";
631}
632
633def GR32orGR64 : RegisterOperand<GR32> {
634  let ParserMatchClass = X86GR32orGR64AsmOperand;
635}
636def AVX512RCOperand : AsmOperandClass {
637  let Name = "AVX512RC";
638}
639def AVX512RC : Operand<i32> {
640  let PrintMethod = "printRoundingControl";
641  let OperandNamespace = "X86";
642  let OperandType = "OPERAND_ROUNDING_CONTROL";
643  let ParserMatchClass = AVX512RCOperand;
644}
645
646// Sign-extended immediate classes. We don't need to define the full lattice
647// here because there is no instruction with an ambiguity between ImmSExti64i32
648// and ImmSExti32i8.
649//
650// The strange ranges come from the fact that the assembler always works with
651// 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
652// (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
653
654// [0, 0x7FFFFFFF]                                            |
655//   [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
656def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
657  let Name = "ImmSExti64i32";
658}
659
660// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
661//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
662def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
663  let Name = "ImmSExti16i8";
664  let SuperClasses = [ImmSExti64i32AsmOperand];
665}
666
667// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
668//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
669def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
670  let Name = "ImmSExti32i8";
671}
672
673// [0, 0x0000007F]                                            |
674//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
675def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
676  let Name = "ImmSExti64i8";
677  let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
678                      ImmSExti64i32AsmOperand];
679}
680
681// 4-bit immediate used by some XOP instructions
682// [0, 0xF]
683def ImmUnsignedi4AsmOperand : AsmOperandClass {
684  let Name = "ImmUnsignedi4";
685  let RenderMethod = "addImmOperands";
686  let DiagnosticType = "InvalidImmUnsignedi4";
687}
688
689// Unsigned immediate used by SSE/AVX instructions
690// [0, 0xFF]
691//   [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
692def ImmUnsignedi8AsmOperand : AsmOperandClass {
693  let Name = "ImmUnsignedi8";
694  let RenderMethod = "addImmOperands";
695}
696
697// A couple of more descriptive operand definitions.
698// 16-bits but only 8 bits are significant.
699def i16i8imm  : Operand<i16> {
700  let ParserMatchClass = ImmSExti16i8AsmOperand;
701  let OperandType = "OPERAND_IMMEDIATE";
702}
703// 32-bits but only 8 bits are significant.
704def i32i8imm  : Operand<i32> {
705  let ParserMatchClass = ImmSExti32i8AsmOperand;
706  let OperandType = "OPERAND_IMMEDIATE";
707}
708
709// 64-bits but only 32 bits are significant.
710def i64i32imm  : Operand<i64> {
711  let ParserMatchClass = ImmSExti64i32AsmOperand;
712  let OperandType = "OPERAND_IMMEDIATE";
713}
714
715// 64-bits but only 8 bits are significant.
716def i64i8imm   : Operand<i64> {
717  let ParserMatchClass = ImmSExti64i8AsmOperand;
718  let OperandType = "OPERAND_IMMEDIATE";
719}
720
721// Unsigned 4-bit immediate used by some XOP instructions.
722def u4imm : Operand<i8> {
723  let PrintMethod = "printU8Imm";
724  let ParserMatchClass = ImmUnsignedi4AsmOperand;
725  let OperandType = "OPERAND_IMMEDIATE";
726}
727
728// Unsigned 8-bit immediate used by SSE/AVX instructions.
729def u8imm : Operand<i8> {
730  let PrintMethod = "printU8Imm";
731  let ParserMatchClass = ImmUnsignedi8AsmOperand;
732  let OperandType = "OPERAND_IMMEDIATE";
733}
734
735// 16-bit immediate but only 8-bits are significant and they are unsigned.
736// Used by BT instructions.
737def i16u8imm : Operand<i16> {
738  let PrintMethod = "printU8Imm";
739  let ParserMatchClass = ImmUnsignedi8AsmOperand;
740  let OperandType = "OPERAND_IMMEDIATE";
741}
742
743// 32-bit immediate but only 8-bits are significant and they are unsigned.
744// Used by some SSE/AVX instructions that use intrinsics.
745def i32u8imm : Operand<i32> {
746  let PrintMethod = "printU8Imm";
747  let ParserMatchClass = ImmUnsignedi8AsmOperand;
748  let OperandType = "OPERAND_IMMEDIATE";
749}
750
751// 64-bit immediate but only 8-bits are significant and they are unsigned.
752// Used by BT instructions.
753def i64u8imm : Operand<i64> {
754  let PrintMethod = "printU8Imm";
755  let ParserMatchClass = ImmUnsignedi8AsmOperand;
756  let OperandType = "OPERAND_IMMEDIATE";
757}
758
759def lea64_32mem : Operand<i32> {
760  let PrintMethod = "printanymem";
761  let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);
762  let ParserMatchClass = X86MemAsmOperand;
763}
764
765// Memory operands that use 64-bit pointers in both ILP32 and LP64.
766def lea64mem : Operand<i64> {
767  let PrintMethod = "printanymem";
768  let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);
769  let ParserMatchClass = X86MemAsmOperand;
770}
771
772let RenderMethod = "addMaskPairOperands" in {
773  def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; }
774  def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; }
775  def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; }
776  def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; }
777  def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; }
778}
779
780def VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> {
781  let ParserMatchClass = VK1PairAsmOperand;
782}
783
784def VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> {
785  let ParserMatchClass = VK2PairAsmOperand;
786}
787
788def VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> {
789  let ParserMatchClass = VK4PairAsmOperand;
790}
791
792def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> {
793  let ParserMatchClass = VK8PairAsmOperand;
794}
795
796def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> {
797  let ParserMatchClass = VK16PairAsmOperand;
798}
799
800//===----------------------------------------------------------------------===//
801// X86 Complex Pattern Definitions.
802//
803
804// Define X86-specific addressing mode.
805def addr      : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
806def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
807                               [add, sub, mul, X86mul_imm, shl, or, frameindex],
808                               []>;
809// In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
810def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr",
811                                  [add, sub, mul, X86mul_imm, shl, or,
812                                   frameindex, X86WrapperRIP],
813                                  []>;
814
815def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
816                               [tglobaltlsaddr], []>;
817
818def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr",
819                               [tglobaltlsaddr], []>;
820
821def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr",
822                        [add, sub, mul, X86mul_imm, shl, or, frameindex,
823                         X86WrapperRIP], []>;
824
825def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
826                               [tglobaltlsaddr], []>;
827
828def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
829                               [tglobaltlsaddr], []>;
830
831def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
832
833// A relocatable immediate is either an immediate operand or an operand that can
834// be relocated by the linker to an immediate, such as a regular symbol in
835// non-PIC code.
836def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", [imm, X86Wrapper], [],
837                              0>;
838
839//===----------------------------------------------------------------------===//
840// X86 Instruction Predicate Definitions.
841def TruePredicate : Predicate<"true">;
842
843def HasCMov      : Predicate<"Subtarget->hasCMov()">;
844def NoCMov       : Predicate<"!Subtarget->hasCMov()">;
845
846def HasMMX       : Predicate<"Subtarget->hasMMX()">;
847def Has3DNow     : Predicate<"Subtarget->has3DNow()">;
848def Has3DNowA    : Predicate<"Subtarget->has3DNowA()">;
849def HasSSE1      : Predicate<"Subtarget->hasSSE1()">;
850def UseSSE1      : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
851def HasSSE2      : Predicate<"Subtarget->hasSSE2()">;
852def UseSSE2      : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
853def HasSSE3      : Predicate<"Subtarget->hasSSE3()">;
854def UseSSE3      : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
855def HasSSSE3     : Predicate<"Subtarget->hasSSSE3()">;
856def UseSSSE3     : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
857def HasSSE41     : Predicate<"Subtarget->hasSSE41()">;
858def NoSSE41      : Predicate<"!Subtarget->hasSSE41()">;
859def UseSSE41     : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
860def HasSSE42     : Predicate<"Subtarget->hasSSE42()">;
861def UseSSE42     : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
862def HasSSE4A     : Predicate<"Subtarget->hasSSE4A()">;
863def NoAVX        : Predicate<"!Subtarget->hasAVX()">;
864def HasAVX       : Predicate<"Subtarget->hasAVX()">;
865def HasAVX2      : Predicate<"Subtarget->hasAVX2()">;
866def HasAVX1Only  : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
867def HasAVX512    : Predicate<"Subtarget->hasAVX512()">;
868def UseAVX       : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
869def UseAVX2      : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
870def NoAVX512     : Predicate<"!Subtarget->hasAVX512()">;
871def HasCDI       : Predicate<"Subtarget->hasCDI()">;
872def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">;
873def HasPFI       : Predicate<"Subtarget->hasPFI()">;
874def HasERI       : Predicate<"Subtarget->hasERI()">;
875def HasDQI       : Predicate<"Subtarget->hasDQI()">;
876def NoDQI        : Predicate<"!Subtarget->hasDQI()">;
877def HasBWI       : Predicate<"Subtarget->hasBWI()">;
878def NoBWI        : Predicate<"!Subtarget->hasBWI()">;
879def HasVLX       : Predicate<"Subtarget->hasVLX()">;
880def NoVLX        : Predicate<"!Subtarget->hasVLX()">;
881def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
882def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
883def PKU        : Predicate<"Subtarget->hasPKU()">;
884def HasVNNI    : Predicate<"Subtarget->hasVNNI()">;
885def HasVP2INTERSECT : Predicate<"Subtarget->hasVP2INTERSECT()">;
886def HasBF16      : Predicate<"Subtarget->hasBF16()">;
887
888def HasBITALG    : Predicate<"Subtarget->hasBITALG()">;
889def HasPOPCNT    : Predicate<"Subtarget->hasPOPCNT()">;
890def HasAES       : Predicate<"Subtarget->hasAES()">;
891def HasVAES      : Predicate<"Subtarget->hasVAES()">;
892def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">;
893def HasFXSR      : Predicate<"Subtarget->hasFXSR()">;
894def HasXSAVE     : Predicate<"Subtarget->hasXSAVE()">;
895def HasXSAVEOPT  : Predicate<"Subtarget->hasXSAVEOPT()">;
896def HasXSAVEC    : Predicate<"Subtarget->hasXSAVEC()">;
897def HasXSAVES    : Predicate<"Subtarget->hasXSAVES()">;
898def HasPCLMUL    : Predicate<"Subtarget->hasPCLMUL()">;
899def NoVLX_Or_NoVPCLMULQDQ :
900                    Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">;
901def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">;
902def HasGFNI      : Predicate<"Subtarget->hasGFNI()">;
903def HasFMA       : Predicate<"Subtarget->hasFMA()">;
904def HasFMA4      : Predicate<"Subtarget->hasFMA4()">;
905def NoFMA4       : Predicate<"!Subtarget->hasFMA4()">;
906def HasXOP       : Predicate<"Subtarget->hasXOP()">;
907def HasTBM       : Predicate<"Subtarget->hasTBM()">;
908def NoTBM        : Predicate<"!Subtarget->hasTBM()">;
909def HasLWP       : Predicate<"Subtarget->hasLWP()">;
910def HasMOVBE     : Predicate<"Subtarget->hasMOVBE()">;
911def HasRDRAND    : Predicate<"Subtarget->hasRDRAND()">;
912def HasF16C      : Predicate<"Subtarget->hasF16C()">;
913def HasFSGSBase  : Predicate<"Subtarget->hasFSGSBase()">;
914def HasLZCNT     : Predicate<"Subtarget->hasLZCNT()">;
915def HasBMI       : Predicate<"Subtarget->hasBMI()">;
916def HasBMI2      : Predicate<"Subtarget->hasBMI2()">;
917def NoBMI2       : Predicate<"!Subtarget->hasBMI2()">;
918def HasVBMI      : Predicate<"Subtarget->hasVBMI()">;
919def HasVBMI2     : Predicate<"Subtarget->hasVBMI2()">;
920def HasIFMA      : Predicate<"Subtarget->hasIFMA()">;
921def HasRTM       : Predicate<"Subtarget->hasRTM()">;
922def HasADX       : Predicate<"Subtarget->hasADX()">;
923def HasSHA       : Predicate<"Subtarget->hasSHA()">;
924def HasSGX       : Predicate<"Subtarget->hasSGX()">;
925def HasPRFCHW    : Predicate<"Subtarget->hasPRFCHW()">;
926def HasRDSEED    : Predicate<"Subtarget->hasRDSEED()">;
927def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
928def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
929def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
930def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
931def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
932def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
933def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
934def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
935def HasMOVDIRI   : Predicate<"Subtarget->hasMOVDIRI()">;
936def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
937def HasPTWRITE   : Predicate<"Subtarget->hasPTWRITE()">;
938def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
939def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
940def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
941def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
942def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
943def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
944def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
945def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
946def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;
947def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">;
948def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
949def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
950def HasENQCMD    : Predicate<"Subtarget->hasENQCMD()">;
951def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
952                             AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
953def In64BitMode  : Predicate<"Subtarget->is64Bit()">,
954                             AssemblerPredicate<"Mode64Bit", "64-bit mode">;
955def IsLP64  : Predicate<"Subtarget->isTarget64BitLP64()">;
956def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
957def In16BitMode  : Predicate<"Subtarget->is16Bit()">,
958                             AssemblerPredicate<"Mode16Bit", "16-bit mode">;
959def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
960                             AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
961def In32BitMode  : Predicate<"Subtarget->is32Bit()">,
962                             AssemblerPredicate<"Mode32Bit", "32-bit mode">;
963def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
964def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
965def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||"
966                                  "Subtarget->getFrameLowering()->hasFP(*MF)"> {
967  let RecomputePerFunction = 1;
968}
969def IsPS4        : Predicate<"Subtarget->isTargetPS4()">;
970def NotPS4       : Predicate<"!Subtarget->isTargetPS4()">;
971def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">;
972def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">;
973def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
974def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
975def NearData     : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
976                             "TM.getCodeModel() == CodeModel::Kernel">;
977def IsNotPIC     : Predicate<"!TM.isPositionIndependent()">;
978
979// We could compute these on a per-module basis but doing so requires accessing
980// the Function object through the <Target>Subtarget and objections were raised
981// to that (see post-commit review comments for r301750).
982let RecomputePerFunction = 1 in {
983  def OptForSize   : Predicate<"shouldOptForSize(MF)">;
984  def OptForMinSize : Predicate<"MF->getFunction().hasMinSize()">;
985  def OptForSpeed  : Predicate<"!shouldOptForSize(MF)">;
986  def UseIncDec : Predicate<"!Subtarget->slowIncDec() || "
987                            "shouldOptForSize(MF)">;
988  def NoSSE41_Or_OptForSize : Predicate<"shouldOptForSize(MF) || "
989                                        "!Subtarget->hasSSE41()">;
990}
991
992def CallImmAddr  : Predicate<"Subtarget->isLegalToCallImmediateAddr()">;
993def FavorMemIndirectCall  : Predicate<"!Subtarget->slowTwoMemOps()">;
994def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
995def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">;
996def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">;
997def HasERMSB : Predicate<"Subtarget->hasERMSB()">;
998def HasMFence    : Predicate<"Subtarget->hasMFence()">;
999def UseIndirectThunkCalls : Predicate<"Subtarget->useIndirectThunkCalls()">;
1000def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">;
1001
1002//===----------------------------------------------------------------------===//
1003// X86 Instruction Format Definitions.
1004//
1005
1006include "X86InstrFormats.td"
1007
1008//===----------------------------------------------------------------------===//
1009// Pattern fragments.
1010//
1011
1012// X86 specific condition code. These correspond to CondCode in
1013// X86InstrInfo.h. They must be kept in synch.
1014def X86_COND_O   : PatLeaf<(i8 0)>;
1015def X86_COND_NO  : PatLeaf<(i8 1)>;
1016def X86_COND_B   : PatLeaf<(i8 2)>;  // alt. COND_C
1017def X86_COND_AE  : PatLeaf<(i8 3)>;  // alt. COND_NC
1018def X86_COND_E   : PatLeaf<(i8 4)>;  // alt. COND_Z
1019def X86_COND_NE  : PatLeaf<(i8 5)>;  // alt. COND_NZ
1020def X86_COND_BE  : PatLeaf<(i8 6)>;  // alt. COND_NA
1021def X86_COND_A   : PatLeaf<(i8 7)>;  // alt. COND_NBE
1022def X86_COND_S   : PatLeaf<(i8 8)>;
1023def X86_COND_NS  : PatLeaf<(i8 9)>;
1024def X86_COND_P   : PatLeaf<(i8 10)>; // alt. COND_PE
1025def X86_COND_NP  : PatLeaf<(i8 11)>; // alt. COND_PO
1026def X86_COND_L   : PatLeaf<(i8 12)>; // alt. COND_NGE
1027def X86_COND_GE  : PatLeaf<(i8 13)>; // alt. COND_NL
1028def X86_COND_LE  : PatLeaf<(i8 14)>; // alt. COND_NG
1029def X86_COND_G   : PatLeaf<(i8 15)>; // alt. COND_NLE
1030
1031def i16immSExt8  : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>;
1032def i32immSExt8  : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
1033def i64immSExt8  : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>;
1034def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>;
1035
1036// FIXME: Ideally we would just replace the above i*immSExt* matchers with
1037// relocImm-based matchers, but then FastISel would be unable to use them.
1038def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{
1039  return isSExtRelocImm<8>(N);
1040}]>;
1041def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{
1042  return isSExtRelocImm<32>(N);
1043}]>;
1044
1045// If we have multiple users of an immediate, it's much smaller to reuse
1046// the register, rather than encode the immediate in every instruction.
1047// This has the risk of increasing register pressure from stretched live
1048// ranges, however, the immediates should be trivial to rematerialize by
1049// the RA in the event of high register pressure.
1050// TODO : This is currently enabled for stores and binary ops. There are more
1051// cases for which this can be enabled, though this catches the bulk of the
1052// issues.
1053// TODO2 : This should really also be enabled under O2, but there's currently
1054// an issue with RA where we don't pull the constants into their users
1055// when we rematerialize them. I'll follow-up on enabling O2 after we fix that
1056// issue.
1057// TODO3 : This is currently limited to single basic blocks (DAG creation
1058// pulls block immediates to the top and merges them if necessary).
1059// Eventually, it would be nice to allow ConstantHoisting to merge constants
1060// globally for potentially added savings.
1061//
1062def relocImm8_su : PatLeaf<(i8 relocImm), [{
1063    return !shouldAvoidImmediateInstFormsForSize(N);
1064}]>;
1065def relocImm16_su : PatLeaf<(i16 relocImm), [{
1066    return !shouldAvoidImmediateInstFormsForSize(N);
1067}]>;
1068def relocImm32_su : PatLeaf<(i32 relocImm), [{
1069    return !shouldAvoidImmediateInstFormsForSize(N);
1070}]>;
1071
1072def i16immSExt8_su : PatLeaf<(i16immSExt8), [{
1073    return !shouldAvoidImmediateInstFormsForSize(N);
1074}]>;
1075def i32immSExt8_su : PatLeaf<(i32immSExt8), [{
1076    return !shouldAvoidImmediateInstFormsForSize(N);
1077}]>;
1078def i64immSExt8_su : PatLeaf<(i64immSExt8), [{
1079    return !shouldAvoidImmediateInstFormsForSize(N);
1080}]>;
1081
1082def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{
1083    return !shouldAvoidImmediateInstFormsForSize(N);
1084}]>;
1085def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{
1086    return !shouldAvoidImmediateInstFormsForSize(N);
1087}]>;
1088
1089// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
1090// unsigned field.
1091def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>;
1092
1093def i64immZExt32SExt8 : ImmLeaf<i64, [{
1094  return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm));
1095}]>;
1096
1097// Helper fragments for loads.
1098
1099// It's safe to fold a zextload/extload from i1 as a regular i8 load. The
1100// upper bits are guaranteed to be zero and we were going to emit a MOV8rm
1101// which might get folded during peephole anyway.
1102def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{
1103  LoadSDNode *LD = cast<LoadSDNode>(N);
1104  ISD::LoadExtType ExtType = LD->getExtensionType();
1105  return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD ||
1106         ExtType == ISD::ZEXTLOAD;
1107}]>;
1108
1109// It's always safe to treat a anyext i16 load as a i32 load if the i16 is
1110// known to be 32-bit aligned or better. Ditto for i8 to i16.
1111def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
1112  LoadSDNode *LD = cast<LoadSDNode>(N);
1113  ISD::LoadExtType ExtType = LD->getExtensionType();
1114  if (ExtType == ISD::NON_EXTLOAD)
1115    return true;
1116  if (ExtType == ISD::EXTLOAD)
1117    return LD->getAlignment() >= 2 && LD->isSimple();
1118  return false;
1119}]>;
1120
1121def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
1122  LoadSDNode *LD = cast<LoadSDNode>(N);
1123  ISD::LoadExtType ExtType = LD->getExtensionType();
1124  if (ExtType == ISD::NON_EXTLOAD)
1125    return true;
1126  if (ExtType == ISD::EXTLOAD)
1127    return LD->getAlignment() >= 4 && LD->isSimple();
1128  return false;
1129}]>;
1130
1131def loadi64  : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
1132def loadf32  : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
1133def loadf64  : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
1134def loadf80  : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
1135def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>;
1136def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{
1137  LoadSDNode *Ld = cast<LoadSDNode>(N);
1138  return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
1139}]>;
1140def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{
1141  LoadSDNode *Ld = cast<LoadSDNode>(N);
1142  return Subtarget->hasSSEUnalignedMem() ||
1143         Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
1144}]>;
1145
1146def sextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
1147def sextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
1148def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
1149def sextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
1150def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
1151def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
1152
1153def zextloadi8i1   : PatFrag<(ops node:$ptr), (i8  (zextloadi1 node:$ptr))>;
1154def zextloadi16i1  : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
1155def zextloadi32i1  : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
1156def zextloadi16i8  : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
1157def zextloadi32i8  : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
1158def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
1159def zextloadi64i1  : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
1160def zextloadi64i8  : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
1161def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
1162def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
1163
1164def extloadi8i1    : PatFrag<(ops node:$ptr), (i8  (extloadi1 node:$ptr))>;
1165def extloadi16i1   : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
1166def extloadi32i1   : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
1167def extloadi16i8   : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
1168def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
1169def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
1170def extloadi64i1   : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
1171def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
1172def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
1173
1174// We can treat an i8/i16 extending load to i64 as a 32 bit load if its known
1175// to be 4 byte aligned or better.
1176def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{
1177  LoadSDNode *LD = cast<LoadSDNode>(N);
1178  ISD::LoadExtType ExtType = LD->getExtensionType();
1179  if (ExtType != ISD::EXTLOAD)
1180    return false;
1181  if (LD->getMemoryVT() == MVT::i32)
1182    return true;
1183
1184  return LD->getAlignment() >= 4 && LD->isSimple();
1185}]>;
1186
1187
1188// An 'and' node with a single use.
1189def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
1190  return N->hasOneUse();
1191}]>;
1192// An 'srl' node with a single use.
1193def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
1194  return N->hasOneUse();
1195}]>;
1196// An 'trunc' node with a single use.
1197def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
1198  return N->hasOneUse();
1199}]>;
1200
1201//===----------------------------------------------------------------------===//
1202// Instruction list.
1203//
1204
1205// Nop
1206let hasSideEffects = 0, SchedRW = [WriteNop] in {
1207  def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
1208  def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
1209                "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable;
1210  def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
1211                "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1212  def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero),
1213                "nop{q}\t$zero", []>, TB, NotMemoryFoldable,
1214                Requires<[In64BitMode]>;
1215  // Also allow register so we can assemble/disassemble
1216  def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero),
1217                 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable;
1218  def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero),
1219                 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable;
1220  def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero),
1221                  "nop{q}\t$zero", []>, TB, NotMemoryFoldable,
1222                  Requires<[In64BitMode]>;
1223}
1224
1225
1226// Constructing a stack frame.
1227def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
1228                 "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>;
1229
1230let SchedRW = [WriteALU] in {
1231let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
1232def LEAVE    : I<0xC9, RawFrm, (outs), (ins), "leave", []>,
1233                 Requires<[Not64BitMode]>;
1234
1235let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1236def LEAVE64  : I<0xC9, RawFrm, (outs), (ins), "leave", []>,
1237                 Requires<[In64BitMode]>;
1238} // SchedRW
1239
1240//===----------------------------------------------------------------------===//
1241//  Miscellaneous Instructions.
1242//
1243
1244let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1,
1245    SchedRW = [WriteSystem] in
1246  def Int_eh_sjlj_setup_dispatch
1247    : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>;
1248
1249let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1250let mayLoad = 1, SchedRW = [WriteLoad] in {
1251def POP16r  : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
1252                OpSize16;
1253def POP32r  : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>,
1254                OpSize32, Requires<[Not64BitMode]>;
1255// Long form for the disassembler.
1256let isCodeGenOnly = 1, ForceDisassemble = 1 in {
1257def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
1258                OpSize16, NotMemoryFoldable;
1259def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>,
1260                OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1261} // isCodeGenOnly = 1, ForceDisassemble = 1
1262} // mayLoad, SchedRW
1263let mayStore = 1, mayLoad = 1, SchedRW = [WriteCopy] in {
1264def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>,
1265                OpSize16;
1266def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>,
1267                OpSize32, Requires<[Not64BitMode]>;
1268} // mayStore, mayLoad, SchedRW
1269
1270let mayStore = 1, SchedRW = [WriteStore] in {
1271def PUSH16r  : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
1272                 OpSize16;
1273def PUSH32r  : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>,
1274                 OpSize32, Requires<[Not64BitMode]>;
1275// Long form for the disassembler.
1276let isCodeGenOnly = 1, ForceDisassemble = 1 in {
1277def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
1278                 OpSize16, NotMemoryFoldable;
1279def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>,
1280                 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable;
1281} // isCodeGenOnly = 1, ForceDisassemble = 1
1282
1283def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1284                   "push{w}\t$imm", []>, OpSize16;
1285def PUSHi16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1286                   "push{w}\t$imm", []>, OpSize16;
1287
1288def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1289                   "push{l}\t$imm", []>, OpSize32,
1290                   Requires<[Not64BitMode]>;
1291def PUSHi32  : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1292                   "push{l}\t$imm", []>, OpSize32,
1293                   Requires<[Not64BitMode]>;
1294} // mayStore, SchedRW
1295
1296let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
1297def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>,
1298                 OpSize16;
1299def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>,
1300                 OpSize32, Requires<[Not64BitMode]>;
1301} // mayLoad, mayStore, SchedRW
1302
1303}
1304
1305let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
1306    SchedRW = [WriteRMW], Defs = [ESP] in {
1307  let Uses = [ESP] in
1308  def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins),
1309                   [(set GR32:$dst, (int_x86_flags_read_u32))]>,
1310                Requires<[Not64BitMode]>;
1311
1312  let Uses = [RSP] in
1313  def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins),
1314                   [(set GR64:$dst, (int_x86_flags_read_u64))]>,
1315                Requires<[In64BitMode]>;
1316}
1317
1318let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
1319    SchedRW = [WriteRMW] in {
1320  let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
1321  def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src),
1322                   [(int_x86_flags_write_u32 GR32:$src)]>,
1323                Requires<[Not64BitMode]>;
1324
1325  let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
1326  def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src),
1327                   [(int_x86_flags_write_u64 GR64:$src)]>,
1328                Requires<[In64BitMode]>;
1329}
1330
1331let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1332    SchedRW = [WriteLoad] in {
1333def POPF16   : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16;
1334def POPF32   : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32,
1335                 Requires<[Not64BitMode]>;
1336}
1337
1338let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
1339    SchedRW = [WriteStore] in {
1340def PUSHF16  : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16;
1341def PUSHF32  : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32,
1342                 Requires<[Not64BitMode]>;
1343}
1344
1345let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1346let mayLoad = 1, SchedRW = [WriteLoad] in {
1347def POP64r   : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>,
1348                 OpSize32, Requires<[In64BitMode]>;
1349// Long form for the disassembler.
1350let isCodeGenOnly = 1, ForceDisassemble = 1 in {
1351def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>,
1352                OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable;
1353} // isCodeGenOnly = 1, ForceDisassemble = 1
1354} // mayLoad, SchedRW
1355let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in
1356def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>,
1357                OpSize32, Requires<[In64BitMode]>;
1358let mayStore = 1, SchedRW = [WriteStore] in {
1359def PUSH64r  : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>,
1360                 OpSize32, Requires<[In64BitMode]>;
1361// Long form for the disassembler.
1362let isCodeGenOnly = 1, ForceDisassemble = 1 in {
1363def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>,
1364                 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable;
1365} // isCodeGenOnly = 1, ForceDisassemble = 1
1366} // mayStore, SchedRW
1367let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
1368def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>,
1369                 OpSize32, Requires<[In64BitMode]>;
1370} // mayLoad, mayStore, SchedRW
1371}
1372
1373let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1374    SchedRW = [WriteStore] in {
1375def PUSH64i8   : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1376                    "push{q}\t$imm", []>, OpSize32,
1377                    Requires<[In64BitMode]>;
1378def PUSH64i32  : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1379                    "push{q}\t$imm", []>, OpSize32,
1380                    Requires<[In64BitMode]>;
1381}
1382
1383let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1384def POPF64   : I<0x9D, RawFrm, (outs), (ins), "popfq", []>,
1385               OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1386let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
1387def PUSHF64    : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>,
1388                 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1389
1390let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1391    mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1392def POPA32   : I<0x61, RawFrm, (outs), (ins), "popal", []>,
1393               OpSize32, Requires<[Not64BitMode]>;
1394def POPA16   : I<0x61, RawFrm, (outs), (ins), "popaw", []>,
1395               OpSize16, Requires<[Not64BitMode]>;
1396}
1397let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1398    mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1399def PUSHA32  : I<0x60, RawFrm, (outs), (ins), "pushal", []>,
1400               OpSize32, Requires<[Not64BitMode]>;
1401def PUSHA16  : I<0x60, RawFrm, (outs), (ins), "pushaw", []>,
1402               OpSize16, Requires<[Not64BitMode]>;
1403}
1404
1405let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in {
1406// This instruction is a consequence of BSWAP32r observing operand size. The
1407// encoding is valid, but the behavior is undefined.
1408let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
1409def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1410                     "bswap{w}\t$dst", []>, OpSize16, TB;
1411// GR32 = bswap GR32
1412def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1413                 "bswap{l}\t$dst",
1414                 [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB;
1415
1416let SchedRW = [WriteBSWAP64] in
1417def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1418                  "bswap{q}\t$dst",
1419                  [(set GR64:$dst, (bswap GR64:$src))]>, TB;
1420} // Constraints = "$src = $dst", SchedRW
1421
1422// Bit scan instructions.
1423let Defs = [EFLAGS] in {
1424def BSF16rr  : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1425                 "bsf{w}\t{$src, $dst|$dst, $src}",
1426                 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>,
1427                  PS, OpSize16, Sched<[WriteBSF]>;
1428def BSF16rm  : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1429                 "bsf{w}\t{$src, $dst|$dst, $src}",
1430                 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>,
1431                 PS, OpSize16, Sched<[WriteBSFLd]>;
1432def BSF32rr  : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1433                 "bsf{l}\t{$src, $dst|$dst, $src}",
1434                 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>,
1435                 PS, OpSize32, Sched<[WriteBSF]>;
1436def BSF32rm  : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1437                 "bsf{l}\t{$src, $dst|$dst, $src}",
1438                 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>,
1439                 PS, OpSize32, Sched<[WriteBSFLd]>;
1440def BSF64rr  : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1441                  "bsf{q}\t{$src, $dst|$dst, $src}",
1442                  [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>,
1443                  PS, Sched<[WriteBSF]>;
1444def BSF64rm  : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1445                  "bsf{q}\t{$src, $dst|$dst, $src}",
1446                  [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>,
1447                  PS, Sched<[WriteBSFLd]>;
1448
1449def BSR16rr  : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1450                 "bsr{w}\t{$src, $dst|$dst, $src}",
1451                 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>,
1452                 PS, OpSize16, Sched<[WriteBSR]>;
1453def BSR16rm  : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1454                 "bsr{w}\t{$src, $dst|$dst, $src}",
1455                 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>,
1456                 PS, OpSize16, Sched<[WriteBSRLd]>;
1457def BSR32rr  : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1458                 "bsr{l}\t{$src, $dst|$dst, $src}",
1459                 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>,
1460                 PS, OpSize32, Sched<[WriteBSR]>;
1461def BSR32rm  : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1462                 "bsr{l}\t{$src, $dst|$dst, $src}",
1463                 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>,
1464                 PS, OpSize32, Sched<[WriteBSRLd]>;
1465def BSR64rr  : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1466                  "bsr{q}\t{$src, $dst|$dst, $src}",
1467                  [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>,
1468                  PS, Sched<[WriteBSR]>;
1469def BSR64rm  : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1470                  "bsr{q}\t{$src, $dst|$dst, $src}",
1471                  [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>,
1472                  PS, Sched<[WriteBSRLd]>;
1473} // Defs = [EFLAGS]
1474
1475let SchedRW = [WriteMicrocoded] in {
1476let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in {
1477def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1478              "movsb\t{$src, $dst|$dst, $src}", []>;
1479def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1480              "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16;
1481def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1482              "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32;
1483def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1484               "movsq\t{$src, $dst|$dst, $src}", []>,
1485               Requires<[In64BitMode]>;
1486}
1487
1488let Defs = [EDI], Uses = [AL,EDI,DF] in
1489def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst),
1490              "stosb\t{%al, $dst|$dst, al}", []>;
1491let Defs = [EDI], Uses = [AX,EDI,DF] in
1492def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst),
1493              "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16;
1494let Defs = [EDI], Uses = [EAX,EDI,DF] in
1495def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst),
1496              "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32;
1497let Defs = [RDI], Uses = [RAX,RDI,DF] in
1498def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst),
1499               "stosq\t{%rax, $dst|$dst, rax}", []>,
1500               Requires<[In64BitMode]>;
1501
1502let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in
1503def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1504              "scasb\t{$dst, %al|al, $dst}", []>;
1505let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in
1506def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1507              "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16;
1508let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in
1509def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1510              "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32;
1511let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in
1512def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1513               "scasq\t{$dst, %rax|rax, $dst}", []>,
1514               Requires<[In64BitMode]>;
1515
1516let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in {
1517def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1518              "cmpsb\t{$dst, $src|$src, $dst}", []>;
1519def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1520              "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16;
1521def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1522              "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32;
1523def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1524               "cmpsq\t{$dst, $src|$src, $dst}", []>,
1525               Requires<[In64BitMode]>;
1526}
1527} // SchedRW
1528
1529//===----------------------------------------------------------------------===//
1530//  Move Instructions.
1531//
1532let SchedRW = [WriteMove] in {
1533let hasSideEffects = 0, isMoveReg = 1 in {
1534def MOV8rr  : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1535                "mov{b}\t{$src, $dst|$dst, $src}", []>;
1536def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1537                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
1538def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1539                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
1540def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1541                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
1542}
1543
1544let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1545def MOV8ri  : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1546                   "mov{b}\t{$src, $dst|$dst, $src}",
1547                   [(set GR8:$dst, imm:$src)]>;
1548def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1549                   "mov{w}\t{$src, $dst|$dst, $src}",
1550                   [(set GR16:$dst, imm:$src)]>, OpSize16;
1551def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1552                   "mov{l}\t{$src, $dst|$dst, $src}",
1553                   [(set GR32:$dst, relocImm:$src)]>, OpSize32;
1554def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1555                       "mov{q}\t{$src, $dst|$dst, $src}",
1556                       [(set GR64:$dst, i64immSExt32:$src)]>;
1557}
1558let isReMaterializable = 1, isMoveImm = 1 in {
1559def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1560                    "movabs{q}\t{$src, $dst|$dst, $src}",
1561                    [(set GR64:$dst, relocImm:$src)]>;
1562}
1563
1564// Longer forms that use a ModR/M byte. Needed for disassembler
1565let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1566def MOV8ri_alt  : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1567                   "mov{b}\t{$src, $dst|$dst, $src}", []>,
1568                   FoldGenData<"MOV8ri">;
1569def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1570                   "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
1571                   FoldGenData<"MOV16ri">;
1572def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1573                   "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
1574                   FoldGenData<"MOV32ri">;
1575}
1576} // SchedRW
1577
1578let SchedRW = [WriteStore] in {
1579def MOV8mi  : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1580                   "mov{b}\t{$src, $dst|$dst, $src}",
1581                   [(store (i8 relocImm8_su:$src), addr:$dst)]>;
1582def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1583                   "mov{w}\t{$src, $dst|$dst, $src}",
1584                   [(store (i16 relocImm16_su:$src), addr:$dst)]>, OpSize16;
1585def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1586                   "mov{l}\t{$src, $dst|$dst, $src}",
1587                   [(store (i32 relocImm32_su:$src), addr:$dst)]>, OpSize32;
1588def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1589                       "mov{q}\t{$src, $dst|$dst, $src}",
1590                       [(store i64relocImmSExt32_su:$src, addr:$dst)]>,
1591                       Requires<[In64BitMode]>;
1592} // SchedRW
1593
1594let hasSideEffects = 0 in {
1595
1596/// Memory offset versions of moves. The immediate is an address mode sized
1597/// offset from the segment base.
1598let SchedRW = [WriteALU] in {
1599let mayLoad = 1 in {
1600let Defs = [AL] in
1601def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1602                    "mov{b}\t{$src, %al|al, $src}", []>,
1603                    AdSize32;
1604let Defs = [AX] in
1605def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1606                     "mov{w}\t{$src, %ax|ax, $src}", []>,
1607                     OpSize16, AdSize32;
1608let Defs = [EAX] in
1609def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1610                     "mov{l}\t{$src, %eax|eax, $src}", []>,
1611                     OpSize32, AdSize32;
1612let Defs = [RAX] in
1613def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src),
1614                      "mov{q}\t{$src, %rax|rax, $src}", []>,
1615                      AdSize32;
1616
1617let Defs = [AL] in
1618def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1619                    "mov{b}\t{$src, %al|al, $src}", []>, AdSize16;
1620let Defs = [AX] in
1621def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1622                     "mov{w}\t{$src, %ax|ax, $src}", []>,
1623                     OpSize16, AdSize16;
1624let Defs = [EAX] in
1625def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1626                     "mov{l}\t{$src, %eax|eax, $src}", []>,
1627                     AdSize16, OpSize32;
1628} // mayLoad
1629let mayStore = 1 in {
1630let Uses = [AL] in
1631def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst),
1632                    "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32;
1633let Uses = [AX] in
1634def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst),
1635                     "mov{w}\t{%ax, $dst|$dst, ax}", []>,
1636                     OpSize16, AdSize32;
1637let Uses = [EAX] in
1638def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst),
1639                     "mov{l}\t{%eax, $dst|$dst, eax}", []>,
1640                     OpSize32, AdSize32;
1641let Uses = [RAX] in
1642def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst),
1643                      "mov{q}\t{%rax, $dst|$dst, rax}", []>,
1644                      AdSize32;
1645
1646let Uses = [AL] in
1647def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst),
1648                    "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16;
1649let Uses = [AX] in
1650def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst),
1651                     "mov{w}\t{%ax, $dst|$dst, ax}", []>,
1652                     OpSize16, AdSize16;
1653let Uses = [EAX] in
1654def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst),
1655                     "mov{l}\t{%eax, $dst|$dst, eax}", []>,
1656                     OpSize32, AdSize16;
1657} // mayStore
1658
1659// These forms all have full 64-bit absolute addresses in their instructions
1660// and use the movabs mnemonic to indicate this specific form.
1661let mayLoad = 1 in {
1662let Defs = [AL] in
1663def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1664                    "movabs{b}\t{$src, %al|al, $src}", []>,
1665                    AdSize64;
1666let Defs = [AX] in
1667def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1668                     "movabs{w}\t{$src, %ax|ax, $src}", []>,
1669                     OpSize16, AdSize64;
1670let Defs = [EAX] in
1671def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1672                     "movabs{l}\t{$src, %eax|eax, $src}", []>,
1673                     OpSize32, AdSize64;
1674let Defs = [RAX] in
1675def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1676                     "movabs{q}\t{$src, %rax|rax, $src}", []>,
1677                     AdSize64;
1678} // mayLoad
1679
1680let mayStore = 1 in {
1681let Uses = [AL] in
1682def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst),
1683                    "movabs{b}\t{%al, $dst|$dst, al}", []>,
1684                    AdSize64;
1685let Uses = [AX] in
1686def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst),
1687                     "movabs{w}\t{%ax, $dst|$dst, ax}", []>,
1688                     OpSize16, AdSize64;
1689let Uses = [EAX] in
1690def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst),
1691                     "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1692                     OpSize32, AdSize64;
1693let Uses = [RAX] in
1694def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst),
1695                     "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1696                     AdSize64;
1697} // mayStore
1698} // SchedRW
1699} // hasSideEffects = 0
1700
1701let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1702    SchedRW = [WriteMove], isMoveReg = 1 in {
1703def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1704                   "mov{b}\t{$src, $dst|$dst, $src}", []>,
1705                   FoldGenData<"MOV8rr">;
1706def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1707                    "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
1708                    FoldGenData<"MOV16rr">;
1709def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1710                    "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
1711                    FoldGenData<"MOV32rr">;
1712def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1713                     "mov{q}\t{$src, $dst|$dst, $src}", []>,
1714                     FoldGenData<"MOV64rr">;
1715}
1716
1717// Reversed version with ".s" suffix for GAS compatibility.
1718def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}",
1719                (MOV8rr_REV GR8:$dst, GR8:$src), 0>;
1720def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}",
1721                (MOV16rr_REV GR16:$dst, GR16:$src), 0>;
1722def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}",
1723                (MOV32rr_REV GR32:$dst, GR32:$src), 0>;
1724def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}",
1725                (MOV64rr_REV GR64:$dst, GR64:$src), 0>;
1726def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
1727                (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">;
1728def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
1729                (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">;
1730def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
1731                (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">;
1732def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
1733                (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">;
1734
1735let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1736def MOV8rm  : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1737                "mov{b}\t{$src, $dst|$dst, $src}",
1738                [(set GR8:$dst, (loadi8 addr:$src))]>;
1739def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1740                "mov{w}\t{$src, $dst|$dst, $src}",
1741                [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16;
1742def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1743                "mov{l}\t{$src, $dst|$dst, $src}",
1744                [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32;
1745def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1746                 "mov{q}\t{$src, $dst|$dst, $src}",
1747                 [(set GR64:$dst, (load addr:$src))]>;
1748}
1749
1750let SchedRW = [WriteStore] in {
1751def MOV8mr  : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1752                "mov{b}\t{$src, $dst|$dst, $src}",
1753                [(store GR8:$src, addr:$dst)]>;
1754def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1755                "mov{w}\t{$src, $dst|$dst, $src}",
1756                [(store GR16:$src, addr:$dst)]>, OpSize16;
1757def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1758                "mov{l}\t{$src, $dst|$dst, $src}",
1759                [(store GR32:$src, addr:$dst)]>, OpSize32;
1760def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1761                 "mov{q}\t{$src, $dst|$dst, $src}",
1762                 [(store GR64:$src, addr:$dst)]>;
1763} // SchedRW
1764
1765// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1766// that they can be used for copying and storing h registers, which can't be
1767// encoded when a REX prefix is present.
1768let isCodeGenOnly = 1 in {
1769let hasSideEffects = 0, isMoveReg = 1 in
1770def MOV8rr_NOREX : I<0x88, MRMDestReg,
1771                     (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1772                     "mov{b}\t{$src, $dst|$dst, $src}", []>,
1773                   Sched<[WriteMove]>;
1774let mayStore = 1, hasSideEffects = 0 in
1775def MOV8mr_NOREX : I<0x88, MRMDestMem,
1776                     (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1777                     "mov{b}\t{$src, $dst|$dst, $src}", []>,
1778                     Sched<[WriteStore]>;
1779let mayLoad = 1, hasSideEffects = 0,
1780    canFoldAsLoad = 1, isReMaterializable = 1 in
1781def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1782                     (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1783                     "mov{b}\t{$src, $dst|$dst, $src}", []>,
1784                     Sched<[WriteLoad]>;
1785}
1786
1787
1788// Condition code ops, incl. set if equal/not equal/...
1789let SchedRW = [WriteLAHFSAHF] in {
1790let Defs = [EFLAGS], Uses = [AH] in
1791def SAHF     : I<0x9E, RawFrm, (outs),  (ins), "sahf",
1792                 [(set EFLAGS, (X86sahf AH))]>,
1793                 Requires<[HasLAHFSAHF]>;
1794let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1795def LAHF     : I<0x9F, RawFrm, (outs),  (ins), "lahf", []>,  // AH = flags
1796               Requires<[HasLAHFSAHF]>;
1797} // SchedRW
1798
1799//===----------------------------------------------------------------------===//
1800// Bit tests instructions: BT, BTS, BTR, BTC.
1801
1802let Defs = [EFLAGS] in {
1803let SchedRW = [WriteBitTest] in {
1804def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1805               "bt{w}\t{$src2, $src1|$src1, $src2}",
1806               [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>,
1807               OpSize16, TB, NotMemoryFoldable;
1808def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1809               "bt{l}\t{$src2, $src1|$src1, $src2}",
1810               [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>,
1811               OpSize32, TB, NotMemoryFoldable;
1812def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1813               "bt{q}\t{$src2, $src1|$src1, $src2}",
1814               [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB,
1815               NotMemoryFoldable;
1816} // SchedRW
1817
1818// Unlike with the register+register form, the memory+register form of the
1819// bt instruction does not ignore the high bits of the index. From ISel's
1820// perspective, this is pretty bizarre. Make these instructions disassembly
1821// only for now. These instructions are also slow on modern CPUs so that's
1822// another reason to avoid generating them.
1823
1824let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteBitTestRegLd] in {
1825  def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1826                 "bt{w}\t{$src2, $src1|$src1, $src2}",
1827                 []>, OpSize16, TB, NotMemoryFoldable;
1828  def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1829                 "bt{l}\t{$src2, $src1|$src1, $src2}",
1830                 []>, OpSize32, TB, NotMemoryFoldable;
1831  def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1832                 "bt{q}\t{$src2, $src1|$src1, $src2}",
1833                  []>, TB, NotMemoryFoldable;
1834}
1835
1836let SchedRW = [WriteBitTest] in {
1837def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16u8imm:$src2),
1838                "bt{w}\t{$src2, $src1|$src1, $src2}",
1839                [(set EFLAGS, (X86bt GR16:$src1, imm:$src2))]>,
1840                OpSize16, TB;
1841def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32u8imm:$src2),
1842                "bt{l}\t{$src2, $src1|$src1, $src2}",
1843                [(set EFLAGS, (X86bt GR32:$src1, imm:$src2))]>,
1844                OpSize32, TB;
1845def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64u8imm:$src2),
1846                "bt{q}\t{$src2, $src1|$src1, $src2}",
1847                [(set EFLAGS, (X86bt GR64:$src1, imm:$src2))]>, TB;
1848} // SchedRW
1849
1850// Note that these instructions aren't slow because that only applies when the
1851// other operand is in a register. When it's an immediate, bt is still fast.
1852let SchedRW = [WriteBitTestImmLd] in {
1853def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16u8imm:$src2),
1854                  "bt{w}\t{$src2, $src1|$src1, $src2}",
1855                  [(set EFLAGS, (X86bt (loadi16 addr:$src1),
1856                                       imm:$src2))]>,
1857                  OpSize16, TB;
1858def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32u8imm:$src2),
1859                  "bt{l}\t{$src2, $src1|$src1, $src2}",
1860                  [(set EFLAGS, (X86bt (loadi32 addr:$src1),
1861                                       imm:$src2))]>,
1862                  OpSize32, TB;
1863def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64u8imm:$src2),
1864                "bt{q}\t{$src2, $src1|$src1, $src2}",
1865                [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1866                                     imm:$src2))]>, TB,
1867                Requires<[In64BitMode]>;
1868} // SchedRW
1869
1870let hasSideEffects = 0 in {
1871let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
1872def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1873                "btc{w}\t{$src2, $src1|$src1, $src2}", []>,
1874                OpSize16, TB, NotMemoryFoldable;
1875def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1876                "btc{l}\t{$src2, $src1|$src1, $src2}", []>,
1877                OpSize32, TB, NotMemoryFoldable;
1878def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1879                 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1880                 NotMemoryFoldable;
1881} // SchedRW
1882
1883let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in {
1884def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1885                "btc{w}\t{$src2, $src1|$src1, $src2}", []>,
1886                OpSize16, TB, NotMemoryFoldable;
1887def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1888                "btc{l}\t{$src2, $src1|$src1, $src2}", []>,
1889                OpSize32, TB, NotMemoryFoldable;
1890def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1891                 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1892                 NotMemoryFoldable;
1893}
1894
1895let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
1896def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2),
1897                    "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
1898def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2),
1899                    "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB;
1900def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2),
1901                    "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1902} // SchedRW
1903
1904let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in {
1905def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16u8imm:$src2),
1906                    "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
1907def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32u8imm:$src2),
1908                    "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB;
1909def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64u8imm:$src2),
1910                    "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1911                    Requires<[In64BitMode]>;
1912}
1913
1914let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
1915def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1916                "btr{w}\t{$src2, $src1|$src1, $src2}", []>,
1917                OpSize16, TB, NotMemoryFoldable;
1918def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1919                "btr{l}\t{$src2, $src1|$src1, $src2}", []>,
1920                OpSize32, TB, NotMemoryFoldable;
1921def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1922                 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1923                 NotMemoryFoldable;
1924} // SchedRW
1925
1926let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in {
1927def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1928                "btr{w}\t{$src2, $src1|$src1, $src2}", []>,
1929                OpSize16, TB, NotMemoryFoldable;
1930def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1931                "btr{l}\t{$src2, $src1|$src1, $src2}", []>,
1932                OpSize32, TB, NotMemoryFoldable;
1933def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1934                 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1935                 NotMemoryFoldable;
1936}
1937
1938let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
1939def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2),
1940                    "btr{w}\t{$src2, $src1|$src1, $src2}", []>,
1941                    OpSize16, TB;
1942def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2),
1943                    "btr{l}\t{$src2, $src1|$src1, $src2}", []>,
1944                    OpSize32, TB;
1945def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2),
1946                    "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1947} // SchedRW
1948
1949let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in {
1950def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16u8imm:$src2),
1951                    "btr{w}\t{$src2, $src1|$src1, $src2}", []>,
1952                    OpSize16, TB;
1953def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32u8imm:$src2),
1954                    "btr{l}\t{$src2, $src1|$src1, $src2}", []>,
1955                    OpSize32, TB;
1956def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64u8imm:$src2),
1957                    "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1958                    Requires<[In64BitMode]>;
1959}
1960
1961let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
1962def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1963                "bts{w}\t{$src2, $src1|$src1, $src2}", []>,
1964                OpSize16, TB, NotMemoryFoldable;
1965def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1966                "bts{l}\t{$src2, $src1|$src1, $src2}", []>,
1967              OpSize32, TB, NotMemoryFoldable;
1968def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1969               "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1970               NotMemoryFoldable;
1971} // SchedRW
1972
1973let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in {
1974def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1975              "bts{w}\t{$src2, $src1|$src1, $src2}", []>,
1976              OpSize16, TB, NotMemoryFoldable;
1977def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1978              "bts{l}\t{$src2, $src1|$src1, $src2}", []>,
1979              OpSize32, TB, NotMemoryFoldable;
1980def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1981                 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
1982                 NotMemoryFoldable;
1983}
1984
1985let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in {
1986def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2),
1987                    "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
1988def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2),
1989                    "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB;
1990def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2),
1991                    "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1992} // SchedRW
1993
1994let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in {
1995def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16u8imm:$src2),
1996                    "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
1997def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32u8imm:$src2),
1998                    "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB;
1999def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64u8imm:$src2),
2000                    "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB,
2001                    Requires<[In64BitMode]>;
2002}
2003} // hasSideEffects = 0
2004} // Defs = [EFLAGS]
2005
2006
2007//===----------------------------------------------------------------------===//
2008// Atomic support
2009//
2010
2011// Atomic swap. These are just normal xchg instructions. But since a memory
2012// operand is referenced, the atomicity is ensured.
2013multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> {
2014  let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
2015    def NAME#8rm  : I<opc8, MRMSrcMem, (outs GR8:$dst),
2016                      (ins GR8:$val, i8mem:$ptr),
2017                      !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
2018                      [(set
2019                         GR8:$dst,
2020                         (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>;
2021    def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
2022                      (ins GR16:$val, i16mem:$ptr),
2023                      !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
2024                      [(set
2025                         GR16:$dst,
2026                         (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>,
2027                      OpSize16;
2028    def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
2029                      (ins GR32:$val, i32mem:$ptr),
2030                      !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
2031                      [(set
2032                         GR32:$dst,
2033                         (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>,
2034                      OpSize32;
2035    def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
2036                       (ins GR64:$val, i64mem:$ptr),
2037                       !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
2038                       [(set
2039                         GR64:$dst,
2040                         (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>;
2041  }
2042}
2043
2044defm XCHG    : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable;
2045
2046// Swap between registers.
2047let SchedRW = [WriteXCHG] in {
2048let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in {
2049def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2),
2050                (ins GR8:$src1, GR8:$src2),
2051                "xchg{b}\t{$src2, $src1|$src1, $src2}", []>, NotMemoryFoldable;
2052def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2),
2053                 (ins GR16:$src1, GR16:$src2),
2054                 "xchg{w}\t{$src2, $src1|$src1, $src2}", []>,
2055                 OpSize16, NotMemoryFoldable;
2056def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2),
2057                 (ins GR32:$src1, GR32:$src2),
2058                 "xchg{l}\t{$src2, $src1|$src1, $src2}", []>,
2059                 OpSize32, NotMemoryFoldable;
2060def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2),
2061                  (ins GR64:$src1 ,GR64:$src2),
2062                  "xchg{q}\t{$src2, $src1|$src1, $src2}", []>, NotMemoryFoldable;
2063}
2064
2065// Swap between EAX and other registers.
2066let Constraints = "$src = $dst", hasSideEffects = 0 in {
2067let Uses = [AX], Defs = [AX] in
2068def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
2069                  "xchg{w}\t{$src, %ax|ax, $src}", []>, OpSize16;
2070let Uses = [EAX], Defs = [EAX] in
2071def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
2072                  "xchg{l}\t{$src, %eax|eax, $src}", []>, OpSize32;
2073let Uses = [RAX], Defs = [RAX] in
2074def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
2075                  "xchg{q}\t{$src, %rax|rax, $src}", []>;
2076}
2077} // SchedRW
2078
2079let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2",
2080    Defs = [EFLAGS], SchedRW = [WriteXCHG] in {
2081def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2),
2082                (ins GR8:$src1, GR8:$src2),
2083                "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB;
2084def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2),
2085                 (ins GR16:$src1, GR16:$src2),
2086                 "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
2087def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2),
2088                  (ins GR32:$src1, GR32:$src2),
2089                 "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
2090def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2),
2091                  (ins GR64:$src1, GR64:$src2),
2092                  "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
2093} // SchedRW
2094
2095let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst",
2096    Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in {
2097def XADD8rm   : I<0xC0, MRMSrcMem, (outs GR8:$dst),
2098                  (ins GR8:$val, i8mem:$ptr),
2099                 "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB;
2100def XADD16rm  : I<0xC1, MRMSrcMem, (outs GR16:$dst),
2101                  (ins GR16:$val, i16mem:$ptr),
2102                 "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB,
2103                 OpSize16;
2104def XADD32rm  : I<0xC1, MRMSrcMem, (outs GR32:$dst),
2105                  (ins GR32:$val, i32mem:$ptr),
2106                 "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB,
2107                 OpSize32;
2108def XADD64rm  : RI<0xC1, MRMSrcMem, (outs GR64:$dst),
2109                   (ins GR64:$val, i64mem:$ptr),
2110                   "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB;
2111
2112}
2113
2114let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in {
2115let Defs = [AL, EFLAGS], Uses = [AL] in
2116def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
2117                   "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB,
2118                   NotMemoryFoldable;
2119let Defs = [AX, EFLAGS], Uses = [AX] in
2120def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
2121                    "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16,
2122                    NotMemoryFoldable;
2123let Defs = [EAX, EFLAGS], Uses = [EAX] in
2124def CMPXCHG32rr  : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
2125                     "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32,
2126                     NotMemoryFoldable;
2127let Defs = [RAX, EFLAGS], Uses = [RAX] in
2128def CMPXCHG64rr  : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
2129                      "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB,
2130                      NotMemoryFoldable;
2131} // SchedRW, hasSideEffects
2132
2133let SchedRW = [WriteCMPXCHGRMW], mayLoad = 1, mayStore = 1,
2134    hasSideEffects = 0 in {
2135let Defs = [AL, EFLAGS], Uses = [AL] in
2136def CMPXCHG8rm   : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2137                     "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB,
2138                     NotMemoryFoldable;
2139let Defs = [AX, EFLAGS], Uses = [AX] in
2140def CMPXCHG16rm  : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2141                     "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16,
2142                     NotMemoryFoldable;
2143let Defs = [EAX, EFLAGS], Uses = [EAX] in
2144def CMPXCHG32rm  : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2145                     "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32,
2146                     NotMemoryFoldable;
2147let Defs = [RAX, EFLAGS], Uses = [RAX] in
2148def CMPXCHG64rm  : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2149                      "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB,
2150                      NotMemoryFoldable;
2151
2152let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
2153def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
2154                  "cmpxchg8b\t$dst", []>, TB, Requires<[HasCmpxchg8b]>;
2155
2156let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
2157// NOTE: In64BitMode check needed for the AssemblerPredicate.
2158def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
2159                    "cmpxchg16b\t$dst", []>,
2160                    TB, Requires<[HasCmpxchg16b,In64BitMode]>;
2161} // SchedRW, mayLoad, mayStore, hasSideEffects
2162
2163
2164// Lock instruction prefix
2165let SchedRW = [WriteMicrocoded] in
2166def LOCK_PREFIX : I<0xF0, RawFrm, (outs),  (ins), "lock", []>;
2167
2168let SchedRW = [WriteNop] in {
2169
2170// Rex64 instruction prefix
2171def REX64_PREFIX : I<0x48, RawFrm, (outs),  (ins), "rex64", []>,
2172                     Requires<[In64BitMode]>;
2173
2174// Data16 instruction prefix
2175def DATA16_PREFIX : I<0x66, RawFrm, (outs),  (ins), "data16", []>;
2176} // SchedRW
2177
2178// Repeat string operation instruction prefixes
2179let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in {
2180// Repeat (used with INS, OUTS, MOVS, LODS and STOS)
2181def REP_PREFIX : I<0xF3, RawFrm, (outs),  (ins), "rep", []>;
2182// Repeat while not equal (used with CMPS and SCAS)
2183def REPNE_PREFIX : I<0xF2, RawFrm, (outs),  (ins), "repne", []>;
2184}
2185
2186// String manipulation instructions
2187let SchedRW = [WriteMicrocoded] in {
2188let Defs = [AL,ESI], Uses = [ESI,DF] in
2189def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
2190              "lodsb\t{$src, %al|al, $src}", []>;
2191let Defs = [AX,ESI], Uses = [ESI,DF] in
2192def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
2193              "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16;
2194let Defs = [EAX,ESI], Uses = [ESI,DF] in
2195def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
2196              "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32;
2197let Defs = [RAX,ESI], Uses = [ESI,DF] in
2198def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
2199               "lodsq\t{$src, %rax|rax, $src}", []>,
2200               Requires<[In64BitMode]>;
2201}
2202
2203let SchedRW = [WriteSystem] in {
2204let Defs = [ESI], Uses = [DX,ESI,DF] in {
2205def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
2206             "outsb\t{$src, %dx|dx, $src}", []>;
2207def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
2208              "outsw\t{$src, %dx|dx, $src}", []>, OpSize16;
2209def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
2210              "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32;
2211}
2212
2213let Defs = [EDI], Uses = [DX,EDI,DF] in {
2214def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst),
2215             "insb\t{%dx, $dst|$dst, dx}", []>;
2216def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst),
2217             "insw\t{%dx, $dst|$dst, dx}", []>,  OpSize16;
2218def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst),
2219             "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32;
2220}
2221}
2222
2223// EFLAGS management instructions.
2224let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
2225def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
2226def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
2227def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
2228}
2229
2230// DF management instructions.
2231let SchedRW = [WriteALU], Defs = [DF] in {
2232def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
2233def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
2234}
2235
2236// Table lookup instructions
2237let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in
2238def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>;
2239
2240let SchedRW = [WriteMicrocoded] in {
2241// ASCII Adjust After Addition
2242let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2243def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>,
2244            Requires<[Not64BitMode]>;
2245
2246// ASCII Adjust AX Before Division
2247let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2248def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
2249                 "aad\t$src", []>, Requires<[Not64BitMode]>;
2250
2251// ASCII Adjust AX After Multiply
2252let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2253def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
2254                 "aam\t$src", []>, Requires<[Not64BitMode]>;
2255
2256// ASCII Adjust AL After Subtraction - sets
2257let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in
2258def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>,
2259            Requires<[Not64BitMode]>;
2260
2261// Decimal Adjust AL after Addition
2262let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2263def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>,
2264            Requires<[Not64BitMode]>;
2265
2266// Decimal Adjust AL after Subtraction
2267let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in
2268def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>,
2269            Requires<[Not64BitMode]>;
2270} // SchedRW
2271
2272let SchedRW = [WriteSystem] in {
2273// Check Array Index Against Bounds
2274// Note: "bound" does not have reversed operands in at&t syntax.
2275def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2276                   "bound\t$dst, $src", []>, OpSize16,
2277                   Requires<[Not64BitMode]>;
2278def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2279                   "bound\t$dst, $src", []>, OpSize32,
2280                   Requires<[Not64BitMode]>;
2281
2282// Adjust RPL Field of Segment Selector
2283def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
2284                 "arpl\t{$src, $dst|$dst, $src}", []>,
2285                 Requires<[Not64BitMode]>, NotMemoryFoldable;
2286let mayStore = 1 in
2287def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2288                 "arpl\t{$src, $dst|$dst, $src}", []>,
2289                 Requires<[Not64BitMode]>, NotMemoryFoldable;
2290} // SchedRW
2291
2292//===----------------------------------------------------------------------===//
2293// MOVBE Instructions
2294//
2295let Predicates = [HasMOVBE] in {
2296  let SchedRW = [WriteALULd] in {
2297  def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2298                    "movbe{w}\t{$src, $dst|$dst, $src}",
2299                    [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>,
2300                    OpSize16, T8PS;
2301  def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2302                    "movbe{l}\t{$src, $dst|$dst, $src}",
2303                    [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>,
2304                    OpSize32, T8PS;
2305  def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2306                     "movbe{q}\t{$src, $dst|$dst, $src}",
2307                     [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>,
2308                     T8PS;
2309  }
2310  let SchedRW = [WriteStore] in {
2311  def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2312                    "movbe{w}\t{$src, $dst|$dst, $src}",
2313                    [(store (bswap GR16:$src), addr:$dst)]>,
2314                    OpSize16, T8PS;
2315  def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2316                    "movbe{l}\t{$src, $dst|$dst, $src}",
2317                    [(store (bswap GR32:$src), addr:$dst)]>,
2318                    OpSize32, T8PS;
2319  def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2320                     "movbe{q}\t{$src, $dst|$dst, $src}",
2321                     [(store (bswap GR64:$src), addr:$dst)]>,
2322                     T8PS;
2323  }
2324}
2325
2326//===----------------------------------------------------------------------===//
2327// RDRAND Instruction
2328//
2329let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in {
2330  def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
2331                    "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>,
2332                    OpSize16, PS;
2333  def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
2334                    "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>,
2335                    OpSize32, PS;
2336  def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2337                     "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>,
2338                     PS;
2339}
2340
2341//===----------------------------------------------------------------------===//
2342// RDSEED Instruction
2343//
2344let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in {
2345  def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst",
2346                    [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS;
2347  def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst",
2348                    [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS;
2349  def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst",
2350                     [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS;
2351}
2352
2353//===----------------------------------------------------------------------===//
2354// LZCNT Instruction
2355//
2356let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2357  def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2358                    "lzcnt{w}\t{$src, $dst|$dst, $src}",
2359                    [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>,
2360                    XS, OpSize16, Sched<[WriteLZCNT]>;
2361  def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2362                    "lzcnt{w}\t{$src, $dst|$dst, $src}",
2363                    [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2364                     (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>;
2365
2366  def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2367                    "lzcnt{l}\t{$src, $dst|$dst, $src}",
2368                    [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>,
2369                    XS, OpSize32, Sched<[WriteLZCNT]>;
2370  def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2371                    "lzcnt{l}\t{$src, $dst|$dst, $src}",
2372                    [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2373                     (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>;
2374
2375  def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2376                     "lzcnt{q}\t{$src, $dst|$dst, $src}",
2377                     [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2378                     XS, Sched<[WriteLZCNT]>;
2379  def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2380                     "lzcnt{q}\t{$src, $dst|$dst, $src}",
2381                     [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2382                      (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>;
2383}
2384
2385//===----------------------------------------------------------------------===//
2386// BMI Instructions
2387//
2388let Predicates = [HasBMI], Defs = [EFLAGS] in {
2389  def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2390                    "tzcnt{w}\t{$src, $dst|$dst, $src}",
2391                    [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>,
2392                    XS, OpSize16, Sched<[WriteTZCNT]>;
2393  def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2394                    "tzcnt{w}\t{$src, $dst|$dst, $src}",
2395                    [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2396                     (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>;
2397
2398  def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2399                    "tzcnt{l}\t{$src, $dst|$dst, $src}",
2400                    [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>,
2401                    XS, OpSize32, Sched<[WriteTZCNT]>;
2402  def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2403                    "tzcnt{l}\t{$src, $dst|$dst, $src}",
2404                    [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2405                     (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>;
2406
2407  def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2408                     "tzcnt{q}\t{$src, $dst|$dst, $src}",
2409                     [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2410                     XS, Sched<[WriteTZCNT]>;
2411  def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2412                     "tzcnt{q}\t{$src, $dst|$dst, $src}",
2413                     [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2414                      (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>;
2415}
2416
2417multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2418                  RegisterClass RC, X86MemOperand x86memop,
2419                  X86FoldableSchedWrite sched> {
2420let hasSideEffects = 0 in {
2421  def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2422             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
2423             T8PS, VEX_4V, Sched<[sched]>;
2424  let mayLoad = 1 in
2425  def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2426             !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
2427             T8PS, VEX_4V, Sched<[sched.Folded]>;
2428}
2429}
2430
2431let Predicates = [HasBMI], Defs = [EFLAGS] in {
2432  defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>;
2433  defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W;
2434  defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>;
2435  defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W;
2436  defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>;
2437  defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, VEX_W;
2438}
2439
2440//===----------------------------------------------------------------------===//
2441// Pattern fragments to auto generate BMI instructions.
2442//===----------------------------------------------------------------------===//
2443
2444def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
2445                           (X86or_flag node:$lhs, node:$rhs), [{
2446  return hasNoCarryFlagUses(SDValue(N, 1));
2447}]>;
2448
2449def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
2450                            (X86xor_flag node:$lhs, node:$rhs), [{
2451  return hasNoCarryFlagUses(SDValue(N, 1));
2452}]>;
2453
2454def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs),
2455                            (X86and_flag node:$lhs, node:$rhs), [{
2456  return hasNoCarryFlagUses(SDValue(N, 1));
2457}]>;
2458
2459let Predicates = [HasBMI] in {
2460  // FIXME: patterns for the load versions are not implemented
2461  def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2462            (BLSR32rr GR32:$src)>;
2463  def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2464            (BLSR64rr GR64:$src)>;
2465
2466  def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2467            (BLSMSK32rr GR32:$src)>;
2468  def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2469            (BLSMSK64rr GR64:$src)>;
2470
2471  def : Pat<(and GR32:$src, (ineg GR32:$src)),
2472            (BLSI32rr GR32:$src)>;
2473  def : Pat<(and GR64:$src, (ineg GR64:$src)),
2474            (BLSI64rr GR64:$src)>;
2475
2476  // Versions to match flag producing ops.
2477  def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, -1)),
2478            (BLSR32rr GR32:$src)>;
2479  def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, -1)),
2480            (BLSR64rr GR64:$src)>;
2481
2482  def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, -1)),
2483            (BLSMSK32rr GR32:$src)>;
2484  def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, -1)),
2485            (BLSMSK64rr GR64:$src)>;
2486
2487  def : Pat<(and_flag_nocf GR32:$src, (ineg GR32:$src)),
2488            (BLSI32rr GR32:$src)>;
2489  def : Pat<(and_flag_nocf GR64:$src, (ineg GR64:$src)),
2490            (BLSI64rr GR64:$src)>;
2491}
2492
2493multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC,
2494                     X86MemOperand x86memop, SDNode OpNode,
2495                     PatFrag ld_frag, X86FoldableSchedWrite Sched> {
2496  def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2497             !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2498             [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2499             T8PS, VEX, Sched<[Sched]>;
2500  def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2501             !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2502             [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)),
2503              (implicit EFLAGS)]>, T8PS, VEX,
2504             Sched<[Sched.Folded,
2505                    // x86memop:$src1
2506                    ReadDefault, ReadDefault, ReadDefault, ReadDefault,
2507                    ReadDefault,
2508                    // RC:$src2
2509                    Sched.ReadAfterFold]>;
2510}
2511
2512let Predicates = [HasBMI], Defs = [EFLAGS] in {
2513  defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem,
2514                           X86bextr, loadi32, WriteBEXTR>;
2515  defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem,
2516                           X86bextr, loadi64, WriteBEXTR>, VEX_W;
2517}
2518
2519multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2520                    X86MemOperand x86memop, Intrinsic Int,
2521                    PatFrag ld_frag, X86FoldableSchedWrite Sched> {
2522  def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2523             !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2524             [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2525             T8PS, VEX, Sched<[Sched]>;
2526  def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2527             !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2528             [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2529              (implicit EFLAGS)]>, T8PS, VEX,
2530             Sched<[Sched.Folded,
2531                    // x86memop:$src1
2532                    ReadDefault, ReadDefault, ReadDefault, ReadDefault,
2533                    ReadDefault,
2534                    // RC:$src2
2535                    Sched.ReadAfterFold]>;
2536}
2537
2538let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2539  defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2540                         X86bzhi, loadi32, WriteBZHI>;
2541  defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2542                         X86bzhi, loadi64, WriteBZHI>, VEX_W;
2543}
2544
2545def CountTrailingOnes : SDNodeXForm<imm, [{
2546  // Count the trailing ones in the immediate.
2547  return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
2548}]>;
2549
2550def BEXTRMaskXForm : SDNodeXForm<imm, [{
2551  unsigned Length = countTrailingOnes(N->getZExtValue());
2552  return getI32Imm(Length << 8, SDLoc(N));
2553}]>;
2554
2555def AndMask64 : ImmLeaf<i64, [{
2556  return isMask_64(Imm) && !isUInt<32>(Imm);
2557}]>;
2558
2559// Use BEXTR for 64-bit 'and' with large immediate 'mask'.
2560let Predicates = [HasBMI, NoBMI2, NoTBM] in {
2561  def : Pat<(and GR64:$src, AndMask64:$mask),
2562            (BEXTR64rr GR64:$src,
2563              (SUBREG_TO_REG (i64 0),
2564                             (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>;
2565  def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
2566            (BEXTR64rm addr:$src,
2567              (SUBREG_TO_REG (i64 0),
2568                             (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>;
2569}
2570
2571// Use BZHI for 64-bit 'and' with large immediate 'mask'.
2572let Predicates = [HasBMI2, NoTBM] in {
2573  def : Pat<(and GR64:$src, AndMask64:$mask),
2574            (BZHI64rr GR64:$src,
2575              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2576                             (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2577  def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
2578            (BZHI64rm addr:$src,
2579              (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2580                             (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2581}
2582
2583multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2584                         X86MemOperand x86memop, Intrinsic Int,
2585                         PatFrag ld_frag> {
2586  def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2587             !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2588             [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2589             VEX_4V, Sched<[WriteALU]>;
2590  def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2591             !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2592             [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>,
2593             VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
2594}
2595
2596let Predicates = [HasBMI2] in {
2597  defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2598                               int_x86_bmi_pdep_32, loadi32>, T8XD;
2599  defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2600                               int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2601  defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2602                               int_x86_bmi_pext_32, loadi32>, T8XS;
2603  defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2604                               int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2605}
2606
2607//===----------------------------------------------------------------------===//
2608// TBM Instructions
2609//
2610let Predicates = [HasTBM], Defs = [EFLAGS] in {
2611
2612multiclass tbm_ternary_imm<bits<8> opc, RegisterClass RC, string OpcodeStr,
2613                           X86MemOperand x86memop, PatFrag ld_frag,
2614                           SDNode OpNode, Operand immtype,
2615                           SDPatternOperator immoperator,
2616                           X86FoldableSchedWrite Sched> {
2617  def ri : Ii32<opc,  MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2618                !strconcat(OpcodeStr,
2619                           "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2620                [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>,
2621                XOP, XOPA, Sched<[Sched]>;
2622  def mi : Ii32<opc,  MRMSrcMem, (outs RC:$dst),
2623                (ins x86memop:$src1, immtype:$cntl),
2624                !strconcat(OpcodeStr,
2625                           "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2626                [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>,
2627                XOP, XOPA, Sched<[Sched.Folded]>;
2628}
2629
2630defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32,
2631                                X86bextr, i32imm, imm, WriteBEXTR>;
2632let ImmT = Imm32S in
2633defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64,
2634                                X86bextr, i64i32imm,
2635                                i64immSExt32, WriteBEXTR>, VEX_W;
2636
2637multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2638                         RegisterClass RC, string OpcodeStr,
2639                         X86MemOperand x86memop, X86FoldableSchedWrite Sched> {
2640let hasSideEffects = 0 in {
2641  def rr : I<opc,  FormReg, (outs RC:$dst), (ins RC:$src),
2642             !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
2643             XOP_4V, XOP9, Sched<[Sched]>;
2644  let mayLoad = 1 in
2645  def rm : I<opc,  FormMem, (outs RC:$dst), (ins x86memop:$src),
2646             !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
2647             XOP_4V, XOP9, Sched<[Sched.Folded]>;
2648}
2649}
2650
2651multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2652                           X86FoldableSchedWrite Sched,
2653                           Format FormReg, Format FormMem> {
2654  defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}",
2655                               i32mem, Sched>;
2656  defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}",
2657                               i64mem, Sched>, VEX_W;
2658}
2659
2660defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>;
2661defm BLCI    : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>;
2662defm BLCIC   : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>;
2663defm BLCMSK  : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>;
2664defm BLCS    : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>;
2665defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>;
2666defm BLSIC   : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>;
2667defm T1MSKC  : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>;
2668defm TZMSK   : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>;
2669} // HasTBM, EFLAGS
2670
2671// Use BEXTRI for 64-bit 'and' with large immediate 'mask'.
2672let Predicates = [HasTBM] in {
2673  def : Pat<(and GR64:$src, AndMask64:$mask),
2674            (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>;
2675
2676  def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
2677            (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>;
2678}
2679
2680//===----------------------------------------------------------------------===//
2681// Lightweight Profiling Instructions
2682
2683let Predicates = [HasLWP], SchedRW = [WriteSystem] in {
2684
2685def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
2686               [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9;
2687def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst",
2688               [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9;
2689
2690def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src",
2691                 [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W;
2692def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst",
2693                 [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W;
2694
2695multiclass lwpins_intr<RegisterClass RC> {
2696  def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
2697                 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2698                 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>,
2699                 XOP_4V, XOPA;
2700  let mayLoad = 1 in
2701  def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
2702                 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2703                 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), timm:$cntl))]>,
2704                 XOP_4V, XOPA;
2705}
2706
2707let Defs = [EFLAGS] in {
2708  defm LWPINS32 : lwpins_intr<GR32>;
2709  defm LWPINS64 : lwpins_intr<GR64>, VEX_W;
2710} // EFLAGS
2711
2712multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> {
2713  def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
2714                 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2715                 [(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP_4V, XOPA;
2716  let mayLoad = 1 in
2717  def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
2718                 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
2719                 [(Int RC:$src0, (loadi32 addr:$src1), timm:$cntl)]>,
2720                 XOP_4V, XOPA;
2721}
2722
2723defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>;
2724defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W;
2725
2726} // HasLWP, SchedRW
2727
2728//===----------------------------------------------------------------------===//
2729// MONITORX/MWAITX Instructions
2730//
2731let SchedRW = [ WriteSystem ] in {
2732  let Uses = [ EAX, ECX, EDX ] in
2733  def MONITORX32rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>,
2734                      TB, Requires<[ HasMWAITX, Not64BitMode ]>;
2735  let Uses = [ RAX, ECX, EDX ] in
2736  def MONITORX64rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>,
2737                      TB, Requires<[ HasMWAITX, In64BitMode ]>;
2738
2739  let Uses = [ ECX, EAX, EBX ] in {
2740    def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx",
2741                    [(int_x86_mwaitx ECX, EAX, EBX)]>,
2742                    TB, Requires<[ HasMWAITX ]>;
2743  }
2744} // SchedRW
2745
2746def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>,
2747      Requires<[ Not64BitMode ]>;
2748def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>,
2749      Requires<[ In64BitMode ]>;
2750
2751def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORX32rrr)>,
2752      Requires<[ Not64BitMode ]>;
2753def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORX64rrr)>,
2754      Requires<[ In64BitMode ]>;
2755
2756//===----------------------------------------------------------------------===//
2757// WAITPKG Instructions
2758//
2759let SchedRW = [WriteSystem] in {
2760  def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src),
2761                     "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>,
2762                     XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>;
2763  def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src),
2764                     "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>,
2765                     XS, AdSize32, Requires<[HasWAITPKG]>;
2766  def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src),
2767                     "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>,
2768                     XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>;
2769  let Uses = [EAX, EDX], Defs = [EFLAGS] in {
2770    def UMWAIT : I<0xAE, MRM6r,
2771                     (outs), (ins GR32orGR64:$src), "umwait\t$src",
2772                     [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>,
2773                     XD, Requires<[HasWAITPKG]>;
2774    def TPAUSE : I<0xAE, MRM6r,
2775                     (outs), (ins GR32orGR64:$src), "tpause\t$src",
2776                     [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>,
2777                     PD, Requires<[HasWAITPKG]>, NotMemoryFoldable;
2778  }
2779} // SchedRW
2780
2781//===----------------------------------------------------------------------===//
2782// MOVDIRI - Move doubleword/quadword as direct store
2783//
2784let SchedRW = [WriteStore] in {
2785def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2786                  "movdiri\t{$src, $dst|$dst, $src}",
2787                  [(int_x86_directstore32 addr:$dst, GR32:$src)]>,
2788                 T8, Requires<[HasMOVDIRI]>;
2789def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2790                   "movdiri\t{$src, $dst|$dst, $src}",
2791                   [(int_x86_directstore64 addr:$dst, GR64:$src)]>,
2792                  T8, Requires<[In64BitMode, HasMOVDIRI]>;
2793} // SchedRW
2794
2795//===----------------------------------------------------------------------===//
2796// MOVDIR64B - Move 64 bytes as direct store
2797//
2798let SchedRW = [WriteStore] in {
2799def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
2800                    "movdir64b\t{$src, $dst|$dst, $src}", []>,
2801                   T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>;
2802def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
2803                    "movdir64b\t{$src, $dst|$dst, $src}",
2804                    [(int_x86_movdir64b GR32:$dst, addr:$src)]>,
2805                   T8PD, AdSize32, Requires<[HasMOVDIR64B]>;
2806def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
2807                    "movdir64b\t{$src, $dst|$dst, $src}",
2808                    [(int_x86_movdir64b GR64:$dst, addr:$src)]>,
2809                   T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>;
2810} // SchedRW
2811
2812//===----------------------------------------------------------------------===//
2813// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
2814//
2815let SchedRW = [WriteStore], Defs = [EFLAGS] in {
2816  def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
2817                 "enqcmd\t{$src, $dst|$dst, $src}",
2818                 [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
2819                 T8XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
2820  def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
2821                 "enqcmd\t{$src, $dst|$dst, $src}",
2822                 [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
2823                 T8XD, AdSize32, Requires<[HasENQCMD]>;
2824  def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
2825                 "enqcmd\t{$src, $dst|$dst, $src}",
2826                 [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
2827                 T8XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
2828
2829  def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
2830                 "enqcmds\t{$src, $dst|$dst, $src}",
2831                 [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
2832                 T8XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
2833  def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
2834                 "enqcmds\t{$src, $dst|$dst, $src}",
2835                 [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
2836                 T8XS, AdSize32, Requires<[HasENQCMD]>;
2837  def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
2838                 "enqcmds\t{$src, $dst|$dst, $src}",
2839                 [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
2840                 T8XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
2841}
2842
2843//===----------------------------------------------------------------------===//
2844// CLZERO Instruction
2845//
2846let SchedRW = [WriteLoad] in {
2847  let Uses = [EAX] in
2848  def CLZERO32r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>,
2849                  TB, Requires<[HasCLZERO, Not64BitMode]>;
2850  let Uses = [RAX] in
2851  def CLZERO64r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>,
2852                  TB, Requires<[HasCLZERO, In64BitMode]>;
2853} // SchedRW
2854
2855def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
2856def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
2857
2858//===----------------------------------------------------------------------===//
2859// Pattern fragments to auto generate TBM instructions.
2860//===----------------------------------------------------------------------===//
2861
2862let Predicates = [HasTBM] in {
2863  // FIXME: patterns for the load versions are not implemented
2864  def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2865            (BLCFILL32rr GR32:$src)>;
2866  def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2867            (BLCFILL64rr GR64:$src)>;
2868
2869  def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2870            (BLCI32rr GR32:$src)>;
2871  def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2872            (BLCI64rr GR64:$src)>;
2873
2874  // Extra patterns because opt can optimize the above patterns to this.
2875  def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2876            (BLCI32rr GR32:$src)>;
2877  def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2878            (BLCI64rr GR64:$src)>;
2879
2880  def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2881            (BLCIC32rr GR32:$src)>;
2882  def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2883            (BLCIC64rr GR64:$src)>;
2884
2885  def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2886            (BLCMSK32rr GR32:$src)>;
2887  def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2888            (BLCMSK64rr GR64:$src)>;
2889
2890  def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2891            (BLCS32rr GR32:$src)>;
2892  def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2893            (BLCS64rr GR64:$src)>;
2894
2895  def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2896            (BLSFILL32rr GR32:$src)>;
2897  def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2898            (BLSFILL64rr GR64:$src)>;
2899
2900  def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2901            (BLSIC32rr GR32:$src)>;
2902  def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2903            (BLSIC64rr GR64:$src)>;
2904
2905  def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2906            (T1MSKC32rr GR32:$src)>;
2907  def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2908            (T1MSKC64rr GR64:$src)>;
2909
2910  def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2911            (TZMSK32rr GR32:$src)>;
2912  def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2913            (TZMSK64rr GR64:$src)>;
2914
2915  // Patterns to match flag producing ops.
2916  def : Pat<(or_flag_nocf GR32:$src, (not (add GR32:$src, 1))),
2917            (BLCI32rr GR32:$src)>;
2918  def : Pat<(or_flag_nocf GR64:$src, (not (add GR64:$src, 1))),
2919            (BLCI64rr GR64:$src)>;
2920
2921  // Extra patterns because opt can optimize the above patterns to this.
2922  def : Pat<(or_flag_nocf GR32:$src, (sub -2, GR32:$src)),
2923            (BLCI32rr GR32:$src)>;
2924  def : Pat<(or_flag_nocf GR64:$src, (sub -2, GR64:$src)),
2925            (BLCI64rr GR64:$src)>;
2926
2927  def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, 1)),
2928            (BLCIC32rr GR32:$src)>;
2929  def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, 1)),
2930            (BLCIC64rr GR64:$src)>;
2931
2932  def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, 1)),
2933            (BLCMSK32rr GR32:$src)>;
2934  def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, 1)),
2935            (BLCMSK64rr GR64:$src)>;
2936
2937  def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, 1)),
2938            (BLCS32rr GR32:$src)>;
2939  def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, 1)),
2940            (BLCS64rr GR64:$src)>;
2941
2942  def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, -1)),
2943            (BLSFILL32rr GR32:$src)>;
2944  def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, -1)),
2945            (BLSFILL64rr GR64:$src)>;
2946
2947  def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, -1)),
2948            (BLSIC32rr GR32:$src)>;
2949  def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, -1)),
2950            (BLSIC64rr GR64:$src)>;
2951
2952  def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, 1)),
2953            (T1MSKC32rr GR32:$src)>;
2954  def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, 1)),
2955            (T1MSKC64rr GR64:$src)>;
2956
2957  def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, -1)),
2958            (TZMSK32rr GR32:$src)>;
2959  def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, -1)),
2960            (TZMSK64rr GR64:$src)>;
2961} // HasTBM
2962
2963//===----------------------------------------------------------------------===//
2964// Memory Instructions
2965//
2966
2967let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
2968def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2969                   "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD;
2970
2971let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
2972def CLWB       : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
2973                   [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable;
2974
2975let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in
2976def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src",
2977                   [(int_x86_cldemote addr:$src)]>, TB;
2978
2979//===----------------------------------------------------------------------===//
2980// Subsystems.
2981//===----------------------------------------------------------------------===//
2982
2983include "X86InstrArithmetic.td"
2984include "X86InstrCMovSetCC.td"
2985include "X86InstrExtension.td"
2986include "X86InstrControl.td"
2987include "X86InstrShiftRotate.td"
2988
2989// X87 Floating Point Stack.
2990include "X86InstrFPStack.td"
2991
2992// SIMD support (SSE, MMX and AVX)
2993include "X86InstrFragmentsSIMD.td"
2994
2995// FMA - Fused Multiply-Add support (requires FMA)
2996include "X86InstrFMA.td"
2997
2998// XOP
2999include "X86InstrXOP.td"
3000
3001// SSE, MMX and 3DNow! vector support.
3002include "X86InstrSSE.td"
3003include "X86InstrAVX512.td"
3004include "X86InstrMMX.td"
3005include "X86Instr3DNow.td"
3006
3007// MPX instructions
3008include "X86InstrMPX.td"
3009
3010include "X86InstrVMX.td"
3011include "X86InstrSVM.td"
3012
3013include "X86InstrTSX.td"
3014include "X86InstrSGX.td"
3015
3016// System instructions.
3017include "X86InstrSystem.td"
3018
3019// Compiler Pseudo Instructions and Pat Patterns
3020include "X86InstrCompiler.td"
3021include "X86InstrVecCompiler.td"
3022
3023//===----------------------------------------------------------------------===//
3024// Assembler Mnemonic Aliases
3025//===----------------------------------------------------------------------===//
3026
3027def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
3028def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
3029def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
3030
3031def : MnemonicAlias<"cbw",  "cbtw", "att">;
3032def : MnemonicAlias<"cwde", "cwtl", "att">;
3033def : MnemonicAlias<"cwd",  "cwtd", "att">;
3034def : MnemonicAlias<"cdq",  "cltd", "att">;
3035def : MnemonicAlias<"cdqe", "cltq", "att">;
3036def : MnemonicAlias<"cqo",  "cqto", "att">;
3037
3038// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
3039def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
3040def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
3041
3042def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
3043def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
3044
3045def : MnemonicAlias<"loopz",  "loope">;
3046def : MnemonicAlias<"loopnz", "loopne">;
3047
3048def : MnemonicAlias<"pop",   "popw",  "att">, Requires<[In16BitMode]>;
3049def : MnemonicAlias<"pop",   "popl",  "att">, Requires<[In32BitMode]>;
3050def : MnemonicAlias<"pop",   "popq",  "att">, Requires<[In64BitMode]>;
3051def : MnemonicAlias<"popf",  "popfw", "att">, Requires<[In16BitMode]>;
3052def : MnemonicAlias<"popf",  "popfl", "att">, Requires<[In32BitMode]>;
3053def : MnemonicAlias<"popf",  "popfq", "att">, Requires<[In64BitMode]>;
3054def : MnemonicAlias<"popf",  "popfq", "intel">, Requires<[In64BitMode]>;
3055def : MnemonicAlias<"popfd", "popfl", "att">;
3056def : MnemonicAlias<"popfw", "popf",  "intel">, Requires<[In32BitMode]>;
3057def : MnemonicAlias<"popfw", "popf",  "intel">, Requires<[In64BitMode]>;
3058
3059// FIXME: This is wrong for "push reg".  "push %bx" should turn into pushw in
3060// all modes.  However: "push (addr)" and "push $42" should default to
3061// pushl/pushq depending on the current mode.  Similar for "pop %bx"
3062def : MnemonicAlias<"push",   "pushw",  "att">, Requires<[In16BitMode]>;
3063def : MnemonicAlias<"push",   "pushl",  "att">, Requires<[In32BitMode]>;
3064def : MnemonicAlias<"push",   "pushq",  "att">, Requires<[In64BitMode]>;
3065def : MnemonicAlias<"pushf",  "pushfw", "att">, Requires<[In16BitMode]>;
3066def : MnemonicAlias<"pushf",  "pushfl", "att">, Requires<[In32BitMode]>;
3067def : MnemonicAlias<"pushf",  "pushfq", "att">, Requires<[In64BitMode]>;
3068def : MnemonicAlias<"pushf",  "pushfq", "intel">, Requires<[In64BitMode]>;
3069def : MnemonicAlias<"pushfd", "pushfl", "att">;
3070def : MnemonicAlias<"pushfw", "pushf",  "intel">, Requires<[In32BitMode]>;
3071def : MnemonicAlias<"pushfw", "pushf",  "intel">, Requires<[In64BitMode]>;
3072
3073def : MnemonicAlias<"popad",  "popal",  "intel">, Requires<[Not64BitMode]>;
3074def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
3075def : MnemonicAlias<"popa",   "popaw",  "intel">, Requires<[In16BitMode]>;
3076def : MnemonicAlias<"pusha",  "pushaw", "intel">, Requires<[In16BitMode]>;
3077def : MnemonicAlias<"popa",   "popal",  "intel">, Requires<[In32BitMode]>;
3078def : MnemonicAlias<"pusha",  "pushal", "intel">, Requires<[In32BitMode]>;
3079
3080def : MnemonicAlias<"popa",   "popaw",  "att">, Requires<[In16BitMode]>;
3081def : MnemonicAlias<"pusha",  "pushaw", "att">, Requires<[In16BitMode]>;
3082def : MnemonicAlias<"popa",   "popal",  "att">, Requires<[In32BitMode]>;
3083def : MnemonicAlias<"pusha",  "pushal", "att">, Requires<[In32BitMode]>;
3084
3085def : MnemonicAlias<"repe",  "rep">;
3086def : MnemonicAlias<"repz",  "rep">;
3087def : MnemonicAlias<"repnz", "repne">;
3088
3089def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
3090def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
3091def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
3092
3093// Apply 'ret' behavior to 'retn'
3094def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>;
3095def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>;
3096def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>;
3097def : MnemonicAlias<"retn", "ret", "intel">;
3098
3099def : MnemonicAlias<"sal", "shl", "intel">;
3100def : MnemonicAlias<"salb", "shlb", "att">;
3101def : MnemonicAlias<"salw", "shlw", "att">;
3102def : MnemonicAlias<"sall", "shll", "att">;
3103def : MnemonicAlias<"salq", "shlq", "att">;
3104
3105def : MnemonicAlias<"smovb", "movsb", "att">;
3106def : MnemonicAlias<"smovw", "movsw", "att">;
3107def : MnemonicAlias<"smovl", "movsl", "att">;
3108def : MnemonicAlias<"smovq", "movsq", "att">;
3109
3110def : MnemonicAlias<"ud2a",  "ud2",  "att">;
3111def : MnemonicAlias<"verrw", "verr", "att">;
3112
3113// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release'
3114def : MnemonicAlias<"acquire", "xacquire", "intel">;
3115def : MnemonicAlias<"release", "xrelease", "intel">;
3116
3117// System instruction aliases.
3118def : MnemonicAlias<"iret",    "iretw",    "att">, Requires<[In16BitMode]>;
3119def : MnemonicAlias<"iret",    "iretl",    "att">, Requires<[Not16BitMode]>;
3120def : MnemonicAlias<"sysret",  "sysretl",  "att">;
3121def : MnemonicAlias<"sysexit", "sysexitl", "att">;
3122
3123def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
3124def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
3125def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
3126def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
3127def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
3128def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
3129def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
3130def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
3131def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
3132def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
3133def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
3134def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
3135def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>;
3136def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>;
3137def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>;
3138def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>;
3139def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>;
3140def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>;
3141def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>;
3142def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>;
3143
3144
3145// Floating point stack aliases.
3146def : MnemonicAlias<"fcmovz",   "fcmove",   "att">;
3147def : MnemonicAlias<"fcmova",   "fcmovnbe", "att">;
3148def : MnemonicAlias<"fcmovnae", "fcmovb",   "att">;
3149def : MnemonicAlias<"fcmovna",  "fcmovbe",  "att">;
3150def : MnemonicAlias<"fcmovae",  "fcmovnb",  "att">;
3151def : MnemonicAlias<"fcomip",   "fcompi">;
3152def : MnemonicAlias<"fildq",    "fildll",   "att">;
3153def : MnemonicAlias<"fistpq",   "fistpll",  "att">;
3154def : MnemonicAlias<"fisttpq",  "fisttpll", "att">;
3155def : MnemonicAlias<"fldcww",   "fldcw",    "att">;
3156def : MnemonicAlias<"fnstcww",  "fnstcw",   "att">;
3157def : MnemonicAlias<"fnstsww",  "fnstsw",   "att">;
3158def : MnemonicAlias<"fucomip",  "fucompi">;
3159def : MnemonicAlias<"fwait",    "wait">;
3160
3161def : MnemonicAlias<"fxsaveq",   "fxsave64",   "att">;
3162def : MnemonicAlias<"fxrstorq",  "fxrstor64",  "att">;
3163def : MnemonicAlias<"xsaveq",    "xsave64",    "att">;
3164def : MnemonicAlias<"xrstorq",   "xrstor64",   "att">;
3165def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">;
3166def : MnemonicAlias<"xrstorsq",  "xrstors64",  "att">;
3167def : MnemonicAlias<"xsavecq",   "xsavec64",   "att">;
3168def : MnemonicAlias<"xsavesq",   "xsaves64",   "att">;
3169
3170class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
3171                    string VariantName>
3172  : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
3173                  !strconcat(Prefix, NewCond, Suffix), VariantName>;
3174
3175/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
3176/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
3177/// example "setz" -> "sete".
3178multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
3179                                        string V = ""> {
3180  def C   : CondCodeAlias<Prefix, Suffix, "c",   "b",  V>; // setc   -> setb
3181  def Z   : CondCodeAlias<Prefix, Suffix, "z" ,  "e",  V>; // setz   -> sete
3182  def NA  : CondCodeAlias<Prefix, Suffix, "na",  "be", V>; // setna  -> setbe
3183  def NB  : CondCodeAlias<Prefix, Suffix, "nb",  "ae", V>; // setnb  -> setae
3184  def NC  : CondCodeAlias<Prefix, Suffix, "nc",  "ae", V>; // setnc  -> setae
3185  def NG  : CondCodeAlias<Prefix, Suffix, "ng",  "le", V>; // setng  -> setle
3186  def NL  : CondCodeAlias<Prefix, Suffix, "nl",  "ge", V>; // setnl  -> setge
3187  def NZ  : CondCodeAlias<Prefix, Suffix, "nz",  "ne", V>; // setnz  -> setne
3188  def PE  : CondCodeAlias<Prefix, Suffix, "pe",  "p",  V>; // setpe  -> setp
3189  def PO  : CondCodeAlias<Prefix, Suffix, "po",  "np", V>; // setpo  -> setnp
3190
3191  def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b",  V>; // setnae -> setb
3192  def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a",  V>; // setnbe -> seta
3193  def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l",  V>; // setnge -> setl
3194  def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g",  V>; // setnle -> setg
3195}
3196
3197// Aliases for set<CC>
3198defm : IntegerCondCodeMnemonicAlias<"set", "">;
3199// Aliases for j<CC>
3200defm : IntegerCondCodeMnemonicAlias<"j", "">;
3201// Aliases for cmov<CC>{w,l,q}
3202defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
3203defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
3204defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
3205// No size suffix for intel-style asm.
3206defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
3207
3208
3209//===----------------------------------------------------------------------===//
3210// Assembler Instruction Aliases
3211//===----------------------------------------------------------------------===//
3212
3213// aad/aam default to base 10 if no operand is specified.
3214def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>;
3215def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>;
3216
3217// Disambiguate the mem/imm form of bt-without-a-suffix as btl.
3218// Likewise for btc/btr/bts.
3219def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}",
3220                (BT32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;
3221def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}",
3222                (BTC32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;
3223def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}",
3224                (BTR32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;
3225def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}",
3226                (BTS32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">;
3227
3228// clr aliases.
3229def : InstAlias<"clr{b}\t$reg", (XOR8rr  GR8 :$reg, GR8 :$reg), 0>;
3230def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
3231def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
3232def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
3233
3234// lods aliases. Accept the destination being omitted because it's implicit
3235// in the mnemonic, or the mnemonic suffix being omitted because it's implicit
3236// in the destination.
3237def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src),  0>;
3238def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>;
3239def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>;
3240def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
3241def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src),  0>;
3242def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
3243def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
3244def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
3245def : InstAlias<"lods\t$src", (LODSB srcidx8:$src),  0, "intel">;
3246def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">;
3247def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">;
3248def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>;
3249
3250
3251// stos aliases. Accept the source being omitted because it's implicit in
3252// the mnemonic, or the mnemonic suffix being omitted because it's implicit
3253// in the source.
3254def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst),  0>;
3255def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>;
3256def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>;
3257def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
3258def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst),  0>;
3259def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
3260def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
3261def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
3262def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst),  0, "intel">;
3263def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">;
3264def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">;
3265def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>;
3266
3267
3268// scas aliases. Accept the destination being omitted because it's implicit
3269// in the mnemonic, or the mnemonic suffix being omitted because it's implicit
3270// in the destination.
3271def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst),  0>;
3272def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>;
3273def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>;
3274def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
3275def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst),  0>;
3276def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
3277def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
3278def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
3279def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst),  0, "intel">;
3280def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">;
3281def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">;
3282def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>;
3283
3284// cmps aliases. Mnemonic suffix being omitted because it's implicit
3285// in the destination.
3286def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src),   0, "intel">;
3287def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">;
3288def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">;
3289def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>;
3290
3291// movs aliases. Mnemonic suffix being omitted because it's implicit
3292// in the destination.
3293def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src),   0, "intel">;
3294def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">;
3295def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">;
3296def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>;
3297
3298// div and idiv aliases for explicit A register.
3299def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r  GR8 :$src)>;
3300def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
3301def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
3302def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
3303def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m  i8mem :$src)>;
3304def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
3305def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
3306def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
3307def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r  GR8 :$src)>;
3308def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
3309def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
3310def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
3311def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m  i8mem :$src)>;
3312def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
3313def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
3314def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
3315
3316
3317
3318// Various unary fpstack operations default to operating on ST1.
3319// For example, "fxch" -> "fxch %st(1)"
3320def : InstAlias<"faddp",        (ADD_FPrST0  ST1), 0>;
3321def:  InstAlias<"fadd",         (ADD_FPrST0  ST1), 0>;
3322def : InstAlias<"fsub{|r}p",    (SUBR_FPrST0 ST1), 0>;
3323def : InstAlias<"fsub{r|}p",    (SUB_FPrST0  ST1), 0>;
3324def : InstAlias<"fmul",         (MUL_FPrST0  ST1), 0>;
3325def : InstAlias<"fmulp",        (MUL_FPrST0  ST1), 0>;
3326def : InstAlias<"fdiv{|r}p",    (DIVR_FPrST0 ST1), 0>;
3327def : InstAlias<"fdiv{r|}p",    (DIV_FPrST0  ST1), 0>;
3328def : InstAlias<"fxch",         (XCH_F       ST1), 0>;
3329def : InstAlias<"fcom",         (COM_FST0r   ST1), 0>;
3330def : InstAlias<"fcomp",        (COMP_FST0r  ST1), 0>;
3331def : InstAlias<"fcomi",        (COM_FIr     ST1), 0>;
3332def : InstAlias<"fcompi",       (COM_FIPr    ST1), 0>;
3333def : InstAlias<"fucom",        (UCOM_Fr     ST1), 0>;
3334def : InstAlias<"fucomp",       (UCOM_FPr    ST1), 0>;
3335def : InstAlias<"fucomi",       (UCOM_FIr    ST1), 0>;
3336def : InstAlias<"fucompi",      (UCOM_FIPr   ST1), 0>;
3337
3338// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
3339// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)".  We also disambiguate
3340// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
3341// gas.
3342multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
3343 def : InstAlias<!strconcat(Mnemonic, "\t$op"),
3344                 (Inst RSTi:$op), EmitAlias>;
3345 def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"),
3346                 (Inst ST0), EmitAlias>;
3347}
3348
3349defm : FpUnaryAlias<"fadd",   ADD_FST0r, 0>;
3350defm : FpUnaryAlias<"faddp",  ADD_FPrST0, 0>;
3351defm : FpUnaryAlias<"fsub",   SUB_FST0r, 0>;
3352defm : FpUnaryAlias<"fsub{|r}p",  SUBR_FPrST0, 0>;
3353defm : FpUnaryAlias<"fsubr",  SUBR_FST0r, 0>;
3354defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>;
3355defm : FpUnaryAlias<"fmul",   MUL_FST0r, 0>;
3356defm : FpUnaryAlias<"fmulp",  MUL_FPrST0, 0>;
3357defm : FpUnaryAlias<"fdiv",   DIV_FST0r, 0>;
3358defm : FpUnaryAlias<"fdiv{|r}p",  DIVR_FPrST0, 0>;
3359defm : FpUnaryAlias<"fdivr",  DIVR_FST0r, 0>;
3360defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>;
3361defm : FpUnaryAlias<"fcomi",   COM_FIr, 0>;
3362defm : FpUnaryAlias<"fucomi",  UCOM_FIr, 0>;
3363defm : FpUnaryAlias<"fcompi",   COM_FIPr, 0>;
3364defm : FpUnaryAlias<"fucompi",  UCOM_FIPr, 0>;
3365
3366
3367// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they
3368// commute.  We also allow fdiv[r]p/fsubrp even though they don't commute,
3369// solely because gas supports it.
3370def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>;
3371def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>;
3372def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>;
3373def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>;
3374def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>;
3375def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>;
3376
3377def : InstAlias<"fnstsw"     , (FNSTSW16r), 0>;
3378
3379// lcall and ljmp aliases.  This seems to be an odd mapping in 64-bit mode, but
3380// this is compatible with what GAS does.
3381def : InstAlias<"lcall\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>;
3382def : InstAlias<"ljmp\t$seg, $off",  (FARJMP32i  i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>;
3383def : InstAlias<"lcall\t{*}$dst",    (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>;
3384def : InstAlias<"ljmp\t{*}$dst",     (FARJMP32m  opaquemem:$dst), 0>, Requires<[Not16BitMode]>;
3385def : InstAlias<"lcall\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
3386def : InstAlias<"ljmp\t$seg, $off",  (FARJMP16i  i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
3387def : InstAlias<"lcall\t{*}$dst",    (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>;
3388def : InstAlias<"ljmp\t{*}$dst",     (FARJMP16m  opaquemem:$dst), 0>, Requires<[In16BitMode]>;
3389
3390def : InstAlias<"jmp\t{*}$dst",      (JMP64m  i64mem:$dst), 0, "att">, Requires<[In64BitMode]>;
3391def : InstAlias<"jmp\t{*}$dst",      (JMP32m  i32mem:$dst), 0, "att">, Requires<[In32BitMode]>;
3392def : InstAlias<"jmp\t{*}$dst",      (JMP16m  i16mem:$dst), 0, "att">, Requires<[In16BitMode]>;
3393
3394
3395// "imul <imm>, B" is an alias for "imul <imm>, B, B".
3396def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri  GR16:$r, GR16:$r, i16imm:$imm), 0>;
3397def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
3398def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri  GR32:$r, GR32:$r, i32imm:$imm), 0>;
3399def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
3400def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
3401def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
3402
3403// ins aliases. Accept the mnemonic suffix being omitted because it's implicit
3404// in the destination.
3405def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst),  0, "intel">;
3406def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">;
3407def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">;
3408
3409// outs aliases. Accept the mnemonic suffix being omitted because it's implicit
3410// in the source.
3411def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src),  0, "intel">;
3412def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">;
3413def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">;
3414
3415// inb %dx -> inb %al, %dx
3416def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
3417def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
3418def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
3419def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>;
3420def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>;
3421def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>;
3422
3423
3424// jmp and call aliases for lcall and ljmp.  jmp $42,$5 -> ljmp
3425def : InstAlias<"call\t$seg, $off",  (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
3426def : InstAlias<"jmp\t$seg, $off",   (FARJMP16i  i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
3427def : InstAlias<"call\t$seg, $off",  (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>;
3428def : InstAlias<"jmp\t$seg, $off",   (FARJMP32i  i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>;
3429def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;
3430def : InstAlias<"jmpw\t$seg, $off",  (FARJMP16i  i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;
3431def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;
3432def : InstAlias<"jmpl\t$seg, $off",  (FARJMP32i  i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>;
3433
3434// Match 'movq <largeimm>, <reg>' as an alias for movabsq.
3435def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
3436
3437// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas,
3438// which supports this due to an old AMD documentation bug when 64-bit mode was
3439// created.
3440def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
3441                (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
3442def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
3443                (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
3444
3445// movsx aliases
3446def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">;
3447def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">;
3448def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">;
3449def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">;
3450def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">;
3451def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">;
3452def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">;
3453
3454// movzx aliases
3455def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">;
3456def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">;
3457def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">;
3458def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">;
3459def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">;
3460def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">;
3461// Note: No GR32->GR64 movzx form.
3462
3463// outb %dx -> outb %al, %dx
3464def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
3465def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
3466def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
3467def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>;
3468def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>;
3469def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>;
3470
3471// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
3472// effect (both store to a 16-bit mem).  Force to sldtw to avoid ambiguity
3473// errors, since its encoding is the most compact.
3474def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
3475
3476// shld/shrd op,op -> shld op, op, CL
3477def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
3478def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
3479def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
3480def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
3481def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
3482def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
3483
3484def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
3485def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
3486def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
3487def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
3488def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
3489def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
3490
3491/*  FIXME: This is disabled because the asm matcher is currently incapable of
3492 *  matching a fixed immediate like $1.
3493// "shl X, $1" is an alias for "shl X".
3494multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
3495 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
3496                 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
3497 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
3498                 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
3499 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
3500                 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
3501 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
3502                 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
3503 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
3504                 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
3505 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
3506                 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
3507 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
3508                 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
3509 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
3510                 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
3511}
3512
3513defm : ShiftRotateByOneAlias<"rcl", "RCL">;
3514defm : ShiftRotateByOneAlias<"rcr", "RCR">;
3515defm : ShiftRotateByOneAlias<"rol", "ROL">;
3516defm : ShiftRotateByOneAlias<"ror", "ROR">;
3517FIXME */
3518
3519// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
3520def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}",
3521                (TEST8mr  i8mem :$mem, GR8 :$val), 0>;
3522def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}",
3523                (TEST16mr i16mem:$mem, GR16:$val), 0>;
3524def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}",
3525                (TEST32mr i32mem:$mem, GR32:$val), 0>;
3526def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}",
3527                (TEST64mr i64mem:$mem, GR64:$val), 0>;
3528
3529// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
3530def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
3531                (XCHG8rm  GR8 :$val, i8mem :$mem), 0>;
3532def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
3533                (XCHG16rm GR16:$val, i16mem:$mem), 0>;
3534def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
3535                (XCHG32rm GR32:$val, i32mem:$mem), 0>;
3536def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
3537                (XCHG64rm GR64:$val, i64mem:$mem), 0>;
3538
3539// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
3540def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
3541def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>;
3542def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;
3543
3544// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we
3545// would get by default because it's defined as NOP. But xchg %eax, %eax implies
3546// implicit zeroing of the upper 32 bits. So alias to the longer encoding.
3547def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}",
3548                (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>;
3549
3550// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this
3551// we emit an unneeded REX.w prefix.
3552def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>;
3553
3554// These aliases exist to get the parser to prioritize matching 8-bit
3555// immediate encodings over matching the implicit ax/eax/rax encodings. By
3556// explicitly mentioning the A register here, these entries will be ordered
3557// first due to the more explicit immediate type.
3558def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>;
3559def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>;
3560def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>;
3561def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>;
3562def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}",  (OR16ri8 AX,  i16i8imm:$imm), 0>;
3563def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>;
3564def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>;
3565def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>;
3566
3567def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>;
3568def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>;
3569def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>;
3570def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>;
3571def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}",  (OR32ri8 EAX,  i32i8imm:$imm), 0>;
3572def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>;
3573def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>;
3574def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>;
3575
3576def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>;
3577def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>;
3578def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>;
3579def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>;
3580def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}",  (OR64ri8 RAX,  i64i8imm:$imm), 0>;
3581def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>;
3582def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>;
3583def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>;
3584