X86InstrInfo.cpp revision 332833
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86MachineFunctionInfo.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/CodeGen/LivePhysRegs.h" 22#include "llvm/CodeGen/LiveVariables.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineDominators.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineModuleInfo.h" 28#include "llvm/CodeGen/MachineRegisterInfo.h" 29#include "llvm/CodeGen/StackMaps.h" 30#include "llvm/IR/DerivedTypes.h" 31#include "llvm/IR/Function.h" 32#include "llvm/IR/LLVMContext.h" 33#include "llvm/MC/MCAsmInfo.h" 34#include "llvm/MC/MCExpr.h" 35#include "llvm/MC/MCInst.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40#include "llvm/Target/TargetOptions.h" 41 42using namespace llvm; 43 44#define DEBUG_TYPE "x86-instr-info" 45 46#define GET_INSTRINFO_CTOR_DTOR 47#include "X86GenInstrInfo.inc" 48 49static cl::opt<bool> 50 NoFusing("disable-spill-fusing", 51 cl::desc("Disable fusing of spill code into instructions"), 52 cl::Hidden); 53static cl::opt<bool> 54PrintFailedFusing("print-failed-fuse-candidates", 55 cl::desc("Print instructions that the allocator wants to" 56 " fuse, but the X86 backend currently can't"), 57 cl::Hidden); 58static cl::opt<bool> 59ReMatPICStubLoad("remat-pic-stub-load", 60 cl::desc("Re-materialize load from stub in PIC mode"), 61 cl::init(false), cl::Hidden); 62static cl::opt<unsigned> 63PartialRegUpdateClearance("partial-reg-update-clearance", 64 cl::desc("Clearance between two register writes " 65 "for inserting XOR to avoid partial " 66 "register update"), 67 cl::init(64), cl::Hidden); 68static cl::opt<unsigned> 69UndefRegClearance("undef-reg-clearance", 70 cl::desc("How many idle instructions we would like before " 71 "certain undef register reads"), 72 cl::init(128), cl::Hidden); 73 74enum { 75 // Select which memory operand is being unfolded. 76 // (stored in bits 0 - 3) 77 TB_INDEX_0 = 0, 78 TB_INDEX_1 = 1, 79 TB_INDEX_2 = 2, 80 TB_INDEX_3 = 3, 81 TB_INDEX_4 = 4, 82 TB_INDEX_MASK = 0xf, 83 84 // Do not insert the reverse map (MemOp -> RegOp) into the table. 85 // This may be needed because there is a many -> one mapping. 86 TB_NO_REVERSE = 1 << 4, 87 88 // Do not insert the forward map (RegOp -> MemOp) into the table. 89 // This is needed for Native Client, which prohibits branch 90 // instructions from using a memory operand. 91 TB_NO_FORWARD = 1 << 5, 92 93 TB_FOLDED_LOAD = 1 << 6, 94 TB_FOLDED_STORE = 1 << 7, 95 96 // Minimum alignment required for load/store. 97 // Used for RegOp->MemOp conversion. 98 // (stored in bits 8 - 15) 99 TB_ALIGN_SHIFT = 8, 100 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 101 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 102 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 103 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, 104 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 105}; 106 107struct X86MemoryFoldTableEntry { 108 uint16_t RegOp; 109 uint16_t MemOp; 110 uint16_t Flags; 111}; 112 113// Pin the vtable to this file. 114void X86InstrInfo::anchor() {} 115 116X86InstrInfo::X86InstrInfo(X86Subtarget &STI) 117 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 118 : X86::ADJCALLSTACKDOWN32), 119 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 120 : X86::ADJCALLSTACKUP32), 121 X86::CATCHRET, 122 (STI.is64Bit() ? X86::RETQ : X86::RETL)), 123 Subtarget(STI), RI(STI.getTargetTriple()) { 124 125 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = { 126 { X86::ADC16ri, X86::ADC16mi, 0 }, 127 { X86::ADC16ri8, X86::ADC16mi8, 0 }, 128 { X86::ADC16rr, X86::ADC16mr, 0 }, 129 { X86::ADC32ri, X86::ADC32mi, 0 }, 130 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 131 { X86::ADC32rr, X86::ADC32mr, 0 }, 132 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 133 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 134 { X86::ADC64rr, X86::ADC64mr, 0 }, 135 { X86::ADC8ri, X86::ADC8mi, 0 }, 136 { X86::ADC8ri8, X86::ADC8mi8, 0 }, 137 { X86::ADC8rr, X86::ADC8mr, 0 }, 138 { X86::ADD16ri, X86::ADD16mi, 0 }, 139 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 140 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 141 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 142 { X86::ADD16rr, X86::ADD16mr, 0 }, 143 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 144 { X86::ADD32ri, X86::ADD32mi, 0 }, 145 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 146 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 147 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 148 { X86::ADD32rr, X86::ADD32mr, 0 }, 149 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 150 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 151 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 152 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 153 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 154 { X86::ADD64rr, X86::ADD64mr, 0 }, 155 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 156 { X86::ADD8ri, X86::ADD8mi, 0 }, 157 { X86::ADD8ri8, X86::ADD8mi8, 0 }, 158 { X86::ADD8rr, X86::ADD8mr, 0 }, 159 { X86::AND16ri, X86::AND16mi, 0 }, 160 { X86::AND16ri8, X86::AND16mi8, 0 }, 161 { X86::AND16rr, X86::AND16mr, 0 }, 162 { X86::AND32ri, X86::AND32mi, 0 }, 163 { X86::AND32ri8, X86::AND32mi8, 0 }, 164 { X86::AND32rr, X86::AND32mr, 0 }, 165 { X86::AND64ri32, X86::AND64mi32, 0 }, 166 { X86::AND64ri8, X86::AND64mi8, 0 }, 167 { X86::AND64rr, X86::AND64mr, 0 }, 168 { X86::AND8ri, X86::AND8mi, 0 }, 169 { X86::AND8ri8, X86::AND8mi8, 0 }, 170 { X86::AND8rr, X86::AND8mr, 0 }, 171 { X86::BTC16ri8, X86::BTC16mi8, 0 }, 172 { X86::BTC32ri8, X86::BTC32mi8, 0 }, 173 { X86::BTC64ri8, X86::BTC64mi8, 0 }, 174 { X86::BTR16ri8, X86::BTR16mi8, 0 }, 175 { X86::BTR32ri8, X86::BTR32mi8, 0 }, 176 { X86::BTR64ri8, X86::BTR64mi8, 0 }, 177 { X86::BTS16ri8, X86::BTS16mi8, 0 }, 178 { X86::BTS32ri8, X86::BTS32mi8, 0 }, 179 { X86::BTS64ri8, X86::BTS64mi8, 0 }, 180 { X86::DEC16r, X86::DEC16m, 0 }, 181 { X86::DEC32r, X86::DEC32m, 0 }, 182 { X86::DEC64r, X86::DEC64m, 0 }, 183 { X86::DEC8r, X86::DEC8m, 0 }, 184 { X86::INC16r, X86::INC16m, 0 }, 185 { X86::INC32r, X86::INC32m, 0 }, 186 { X86::INC64r, X86::INC64m, 0 }, 187 { X86::INC8r, X86::INC8m, 0 }, 188 { X86::NEG16r, X86::NEG16m, 0 }, 189 { X86::NEG32r, X86::NEG32m, 0 }, 190 { X86::NEG64r, X86::NEG64m, 0 }, 191 { X86::NEG8r, X86::NEG8m, 0 }, 192 { X86::NOT16r, X86::NOT16m, 0 }, 193 { X86::NOT32r, X86::NOT32m, 0 }, 194 { X86::NOT64r, X86::NOT64m, 0 }, 195 { X86::NOT8r, X86::NOT8m, 0 }, 196 { X86::OR16ri, X86::OR16mi, 0 }, 197 { X86::OR16ri8, X86::OR16mi8, 0 }, 198 { X86::OR16rr, X86::OR16mr, 0 }, 199 { X86::OR32ri, X86::OR32mi, 0 }, 200 { X86::OR32ri8, X86::OR32mi8, 0 }, 201 { X86::OR32rr, X86::OR32mr, 0 }, 202 { X86::OR64ri32, X86::OR64mi32, 0 }, 203 { X86::OR64ri8, X86::OR64mi8, 0 }, 204 { X86::OR64rr, X86::OR64mr, 0 }, 205 { X86::OR8ri, X86::OR8mi, 0 }, 206 { X86::OR8ri8, X86::OR8mi8, 0 }, 207 { X86::OR8rr, X86::OR8mr, 0 }, 208 { X86::RCL16r1, X86::RCL16m1, 0 }, 209 { X86::RCL16rCL, X86::RCL16mCL, 0 }, 210 { X86::RCL16ri, X86::RCL16mi, 0 }, 211 { X86::RCL32r1, X86::RCL32m1, 0 }, 212 { X86::RCL32rCL, X86::RCL32mCL, 0 }, 213 { X86::RCL32ri, X86::RCL32mi, 0 }, 214 { X86::RCL64r1, X86::RCL64m1, 0 }, 215 { X86::RCL64rCL, X86::RCL64mCL, 0 }, 216 { X86::RCL64ri, X86::RCL64mi, 0 }, 217 { X86::RCL8r1, X86::RCL8m1, 0 }, 218 { X86::RCL8rCL, X86::RCL8mCL, 0 }, 219 { X86::RCL8ri, X86::RCL8mi, 0 }, 220 { X86::RCR16r1, X86::RCR16m1, 0 }, 221 { X86::RCR16rCL, X86::RCR16mCL, 0 }, 222 { X86::RCR16ri, X86::RCR16mi, 0 }, 223 { X86::RCR32r1, X86::RCR32m1, 0 }, 224 { X86::RCR32rCL, X86::RCR32mCL, 0 }, 225 { X86::RCR32ri, X86::RCR32mi, 0 }, 226 { X86::RCR64r1, X86::RCR64m1, 0 }, 227 { X86::RCR64rCL, X86::RCR64mCL, 0 }, 228 { X86::RCR64ri, X86::RCR64mi, 0 }, 229 { X86::RCR8r1, X86::RCR8m1, 0 }, 230 { X86::RCR8rCL, X86::RCR8mCL, 0 }, 231 { X86::RCR8ri, X86::RCR8mi, 0 }, 232 { X86::ROL16r1, X86::ROL16m1, 0 }, 233 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 234 { X86::ROL16ri, X86::ROL16mi, 0 }, 235 { X86::ROL32r1, X86::ROL32m1, 0 }, 236 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 237 { X86::ROL32ri, X86::ROL32mi, 0 }, 238 { X86::ROL64r1, X86::ROL64m1, 0 }, 239 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 240 { X86::ROL64ri, X86::ROL64mi, 0 }, 241 { X86::ROL8r1, X86::ROL8m1, 0 }, 242 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 243 { X86::ROL8ri, X86::ROL8mi, 0 }, 244 { X86::ROR16r1, X86::ROR16m1, 0 }, 245 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 246 { X86::ROR16ri, X86::ROR16mi, 0 }, 247 { X86::ROR32r1, X86::ROR32m1, 0 }, 248 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 249 { X86::ROR32ri, X86::ROR32mi, 0 }, 250 { X86::ROR64r1, X86::ROR64m1, 0 }, 251 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 252 { X86::ROR64ri, X86::ROR64mi, 0 }, 253 { X86::ROR8r1, X86::ROR8m1, 0 }, 254 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 255 { X86::ROR8ri, X86::ROR8mi, 0 }, 256 { X86::SAR16r1, X86::SAR16m1, 0 }, 257 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 258 { X86::SAR16ri, X86::SAR16mi, 0 }, 259 { X86::SAR32r1, X86::SAR32m1, 0 }, 260 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 261 { X86::SAR32ri, X86::SAR32mi, 0 }, 262 { X86::SAR64r1, X86::SAR64m1, 0 }, 263 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 264 { X86::SAR64ri, X86::SAR64mi, 0 }, 265 { X86::SAR8r1, X86::SAR8m1, 0 }, 266 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 267 { X86::SAR8ri, X86::SAR8mi, 0 }, 268 { X86::SBB16ri, X86::SBB16mi, 0 }, 269 { X86::SBB16ri8, X86::SBB16mi8, 0 }, 270 { X86::SBB16rr, X86::SBB16mr, 0 }, 271 { X86::SBB32ri, X86::SBB32mi, 0 }, 272 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 273 { X86::SBB32rr, X86::SBB32mr, 0 }, 274 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 275 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 276 { X86::SBB64rr, X86::SBB64mr, 0 }, 277 { X86::SBB8ri, X86::SBB8mi, 0 }, 278 { X86::SBB8ri8, X86::SBB8mi8, 0 }, 279 { X86::SBB8rr, X86::SBB8mr, 0 }, 280 { X86::SHL16r1, X86::SHL16m1, 0 }, 281 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 282 { X86::SHL16ri, X86::SHL16mi, 0 }, 283 { X86::SHL32r1, X86::SHL32m1, 0 }, 284 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 285 { X86::SHL32ri, X86::SHL32mi, 0 }, 286 { X86::SHL64r1, X86::SHL64m1, 0 }, 287 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 288 { X86::SHL64ri, X86::SHL64mi, 0 }, 289 { X86::SHL8r1, X86::SHL8m1, 0 }, 290 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 291 { X86::SHL8ri, X86::SHL8mi, 0 }, 292 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 293 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 294 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 295 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 296 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 297 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 298 { X86::SHR16r1, X86::SHR16m1, 0 }, 299 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 300 { X86::SHR16ri, X86::SHR16mi, 0 }, 301 { X86::SHR32r1, X86::SHR32m1, 0 }, 302 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 303 { X86::SHR32ri, X86::SHR32mi, 0 }, 304 { X86::SHR64r1, X86::SHR64m1, 0 }, 305 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 306 { X86::SHR64ri, X86::SHR64mi, 0 }, 307 { X86::SHR8r1, X86::SHR8m1, 0 }, 308 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 309 { X86::SHR8ri, X86::SHR8mi, 0 }, 310 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 311 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 312 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 313 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 314 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 315 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 316 { X86::SUB16ri, X86::SUB16mi, 0 }, 317 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 318 { X86::SUB16rr, X86::SUB16mr, 0 }, 319 { X86::SUB32ri, X86::SUB32mi, 0 }, 320 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 321 { X86::SUB32rr, X86::SUB32mr, 0 }, 322 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 323 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 324 { X86::SUB64rr, X86::SUB64mr, 0 }, 325 { X86::SUB8ri, X86::SUB8mi, 0 }, 326 { X86::SUB8ri8, X86::SUB8mi8, 0 }, 327 { X86::SUB8rr, X86::SUB8mr, 0 }, 328 { X86::XOR16ri, X86::XOR16mi, 0 }, 329 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 330 { X86::XOR16rr, X86::XOR16mr, 0 }, 331 { X86::XOR32ri, X86::XOR32mi, 0 }, 332 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 333 { X86::XOR32rr, X86::XOR32mr, 0 }, 334 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 335 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 336 { X86::XOR64rr, X86::XOR64mr, 0 }, 337 { X86::XOR8ri, X86::XOR8mi, 0 }, 338 { X86::XOR8ri8, X86::XOR8mi8, 0 }, 339 { X86::XOR8rr, X86::XOR8mr, 0 } 340 }; 341 342 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) { 343 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 344 Entry.RegOp, Entry.MemOp, 345 // Index 0, folded load and store, no alignment requirement. 346 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 347 } 348 349 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = { 350 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 351 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 352 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 353 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 354 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 355 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 356 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 357 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 358 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 359 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 360 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 361 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 362 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 363 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 364 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 365 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 366 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 367 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 368 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 369 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 370 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 371 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 372 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 373 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 374 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 375 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 376 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 377 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 378 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 379 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 380 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 381 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 382 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 383 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 384 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 385 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 386 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 387 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 388 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 389 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 390 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 391 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 392 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 393 { X86::MOVDQUrr, X86::MOVDQUmr, TB_FOLDED_STORE }, 394 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 395 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 396 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 397 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 398 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 399 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 400 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 401 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 402 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 403 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 404 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE }, 405 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE }, 406 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD }, 407 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD }, 408 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD }, 409 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 410 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 411 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 412 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 413 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 414 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 415 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 416 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 417 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 418 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 419 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 420 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 421 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 422 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 423 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 424 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 425 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 426 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 427 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD }, 428 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 429 { X86::TEST16rr, X86::TEST16mr, TB_FOLDED_LOAD }, 430 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 431 { X86::TEST32rr, X86::TEST32mr, TB_FOLDED_LOAD }, 432 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 433 { X86::TEST64rr, X86::TEST64mr, TB_FOLDED_LOAD }, 434 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 435 { X86::TEST8rr, X86::TEST8mr, TB_FOLDED_LOAD }, 436 437 // AVX 128-bit versions of foldable instructions 438 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 439 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 440 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 441 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 442 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 443 { X86::VMOVDQUrr, X86::VMOVDQUmr, TB_FOLDED_STORE }, 444 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 445 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 446 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 447 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 448 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 449 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 450 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE }, 451 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE }, 452 453 // AVX 256-bit foldable instructions 454 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 455 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 456 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 457 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 458 { X86::VMOVDQUYrr, X86::VMOVDQUYmr, TB_FOLDED_STORE }, 459 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 460 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }, 461 462 // AVX-512 foldable instructions 463 { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE }, 464 { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE }, 465 { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE }, 466 { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE }, 467 { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE }, 468 { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE }, 469 { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE }, 470 { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE }, 471 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZmr, TB_FOLDED_STORE }, 472 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 473 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 474 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 475 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 476 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE }, 477 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE }, 478 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE }, 479 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE }, 480 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }, 481 { X86::VMOVPQIto64Zrr, X86::VMOVPQI2QIZmr, TB_FOLDED_STORE }, 482 { X86::VMOVSDto64Zrr, X86::VMOVSDto64Zmr, TB_FOLDED_STORE }, 483 { X86::VMOVSS2DIZrr, X86::VMOVSS2DIZmr, TB_FOLDED_STORE }, 484 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE }, 485 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE }, 486 { X86::VPEXTRDZrr, X86::VPEXTRDZmr, TB_FOLDED_STORE }, 487 { X86::VPEXTRQZrr, X86::VPEXTRQZmr, TB_FOLDED_STORE }, 488 { X86::VPMOVDBZrr, X86::VPMOVDBZmr, TB_FOLDED_STORE }, 489 { X86::VPMOVDWZrr, X86::VPMOVDWZmr, TB_FOLDED_STORE }, 490 { X86::VPMOVQDZrr, X86::VPMOVQDZmr, TB_FOLDED_STORE }, 491 { X86::VPMOVQWZrr, X86::VPMOVQWZmr, TB_FOLDED_STORE }, 492 { X86::VPMOVWBZrr, X86::VPMOVWBZmr, TB_FOLDED_STORE }, 493 { X86::VPMOVSDBZrr, X86::VPMOVSDBZmr, TB_FOLDED_STORE }, 494 { X86::VPMOVSDWZrr, X86::VPMOVSDWZmr, TB_FOLDED_STORE }, 495 { X86::VPMOVSQDZrr, X86::VPMOVSQDZmr, TB_FOLDED_STORE }, 496 { X86::VPMOVSQWZrr, X86::VPMOVSQWZmr, TB_FOLDED_STORE }, 497 { X86::VPMOVSWBZrr, X86::VPMOVSWBZmr, TB_FOLDED_STORE }, 498 { X86::VPMOVUSDBZrr, X86::VPMOVUSDBZmr, TB_FOLDED_STORE }, 499 { X86::VPMOVUSDWZrr, X86::VPMOVUSDWZmr, TB_FOLDED_STORE }, 500 { X86::VPMOVUSQDZrr, X86::VPMOVUSQDZmr, TB_FOLDED_STORE }, 501 { X86::VPMOVUSQWZrr, X86::VPMOVUSQWZmr, TB_FOLDED_STORE }, 502 { X86::VPMOVUSWBZrr, X86::VPMOVUSWBZmr, TB_FOLDED_STORE }, 503 504 // AVX-512 foldable instructions (256-bit versions) 505 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE }, 506 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE }, 507 { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE }, 508 { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE }, 509 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 510 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 511 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 512 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 513 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE }, 514 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE }, 515 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE }, 516 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE }, 517 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE }, 518 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE }, 519 { X86::VPMOVDWZ256rr, X86::VPMOVDWZ256mr, TB_FOLDED_STORE }, 520 { X86::VPMOVQDZ256rr, X86::VPMOVQDZ256mr, TB_FOLDED_STORE }, 521 { X86::VPMOVWBZ256rr, X86::VPMOVWBZ256mr, TB_FOLDED_STORE }, 522 { X86::VPMOVSDWZ256rr, X86::VPMOVSDWZ256mr, TB_FOLDED_STORE }, 523 { X86::VPMOVSQDZ256rr, X86::VPMOVSQDZ256mr, TB_FOLDED_STORE }, 524 { X86::VPMOVSWBZ256rr, X86::VPMOVSWBZ256mr, TB_FOLDED_STORE }, 525 { X86::VPMOVUSDWZ256rr, X86::VPMOVUSDWZ256mr, TB_FOLDED_STORE }, 526 { X86::VPMOVUSQDZ256rr, X86::VPMOVUSQDZ256mr, TB_FOLDED_STORE }, 527 { X86::VPMOVUSWBZ256rr, X86::VPMOVUSWBZ256mr, TB_FOLDED_STORE }, 528 529 // AVX-512 foldable instructions (128-bit versions) 530 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 531 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 532 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 533 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 534 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE }, 535 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE }, 536 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE }, 537 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE }, 538 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE }, 539 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE }, 540 541 // F16C foldable instructions 542 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE }, 543 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE } 544 }; 545 546 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) { 547 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 548 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags); 549 } 550 551 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = { 552 { X86::BSF16rr, X86::BSF16rm, 0 }, 553 { X86::BSF32rr, X86::BSF32rm, 0 }, 554 { X86::BSF64rr, X86::BSF64rm, 0 }, 555 { X86::BSR16rr, X86::BSR16rm, 0 }, 556 { X86::BSR32rr, X86::BSR32rm, 0 }, 557 { X86::BSR64rr, X86::BSR64rm, 0 }, 558 { X86::CMP16rr, X86::CMP16rm, 0 }, 559 { X86::CMP32rr, X86::CMP32rm, 0 }, 560 { X86::CMP64rr, X86::CMP64rm, 0 }, 561 { X86::CMP8rr, X86::CMP8rm, 0 }, 562 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_NO_REVERSE }, 563 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 }, 564 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 }, 565 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 }, 566 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 }, 567 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_NO_REVERSE }, 568 { X86::CVTSD2SI64rr_Int, X86::CVTSD2SI64rm_Int, TB_NO_REVERSE }, 569 { X86::CVTSD2SIrr_Int, X86::CVTSD2SIrm_Int, TB_NO_REVERSE }, 570 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 571 { X86::CVTSI642SDrr, X86::CVTSI642SDrm, 0 }, 572 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 573 { X86::CVTSI642SSrr, X86::CVTSI642SSrm, 0 }, 574 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 575 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 576 { X86::CVTSS2SI64rr_Int, X86::CVTSS2SI64rm_Int, TB_NO_REVERSE }, 577 { X86::CVTSS2SIrr_Int, X86::CVTSS2SIrm_Int, TB_NO_REVERSE }, 578 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 579 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 580 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 581 { X86::CVTTSD2SI64rr_Int,X86::CVTTSD2SI64rm_Int, TB_NO_REVERSE }, 582 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 583 { X86::CVTTSD2SIrr_Int, X86::CVTTSD2SIrm_Int, TB_NO_REVERSE }, 584 { X86::CVTTSS2SI64rr_Int,X86::CVTTSS2SI64rm_Int, TB_NO_REVERSE }, 585 { X86::CVTTSS2SIrr_Int, X86::CVTTSS2SIrm_Int, TB_NO_REVERSE }, 586 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 587 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 588 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 589 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 590 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 591 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 592 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 593 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 594 { X86::Int_COMISDrr, X86::Int_COMISDrm, TB_NO_REVERSE }, 595 { X86::Int_COMISSrr, X86::Int_COMISSrm, TB_NO_REVERSE }, 596 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, TB_NO_REVERSE }, 597 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, TB_NO_REVERSE }, 598 { X86::MOV16rr, X86::MOV16rm, 0 }, 599 { X86::MOV32rr, X86::MOV32rm, 0 }, 600 { X86::MOV64rr, X86::MOV64rm, 0 }, 601 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 602 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 603 { X86::MOV8rr, X86::MOV8rm, 0 }, 604 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 605 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 606 { X86::MOVDDUPrr, X86::MOVDDUPrm, TB_NO_REVERSE }, 607 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 608 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 609 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 610 { X86::MOVDQUrr, X86::MOVDQUrm, 0 }, 611 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 612 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 613 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 614 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 615 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 616 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 617 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 618 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 619 { X86::MOVUPDrr, X86::MOVUPDrm, 0 }, 620 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 621 { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm, TB_NO_REVERSE }, 622 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 623 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 624 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 625 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 626 { X86::PABSBrr, X86::PABSBrm, TB_ALIGN_16 }, 627 { X86::PABSDrr, X86::PABSDrm, TB_ALIGN_16 }, 628 { X86::PABSWrr, X86::PABSWrm, TB_ALIGN_16 }, 629 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 }, 630 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 }, 631 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 }, 632 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 }, 633 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 }, 634 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_NO_REVERSE }, 635 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_NO_REVERSE }, 636 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_NO_REVERSE }, 637 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_NO_REVERSE }, 638 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_NO_REVERSE }, 639 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_NO_REVERSE }, 640 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_NO_REVERSE }, 641 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_NO_REVERSE }, 642 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_NO_REVERSE }, 643 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_NO_REVERSE }, 644 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_NO_REVERSE }, 645 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_NO_REVERSE }, 646 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 647 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 648 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 649 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 }, 650 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 651 { X86::RCPSSr, X86::RCPSSm, 0 }, 652 { X86::RCPSSr_Int, X86::RCPSSm_Int, TB_NO_REVERSE }, 653 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 }, 654 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 }, 655 { X86::ROUNDSDr, X86::ROUNDSDm, 0 }, 656 { X86::ROUNDSSr, X86::ROUNDSSm, 0 }, 657 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 658 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 659 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, TB_NO_REVERSE }, 660 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 661 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 662 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 663 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE }, 664 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 665 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE }, 666 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 667 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 668 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 669 670 // MMX version of foldable instructions 671 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 }, 672 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 }, 673 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 }, 674 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 }, 675 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 }, 676 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 }, 677 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 }, 678 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 }, 679 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 }, 680 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 }, 681 682 // 3DNow! version of foldable instructions 683 { X86::PF2IDrr, X86::PF2IDrm, 0 }, 684 { X86::PF2IWrr, X86::PF2IWrm, 0 }, 685 { X86::PFRCPrr, X86::PFRCPrm, 0 }, 686 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 }, 687 { X86::PI2FDrr, X86::PI2FDrm, 0 }, 688 { X86::PI2FWrr, X86::PI2FWrm, 0 }, 689 { X86::PSWAPDrr, X86::PSWAPDrm, 0 }, 690 691 // AVX 128-bit versions of foldable instructions 692 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, TB_NO_REVERSE }, 693 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, TB_NO_REVERSE }, 694 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, TB_NO_REVERSE }, 695 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, TB_NO_REVERSE }, 696 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 697 { X86::VCVTTSD2SI64rr_Int,X86::VCVTTSD2SI64rm_Int,TB_NO_REVERSE }, 698 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 699 { X86::VCVTTSD2SIrr_Int,X86::VCVTTSD2SIrm_Int, TB_NO_REVERSE }, 700 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 701 { X86::VCVTTSS2SI64rr_Int,X86::VCVTTSS2SI64rm_Int,TB_NO_REVERSE }, 702 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 703 { X86::VCVTTSS2SIrr_Int,X86::VCVTTSS2SIrm_Int, TB_NO_REVERSE }, 704 { X86::VCVTSD2SI64rr_Int, X86::VCVTSD2SI64rm_Int, TB_NO_REVERSE }, 705 { X86::VCVTSD2SIrr_Int, X86::VCVTSD2SIrm_Int, TB_NO_REVERSE }, 706 { X86::VCVTSS2SI64rr_Int, X86::VCVTSS2SI64rm_Int, TB_NO_REVERSE }, 707 { X86::VCVTSS2SIrr_Int, X86::VCVTSS2SIrm_Int, TB_NO_REVERSE }, 708 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, TB_NO_REVERSE }, 709 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 }, 710 { X86::VCVTPD2DQrr, X86::VCVTPD2DQrm, 0 }, 711 { X86::VCVTPD2PSrr, X86::VCVTPD2PSrm, 0 }, 712 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 }, 713 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, TB_NO_REVERSE }, 714 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, 0 }, 715 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 716 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 717 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 718 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 719 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 720 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, TB_NO_REVERSE }, 721 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 722 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 723 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 724 { X86::VMOVDQUrr, X86::VMOVDQUrm, 0 }, 725 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 }, 726 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 }, 727 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 728 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 729 { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm, TB_NO_REVERSE }, 730 { X86::VPABSBrr, X86::VPABSBrm, 0 }, 731 { X86::VPABSDrr, X86::VPABSDrm, 0 }, 732 { X86::VPABSWrr, X86::VPABSWrm, 0 }, 733 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 }, 734 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 }, 735 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 }, 736 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 }, 737 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 }, 738 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 739 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 740 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, TB_NO_REVERSE }, 741 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, TB_NO_REVERSE }, 742 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, TB_NO_REVERSE }, 743 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, TB_NO_REVERSE }, 744 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, TB_NO_REVERSE }, 745 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, TB_NO_REVERSE }, 746 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, TB_NO_REVERSE }, 747 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, TB_NO_REVERSE }, 748 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, TB_NO_REVERSE }, 749 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, TB_NO_REVERSE }, 750 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, TB_NO_REVERSE }, 751 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, TB_NO_REVERSE }, 752 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 753 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 754 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 755 { X86::VPTESTrr, X86::VPTESTrm, 0 }, 756 { X86::VRCPPSr, X86::VRCPPSm, 0 }, 757 { X86::VROUNDPDr, X86::VROUNDPDm, 0 }, 758 { X86::VROUNDPSr, X86::VROUNDPSm, 0 }, 759 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 760 { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 761 { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 762 { X86::VTESTPDrr, X86::VTESTPDrm, 0 }, 763 { X86::VTESTPSrr, X86::VTESTPSrm, 0 }, 764 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 765 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 766 767 // AVX 256-bit foldable instructions 768 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 }, 769 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 }, 770 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 }, 771 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 }, 772 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 }, 773 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 }, 774 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 }, 775 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 }, 776 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 777 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 778 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 }, 779 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 780 { X86::VMOVDQUYrr, X86::VMOVDQUYrm, 0 }, 781 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 }, 782 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 }, 783 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 784 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 785 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 786 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 787 { X86::VPTESTYrr, X86::VPTESTYrm, 0 }, 788 { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 789 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 }, 790 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 }, 791 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 792 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 793 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 794 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 }, 795 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 }, 796 797 // AVX2 foldable instructions 798 799 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the 800 // VBROADCASTS{SD}rm memory instructions were available from AVX1. 801 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction 802 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions 803 // so they don't need an equivalent limitation. 804 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 805 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 806 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 807 { X86::VPABSBYrr, X86::VPABSBYrm, 0 }, 808 { X86::VPABSDYrr, X86::VPABSDYrm, 0 }, 809 { X86::VPABSWYrr, X86::VPABSWYrm, 0 }, 810 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, TB_NO_REVERSE }, 811 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, TB_NO_REVERSE }, 812 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, TB_NO_REVERSE }, 813 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, TB_NO_REVERSE }, 814 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, TB_NO_REVERSE }, 815 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, TB_NO_REVERSE }, 816 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, TB_NO_REVERSE }, 817 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, TB_NO_REVERSE }, 818 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 819 { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 820 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, TB_NO_REVERSE }, 821 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, TB_NO_REVERSE }, 822 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 }, 823 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 }, 824 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 }, 825 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, TB_NO_REVERSE }, 826 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, TB_NO_REVERSE }, 827 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, TB_NO_REVERSE }, 828 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 }, 829 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 }, 830 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 }, 831 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, TB_NO_REVERSE }, 832 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 833 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 834 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 835 836 // XOP foldable instructions 837 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 }, 838 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 }, 839 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 }, 840 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 }, 841 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 }, 842 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 }, 843 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 }, 844 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 }, 845 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 }, 846 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 }, 847 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 }, 848 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 }, 849 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 }, 850 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 }, 851 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 }, 852 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 }, 853 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 }, 854 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 }, 855 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 }, 856 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 }, 857 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 }, 858 { X86::VPROTBri, X86::VPROTBmi, 0 }, 859 { X86::VPROTBrr, X86::VPROTBmr, 0 }, 860 { X86::VPROTDri, X86::VPROTDmi, 0 }, 861 { X86::VPROTDrr, X86::VPROTDmr, 0 }, 862 { X86::VPROTQri, X86::VPROTQmi, 0 }, 863 { X86::VPROTQrr, X86::VPROTQmr, 0 }, 864 { X86::VPROTWri, X86::VPROTWmi, 0 }, 865 { X86::VPROTWrr, X86::VPROTWmr, 0 }, 866 { X86::VPSHABrr, X86::VPSHABmr, 0 }, 867 { X86::VPSHADrr, X86::VPSHADmr, 0 }, 868 { X86::VPSHAQrr, X86::VPSHAQmr, 0 }, 869 { X86::VPSHAWrr, X86::VPSHAWmr, 0 }, 870 { X86::VPSHLBrr, X86::VPSHLBmr, 0 }, 871 { X86::VPSHLDrr, X86::VPSHLDmr, 0 }, 872 { X86::VPSHLQrr, X86::VPSHLQmr, 0 }, 873 { X86::VPSHLWrr, X86::VPSHLWmr, 0 }, 874 875 // LWP foldable instructions 876 { X86::LWPINS32rri, X86::LWPINS32rmi, 0 }, 877 { X86::LWPINS64rri, X86::LWPINS64rmi, 0 }, 878 { X86::LWPVAL32rri, X86::LWPVAL32rmi, 0 }, 879 { X86::LWPVAL64rri, X86::LWPVAL64rmi, 0 }, 880 881 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions 882 { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 883 { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 884 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 }, 885 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 }, 886 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 }, 887 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 }, 888 { X86::BLCI32rr, X86::BLCI32rm, 0 }, 889 { X86::BLCI64rr, X86::BLCI64rm, 0 }, 890 { X86::BLCIC32rr, X86::BLCIC32rm, 0 }, 891 { X86::BLCIC64rr, X86::BLCIC64rm, 0 }, 892 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 }, 893 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 }, 894 { X86::BLCS32rr, X86::BLCS32rm, 0 }, 895 { X86::BLCS64rr, X86::BLCS64rm, 0 }, 896 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 }, 897 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 }, 898 { X86::BLSI32rr, X86::BLSI32rm, 0 }, 899 { X86::BLSI64rr, X86::BLSI64rm, 0 }, 900 { X86::BLSIC32rr, X86::BLSIC32rm, 0 }, 901 { X86::BLSIC64rr, X86::BLSIC64rm, 0 }, 902 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 903 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 904 { X86::BLSR32rr, X86::BLSR32rm, 0 }, 905 { X86::BLSR64rr, X86::BLSR64rm, 0 }, 906 { X86::BZHI32rr, X86::BZHI32rm, 0 }, 907 { X86::BZHI64rr, X86::BZHI64rm, 0 }, 908 { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 909 { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 910 { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 911 { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 912 { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 913 { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 914 { X86::RORX32ri, X86::RORX32mi, 0 }, 915 { X86::RORX64ri, X86::RORX64mi, 0 }, 916 { X86::SARX32rr, X86::SARX32rm, 0 }, 917 { X86::SARX64rr, X86::SARX64rm, 0 }, 918 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 919 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 920 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 921 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 922 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 }, 923 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 }, 924 { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 925 { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 926 { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 927 { X86::TZMSK32rr, X86::TZMSK32rm, 0 }, 928 { X86::TZMSK64rr, X86::TZMSK64rm, 0 }, 929 930 // AVX-512 foldable instructions 931 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE }, 932 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE }, 933 { X86::VCVTDQ2PDZrr, X86::VCVTDQ2PDZrm, 0 }, 934 { X86::VCVTPD2PSZrr, X86::VCVTPD2PSZrm, 0 }, 935 { X86::VCVTUDQ2PDZrr, X86::VCVTUDQ2PDZrm, 0 }, 936 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 }, 937 { X86::VMOV64toSDZrr, X86::VMOV64toSDZrm, 0 }, 938 { X86::VMOVDI2PDIZrr, X86::VMOVDI2PDIZrm, 0 }, 939 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 }, 940 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 }, 941 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 }, 942 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 }, 943 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 }, 944 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 }, 945 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 }, 946 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 }, 947 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 }, 948 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 }, 949 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 }, 950 { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm, TB_NO_REVERSE }, 951 { X86::VPABSBZrr, X86::VPABSBZrm, 0 }, 952 { X86::VPABSDZrr, X86::VPABSDZrm, 0 }, 953 { X86::VPABSQZrr, X86::VPABSQZrm, 0 }, 954 { X86::VPABSWZrr, X86::VPABSWZrm, 0 }, 955 { X86::VPCONFLICTDZrr, X86::VPCONFLICTDZrm, 0 }, 956 { X86::VPCONFLICTQZrr, X86::VPCONFLICTQZrm, 0 }, 957 { X86::VPERMILPDZri, X86::VPERMILPDZmi, 0 }, 958 { X86::VPERMILPSZri, X86::VPERMILPSZmi, 0 }, 959 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 }, 960 { X86::VPERMQZri, X86::VPERMQZmi, 0 }, 961 { X86::VPLZCNTDZrr, X86::VPLZCNTDZrm, 0 }, 962 { X86::VPLZCNTQZrr, X86::VPLZCNTQZrm, 0 }, 963 { X86::VPMOVSXBDZrr, X86::VPMOVSXBDZrm, 0 }, 964 { X86::VPMOVSXBQZrr, X86::VPMOVSXBQZrm, TB_NO_REVERSE }, 965 { X86::VPMOVSXBWZrr, X86::VPMOVSXBWZrm, 0 }, 966 { X86::VPMOVSXDQZrr, X86::VPMOVSXDQZrm, 0 }, 967 { X86::VPMOVSXWDZrr, X86::VPMOVSXWDZrm, 0 }, 968 { X86::VPMOVSXWQZrr, X86::VPMOVSXWQZrm, 0 }, 969 { X86::VPMOVZXBDZrr, X86::VPMOVZXBDZrm, 0 }, 970 { X86::VPMOVZXBQZrr, X86::VPMOVZXBQZrm, TB_NO_REVERSE }, 971 { X86::VPMOVZXBWZrr, X86::VPMOVZXBWZrm, 0 }, 972 { X86::VPMOVZXDQZrr, X86::VPMOVZXDQZrm, 0 }, 973 { X86::VPMOVZXWDZrr, X86::VPMOVZXWDZrm, 0 }, 974 { X86::VPMOVZXWQZrr, X86::VPMOVZXWQZrm, 0 }, 975 { X86::VPOPCNTDZrr, X86::VPOPCNTDZrm, 0 }, 976 { X86::VPOPCNTQZrr, X86::VPOPCNTQZrm, 0 }, 977 { X86::VPSHUFDZri, X86::VPSHUFDZmi, 0 }, 978 { X86::VPSHUFHWZri, X86::VPSHUFHWZmi, 0 }, 979 { X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 }, 980 { X86::VPSLLDQZrr, X86::VPSLLDQZrm, 0 }, 981 { X86::VPSLLDZri, X86::VPSLLDZmi, 0 }, 982 { X86::VPSLLQZri, X86::VPSLLQZmi, 0 }, 983 { X86::VPSLLWZri, X86::VPSLLWZmi, 0 }, 984 { X86::VPSRADZri, X86::VPSRADZmi, 0 }, 985 { X86::VPSRAQZri, X86::VPSRAQZmi, 0 }, 986 { X86::VPSRAWZri, X86::VPSRAWZmi, 0 }, 987 { X86::VPSRLDQZrr, X86::VPSRLDQZrm, 0 }, 988 { X86::VPSRLDZri, X86::VPSRLDZmi, 0 }, 989 { X86::VPSRLQZri, X86::VPSRLQZmi, 0 }, 990 { X86::VPSRLWZri, X86::VPSRLWZmi, 0 }, 991 992 // AVX-512 foldable instructions (256-bit versions) 993 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE }, 994 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE }, 995 { X86::VCVTDQ2PDZ256rr, X86::VCVTDQ2PDZ256rm, 0 }, 996 { X86::VCVTPD2PSZ256rr, X86::VCVTPD2PSZ256rm, 0 }, 997 { X86::VCVTUDQ2PDZ256rr, X86::VCVTUDQ2PDZ256rm, 0 }, 998 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 }, 999 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 }, 1000 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 }, 1001 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 }, 1002 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 }, 1003 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 }, 1004 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 }, 1005 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 }, 1006 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 }, 1007 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 }, 1008 { X86::VPABSBZ256rr, X86::VPABSBZ256rm, 0 }, 1009 { X86::VPABSDZ256rr, X86::VPABSDZ256rm, 0 }, 1010 { X86::VPABSQZ256rr, X86::VPABSQZ256rm, 0 }, 1011 { X86::VPABSWZ256rr, X86::VPABSWZ256rm, 0 }, 1012 { X86::VPCONFLICTDZ256rr, X86::VPCONFLICTDZ256rm, 0 }, 1013 { X86::VPCONFLICTQZ256rr, X86::VPCONFLICTQZ256rm, 0 }, 1014 { X86::VPERMILPDZ256ri, X86::VPERMILPDZ256mi, 0 }, 1015 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256mi, 0 }, 1016 { X86::VPERMPDZ256ri, X86::VPERMPDZ256mi, 0 }, 1017 { X86::VPERMQZ256ri, X86::VPERMQZ256mi, 0 }, 1018 { X86::VPLZCNTDZ256rr, X86::VPLZCNTDZ256rm, 0 }, 1019 { X86::VPLZCNTQZ256rr, X86::VPLZCNTQZ256rm, 0 }, 1020 { X86::VPMOVSXBDZ256rr, X86::VPMOVSXBDZ256rm, TB_NO_REVERSE }, 1021 { X86::VPMOVSXBQZ256rr, X86::VPMOVSXBQZ256rm, TB_NO_REVERSE }, 1022 { X86::VPMOVSXBWZ256rr, X86::VPMOVSXBWZ256rm, 0 }, 1023 { X86::VPMOVSXDQZ256rr, X86::VPMOVSXDQZ256rm, 0 }, 1024 { X86::VPMOVSXWDZ256rr, X86::VPMOVSXWDZ256rm, 0 }, 1025 { X86::VPMOVSXWQZ256rr, X86::VPMOVSXWQZ256rm, TB_NO_REVERSE }, 1026 { X86::VPMOVZXBDZ256rr, X86::VPMOVZXBDZ256rm, TB_NO_REVERSE }, 1027 { X86::VPMOVZXBQZ256rr, X86::VPMOVZXBQZ256rm, TB_NO_REVERSE }, 1028 { X86::VPMOVZXBWZ256rr, X86::VPMOVZXBWZ256rm, 0 }, 1029 { X86::VPMOVZXDQZ256rr, X86::VPMOVZXDQZ256rm, 0 }, 1030 { X86::VPMOVZXWDZ256rr, X86::VPMOVZXWDZ256rm, 0 }, 1031 { X86::VPMOVZXWQZ256rr, X86::VPMOVZXWQZ256rm, TB_NO_REVERSE }, 1032 { X86::VPSHUFDZ256ri, X86::VPSHUFDZ256mi, 0 }, 1033 { X86::VPSHUFHWZ256ri, X86::VPSHUFHWZ256mi, 0 }, 1034 { X86::VPSHUFLWZ256ri, X86::VPSHUFLWZ256mi, 0 }, 1035 { X86::VPSLLDQZ256rr, X86::VPSLLDQZ256rm, 0 }, 1036 { X86::VPSLLDZ256ri, X86::VPSLLDZ256mi, 0 }, 1037 { X86::VPSLLQZ256ri, X86::VPSLLQZ256mi, 0 }, 1038 { X86::VPSLLWZ256ri, X86::VPSLLWZ256mi, 0 }, 1039 { X86::VPSRADZ256ri, X86::VPSRADZ256mi, 0 }, 1040 { X86::VPSRAQZ256ri, X86::VPSRAQZ256mi, 0 }, 1041 { X86::VPSRAWZ256ri, X86::VPSRAWZ256mi, 0 }, 1042 { X86::VPSRLDQZ256rr, X86::VPSRLDQZ256rm, 0 }, 1043 { X86::VPSRLDZ256ri, X86::VPSRLDZ256mi, 0 }, 1044 { X86::VPSRLQZ256ri, X86::VPSRLQZ256mi, 0 }, 1045 { X86::VPSRLWZ256ri, X86::VPSRLWZ256mi, 0 }, 1046 1047 // AVX-512 foldable instructions (128-bit versions) 1048 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE }, 1049 { X86::VCVTDQ2PDZ128rr, X86::VCVTDQ2PDZ128rm, TB_NO_REVERSE }, 1050 { X86::VCVTPD2PSZ128rr, X86::VCVTPD2PSZ128rm, 0 }, 1051 { X86::VCVTUDQ2PDZ128rr, X86::VCVTUDQ2PDZ128rm, TB_NO_REVERSE }, 1052 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 }, 1053 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 }, 1054 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 }, 1055 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 }, 1056 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 }, 1057 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 }, 1058 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 }, 1059 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 }, 1060 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 }, 1061 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 }, 1062 { X86::VPABSBZ128rr, X86::VPABSBZ128rm, 0 }, 1063 { X86::VPABSDZ128rr, X86::VPABSDZ128rm, 0 }, 1064 { X86::VPABSQZ128rr, X86::VPABSQZ128rm, 0 }, 1065 { X86::VPABSWZ128rr, X86::VPABSWZ128rm, 0 }, 1066 { X86::VPCONFLICTDZ128rr, X86::VPCONFLICTDZ128rm, 0 }, 1067 { X86::VPCONFLICTQZ128rr, X86::VPCONFLICTQZ128rm, 0 }, 1068 { X86::VPERMILPDZ128ri, X86::VPERMILPDZ128mi, 0 }, 1069 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128mi, 0 }, 1070 { X86::VPLZCNTDZ128rr, X86::VPLZCNTDZ128rm, 0 }, 1071 { X86::VPLZCNTQZ128rr, X86::VPLZCNTQZ128rm, 0 }, 1072 { X86::VPMOVSXBDZ128rr, X86::VPMOVSXBDZ128rm, TB_NO_REVERSE }, 1073 { X86::VPMOVSXBQZ128rr, X86::VPMOVSXBQZ128rm, TB_NO_REVERSE }, 1074 { X86::VPMOVSXBWZ128rr, X86::VPMOVSXBWZ128rm, TB_NO_REVERSE }, 1075 { X86::VPMOVSXDQZ128rr, X86::VPMOVSXDQZ128rm, TB_NO_REVERSE }, 1076 { X86::VPMOVSXWDZ128rr, X86::VPMOVSXWDZ128rm, TB_NO_REVERSE }, 1077 { X86::VPMOVSXWQZ128rr, X86::VPMOVSXWQZ128rm, TB_NO_REVERSE }, 1078 { X86::VPMOVZXBDZ128rr, X86::VPMOVZXBDZ128rm, TB_NO_REVERSE }, 1079 { X86::VPMOVZXBQZ128rr, X86::VPMOVZXBQZ128rm, TB_NO_REVERSE }, 1080 { X86::VPMOVZXBWZ128rr, X86::VPMOVZXBWZ128rm, TB_NO_REVERSE }, 1081 { X86::VPMOVZXDQZ128rr, X86::VPMOVZXDQZ128rm, TB_NO_REVERSE }, 1082 { X86::VPMOVZXWDZ128rr, X86::VPMOVZXWDZ128rm, TB_NO_REVERSE }, 1083 { X86::VPMOVZXWQZ128rr, X86::VPMOVZXWQZ128rm, TB_NO_REVERSE }, 1084 { X86::VPSHUFDZ128ri, X86::VPSHUFDZ128mi, 0 }, 1085 { X86::VPSHUFHWZ128ri, X86::VPSHUFHWZ128mi, 0 }, 1086 { X86::VPSHUFLWZ128ri, X86::VPSHUFLWZ128mi, 0 }, 1087 { X86::VPSLLDQZ128rr, X86::VPSLLDQZ128rm, 0 }, 1088 { X86::VPSLLDZ128ri, X86::VPSLLDZ128mi, 0 }, 1089 { X86::VPSLLQZ128ri, X86::VPSLLQZ128mi, 0 }, 1090 { X86::VPSLLWZ128ri, X86::VPSLLWZ128mi, 0 }, 1091 { X86::VPSRADZ128ri, X86::VPSRADZ128mi, 0 }, 1092 { X86::VPSRAQZ128ri, X86::VPSRAQZ128mi, 0 }, 1093 { X86::VPSRAWZ128ri, X86::VPSRAWZ128mi, 0 }, 1094 { X86::VPSRLDQZ128rr, X86::VPSRLDQZ128rm, 0 }, 1095 { X86::VPSRLDZ128ri, X86::VPSRLDZ128mi, 0 }, 1096 { X86::VPSRLQZ128ri, X86::VPSRLQZ128mi, 0 }, 1097 { X86::VPSRLWZ128ri, X86::VPSRLWZ128mi, 0 }, 1098 1099 // F16C foldable instructions 1100 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 }, 1101 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 }, 1102 1103 // AES foldable instructions 1104 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 }, 1105 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 }, 1106 { X86::VAESIMCrr, X86::VAESIMCrm, 0 }, 1107 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 } 1108 }; 1109 1110 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) { 1111 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 1112 Entry.RegOp, Entry.MemOp, 1113 // Index 1, folded load 1114 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 1115 } 1116 1117 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = { 1118 { X86::ADC32rr, X86::ADC32rm, 0 }, 1119 { X86::ADC64rr, X86::ADC64rm, 0 }, 1120 { X86::ADD16rr, X86::ADD16rm, 0 }, 1121 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 1122 { X86::ADD32rr, X86::ADD32rm, 0 }, 1123 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 1124 { X86::ADD64rr, X86::ADD64rm, 0 }, 1125 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 1126 { X86::ADD8rr, X86::ADD8rm, 0 }, 1127 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 1128 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 1129 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 1130 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, TB_NO_REVERSE }, 1131 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 1132 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, TB_NO_REVERSE }, 1133 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 1134 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 1135 { X86::AND16rr, X86::AND16rm, 0 }, 1136 { X86::AND32rr, X86::AND32rm, 0 }, 1137 { X86::AND64rr, X86::AND64rm, 0 }, 1138 { X86::AND8rr, X86::AND8rm, 0 }, 1139 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 1140 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 1141 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 1142 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 1143 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 1144 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 1145 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 1146 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 1147 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 1148 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 1149 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 1150 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 1151 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 1152 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 1153 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 1154 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 1155 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 1156 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 1157 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 1158 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 1159 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 1160 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 1161 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 1162 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 1163 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 1164 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 1165 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 1166 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 1167 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 1168 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 1169 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 1170 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 1171 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 1172 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 1173 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 1174 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 1175 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 1176 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 1177 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 1178 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 1179 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 1180 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 1181 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 1182 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 1183 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 1184 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 1185 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 1186 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 1187 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 1188 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 1189 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 1190 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 1191 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 1192 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 1193 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 1194 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 1195 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 1196 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 1197 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 1198 { X86::CMPSDrr_Int, X86::CMPSDrm_Int, TB_NO_REVERSE }, 1199 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 1200 { X86::CMPSSrr_Int, X86::CMPSSrm_Int, TB_NO_REVERSE }, 1201 { X86::CRC32r32r32, X86::CRC32r32m32, 0 }, 1202 { X86::CRC32r64r64, X86::CRC32r64m64, 0 }, 1203 { X86::CVTSD2SSrr_Int, X86::CVTSD2SSrm_Int, TB_NO_REVERSE }, 1204 { X86::CVTSS2SDrr_Int, X86::CVTSS2SDrm_Int, TB_NO_REVERSE }, 1205 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 1206 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 1207 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 1208 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, TB_NO_REVERSE }, 1209 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 1210 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, TB_NO_REVERSE }, 1211 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 }, 1212 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 }, 1213 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 1214 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 1215 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 1216 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 1217 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 1218 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 1219 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 1220 { X86::CVTSI642SDrr_Int,X86::CVTSI642SDrm_Int, 0 }, 1221 { X86::CVTSI2SDrr_Int, X86::CVTSI2SDrm_Int, 0 }, 1222 { X86::CVTSI642SSrr_Int,X86::CVTSI642SSrm_Int, 0 }, 1223 { X86::CVTSI2SSrr_Int, X86::CVTSI2SSrm_Int, 0 }, 1224 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 1225 { X86::MAXCPDrr, X86::MAXCPDrm, TB_ALIGN_16 }, 1226 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 1227 { X86::MAXCPSrr, X86::MAXCPSrm, TB_ALIGN_16 }, 1228 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 1229 { X86::MAXCSDrr, X86::MAXCSDrm, 0 }, 1230 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, TB_NO_REVERSE }, 1231 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 1232 { X86::MAXCSSrr, X86::MAXCSSrm, 0 }, 1233 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, TB_NO_REVERSE }, 1234 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 1235 { X86::MINCPDrr, X86::MINCPDrm, TB_ALIGN_16 }, 1236 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 1237 { X86::MINCPSrr, X86::MINCPSrm, TB_ALIGN_16 }, 1238 { X86::MINSDrr, X86::MINSDrm, 0 }, 1239 { X86::MINCSDrr, X86::MINCSDrm, 0 }, 1240 { X86::MINSDrr_Int, X86::MINSDrm_Int, TB_NO_REVERSE }, 1241 { X86::MINSSrr, X86::MINSSrm, 0 }, 1242 { X86::MINCSSrr, X86::MINCSSrm, 0 }, 1243 { X86::MINSSrr_Int, X86::MINSSrm_Int, TB_NO_REVERSE }, 1244 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE }, 1245 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 1246 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 1247 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 1248 { X86::MULSDrr, X86::MULSDrm, 0 }, 1249 { X86::MULSDrr_Int, X86::MULSDrm_Int, TB_NO_REVERSE }, 1250 { X86::MULSSrr, X86::MULSSrm, 0 }, 1251 { X86::MULSSrr_Int, X86::MULSSrm_Int, TB_NO_REVERSE }, 1252 { X86::OR16rr, X86::OR16rm, 0 }, 1253 { X86::OR32rr, X86::OR32rm, 0 }, 1254 { X86::OR64rr, X86::OR64rm, 0 }, 1255 { X86::OR8rr, X86::OR8rm, 0 }, 1256 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 1257 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 1258 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 1259 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 1260 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 1261 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 1262 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 1263 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 1264 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 1265 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 1266 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 1267 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 1268 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 1269 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 1270 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 }, 1271 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 1272 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 1273 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 1274 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 1275 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 }, 1276 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 1277 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 }, 1278 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 1279 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 1280 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 1281 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 1282 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 1283 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 1284 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 1285 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 1286 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 1287 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 1288 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 1289 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 1290 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 1291 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 1292 { X86::PINSRBrr, X86::PINSRBrm, 0 }, 1293 { X86::PINSRDrr, X86::PINSRDrm, 0 }, 1294 { X86::PINSRQrr, X86::PINSRQrm, 0 }, 1295 { X86::PINSRWrri, X86::PINSRWrmi, 0 }, 1296 { X86::PMADDUBSWrr, X86::PMADDUBSWrm, TB_ALIGN_16 }, 1297 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 1298 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 1299 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 1300 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 1301 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 1302 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 1303 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 1304 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 1305 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 1306 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 1307 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 1308 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 1309 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 1310 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 1311 { X86::PMULHRSWrr, X86::PMULHRSWrm, TB_ALIGN_16 }, 1312 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 1313 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 1314 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 1315 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 1316 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 1317 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 1318 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 1319 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 1320 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 }, 1321 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 }, 1322 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 }, 1323 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 1324 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 1325 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 1326 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 1327 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 1328 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 1329 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 1330 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 1331 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 1332 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 1333 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 }, 1334 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 1335 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 1336 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 }, 1337 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 }, 1338 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 1339 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 1340 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 1341 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 1342 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 1343 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 1344 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 1345 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 1346 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 1347 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 1348 { X86::ROUNDSDr_Int, X86::ROUNDSDm_Int, TB_NO_REVERSE }, 1349 { X86::ROUNDSSr_Int, X86::ROUNDSSm_Int, TB_NO_REVERSE }, 1350 { X86::SBB32rr, X86::SBB32rm, 0 }, 1351 { X86::SBB64rr, X86::SBB64rm, 0 }, 1352 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 1353 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 1354 { X86::SUB16rr, X86::SUB16rm, 0 }, 1355 { X86::SUB32rr, X86::SUB32rm, 0 }, 1356 { X86::SUB64rr, X86::SUB64rm, 0 }, 1357 { X86::SUB8rr, X86::SUB8rm, 0 }, 1358 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 1359 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 1360 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 1361 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, TB_NO_REVERSE }, 1362 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 1363 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, TB_NO_REVERSE }, 1364 // FIXME: TEST*rr -> swapped operand of TEST*mr. 1365 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 1366 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 1367 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 1368 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 1369 { X86::XOR16rr, X86::XOR16rm, 0 }, 1370 { X86::XOR32rr, X86::XOR32rm, 0 }, 1371 { X86::XOR64rr, X86::XOR64rm, 0 }, 1372 { X86::XOR8rr, X86::XOR8rm, 0 }, 1373 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 1374 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 1375 1376 // MMX version of foldable instructions 1377 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 }, 1378 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 }, 1379 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 }, 1380 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 }, 1381 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 }, 1382 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 }, 1383 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 }, 1384 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 }, 1385 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 }, 1386 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 }, 1387 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 }, 1388 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 }, 1389 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 }, 1390 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 }, 1391 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 }, 1392 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 }, 1393 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 }, 1394 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 }, 1395 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 }, 1396 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 }, 1397 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 }, 1398 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 }, 1399 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 }, 1400 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 }, 1401 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 }, 1402 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 }, 1403 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 }, 1404 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 }, 1405 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 }, 1406 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 }, 1407 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 }, 1408 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 }, 1409 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 }, 1410 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 }, 1411 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 }, 1412 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 }, 1413 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 }, 1414 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 }, 1415 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 }, 1416 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 }, 1417 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 }, 1418 { X86::MMX_PORirr, X86::MMX_PORirm, 0 }, 1419 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 }, 1420 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 }, 1421 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 }, 1422 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 }, 1423 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 }, 1424 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 }, 1425 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 }, 1426 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 }, 1427 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 }, 1428 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 }, 1429 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 }, 1430 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 }, 1431 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 }, 1432 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 }, 1433 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 }, 1434 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 }, 1435 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 }, 1436 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 }, 1437 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 }, 1438 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 }, 1439 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 }, 1440 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 }, 1441 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 }, 1442 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 }, 1443 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 }, 1444 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 }, 1445 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 }, 1446 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 }, 1447 1448 // 3DNow! version of foldable instructions 1449 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 }, 1450 { X86::PFACCrr, X86::PFACCrm, 0 }, 1451 { X86::PFADDrr, X86::PFADDrm, 0 }, 1452 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 }, 1453 { X86::PFCMPGErr, X86::PFCMPGErm, 0 }, 1454 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 }, 1455 { X86::PFMAXrr, X86::PFMAXrm, 0 }, 1456 { X86::PFMINrr, X86::PFMINrm, 0 }, 1457 { X86::PFMULrr, X86::PFMULrm, 0 }, 1458 { X86::PFNACCrr, X86::PFNACCrm, 0 }, 1459 { X86::PFPNACCrr, X86::PFPNACCrm, 0 }, 1460 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 }, 1461 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 }, 1462 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 }, 1463 { X86::PFSUBrr, X86::PFSUBrm, 0 }, 1464 { X86::PFSUBRrr, X86::PFSUBRrm, 0 }, 1465 { X86::PMULHRWrr, X86::PMULHRWrm, 0 }, 1466 1467 // AVX 128-bit versions of foldable instructions 1468 { X86::VCVTSI642SDrr, X86::VCVTSI642SDrm, 0 }, 1469 { X86::VCVTSI642SDrr_Int, X86::VCVTSI642SDrm_Int, 0 }, 1470 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 1471 { X86::VCVTSI2SDrr_Int, X86::VCVTSI2SDrm_Int, 0 }, 1472 { X86::VCVTSI642SSrr, X86::VCVTSI642SSrm, 0 }, 1473 { X86::VCVTSI642SSrr_Int, X86::VCVTSI642SSrm_Int, 0 }, 1474 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 1475 { X86::VCVTSI2SSrr_Int, X86::VCVTSI2SSrm_Int, 0 }, 1476 { X86::VADDPDrr, X86::VADDPDrm, 0 }, 1477 { X86::VADDPSrr, X86::VADDPSrm, 0 }, 1478 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 1479 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, TB_NO_REVERSE }, 1480 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 1481 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, TB_NO_REVERSE }, 1482 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 1483 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 1484 { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 1485 { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 1486 { X86::VANDPDrr, X86::VANDPDrm, 0 }, 1487 { X86::VANDPSrr, X86::VANDPSrm, 0 }, 1488 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 1489 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 1490 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 1491 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 1492 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 1493 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 1494 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 1495 { X86::VCMPSDrr_Int, X86::VCMPSDrm_Int, TB_NO_REVERSE }, 1496 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 1497 { X86::VCMPSSrr_Int, X86::VCMPSSrm_Int, TB_NO_REVERSE }, 1498 { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 1499 { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 1500 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 1501 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, TB_NO_REVERSE }, 1502 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 1503 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, TB_NO_REVERSE }, 1504 { X86::VDPPDrri, X86::VDPPDrmi, 0 }, 1505 { X86::VDPPSrri, X86::VDPPSrmi, 0 }, 1506 { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 1507 { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 1508 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 1509 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 1510 { X86::VMAXCPDrr, X86::VMAXCPDrm, 0 }, 1511 { X86::VMAXCPSrr, X86::VMAXCPSrm, 0 }, 1512 { X86::VMAXCSDrr, X86::VMAXCSDrm, 0 }, 1513 { X86::VMAXCSSrr, X86::VMAXCSSrm, 0 }, 1514 { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 1515 { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 1516 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 1517 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, TB_NO_REVERSE }, 1518 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 1519 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, TB_NO_REVERSE }, 1520 { X86::VMINCPDrr, X86::VMINCPDrm, 0 }, 1521 { X86::VMINCPSrr, X86::VMINCPSrm, 0 }, 1522 { X86::VMINCSDrr, X86::VMINCSDrm, 0 }, 1523 { X86::VMINCSSrr, X86::VMINCSSrm, 0 }, 1524 { X86::VMINPDrr, X86::VMINPDrm, 0 }, 1525 { X86::VMINPSrr, X86::VMINPSrm, 0 }, 1526 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 1527 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, TB_NO_REVERSE }, 1528 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 1529 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, TB_NO_REVERSE }, 1530 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE }, 1531 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 1532 { X86::VMULPDrr, X86::VMULPDrm, 0 }, 1533 { X86::VMULPSrr, X86::VMULPSrm, 0 }, 1534 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 1535 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, TB_NO_REVERSE }, 1536 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 1537 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, TB_NO_REVERSE }, 1538 { X86::VORPDrr, X86::VORPDrm, 0 }, 1539 { X86::VORPSrr, X86::VORPSrm, 0 }, 1540 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 1541 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 1542 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 1543 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 1544 { X86::VPADDBrr, X86::VPADDBrm, 0 }, 1545 { X86::VPADDDrr, X86::VPADDDrm, 0 }, 1546 { X86::VPADDQrr, X86::VPADDQrm, 0 }, 1547 { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 1548 { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 1549 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 1550 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 1551 { X86::VPADDWrr, X86::VPADDWrm, 0 }, 1552 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 }, 1553 { X86::VPANDNrr, X86::VPANDNrm, 0 }, 1554 { X86::VPANDrr, X86::VPANDrm, 0 }, 1555 { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 1556 { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 1557 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 }, 1558 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 1559 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 }, 1560 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 1561 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 1562 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 1563 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 1564 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 1565 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 1566 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 1567 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 1568 { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 1569 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 1570 { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 1571 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 1572 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 1573 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 1574 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 1575 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 1576 { X86::VPINSRBrr, X86::VPINSRBrm, 0 }, 1577 { X86::VPINSRDrr, X86::VPINSRDrm, 0 }, 1578 { X86::VPINSRQrr, X86::VPINSRQrm, 0 }, 1579 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 1580 { X86::VPMADDUBSWrr, X86::VPMADDUBSWrm, 0 }, 1581 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 1582 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 1583 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 1584 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 1585 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 1586 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 1587 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 1588 { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 1589 { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 1590 { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 1591 { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 1592 { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 1593 { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 1594 { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 1595 { X86::VPMULHRSWrr, X86::VPMULHRSWrm, 0 }, 1596 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 1597 { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 1598 { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 1599 { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 1600 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 1601 { X86::VPORrr, X86::VPORrm, 0 }, 1602 { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 1603 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 1604 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 }, 1605 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 }, 1606 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 }, 1607 { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 1608 { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 1609 { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 1610 { X86::VPSRADrr, X86::VPSRADrm, 0 }, 1611 { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 1612 { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 1613 { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 1614 { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 1615 { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 1616 { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 1617 { X86::VPSUBQrr, X86::VPSUBQrm, 0 }, 1618 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 1619 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 1620 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 }, 1621 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 }, 1622 { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 1623 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 1624 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 1625 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 1626 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 1627 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 1628 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 1629 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 1630 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 1631 { X86::VPXORrr, X86::VPXORrm, 0 }, 1632 { X86::VRCPSSr, X86::VRCPSSm, 0 }, 1633 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, TB_NO_REVERSE }, 1634 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 1635 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, TB_NO_REVERSE }, 1636 { X86::VROUNDSDr, X86::VROUNDSDm, 0 }, 1637 { X86::VROUNDSDr_Int, X86::VROUNDSDm_Int, TB_NO_REVERSE }, 1638 { X86::VROUNDSSr, X86::VROUNDSSm, 0 }, 1639 { X86::VROUNDSSr_Int, X86::VROUNDSSm_Int, TB_NO_REVERSE }, 1640 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 1641 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 1642 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 1643 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, TB_NO_REVERSE }, 1644 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 1645 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, TB_NO_REVERSE }, 1646 { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 1647 { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 1648 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 1649 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, TB_NO_REVERSE }, 1650 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 1651 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, TB_NO_REVERSE }, 1652 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 1653 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 1654 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 1655 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 1656 { X86::VXORPDrr, X86::VXORPDrm, 0 }, 1657 { X86::VXORPSrr, X86::VXORPSrm, 0 }, 1658 1659 // AVX 256-bit foldable instructions 1660 { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 1661 { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 1662 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 1663 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 1664 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 1665 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 1666 { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 1667 { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1668 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1669 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1670 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1671 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1672 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1673 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1674 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1675 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1676 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 }, 1677 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1678 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1679 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1680 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1681 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1682 { X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0 }, 1683 { X86::VMAXCPSYrr, X86::VMAXCPSYrm, 0 }, 1684 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1685 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1686 { X86::VMINCPDYrr, X86::VMINCPDYrm, 0 }, 1687 { X86::VMINCPSYrr, X86::VMINCPSYrm, 0 }, 1688 { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1689 { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1690 { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1691 { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1692 { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1693 { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1694 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1695 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1696 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1697 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1698 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1699 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1700 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1701 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1702 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1703 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1704 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1705 { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1706 { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1707 1708 // AVX2 foldable instructions 1709 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1710 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1711 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1712 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1713 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1714 { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1715 { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1716 { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1717 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1718 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1719 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1720 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1721 { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1722 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 }, 1723 { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1724 { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1725 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1726 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1727 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1728 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1729 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 }, 1730 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1731 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1732 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1733 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1734 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1735 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1736 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1737 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1738 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1739 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1740 { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1741 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1742 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1743 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1744 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1745 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1746 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1747 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1748 { X86::VPMADDUBSWYrr, X86::VPMADDUBSWYrm, 0 }, 1749 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1750 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1751 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1752 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1753 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1754 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1755 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1756 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1757 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1758 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1759 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1760 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1761 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1762 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1763 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1764 { X86::VPMULHRSWYrr, X86::VPMULHRSWYrm, 0 }, 1765 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1766 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1767 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1768 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1769 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1770 { X86::VPORYrr, X86::VPORYrm, 0 }, 1771 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1772 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1773 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 }, 1774 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 }, 1775 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 }, 1776 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1777 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1778 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1779 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1780 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1781 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1782 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1783 { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1784 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1785 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1786 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1787 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1788 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1789 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1790 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1791 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1792 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1793 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1794 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1795 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1796 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 }, 1797 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1798 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1799 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 }, 1800 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 }, 1801 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1802 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1803 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1804 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1805 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1806 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1807 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1808 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1809 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1810 { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1811 1812 // FMA4 foldable patterns 1813 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE }, 1814 { X86::VFMADDSS4rr_Int, X86::VFMADDSS4mr_Int, TB_NO_REVERSE }, 1815 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE }, 1816 { X86::VFMADDSD4rr_Int, X86::VFMADDSD4mr_Int, TB_NO_REVERSE }, 1817 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE }, 1818 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE }, 1819 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Ymr, TB_ALIGN_NONE }, 1820 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Ymr, TB_ALIGN_NONE }, 1821 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE }, 1822 { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4mr_Int, TB_NO_REVERSE }, 1823 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE }, 1824 { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4mr_Int, TB_NO_REVERSE }, 1825 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE }, 1826 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE }, 1827 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Ymr, TB_ALIGN_NONE }, 1828 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Ymr, TB_ALIGN_NONE }, 1829 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE }, 1830 { X86::VFMSUBSS4rr_Int, X86::VFMSUBSS4mr_Int, TB_NO_REVERSE }, 1831 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE }, 1832 { X86::VFMSUBSD4rr_Int, X86::VFMSUBSD4mr_Int, TB_NO_REVERSE }, 1833 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE }, 1834 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE }, 1835 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Ymr, TB_ALIGN_NONE }, 1836 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Ymr, TB_ALIGN_NONE }, 1837 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE }, 1838 { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4mr_Int, TB_NO_REVERSE }, 1839 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE }, 1840 { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4mr_Int, TB_NO_REVERSE }, 1841 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE }, 1842 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE }, 1843 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Ymr, TB_ALIGN_NONE }, 1844 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Ymr, TB_ALIGN_NONE }, 1845 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE }, 1846 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE }, 1847 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Ymr, TB_ALIGN_NONE }, 1848 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Ymr, TB_ALIGN_NONE }, 1849 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE }, 1850 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE }, 1851 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Ymr, TB_ALIGN_NONE }, 1852 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Ymr, TB_ALIGN_NONE }, 1853 1854 // XOP foldable instructions 1855 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 }, 1856 { X86::VPCMOVYrrr, X86::VPCMOVYrmr, 0 }, 1857 { X86::VPCOMBri, X86::VPCOMBmi, 0 }, 1858 { X86::VPCOMDri, X86::VPCOMDmi, 0 }, 1859 { X86::VPCOMQri, X86::VPCOMQmi, 0 }, 1860 { X86::VPCOMWri, X86::VPCOMWmi, 0 }, 1861 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 }, 1862 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 }, 1863 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 }, 1864 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 }, 1865 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 }, 1866 { X86::VPERMIL2PDYrr, X86::VPERMIL2PDYmr, 0 }, 1867 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 }, 1868 { X86::VPERMIL2PSYrr, X86::VPERMIL2PSYmr, 0 }, 1869 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 }, 1870 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 }, 1871 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 }, 1872 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 }, 1873 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 }, 1874 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 }, 1875 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 }, 1876 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 }, 1877 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 }, 1878 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 }, 1879 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 }, 1880 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 }, 1881 { X86::VPPERMrrr, X86::VPPERMrmr, 0 }, 1882 { X86::VPROTBrr, X86::VPROTBrm, 0 }, 1883 { X86::VPROTDrr, X86::VPROTDrm, 0 }, 1884 { X86::VPROTQrr, X86::VPROTQrm, 0 }, 1885 { X86::VPROTWrr, X86::VPROTWrm, 0 }, 1886 { X86::VPSHABrr, X86::VPSHABrm, 0 }, 1887 { X86::VPSHADrr, X86::VPSHADrm, 0 }, 1888 { X86::VPSHAQrr, X86::VPSHAQrm, 0 }, 1889 { X86::VPSHAWrr, X86::VPSHAWrm, 0 }, 1890 { X86::VPSHLBrr, X86::VPSHLBrm, 0 }, 1891 { X86::VPSHLDrr, X86::VPSHLDrm, 0 }, 1892 { X86::VPSHLQrr, X86::VPSHLQrm, 0 }, 1893 { X86::VPSHLWrr, X86::VPSHLWrm, 0 }, 1894 1895 // BMI/BMI2 foldable instructions 1896 { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1897 { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1898 { X86::MULX32rr, X86::MULX32rm, 0 }, 1899 { X86::MULX64rr, X86::MULX64rm, 0 }, 1900 { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1901 { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1902 { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1903 { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1904 1905 // ADX foldable instructions 1906 { X86::ADCX32rr, X86::ADCX32rm, 0 }, 1907 { X86::ADCX64rr, X86::ADCX64rm, 0 }, 1908 { X86::ADOX32rr, X86::ADOX32rm, 0 }, 1909 { X86::ADOX64rr, X86::ADOX64rm, 0 }, 1910 1911 // AVX-512 foldable instructions 1912 { X86::VADDPDZrr, X86::VADDPDZrm, 0 }, 1913 { X86::VADDPSZrr, X86::VADDPSZrm, 0 }, 1914 { X86::VADDSDZrr, X86::VADDSDZrm, 0 }, 1915 { X86::VADDSDZrr_Int, X86::VADDSDZrm_Int, TB_NO_REVERSE }, 1916 { X86::VADDSSZrr, X86::VADDSSZrm, 0 }, 1917 { X86::VADDSSZrr_Int, X86::VADDSSZrm_Int, TB_NO_REVERSE }, 1918 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 }, 1919 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 }, 1920 { X86::VANDNPDZrr, X86::VANDNPDZrm, 0 }, 1921 { X86::VANDNPSZrr, X86::VANDNPSZrm, 0 }, 1922 { X86::VANDPDZrr, X86::VANDPDZrm, 0 }, 1923 { X86::VANDPSZrr, X86::VANDPSZrm, 0 }, 1924 { X86::VCMPPDZrri, X86::VCMPPDZrmi, 0 }, 1925 { X86::VCMPPSZrri, X86::VCMPPSZrmi, 0 }, 1926 { X86::VCMPSDZrr, X86::VCMPSDZrm, 0 }, 1927 { X86::VCMPSDZrr_Int, X86::VCMPSDZrm_Int, TB_NO_REVERSE }, 1928 { X86::VCMPSSZrr, X86::VCMPSSZrm, 0 }, 1929 { X86::VCMPSSZrr_Int, X86::VCMPSSZrm_Int, TB_NO_REVERSE }, 1930 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 }, 1931 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 }, 1932 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 }, 1933 { X86::VDIVSDZrr_Int, X86::VDIVSDZrm_Int, TB_NO_REVERSE }, 1934 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 }, 1935 { X86::VDIVSSZrr_Int, X86::VDIVSSZrm_Int, TB_NO_REVERSE }, 1936 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrm, 0 }, 1937 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrm, 0 }, 1938 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrm, 0 }, 1939 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrm, 0 }, 1940 { X86::VINSERTI32x4Zrr, X86::VINSERTI32x4Zrm, 0 }, 1941 { X86::VINSERTI32x8Zrr, X86::VINSERTI32x8Zrm, 0 }, 1942 { X86::VINSERTI64x2Zrr, X86::VINSERTI64x2Zrm, 0 }, 1943 { X86::VINSERTI64x4Zrr, X86::VINSERTI64x4Zrm, 0 }, 1944 { X86::VMAXCPDZrr, X86::VMAXCPDZrm, 0 }, 1945 { X86::VMAXCPSZrr, X86::VMAXCPSZrm, 0 }, 1946 { X86::VMAXCSDZrr, X86::VMAXCSDZrm, 0 }, 1947 { X86::VMAXCSSZrr, X86::VMAXCSSZrm, 0 }, 1948 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 }, 1949 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 }, 1950 { X86::VMAXSDZrr, X86::VMAXSDZrm, 0 }, 1951 { X86::VMAXSDZrr_Int, X86::VMAXSDZrm_Int, TB_NO_REVERSE }, 1952 { X86::VMAXSSZrr, X86::VMAXSSZrm, 0 }, 1953 { X86::VMAXSSZrr_Int, X86::VMAXSSZrm_Int, TB_NO_REVERSE }, 1954 { X86::VMINCPDZrr, X86::VMINCPDZrm, 0 }, 1955 { X86::VMINCPSZrr, X86::VMINCPSZrm, 0 }, 1956 { X86::VMINCSDZrr, X86::VMINCSDZrm, 0 }, 1957 { X86::VMINCSSZrr, X86::VMINCSSZrm, 0 }, 1958 { X86::VMINPDZrr, X86::VMINPDZrm, 0 }, 1959 { X86::VMINPSZrr, X86::VMINPSZrm, 0 }, 1960 { X86::VMINSDZrr, X86::VMINSDZrm, 0 }, 1961 { X86::VMINSDZrr_Int, X86::VMINSDZrm_Int, TB_NO_REVERSE }, 1962 { X86::VMINSSZrr, X86::VMINSSZrm, 0 }, 1963 { X86::VMINSSZrr_Int, X86::VMINSSZrm_Int, TB_NO_REVERSE }, 1964 { X86::VMOVLHPSZrr, X86::VMOVHPSZ128rm, TB_NO_REVERSE }, 1965 { X86::VMULPDZrr, X86::VMULPDZrm, 0 }, 1966 { X86::VMULPSZrr, X86::VMULPSZrm, 0 }, 1967 { X86::VMULSDZrr, X86::VMULSDZrm, 0 }, 1968 { X86::VMULSDZrr_Int, X86::VMULSDZrm_Int, TB_NO_REVERSE }, 1969 { X86::VMULSSZrr, X86::VMULSSZrm, 0 }, 1970 { X86::VMULSSZrr_Int, X86::VMULSSZrm_Int, TB_NO_REVERSE }, 1971 { X86::VORPDZrr, X86::VORPDZrm, 0 }, 1972 { X86::VORPSZrr, X86::VORPSZrm, 0 }, 1973 { X86::VPACKSSDWZrr, X86::VPACKSSDWZrm, 0 }, 1974 { X86::VPACKSSWBZrr, X86::VPACKSSWBZrm, 0 }, 1975 { X86::VPACKUSDWZrr, X86::VPACKUSDWZrm, 0 }, 1976 { X86::VPACKUSWBZrr, X86::VPACKUSWBZrm, 0 }, 1977 { X86::VPADDBZrr, X86::VPADDBZrm, 0 }, 1978 { X86::VPADDDZrr, X86::VPADDDZrm, 0 }, 1979 { X86::VPADDQZrr, X86::VPADDQZrm, 0 }, 1980 { X86::VPADDSBZrr, X86::VPADDSBZrm, 0 }, 1981 { X86::VPADDSWZrr, X86::VPADDSWZrm, 0 }, 1982 { X86::VPADDUSBZrr, X86::VPADDUSBZrm, 0 }, 1983 { X86::VPADDUSWZrr, X86::VPADDUSWZrm, 0 }, 1984 { X86::VPADDWZrr, X86::VPADDWZrm, 0 }, 1985 { X86::VPALIGNRZrri, X86::VPALIGNRZrmi, 0 }, 1986 { X86::VPANDDZrr, X86::VPANDDZrm, 0 }, 1987 { X86::VPANDNDZrr, X86::VPANDNDZrm, 0 }, 1988 { X86::VPANDNQZrr, X86::VPANDNQZrm, 0 }, 1989 { X86::VPANDQZrr, X86::VPANDQZrm, 0 }, 1990 { X86::VPAVGBZrr, X86::VPAVGBZrm, 0 }, 1991 { X86::VPAVGWZrr, X86::VPAVGWZrm, 0 }, 1992 { X86::VPCMPBZrri, X86::VPCMPBZrmi, 0 }, 1993 { X86::VPCMPDZrri, X86::VPCMPDZrmi, 0 }, 1994 { X86::VPCMPEQBZrr, X86::VPCMPEQBZrm, 0 }, 1995 { X86::VPCMPEQDZrr, X86::VPCMPEQDZrm, 0 }, 1996 { X86::VPCMPEQQZrr, X86::VPCMPEQQZrm, 0 }, 1997 { X86::VPCMPEQWZrr, X86::VPCMPEQWZrm, 0 }, 1998 { X86::VPCMPGTBZrr, X86::VPCMPGTBZrm, 0 }, 1999 { X86::VPCMPGTDZrr, X86::VPCMPGTDZrm, 0 }, 2000 { X86::VPCMPGTQZrr, X86::VPCMPGTQZrm, 0 }, 2001 { X86::VPCMPGTWZrr, X86::VPCMPGTWZrm, 0 }, 2002 { X86::VPCMPQZrri, X86::VPCMPQZrmi, 0 }, 2003 { X86::VPCMPUBZrri, X86::VPCMPUBZrmi, 0 }, 2004 { X86::VPCMPUDZrri, X86::VPCMPUDZrmi, 0 }, 2005 { X86::VPCMPUQZrri, X86::VPCMPUQZrmi, 0 }, 2006 { X86::VPCMPUWZrri, X86::VPCMPUWZrmi, 0 }, 2007 { X86::VPCMPWZrri, X86::VPCMPWZrmi, 0 }, 2008 { X86::VPERMBZrr, X86::VPERMBZrm, 0 }, 2009 { X86::VPERMDZrr, X86::VPERMDZrm, 0 }, 2010 { X86::VPERMILPDZrr, X86::VPERMILPDZrm, 0 }, 2011 { X86::VPERMILPSZrr, X86::VPERMILPSZrm, 0 }, 2012 { X86::VPERMPDZrr, X86::VPERMPDZrm, 0 }, 2013 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 }, 2014 { X86::VPERMQZrr, X86::VPERMQZrm, 0 }, 2015 { X86::VPERMWZrr, X86::VPERMWZrm, 0 }, 2016 { X86::VPINSRBZrr, X86::VPINSRBZrm, 0 }, 2017 { X86::VPINSRDZrr, X86::VPINSRDZrm, 0 }, 2018 { X86::VPINSRQZrr, X86::VPINSRQZrm, 0 }, 2019 { X86::VPINSRWZrr, X86::VPINSRWZrm, 0 }, 2020 { X86::VPMADDUBSWZrr, X86::VPMADDUBSWZrm, 0 }, 2021 { X86::VPMADDWDZrr, X86::VPMADDWDZrm, 0 }, 2022 { X86::VPMAXSBZrr, X86::VPMAXSBZrm, 0 }, 2023 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 }, 2024 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 }, 2025 { X86::VPMAXSWZrr, X86::VPMAXSWZrm, 0 }, 2026 { X86::VPMAXUBZrr, X86::VPMAXUBZrm, 0 }, 2027 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 }, 2028 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 }, 2029 { X86::VPMAXUWZrr, X86::VPMAXUWZrm, 0 }, 2030 { X86::VPMINSBZrr, X86::VPMINSBZrm, 0 }, 2031 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 }, 2032 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 }, 2033 { X86::VPMINSWZrr, X86::VPMINSWZrm, 0 }, 2034 { X86::VPMINUBZrr, X86::VPMINUBZrm, 0 }, 2035 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 }, 2036 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 }, 2037 { X86::VPMINUWZrr, X86::VPMINUWZrm, 0 }, 2038 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 }, 2039 { X86::VPMULLDZrr, X86::VPMULLDZrm, 0 }, 2040 { X86::VPMULLQZrr, X86::VPMULLQZrm, 0 }, 2041 { X86::VPMULLWZrr, X86::VPMULLWZrm, 0 }, 2042 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 }, 2043 { X86::VPORDZrr, X86::VPORDZrm, 0 }, 2044 { X86::VPORQZrr, X86::VPORQZrm, 0 }, 2045 { X86::VPSADBWZrr, X86::VPSADBWZrm, 0 }, 2046 { X86::VPSHUFBZrr, X86::VPSHUFBZrm, 0 }, 2047 { X86::VPSLLDZrr, X86::VPSLLDZrm, 0 }, 2048 { X86::VPSLLQZrr, X86::VPSLLQZrm, 0 }, 2049 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 }, 2050 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 }, 2051 { X86::VPSLLVWZrr, X86::VPSLLVWZrm, 0 }, 2052 { X86::VPSLLWZrr, X86::VPSLLWZrm, 0 }, 2053 { X86::VPSRADZrr, X86::VPSRADZrm, 0 }, 2054 { X86::VPSRAQZrr, X86::VPSRAQZrm, 0 }, 2055 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 }, 2056 { X86::VPSRAVQZrr, X86::VPSRAVQZrm, 0 }, 2057 { X86::VPSRAVWZrr, X86::VPSRAVWZrm, 0 }, 2058 { X86::VPSRAWZrr, X86::VPSRAWZrm, 0 }, 2059 { X86::VPSRLDZrr, X86::VPSRLDZrm, 0 }, 2060 { X86::VPSRLQZrr, X86::VPSRLQZrm, 0 }, 2061 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 }, 2062 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 }, 2063 { X86::VPSRLVWZrr, X86::VPSRLVWZrm, 0 }, 2064 { X86::VPSRLWZrr, X86::VPSRLWZrm, 0 }, 2065 { X86::VPSUBBZrr, X86::VPSUBBZrm, 0 }, 2066 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 }, 2067 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 }, 2068 { X86::VPSUBSBZrr, X86::VPSUBSBZrm, 0 }, 2069 { X86::VPSUBSWZrr, X86::VPSUBSWZrm, 0 }, 2070 { X86::VPSUBUSBZrr, X86::VPSUBUSBZrm, 0 }, 2071 { X86::VPSUBUSWZrr, X86::VPSUBUSWZrm, 0 }, 2072 { X86::VPSUBWZrr, X86::VPSUBWZrm, 0 }, 2073 { X86::VPUNPCKHBWZrr, X86::VPUNPCKHBWZrm, 0 }, 2074 { X86::VPUNPCKHDQZrr, X86::VPUNPCKHDQZrm, 0 }, 2075 { X86::VPUNPCKHQDQZrr, X86::VPUNPCKHQDQZrm, 0 }, 2076 { X86::VPUNPCKHWDZrr, X86::VPUNPCKHWDZrm, 0 }, 2077 { X86::VPUNPCKLBWZrr, X86::VPUNPCKLBWZrm, 0 }, 2078 { X86::VPUNPCKLDQZrr, X86::VPUNPCKLDQZrm, 0 }, 2079 { X86::VPUNPCKLQDQZrr, X86::VPUNPCKLQDQZrm, 0 }, 2080 { X86::VPUNPCKLWDZrr, X86::VPUNPCKLWDZrm, 0 }, 2081 { X86::VPXORDZrr, X86::VPXORDZrm, 0 }, 2082 { X86::VPXORQZrr, X86::VPXORQZrm, 0 }, 2083 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 }, 2084 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 }, 2085 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 }, 2086 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 }, 2087 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 }, 2088 { X86::VSUBSDZrr_Int, X86::VSUBSDZrm_Int, TB_NO_REVERSE }, 2089 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 }, 2090 { X86::VSUBSSZrr_Int, X86::VSUBSSZrm_Int, TB_NO_REVERSE }, 2091 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrm, 0 }, 2092 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrm, 0 }, 2093 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrm, 0 }, 2094 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrm, 0 }, 2095 { X86::VXORPDZrr, X86::VXORPDZrm, 0 }, 2096 { X86::VXORPSZrr, X86::VXORPSZrm, 0 }, 2097 2098 // AVX-512{F,VL} foldable instructions 2099 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 }, 2100 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 }, 2101 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 }, 2102 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 }, 2103 { X86::VALIGNDZ128rri, X86::VALIGNDZ128rmi, 0 }, 2104 { X86::VALIGNDZ256rri, X86::VALIGNDZ256rmi, 0 }, 2105 { X86::VALIGNQZ128rri, X86::VALIGNQZ128rmi, 0 }, 2106 { X86::VALIGNQZ256rri, X86::VALIGNQZ256rmi, 0 }, 2107 { X86::VANDNPDZ128rr, X86::VANDNPDZ128rm, 0 }, 2108 { X86::VANDNPDZ256rr, X86::VANDNPDZ256rm, 0 }, 2109 { X86::VANDNPSZ128rr, X86::VANDNPSZ128rm, 0 }, 2110 { X86::VANDNPSZ256rr, X86::VANDNPSZ256rm, 0 }, 2111 { X86::VANDPDZ128rr, X86::VANDPDZ128rm, 0 }, 2112 { X86::VANDPDZ256rr, X86::VANDPDZ256rm, 0 }, 2113 { X86::VANDPSZ128rr, X86::VANDPSZ128rm, 0 }, 2114 { X86::VANDPSZ256rr, X86::VANDPSZ256rm, 0 }, 2115 { X86::VCMPPDZ128rri, X86::VCMPPDZ128rmi, 0 }, 2116 { X86::VCMPPDZ256rri, X86::VCMPPDZ256rmi, 0 }, 2117 { X86::VCMPPSZ128rri, X86::VCMPPSZ128rmi, 0 }, 2118 { X86::VCMPPSZ256rri, X86::VCMPPSZ256rmi, 0 }, 2119 { X86::VDIVPDZ128rr, X86::VDIVPDZ128rm, 0 }, 2120 { X86::VDIVPDZ256rr, X86::VDIVPDZ256rm, 0 }, 2121 { X86::VDIVPSZ128rr, X86::VDIVPSZ128rm, 0 }, 2122 { X86::VDIVPSZ256rr, X86::VDIVPSZ256rm, 0 }, 2123 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm, 0 }, 2124 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm, 0 }, 2125 { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm, 0 }, 2126 { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm, 0 }, 2127 { X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0 }, 2128 { X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0 }, 2129 { X86::VMAXCPSZ128rr, X86::VMAXCPSZ128rm, 0 }, 2130 { X86::VMAXCPSZ256rr, X86::VMAXCPSZ256rm, 0 }, 2131 { X86::VMAXPDZ128rr, X86::VMAXPDZ128rm, 0 }, 2132 { X86::VMAXPDZ256rr, X86::VMAXPDZ256rm, 0 }, 2133 { X86::VMAXPSZ128rr, X86::VMAXPSZ128rm, 0 }, 2134 { X86::VMAXPSZ256rr, X86::VMAXPSZ256rm, 0 }, 2135 { X86::VMINCPDZ128rr, X86::VMINCPDZ128rm, 0 }, 2136 { X86::VMINCPDZ256rr, X86::VMINCPDZ256rm, 0 }, 2137 { X86::VMINCPSZ128rr, X86::VMINCPSZ128rm, 0 }, 2138 { X86::VMINCPSZ256rr, X86::VMINCPSZ256rm, 0 }, 2139 { X86::VMINPDZ128rr, X86::VMINPDZ128rm, 0 }, 2140 { X86::VMINPDZ256rr, X86::VMINPDZ256rm, 0 }, 2141 { X86::VMINPSZ128rr, X86::VMINPSZ128rm, 0 }, 2142 { X86::VMINPSZ256rr, X86::VMINPSZ256rm, 0 }, 2143 { X86::VMULPDZ128rr, X86::VMULPDZ128rm, 0 }, 2144 { X86::VMULPDZ256rr, X86::VMULPDZ256rm, 0 }, 2145 { X86::VMULPSZ128rr, X86::VMULPSZ128rm, 0 }, 2146 { X86::VMULPSZ256rr, X86::VMULPSZ256rm, 0 }, 2147 { X86::VORPDZ128rr, X86::VORPDZ128rm, 0 }, 2148 { X86::VORPDZ256rr, X86::VORPDZ256rm, 0 }, 2149 { X86::VORPSZ128rr, X86::VORPSZ128rm, 0 }, 2150 { X86::VORPSZ256rr, X86::VORPSZ256rm, 0 }, 2151 { X86::VPACKSSDWZ256rr, X86::VPACKSSDWZ256rm, 0 }, 2152 { X86::VPACKSSDWZ128rr, X86::VPACKSSDWZ128rm, 0 }, 2153 { X86::VPACKSSWBZ256rr, X86::VPACKSSWBZ256rm, 0 }, 2154 { X86::VPACKSSWBZ128rr, X86::VPACKSSWBZ128rm, 0 }, 2155 { X86::VPACKUSDWZ256rr, X86::VPACKUSDWZ256rm, 0 }, 2156 { X86::VPACKUSDWZ128rr, X86::VPACKUSDWZ128rm, 0 }, 2157 { X86::VPACKUSWBZ256rr, X86::VPACKUSWBZ256rm, 0 }, 2158 { X86::VPACKUSWBZ128rr, X86::VPACKUSWBZ128rm, 0 }, 2159 { X86::VPADDBZ128rr, X86::VPADDBZ128rm, 0 }, 2160 { X86::VPADDBZ256rr, X86::VPADDBZ256rm, 0 }, 2161 { X86::VPADDDZ128rr, X86::VPADDDZ128rm, 0 }, 2162 { X86::VPADDDZ256rr, X86::VPADDDZ256rm, 0 }, 2163 { X86::VPADDQZ128rr, X86::VPADDQZ128rm, 0 }, 2164 { X86::VPADDQZ256rr, X86::VPADDQZ256rm, 0 }, 2165 { X86::VPADDSBZ128rr, X86::VPADDSBZ128rm, 0 }, 2166 { X86::VPADDSBZ256rr, X86::VPADDSBZ256rm, 0 }, 2167 { X86::VPADDSWZ128rr, X86::VPADDSWZ128rm, 0 }, 2168 { X86::VPADDSWZ256rr, X86::VPADDSWZ256rm, 0 }, 2169 { X86::VPADDUSBZ128rr, X86::VPADDUSBZ128rm, 0 }, 2170 { X86::VPADDUSBZ256rr, X86::VPADDUSBZ256rm, 0 }, 2171 { X86::VPADDUSWZ128rr, X86::VPADDUSWZ128rm, 0 }, 2172 { X86::VPADDUSWZ256rr, X86::VPADDUSWZ256rm, 0 }, 2173 { X86::VPADDWZ128rr, X86::VPADDWZ128rm, 0 }, 2174 { X86::VPADDWZ256rr, X86::VPADDWZ256rm, 0 }, 2175 { X86::VPALIGNRZ128rri, X86::VPALIGNRZ128rmi, 0 }, 2176 { X86::VPALIGNRZ256rri, X86::VPALIGNRZ256rmi, 0 }, 2177 { X86::VPANDDZ128rr, X86::VPANDDZ128rm, 0 }, 2178 { X86::VPANDDZ256rr, X86::VPANDDZ256rm, 0 }, 2179 { X86::VPANDNDZ128rr, X86::VPANDNDZ128rm, 0 }, 2180 { X86::VPANDNDZ256rr, X86::VPANDNDZ256rm, 0 }, 2181 { X86::VPANDNQZ128rr, X86::VPANDNQZ128rm, 0 }, 2182 { X86::VPANDNQZ256rr, X86::VPANDNQZ256rm, 0 }, 2183 { X86::VPANDQZ128rr, X86::VPANDQZ128rm, 0 }, 2184 { X86::VPANDQZ256rr, X86::VPANDQZ256rm, 0 }, 2185 { X86::VPAVGBZ128rr, X86::VPAVGBZ128rm, 0 }, 2186 { X86::VPAVGBZ256rr, X86::VPAVGBZ256rm, 0 }, 2187 { X86::VPAVGWZ128rr, X86::VPAVGWZ128rm, 0 }, 2188 { X86::VPAVGWZ256rr, X86::VPAVGWZ256rm, 0 }, 2189 { X86::VPCMPBZ128rri, X86::VPCMPBZ128rmi, 0 }, 2190 { X86::VPCMPBZ256rri, X86::VPCMPBZ256rmi, 0 }, 2191 { X86::VPCMPDZ128rri, X86::VPCMPDZ128rmi, 0 }, 2192 { X86::VPCMPDZ256rri, X86::VPCMPDZ256rmi, 0 }, 2193 { X86::VPCMPEQBZ128rr, X86::VPCMPEQBZ128rm, 0 }, 2194 { X86::VPCMPEQBZ256rr, X86::VPCMPEQBZ256rm, 0 }, 2195 { X86::VPCMPEQDZ128rr, X86::VPCMPEQDZ128rm, 0 }, 2196 { X86::VPCMPEQDZ256rr, X86::VPCMPEQDZ256rm, 0 }, 2197 { X86::VPCMPEQQZ128rr, X86::VPCMPEQQZ128rm, 0 }, 2198 { X86::VPCMPEQQZ256rr, X86::VPCMPEQQZ256rm, 0 }, 2199 { X86::VPCMPEQWZ128rr, X86::VPCMPEQWZ128rm, 0 }, 2200 { X86::VPCMPEQWZ256rr, X86::VPCMPEQWZ256rm, 0 }, 2201 { X86::VPCMPGTBZ128rr, X86::VPCMPGTBZ128rm, 0 }, 2202 { X86::VPCMPGTBZ256rr, X86::VPCMPGTBZ256rm, 0 }, 2203 { X86::VPCMPGTDZ128rr, X86::VPCMPGTDZ128rm, 0 }, 2204 { X86::VPCMPGTDZ256rr, X86::VPCMPGTDZ256rm, 0 }, 2205 { X86::VPCMPGTQZ128rr, X86::VPCMPGTQZ128rm, 0 }, 2206 { X86::VPCMPGTQZ256rr, X86::VPCMPGTQZ256rm, 0 }, 2207 { X86::VPCMPGTWZ128rr, X86::VPCMPGTWZ128rm, 0 }, 2208 { X86::VPCMPGTWZ256rr, X86::VPCMPGTWZ256rm, 0 }, 2209 { X86::VPCMPQZ128rri, X86::VPCMPQZ128rmi, 0 }, 2210 { X86::VPCMPQZ256rri, X86::VPCMPQZ256rmi, 0 }, 2211 { X86::VPCMPUBZ128rri, X86::VPCMPUBZ128rmi, 0 }, 2212 { X86::VPCMPUBZ256rri, X86::VPCMPUBZ256rmi, 0 }, 2213 { X86::VPCMPUDZ128rri, X86::VPCMPUDZ128rmi, 0 }, 2214 { X86::VPCMPUDZ256rri, X86::VPCMPUDZ256rmi, 0 }, 2215 { X86::VPCMPUQZ128rri, X86::VPCMPUQZ128rmi, 0 }, 2216 { X86::VPCMPUQZ256rri, X86::VPCMPUQZ256rmi, 0 }, 2217 { X86::VPCMPUWZ128rri, X86::VPCMPUWZ128rmi, 0 }, 2218 { X86::VPCMPUWZ256rri, X86::VPCMPUWZ256rmi, 0 }, 2219 { X86::VPCMPWZ128rri, X86::VPCMPWZ128rmi, 0 }, 2220 { X86::VPCMPWZ256rri, X86::VPCMPWZ256rmi, 0 }, 2221 { X86::VPERMBZ128rr, X86::VPERMBZ128rm, 0 }, 2222 { X86::VPERMBZ256rr, X86::VPERMBZ256rm, 0 }, 2223 { X86::VPERMDZ256rr, X86::VPERMDZ256rm, 0 }, 2224 { X86::VPERMILPDZ128rr, X86::VPERMILPDZ128rm, 0 }, 2225 { X86::VPERMILPDZ256rr, X86::VPERMILPDZ256rm, 0 }, 2226 { X86::VPERMILPSZ128rr, X86::VPERMILPSZ128rm, 0 }, 2227 { X86::VPERMILPSZ256rr, X86::VPERMILPSZ256rm, 0 }, 2228 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rm, 0 }, 2229 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rm, 0 }, 2230 { X86::VPERMQZ256rr, X86::VPERMQZ256rm, 0 }, 2231 { X86::VPERMWZ128rr, X86::VPERMWZ128rm, 0 }, 2232 { X86::VPERMWZ256rr, X86::VPERMWZ256rm, 0 }, 2233 { X86::VPMADDUBSWZ128rr, X86::VPMADDUBSWZ128rm, 0 }, 2234 { X86::VPMADDUBSWZ256rr, X86::VPMADDUBSWZ256rm, 0 }, 2235 { X86::VPMADDWDZ128rr, X86::VPMADDWDZ128rm, 0 }, 2236 { X86::VPMADDWDZ256rr, X86::VPMADDWDZ256rm, 0 }, 2237 { X86::VPMAXSBZ128rr, X86::VPMAXSBZ128rm, 0 }, 2238 { X86::VPMAXSBZ256rr, X86::VPMAXSBZ256rm, 0 }, 2239 { X86::VPMAXSDZ128rr, X86::VPMAXSDZ128rm, 0 }, 2240 { X86::VPMAXSDZ256rr, X86::VPMAXSDZ256rm, 0 }, 2241 { X86::VPMAXSQZ128rr, X86::VPMAXSQZ128rm, 0 }, 2242 { X86::VPMAXSQZ256rr, X86::VPMAXSQZ256rm, 0 }, 2243 { X86::VPMAXSWZ128rr, X86::VPMAXSWZ128rm, 0 }, 2244 { X86::VPMAXSWZ256rr, X86::VPMAXSWZ256rm, 0 }, 2245 { X86::VPMAXUBZ128rr, X86::VPMAXUBZ128rm, 0 }, 2246 { X86::VPMAXUBZ256rr, X86::VPMAXUBZ256rm, 0 }, 2247 { X86::VPMAXUDZ128rr, X86::VPMAXUDZ128rm, 0 }, 2248 { X86::VPMAXUDZ256rr, X86::VPMAXUDZ256rm, 0 }, 2249 { X86::VPMAXUQZ128rr, X86::VPMAXUQZ128rm, 0 }, 2250 { X86::VPMAXUQZ256rr, X86::VPMAXUQZ256rm, 0 }, 2251 { X86::VPMAXUWZ128rr, X86::VPMAXUWZ128rm, 0 }, 2252 { X86::VPMAXUWZ256rr, X86::VPMAXUWZ256rm, 0 }, 2253 { X86::VPMINSBZ128rr, X86::VPMINSBZ128rm, 0 }, 2254 { X86::VPMINSBZ256rr, X86::VPMINSBZ256rm, 0 }, 2255 { X86::VPMINSDZ128rr, X86::VPMINSDZ128rm, 0 }, 2256 { X86::VPMINSDZ256rr, X86::VPMINSDZ256rm, 0 }, 2257 { X86::VPMINSQZ128rr, X86::VPMINSQZ128rm, 0 }, 2258 { X86::VPMINSQZ256rr, X86::VPMINSQZ256rm, 0 }, 2259 { X86::VPMINSWZ128rr, X86::VPMINSWZ128rm, 0 }, 2260 { X86::VPMINSWZ256rr, X86::VPMINSWZ256rm, 0 }, 2261 { X86::VPMINUBZ128rr, X86::VPMINUBZ128rm, 0 }, 2262 { X86::VPMINUBZ256rr, X86::VPMINUBZ256rm, 0 }, 2263 { X86::VPMINUDZ128rr, X86::VPMINUDZ128rm, 0 }, 2264 { X86::VPMINUDZ256rr, X86::VPMINUDZ256rm, 0 }, 2265 { X86::VPMINUQZ128rr, X86::VPMINUQZ128rm, 0 }, 2266 { X86::VPMINUQZ256rr, X86::VPMINUQZ256rm, 0 }, 2267 { X86::VPMINUWZ128rr, X86::VPMINUWZ128rm, 0 }, 2268 { X86::VPMINUWZ256rr, X86::VPMINUWZ256rm, 0 }, 2269 { X86::VPMULDQZ128rr, X86::VPMULDQZ128rm, 0 }, 2270 { X86::VPMULDQZ256rr, X86::VPMULDQZ256rm, 0 }, 2271 { X86::VPMULLDZ128rr, X86::VPMULLDZ128rm, 0 }, 2272 { X86::VPMULLDZ256rr, X86::VPMULLDZ256rm, 0 }, 2273 { X86::VPMULLQZ128rr, X86::VPMULLQZ128rm, 0 }, 2274 { X86::VPMULLQZ256rr, X86::VPMULLQZ256rm, 0 }, 2275 { X86::VPMULLWZ128rr, X86::VPMULLWZ128rm, 0 }, 2276 { X86::VPMULLWZ256rr, X86::VPMULLWZ256rm, 0 }, 2277 { X86::VPMULUDQZ128rr, X86::VPMULUDQZ128rm, 0 }, 2278 { X86::VPMULUDQZ256rr, X86::VPMULUDQZ256rm, 0 }, 2279 { X86::VPORDZ128rr, X86::VPORDZ128rm, 0 }, 2280 { X86::VPORDZ256rr, X86::VPORDZ256rm, 0 }, 2281 { X86::VPORQZ128rr, X86::VPORQZ128rm, 0 }, 2282 { X86::VPORQZ256rr, X86::VPORQZ256rm, 0 }, 2283 { X86::VPSADBWZ128rr, X86::VPSADBWZ128rm, 0 }, 2284 { X86::VPSADBWZ256rr, X86::VPSADBWZ256rm, 0 }, 2285 { X86::VPSHUFBZ128rr, X86::VPSHUFBZ128rm, 0 }, 2286 { X86::VPSHUFBZ256rr, X86::VPSHUFBZ256rm, 0 }, 2287 { X86::VPSLLDZ128rr, X86::VPSLLDZ128rm, 0 }, 2288 { X86::VPSLLDZ256rr, X86::VPSLLDZ256rm, 0 }, 2289 { X86::VPSLLQZ128rr, X86::VPSLLQZ128rm, 0 }, 2290 { X86::VPSLLQZ256rr, X86::VPSLLQZ256rm, 0 }, 2291 { X86::VPSLLVDZ128rr, X86::VPSLLVDZ128rm, 0 }, 2292 { X86::VPSLLVDZ256rr, X86::VPSLLVDZ256rm, 0 }, 2293 { X86::VPSLLVQZ128rr, X86::VPSLLVQZ128rm, 0 }, 2294 { X86::VPSLLVQZ256rr, X86::VPSLLVQZ256rm, 0 }, 2295 { X86::VPSLLVWZ128rr, X86::VPSLLVWZ128rm, 0 }, 2296 { X86::VPSLLVWZ256rr, X86::VPSLLVWZ256rm, 0 }, 2297 { X86::VPSLLWZ128rr, X86::VPSLLWZ128rm, 0 }, 2298 { X86::VPSLLWZ256rr, X86::VPSLLWZ256rm, 0 }, 2299 { X86::VPSRADZ128rr, X86::VPSRADZ128rm, 0 }, 2300 { X86::VPSRADZ256rr, X86::VPSRADZ256rm, 0 }, 2301 { X86::VPSRAQZ128rr, X86::VPSRAQZ128rm, 0 }, 2302 { X86::VPSRAQZ256rr, X86::VPSRAQZ256rm, 0 }, 2303 { X86::VPSRAVDZ128rr, X86::VPSRAVDZ128rm, 0 }, 2304 { X86::VPSRAVDZ256rr, X86::VPSRAVDZ256rm, 0 }, 2305 { X86::VPSRAVQZ128rr, X86::VPSRAVQZ128rm, 0 }, 2306 { X86::VPSRAVQZ256rr, X86::VPSRAVQZ256rm, 0 }, 2307 { X86::VPSRAVWZ128rr, X86::VPSRAVWZ128rm, 0 }, 2308 { X86::VPSRAVWZ256rr, X86::VPSRAVWZ256rm, 0 }, 2309 { X86::VPSRAWZ128rr, X86::VPSRAWZ128rm, 0 }, 2310 { X86::VPSRAWZ256rr, X86::VPSRAWZ256rm, 0 }, 2311 { X86::VPSRLDZ128rr, X86::VPSRLDZ128rm, 0 }, 2312 { X86::VPSRLDZ256rr, X86::VPSRLDZ256rm, 0 }, 2313 { X86::VPSRLQZ128rr, X86::VPSRLQZ128rm, 0 }, 2314 { X86::VPSRLQZ256rr, X86::VPSRLQZ256rm, 0 }, 2315 { X86::VPSRLVDZ128rr, X86::VPSRLVDZ128rm, 0 }, 2316 { X86::VPSRLVDZ256rr, X86::VPSRLVDZ256rm, 0 }, 2317 { X86::VPSRLVQZ128rr, X86::VPSRLVQZ128rm, 0 }, 2318 { X86::VPSRLVQZ256rr, X86::VPSRLVQZ256rm, 0 }, 2319 { X86::VPSRLVWZ128rr, X86::VPSRLVWZ128rm, 0 }, 2320 { X86::VPSRLVWZ256rr, X86::VPSRLVWZ256rm, 0 }, 2321 { X86::VPSRLWZ128rr, X86::VPSRLWZ128rm, 0 }, 2322 { X86::VPSRLWZ256rr, X86::VPSRLWZ256rm, 0 }, 2323 { X86::VPSUBBZ128rr, X86::VPSUBBZ128rm, 0 }, 2324 { X86::VPSUBBZ256rr, X86::VPSUBBZ256rm, 0 }, 2325 { X86::VPSUBDZ128rr, X86::VPSUBDZ128rm, 0 }, 2326 { X86::VPSUBDZ256rr, X86::VPSUBDZ256rm, 0 }, 2327 { X86::VPSUBQZ128rr, X86::VPSUBQZ128rm, 0 }, 2328 { X86::VPSUBQZ256rr, X86::VPSUBQZ256rm, 0 }, 2329 { X86::VPSUBSBZ128rr, X86::VPSUBSBZ128rm, 0 }, 2330 { X86::VPSUBSBZ256rr, X86::VPSUBSBZ256rm, 0 }, 2331 { X86::VPSUBSWZ128rr, X86::VPSUBSWZ128rm, 0 }, 2332 { X86::VPSUBSWZ256rr, X86::VPSUBSWZ256rm, 0 }, 2333 { X86::VPSUBUSBZ128rr, X86::VPSUBUSBZ128rm, 0 }, 2334 { X86::VPSUBUSBZ256rr, X86::VPSUBUSBZ256rm, 0 }, 2335 { X86::VPSUBUSWZ128rr, X86::VPSUBUSWZ128rm, 0 }, 2336 { X86::VPSUBUSWZ256rr, X86::VPSUBUSWZ256rm, 0 }, 2337 { X86::VPSUBWZ128rr, X86::VPSUBWZ128rm, 0 }, 2338 { X86::VPSUBWZ256rr, X86::VPSUBWZ256rm, 0 }, 2339 { X86::VPUNPCKHBWZ128rr, X86::VPUNPCKHBWZ128rm, 0 }, 2340 { X86::VPUNPCKHBWZ256rr, X86::VPUNPCKHBWZ256rm, 0 }, 2341 { X86::VPUNPCKHDQZ128rr, X86::VPUNPCKHDQZ128rm, 0 }, 2342 { X86::VPUNPCKHDQZ256rr, X86::VPUNPCKHDQZ256rm, 0 }, 2343 { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm, 0 }, 2344 { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm, 0 }, 2345 { X86::VPUNPCKHWDZ128rr, X86::VPUNPCKHWDZ128rm, 0 }, 2346 { X86::VPUNPCKHWDZ256rr, X86::VPUNPCKHWDZ256rm, 0 }, 2347 { X86::VPUNPCKLBWZ128rr, X86::VPUNPCKLBWZ128rm, 0 }, 2348 { X86::VPUNPCKLBWZ256rr, X86::VPUNPCKLBWZ256rm, 0 }, 2349 { X86::VPUNPCKLDQZ128rr, X86::VPUNPCKLDQZ128rm, 0 }, 2350 { X86::VPUNPCKLDQZ256rr, X86::VPUNPCKLDQZ256rm, 0 }, 2351 { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm, 0 }, 2352 { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm, 0 }, 2353 { X86::VPUNPCKLWDZ128rr, X86::VPUNPCKLWDZ128rm, 0 }, 2354 { X86::VPUNPCKLWDZ256rr, X86::VPUNPCKLWDZ256rm, 0 }, 2355 { X86::VPXORDZ128rr, X86::VPXORDZ128rm, 0 }, 2356 { X86::VPXORDZ256rr, X86::VPXORDZ256rm, 0 }, 2357 { X86::VPXORQZ128rr, X86::VPXORQZ128rm, 0 }, 2358 { X86::VPXORQZ256rr, X86::VPXORQZ256rm, 0 }, 2359 { X86::VSHUFPDZ128rri, X86::VSHUFPDZ128rmi, 0 }, 2360 { X86::VSHUFPDZ256rri, X86::VSHUFPDZ256rmi, 0 }, 2361 { X86::VSHUFPSZ128rri, X86::VSHUFPSZ128rmi, 0 }, 2362 { X86::VSHUFPSZ256rri, X86::VSHUFPSZ256rmi, 0 }, 2363 { X86::VSUBPDZ128rr, X86::VSUBPDZ128rm, 0 }, 2364 { X86::VSUBPDZ256rr, X86::VSUBPDZ256rm, 0 }, 2365 { X86::VSUBPSZ128rr, X86::VSUBPSZ128rm, 0 }, 2366 { X86::VSUBPSZ256rr, X86::VSUBPSZ256rm, 0 }, 2367 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rm, 0 }, 2368 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rm, 0 }, 2369 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rm, 0 }, 2370 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rm, 0 }, 2371 { X86::VUNPCKLPDZ128rr, X86::VUNPCKLPDZ128rm, 0 }, 2372 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rm, 0 }, 2373 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rm, 0 }, 2374 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rm, 0 }, 2375 { X86::VXORPDZ128rr, X86::VXORPDZ128rm, 0 }, 2376 { X86::VXORPDZ256rr, X86::VXORPDZ256rm, 0 }, 2377 { X86::VXORPSZ128rr, X86::VXORPSZ128rm, 0 }, 2378 { X86::VXORPSZ256rr, X86::VXORPSZ256rm, 0 }, 2379 2380 // AVX-512 masked foldable instructions 2381 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE }, 2382 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE }, 2383 { X86::VPABSBZrrkz, X86::VPABSBZrmkz, 0 }, 2384 { X86::VPABSDZrrkz, X86::VPABSDZrmkz, 0 }, 2385 { X86::VPABSQZrrkz, X86::VPABSQZrmkz, 0 }, 2386 { X86::VPABSWZrrkz, X86::VPABSWZrmkz, 0 }, 2387 { X86::VPCONFLICTDZrrkz, X86::VPCONFLICTDZrmkz, 0 }, 2388 { X86::VPCONFLICTQZrrkz, X86::VPCONFLICTQZrmkz, 0 }, 2389 { X86::VPERMILPDZrikz, X86::VPERMILPDZmikz, 0 }, 2390 { X86::VPERMILPSZrikz, X86::VPERMILPSZmikz, 0 }, 2391 { X86::VPERMPDZrikz, X86::VPERMPDZmikz, 0 }, 2392 { X86::VPERMQZrikz, X86::VPERMQZmikz, 0 }, 2393 { X86::VPLZCNTDZrrkz, X86::VPLZCNTDZrmkz, 0 }, 2394 { X86::VPLZCNTQZrrkz, X86::VPLZCNTQZrmkz, 0 }, 2395 { X86::VPMOVSXBDZrrkz, X86::VPMOVSXBDZrmkz, 0 }, 2396 { X86::VPMOVSXBQZrrkz, X86::VPMOVSXBQZrmkz, TB_NO_REVERSE }, 2397 { X86::VPMOVSXBWZrrkz, X86::VPMOVSXBWZrmkz, 0 }, 2398 { X86::VPMOVSXDQZrrkz, X86::VPMOVSXDQZrmkz, 0 }, 2399 { X86::VPMOVSXWDZrrkz, X86::VPMOVSXWDZrmkz, 0 }, 2400 { X86::VPMOVSXWQZrrkz, X86::VPMOVSXWQZrmkz, 0 }, 2401 { X86::VPMOVZXBDZrrkz, X86::VPMOVZXBDZrmkz, 0 }, 2402 { X86::VPMOVZXBQZrrkz, X86::VPMOVZXBQZrmkz, TB_NO_REVERSE }, 2403 { X86::VPMOVZXBWZrrkz, X86::VPMOVZXBWZrmkz, 0 }, 2404 { X86::VPMOVZXDQZrrkz, X86::VPMOVZXDQZrmkz, 0 }, 2405 { X86::VPMOVZXWDZrrkz, X86::VPMOVZXWDZrmkz, 0 }, 2406 { X86::VPMOVZXWQZrrkz, X86::VPMOVZXWQZrmkz, 0 }, 2407 { X86::VPOPCNTDZrrkz, X86::VPOPCNTDZrmkz, 0 }, 2408 { X86::VPOPCNTQZrrkz, X86::VPOPCNTQZrmkz, 0 }, 2409 { X86::VPSHUFDZrikz, X86::VPSHUFDZmikz, 0 }, 2410 { X86::VPSHUFHWZrikz, X86::VPSHUFHWZmikz, 0 }, 2411 { X86::VPSHUFLWZrikz, X86::VPSHUFLWZmikz, 0 }, 2412 { X86::VPSLLDZrikz, X86::VPSLLDZmikz, 0 }, 2413 { X86::VPSLLQZrikz, X86::VPSLLQZmikz, 0 }, 2414 { X86::VPSLLWZrikz, X86::VPSLLWZmikz, 0 }, 2415 { X86::VPSRADZrikz, X86::VPSRADZmikz, 0 }, 2416 { X86::VPSRAQZrikz, X86::VPSRAQZmikz, 0 }, 2417 { X86::VPSRAWZrikz, X86::VPSRAWZmikz, 0 }, 2418 { X86::VPSRLDZrikz, X86::VPSRLDZmikz, 0 }, 2419 { X86::VPSRLQZrikz, X86::VPSRLQZmikz, 0 }, 2420 { X86::VPSRLWZrikz, X86::VPSRLWZmikz, 0 }, 2421 2422 // AVX-512VL 256-bit masked foldable instructions 2423 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE }, 2424 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE }, 2425 { X86::VPABSBZ256rrkz, X86::VPABSBZ256rmkz, 0 }, 2426 { X86::VPABSDZ256rrkz, X86::VPABSDZ256rmkz, 0 }, 2427 { X86::VPABSQZ256rrkz, X86::VPABSQZ256rmkz, 0 }, 2428 { X86::VPABSWZ256rrkz, X86::VPABSWZ256rmkz, 0 }, 2429 { X86::VPCONFLICTDZ256rrkz, X86::VPCONFLICTDZ256rmkz, 0 }, 2430 { X86::VPCONFLICTQZ256rrkz, X86::VPCONFLICTQZ256rmkz, 0 }, 2431 { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz, 0 }, 2432 { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz, 0 }, 2433 { X86::VPERMPDZ256rikz, X86::VPERMPDZ256mikz, 0 }, 2434 { X86::VPERMQZ256rikz, X86::VPERMQZ256mikz, 0 }, 2435 { X86::VPLZCNTDZ256rrkz, X86::VPLZCNTDZ256rmkz, 0 }, 2436 { X86::VPLZCNTQZ256rrkz, X86::VPLZCNTQZ256rmkz, 0 }, 2437 { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz, TB_NO_REVERSE }, 2438 { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz, TB_NO_REVERSE }, 2439 { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz, 0 }, 2440 { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz, 0 }, 2441 { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz, 0 }, 2442 { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz, TB_NO_REVERSE }, 2443 { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz, TB_NO_REVERSE }, 2444 { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz, TB_NO_REVERSE }, 2445 { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz, 0 }, 2446 { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz, 0 }, 2447 { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz, 0 }, 2448 { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz, TB_NO_REVERSE }, 2449 { X86::VPSHUFDZ256rikz, X86::VPSHUFDZ256mikz, 0 }, 2450 { X86::VPSHUFHWZ256rikz, X86::VPSHUFHWZ256mikz, 0 }, 2451 { X86::VPSHUFLWZ256rikz, X86::VPSHUFLWZ256mikz, 0 }, 2452 { X86::VPSLLDZ256rikz, X86::VPSLLDZ256mikz, 0 }, 2453 { X86::VPSLLQZ256rikz, X86::VPSLLQZ256mikz, 0 }, 2454 { X86::VPSLLWZ256rikz, X86::VPSLLWZ256mikz, 0 }, 2455 { X86::VPSRADZ256rikz, X86::VPSRADZ256mikz, 0 }, 2456 { X86::VPSRAQZ256rikz, X86::VPSRAQZ256mikz, 0 }, 2457 { X86::VPSRAWZ256rikz, X86::VPSRAWZ256mikz, 0 }, 2458 { X86::VPSRLDZ256rikz, X86::VPSRLDZ256mikz, 0 }, 2459 { X86::VPSRLQZ256rikz, X86::VPSRLQZ256mikz, 0 }, 2460 { X86::VPSRLWZ256rikz, X86::VPSRLWZ256mikz, 0 }, 2461 2462 // AVX-512VL 128-bit masked foldable instructions 2463 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE }, 2464 { X86::VPABSBZ128rrkz, X86::VPABSBZ128rmkz, 0 }, 2465 { X86::VPABSDZ128rrkz, X86::VPABSDZ128rmkz, 0 }, 2466 { X86::VPABSQZ128rrkz, X86::VPABSQZ128rmkz, 0 }, 2467 { X86::VPABSWZ128rrkz, X86::VPABSWZ128rmkz, 0 }, 2468 { X86::VPCONFLICTDZ128rrkz, X86::VPCONFLICTDZ128rmkz, 0 }, 2469 { X86::VPCONFLICTQZ128rrkz, X86::VPCONFLICTQZ128rmkz, 0 }, 2470 { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz, 0 }, 2471 { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz, 0 }, 2472 { X86::VPLZCNTDZ128rrkz, X86::VPLZCNTDZ128rmkz, 0 }, 2473 { X86::VPLZCNTQZ128rrkz, X86::VPLZCNTQZ128rmkz, 0 }, 2474 { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz, TB_NO_REVERSE }, 2475 { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz, TB_NO_REVERSE }, 2476 { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz, TB_NO_REVERSE }, 2477 { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz, TB_NO_REVERSE }, 2478 { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz, TB_NO_REVERSE }, 2479 { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz, TB_NO_REVERSE }, 2480 { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz, TB_NO_REVERSE }, 2481 { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz, TB_NO_REVERSE }, 2482 { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz, TB_NO_REVERSE }, 2483 { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz, TB_NO_REVERSE }, 2484 { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz, TB_NO_REVERSE }, 2485 { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz, TB_NO_REVERSE }, 2486 { X86::VPSHUFDZ128rikz, X86::VPSHUFDZ128mikz, 0 }, 2487 { X86::VPSHUFHWZ128rikz, X86::VPSHUFHWZ128mikz, 0 }, 2488 { X86::VPSHUFLWZ128rikz, X86::VPSHUFLWZ128mikz, 0 }, 2489 { X86::VPSLLDZ128rikz, X86::VPSLLDZ128mikz, 0 }, 2490 { X86::VPSLLQZ128rikz, X86::VPSLLQZ128mikz, 0 }, 2491 { X86::VPSLLWZ128rikz, X86::VPSLLWZ128mikz, 0 }, 2492 { X86::VPSRADZ128rikz, X86::VPSRADZ128mikz, 0 }, 2493 { X86::VPSRAQZ128rikz, X86::VPSRAQZ128mikz, 0 }, 2494 { X86::VPSRAWZ128rikz, X86::VPSRAWZ128mikz, 0 }, 2495 { X86::VPSRLDZ128rikz, X86::VPSRLDZ128mikz, 0 }, 2496 { X86::VPSRLQZ128rikz, X86::VPSRLQZ128mikz, 0 }, 2497 { X86::VPSRLWZ128rikz, X86::VPSRLWZ128mikz, 0 }, 2498 2499 // AES foldable instructions 2500 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 }, 2501 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 }, 2502 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 }, 2503 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 }, 2504 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 }, 2505 { X86::VAESDECrr, X86::VAESDECrm, 0 }, 2506 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 }, 2507 { X86::VAESENCrr, X86::VAESENCrm, 0 }, 2508 2509 // SHA foldable instructions 2510 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 }, 2511 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 }, 2512 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 }, 2513 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 }, 2514 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 }, 2515 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 }, 2516 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 } 2517 }; 2518 2519 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) { 2520 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 2521 Entry.RegOp, Entry.MemOp, 2522 // Index 2, folded load 2523 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 2524 } 2525 2526 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = { 2527 // FMA4 foldable patterns 2528 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE }, 2529 { X86::VFMADDSS4rr_Int, X86::VFMADDSS4rm_Int, TB_NO_REVERSE }, 2530 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE }, 2531 { X86::VFMADDSD4rr_Int, X86::VFMADDSD4rm_Int, TB_NO_REVERSE }, 2532 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE }, 2533 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE }, 2534 { X86::VFMADDPS4Yrr, X86::VFMADDPS4Yrm, TB_ALIGN_NONE }, 2535 { X86::VFMADDPD4Yrr, X86::VFMADDPD4Yrm, TB_ALIGN_NONE }, 2536 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE }, 2537 { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4rm_Int, TB_NO_REVERSE }, 2538 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE }, 2539 { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4rm_Int, TB_NO_REVERSE }, 2540 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE }, 2541 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE }, 2542 { X86::VFNMADDPS4Yrr, X86::VFNMADDPS4Yrm, TB_ALIGN_NONE }, 2543 { X86::VFNMADDPD4Yrr, X86::VFNMADDPD4Yrm, TB_ALIGN_NONE }, 2544 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE }, 2545 { X86::VFMSUBSS4rr_Int, X86::VFMSUBSS4rm_Int, TB_NO_REVERSE }, 2546 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE }, 2547 { X86::VFMSUBSD4rr_Int, X86::VFMSUBSD4rm_Int, TB_NO_REVERSE }, 2548 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE }, 2549 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE }, 2550 { X86::VFMSUBPS4Yrr, X86::VFMSUBPS4Yrm, TB_ALIGN_NONE }, 2551 { X86::VFMSUBPD4Yrr, X86::VFMSUBPD4Yrm, TB_ALIGN_NONE }, 2552 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE }, 2553 { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4rm_Int, TB_NO_REVERSE }, 2554 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE }, 2555 { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4rm_Int, TB_NO_REVERSE }, 2556 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE }, 2557 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE }, 2558 { X86::VFNMSUBPS4Yrr, X86::VFNMSUBPS4Yrm, TB_ALIGN_NONE }, 2559 { X86::VFNMSUBPD4Yrr, X86::VFNMSUBPD4Yrm, TB_ALIGN_NONE }, 2560 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE }, 2561 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE }, 2562 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Yrm, TB_ALIGN_NONE }, 2563 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Yrm, TB_ALIGN_NONE }, 2564 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE }, 2565 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE }, 2566 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Yrm, TB_ALIGN_NONE }, 2567 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Yrm, TB_ALIGN_NONE }, 2568 2569 // XOP foldable instructions 2570 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 }, 2571 { X86::VPCMOVYrrr, X86::VPCMOVYrrm, 0 }, 2572 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 }, 2573 { X86::VPERMIL2PDYrr, X86::VPERMIL2PDYrm, 0 }, 2574 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 }, 2575 { X86::VPERMIL2PSYrr, X86::VPERMIL2PSYrm, 0 }, 2576 { X86::VPPERMrrr, X86::VPPERMrrm, 0 }, 2577 2578 // AVX-512 instructions with 3 source operands. 2579 { X86::VPERMI2Brr, X86::VPERMI2Brm, 0 }, 2580 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 }, 2581 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 }, 2582 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 }, 2583 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 }, 2584 { X86::VPERMI2Wrr, X86::VPERMI2Wrm, 0 }, 2585 { X86::VPERMT2Brr, X86::VPERMT2Brm, 0 }, 2586 { X86::VPERMT2Drr, X86::VPERMT2Drm, 0 }, 2587 { X86::VPERMT2PSrr, X86::VPERMT2PSrm, 0 }, 2588 { X86::VPERMT2PDrr, X86::VPERMT2PDrm, 0 }, 2589 { X86::VPERMT2Qrr, X86::VPERMT2Qrm, 0 }, 2590 { X86::VPERMT2Wrr, X86::VPERMT2Wrm, 0 }, 2591 { X86::VPMADD52HUQZr, X86::VPMADD52HUQZm, 0 }, 2592 { X86::VPMADD52LUQZr, X86::VPMADD52LUQZm, 0 }, 2593 { X86::VPTERNLOGDZrri, X86::VPTERNLOGDZrmi, 0 }, 2594 { X86::VPTERNLOGQZrri, X86::VPTERNLOGQZrmi, 0 }, 2595 2596 // AVX-512VL 256-bit instructions with 3 source operands. 2597 { X86::VPERMI2B256rr, X86::VPERMI2B256rm, 0 }, 2598 { X86::VPERMI2D256rr, X86::VPERMI2D256rm, 0 }, 2599 { X86::VPERMI2PD256rr, X86::VPERMI2PD256rm, 0 }, 2600 { X86::VPERMI2PS256rr, X86::VPERMI2PS256rm, 0 }, 2601 { X86::VPERMI2Q256rr, X86::VPERMI2Q256rm, 0 }, 2602 { X86::VPERMI2W256rr, X86::VPERMI2W256rm, 0 }, 2603 { X86::VPERMT2B256rr, X86::VPERMT2B256rm, 0 }, 2604 { X86::VPERMT2D256rr, X86::VPERMT2D256rm, 0 }, 2605 { X86::VPERMT2PD256rr, X86::VPERMT2PD256rm, 0 }, 2606 { X86::VPERMT2PS256rr, X86::VPERMT2PS256rm, 0 }, 2607 { X86::VPERMT2Q256rr, X86::VPERMT2Q256rm, 0 }, 2608 { X86::VPERMT2W256rr, X86::VPERMT2W256rm, 0 }, 2609 { X86::VPMADD52HUQZ256r, X86::VPMADD52HUQZ256m, 0 }, 2610 { X86::VPMADD52LUQZ256r, X86::VPMADD52LUQZ256m, 0 }, 2611 { X86::VPTERNLOGDZ256rri, X86::VPTERNLOGDZ256rmi, 0 }, 2612 { X86::VPTERNLOGQZ256rri, X86::VPTERNLOGQZ256rmi, 0 }, 2613 2614 // AVX-512VL 128-bit instructions with 3 source operands. 2615 { X86::VPERMI2B128rr, X86::VPERMI2B128rm, 0 }, 2616 { X86::VPERMI2D128rr, X86::VPERMI2D128rm, 0 }, 2617 { X86::VPERMI2PD128rr, X86::VPERMI2PD128rm, 0 }, 2618 { X86::VPERMI2PS128rr, X86::VPERMI2PS128rm, 0 }, 2619 { X86::VPERMI2Q128rr, X86::VPERMI2Q128rm, 0 }, 2620 { X86::VPERMI2W128rr, X86::VPERMI2W128rm, 0 }, 2621 { X86::VPERMT2B128rr, X86::VPERMT2B128rm, 0 }, 2622 { X86::VPERMT2D128rr, X86::VPERMT2D128rm, 0 }, 2623 { X86::VPERMT2PD128rr, X86::VPERMT2PD128rm, 0 }, 2624 { X86::VPERMT2PS128rr, X86::VPERMT2PS128rm, 0 }, 2625 { X86::VPERMT2Q128rr, X86::VPERMT2Q128rm, 0 }, 2626 { X86::VPERMT2W128rr, X86::VPERMT2W128rm, 0 }, 2627 { X86::VPMADD52HUQZ128r, X86::VPMADD52HUQZ128m, 0 }, 2628 { X86::VPMADD52LUQZ128r, X86::VPMADD52LUQZ128m, 0 }, 2629 { X86::VPTERNLOGDZ128rri, X86::VPTERNLOGDZ128rmi, 0 }, 2630 { X86::VPTERNLOGQZ128rri, X86::VPTERNLOGQZ128rmi, 0 }, 2631 2632 // AVX-512 masked instructions 2633 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 }, 2634 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 }, 2635 { X86::VADDSDZrr_Intkz, X86::VADDSDZrm_Intkz, TB_NO_REVERSE }, 2636 { X86::VADDSSZrr_Intkz, X86::VADDSSZrm_Intkz, TB_NO_REVERSE }, 2637 { X86::VALIGNDZrrikz, X86::VALIGNDZrmikz, 0 }, 2638 { X86::VALIGNQZrrikz, X86::VALIGNQZrmikz, 0 }, 2639 { X86::VANDNPDZrrkz, X86::VANDNPDZrmkz, 0 }, 2640 { X86::VANDNPSZrrkz, X86::VANDNPSZrmkz, 0 }, 2641 { X86::VANDPDZrrkz, X86::VANDPDZrmkz, 0 }, 2642 { X86::VANDPSZrrkz, X86::VANDPSZrmkz, 0 }, 2643 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 }, 2644 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 }, 2645 { X86::VDIVSDZrr_Intkz, X86::VDIVSDZrm_Intkz, TB_NO_REVERSE }, 2646 { X86::VDIVSSZrr_Intkz, X86::VDIVSSZrm_Intkz, TB_NO_REVERSE }, 2647 { X86::VINSERTF32x4Zrrkz, X86::VINSERTF32x4Zrmkz, 0 }, 2648 { X86::VINSERTF32x8Zrrkz, X86::VINSERTF32x8Zrmkz, 0 }, 2649 { X86::VINSERTF64x2Zrrkz, X86::VINSERTF64x2Zrmkz, 0 }, 2650 { X86::VINSERTF64x4Zrrkz, X86::VINSERTF64x4Zrmkz, 0 }, 2651 { X86::VINSERTI32x4Zrrkz, X86::VINSERTI32x4Zrmkz, 0 }, 2652 { X86::VINSERTI32x8Zrrkz, X86::VINSERTI32x8Zrmkz, 0 }, 2653 { X86::VINSERTI64x2Zrrkz, X86::VINSERTI64x2Zrmkz, 0 }, 2654 { X86::VINSERTI64x4Zrrkz, X86::VINSERTI64x4Zrmkz, 0 }, 2655 { X86::VMAXCPDZrrkz, X86::VMAXCPDZrmkz, 0 }, 2656 { X86::VMAXCPSZrrkz, X86::VMAXCPSZrmkz, 0 }, 2657 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 }, 2658 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 }, 2659 { X86::VMAXSDZrr_Intkz, X86::VMAXSDZrm_Intkz, 0 }, 2660 { X86::VMAXSSZrr_Intkz, X86::VMAXSSZrm_Intkz, 0 }, 2661 { X86::VMINCPDZrrkz, X86::VMINCPDZrmkz, 0 }, 2662 { X86::VMINCPSZrrkz, X86::VMINCPSZrmkz, 0 }, 2663 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 }, 2664 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 }, 2665 { X86::VMINSDZrr_Intkz, X86::VMINSDZrm_Intkz, 0 }, 2666 { X86::VMINSSZrr_Intkz, X86::VMINSSZrm_Intkz, 0 }, 2667 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 }, 2668 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 }, 2669 { X86::VMULSDZrr_Intkz, X86::VMULSDZrm_Intkz, TB_NO_REVERSE }, 2670 { X86::VMULSSZrr_Intkz, X86::VMULSSZrm_Intkz, TB_NO_REVERSE }, 2671 { X86::VORPDZrrkz, X86::VORPDZrmkz, 0 }, 2672 { X86::VORPSZrrkz, X86::VORPSZrmkz, 0 }, 2673 { X86::VPACKSSDWZrrkz, X86::VPACKSSDWZrmkz, 0 }, 2674 { X86::VPACKSSWBZrrkz, X86::VPACKSSWBZrmkz, 0 }, 2675 { X86::VPACKUSDWZrrkz, X86::VPACKUSDWZrmkz, 0 }, 2676 { X86::VPACKUSWBZrrkz, X86::VPACKUSWBZrmkz, 0 }, 2677 { X86::VPADDBZrrkz, X86::VPADDBZrmkz, 0 }, 2678 { X86::VPADDDZrrkz, X86::VPADDDZrmkz, 0 }, 2679 { X86::VPADDQZrrkz, X86::VPADDQZrmkz, 0 }, 2680 { X86::VPADDSBZrrkz, X86::VPADDSBZrmkz, 0 }, 2681 { X86::VPADDSWZrrkz, X86::VPADDSWZrmkz, 0 }, 2682 { X86::VPADDUSBZrrkz, X86::VPADDUSBZrmkz, 0 }, 2683 { X86::VPADDUSWZrrkz, X86::VPADDUSWZrmkz, 0 }, 2684 { X86::VPADDWZrrkz, X86::VPADDWZrmkz, 0 }, 2685 { X86::VPALIGNRZrrikz, X86::VPALIGNRZrmikz, 0 }, 2686 { X86::VPANDDZrrkz, X86::VPANDDZrmkz, 0 }, 2687 { X86::VPANDNDZrrkz, X86::VPANDNDZrmkz, 0 }, 2688 { X86::VPANDNQZrrkz, X86::VPANDNQZrmkz, 0 }, 2689 { X86::VPANDQZrrkz, X86::VPANDQZrmkz, 0 }, 2690 { X86::VPAVGBZrrkz, X86::VPAVGBZrmkz, 0 }, 2691 { X86::VPAVGWZrrkz, X86::VPAVGWZrmkz, 0 }, 2692 { X86::VPERMBZrrkz, X86::VPERMBZrmkz, 0 }, 2693 { X86::VPERMDZrrkz, X86::VPERMDZrmkz, 0 }, 2694 { X86::VPERMILPDZrrkz, X86::VPERMILPDZrmkz, 0 }, 2695 { X86::VPERMILPSZrrkz, X86::VPERMILPSZrmkz, 0 }, 2696 { X86::VPERMPDZrrkz, X86::VPERMPDZrmkz, 0 }, 2697 { X86::VPERMPSZrrkz, X86::VPERMPSZrmkz, 0 }, 2698 { X86::VPERMQZrrkz, X86::VPERMQZrmkz, 0 }, 2699 { X86::VPERMWZrrkz, X86::VPERMWZrmkz, 0 }, 2700 { X86::VPMADDUBSWZrrkz, X86::VPMADDUBSWZrmkz, 0 }, 2701 { X86::VPMADDWDZrrkz, X86::VPMADDWDZrmkz, 0 }, 2702 { X86::VPMAXSBZrrkz, X86::VPMAXSBZrmkz, 0 }, 2703 { X86::VPMAXSDZrrkz, X86::VPMAXSDZrmkz, 0 }, 2704 { X86::VPMAXSQZrrkz, X86::VPMAXSQZrmkz, 0 }, 2705 { X86::VPMAXSWZrrkz, X86::VPMAXSWZrmkz, 0 }, 2706 { X86::VPMAXUBZrrkz, X86::VPMAXUBZrmkz, 0 }, 2707 { X86::VPMAXUDZrrkz, X86::VPMAXUDZrmkz, 0 }, 2708 { X86::VPMAXUQZrrkz, X86::VPMAXUQZrmkz, 0 }, 2709 { X86::VPMAXUWZrrkz, X86::VPMAXUWZrmkz, 0 }, 2710 { X86::VPMINSBZrrkz, X86::VPMINSBZrmkz, 0 }, 2711 { X86::VPMINSDZrrkz, X86::VPMINSDZrmkz, 0 }, 2712 { X86::VPMINSQZrrkz, X86::VPMINSQZrmkz, 0 }, 2713 { X86::VPMINSWZrrkz, X86::VPMINSWZrmkz, 0 }, 2714 { X86::VPMINUBZrrkz, X86::VPMINUBZrmkz, 0 }, 2715 { X86::VPMINUDZrrkz, X86::VPMINUDZrmkz, 0 }, 2716 { X86::VPMINUQZrrkz, X86::VPMINUQZrmkz, 0 }, 2717 { X86::VPMINUWZrrkz, X86::VPMINUWZrmkz, 0 }, 2718 { X86::VPMULLDZrrkz, X86::VPMULLDZrmkz, 0 }, 2719 { X86::VPMULLQZrrkz, X86::VPMULLQZrmkz, 0 }, 2720 { X86::VPMULLWZrrkz, X86::VPMULLWZrmkz, 0 }, 2721 { X86::VPMULDQZrrkz, X86::VPMULDQZrmkz, 0 }, 2722 { X86::VPMULUDQZrrkz, X86::VPMULUDQZrmkz, 0 }, 2723 { X86::VPORDZrrkz, X86::VPORDZrmkz, 0 }, 2724 { X86::VPORQZrrkz, X86::VPORQZrmkz, 0 }, 2725 { X86::VPSHUFBZrrkz, X86::VPSHUFBZrmkz, 0 }, 2726 { X86::VPSLLDZrrkz, X86::VPSLLDZrmkz, 0 }, 2727 { X86::VPSLLQZrrkz, X86::VPSLLQZrmkz, 0 }, 2728 { X86::VPSLLVDZrrkz, X86::VPSLLVDZrmkz, 0 }, 2729 { X86::VPSLLVQZrrkz, X86::VPSLLVQZrmkz, 0 }, 2730 { X86::VPSLLVWZrrkz, X86::VPSLLVWZrmkz, 0 }, 2731 { X86::VPSLLWZrrkz, X86::VPSLLWZrmkz, 0 }, 2732 { X86::VPSRADZrrkz, X86::VPSRADZrmkz, 0 }, 2733 { X86::VPSRAQZrrkz, X86::VPSRAQZrmkz, 0 }, 2734 { X86::VPSRAVDZrrkz, X86::VPSRAVDZrmkz, 0 }, 2735 { X86::VPSRAVQZrrkz, X86::VPSRAVQZrmkz, 0 }, 2736 { X86::VPSRAVWZrrkz, X86::VPSRAVWZrmkz, 0 }, 2737 { X86::VPSRAWZrrkz, X86::VPSRAWZrmkz, 0 }, 2738 { X86::VPSRLDZrrkz, X86::VPSRLDZrmkz, 0 }, 2739 { X86::VPSRLQZrrkz, X86::VPSRLQZrmkz, 0 }, 2740 { X86::VPSRLVDZrrkz, X86::VPSRLVDZrmkz, 0 }, 2741 { X86::VPSRLVQZrrkz, X86::VPSRLVQZrmkz, 0 }, 2742 { X86::VPSRLVWZrrkz, X86::VPSRLVWZrmkz, 0 }, 2743 { X86::VPSRLWZrrkz, X86::VPSRLWZrmkz, 0 }, 2744 { X86::VPSUBBZrrkz, X86::VPSUBBZrmkz, 0 }, 2745 { X86::VPSUBDZrrkz, X86::VPSUBDZrmkz, 0 }, 2746 { X86::VPSUBQZrrkz, X86::VPSUBQZrmkz, 0 }, 2747 { X86::VPSUBSBZrrkz, X86::VPSUBSBZrmkz, 0 }, 2748 { X86::VPSUBSWZrrkz, X86::VPSUBSWZrmkz, 0 }, 2749 { X86::VPSUBUSBZrrkz, X86::VPSUBUSBZrmkz, 0 }, 2750 { X86::VPSUBUSWZrrkz, X86::VPSUBUSWZrmkz, 0 }, 2751 { X86::VPSUBWZrrkz, X86::VPSUBWZrmkz, 0 }, 2752 { X86::VPUNPCKHBWZrrkz, X86::VPUNPCKHBWZrmkz, 0 }, 2753 { X86::VPUNPCKHDQZrrkz, X86::VPUNPCKHDQZrmkz, 0 }, 2754 { X86::VPUNPCKHQDQZrrkz, X86::VPUNPCKHQDQZrmkz, 0 }, 2755 { X86::VPUNPCKHWDZrrkz, X86::VPUNPCKHWDZrmkz, 0 }, 2756 { X86::VPUNPCKLBWZrrkz, X86::VPUNPCKLBWZrmkz, 0 }, 2757 { X86::VPUNPCKLDQZrrkz, X86::VPUNPCKLDQZrmkz, 0 }, 2758 { X86::VPUNPCKLQDQZrrkz, X86::VPUNPCKLQDQZrmkz, 0 }, 2759 { X86::VPUNPCKLWDZrrkz, X86::VPUNPCKLWDZrmkz, 0 }, 2760 { X86::VPXORDZrrkz, X86::VPXORDZrmkz, 0 }, 2761 { X86::VPXORQZrrkz, X86::VPXORQZrmkz, 0 }, 2762 { X86::VSHUFPDZrrikz, X86::VSHUFPDZrmikz, 0 }, 2763 { X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0 }, 2764 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 }, 2765 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 }, 2766 { X86::VSUBSDZrr_Intkz, X86::VSUBSDZrm_Intkz, TB_NO_REVERSE }, 2767 { X86::VSUBSSZrr_Intkz, X86::VSUBSSZrm_Intkz, TB_NO_REVERSE }, 2768 { X86::VUNPCKHPDZrrkz, X86::VUNPCKHPDZrmkz, 0 }, 2769 { X86::VUNPCKHPSZrrkz, X86::VUNPCKHPSZrmkz, 0 }, 2770 { X86::VUNPCKLPDZrrkz, X86::VUNPCKLPDZrmkz, 0 }, 2771 { X86::VUNPCKLPSZrrkz, X86::VUNPCKLPSZrmkz, 0 }, 2772 { X86::VXORPDZrrkz, X86::VXORPDZrmkz, 0 }, 2773 { X86::VXORPSZrrkz, X86::VXORPSZrmkz, 0 }, 2774 2775 // AVX-512{F,VL} masked arithmetic instructions 256-bit 2776 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 }, 2777 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 }, 2778 { X86::VALIGNDZ256rrikz, X86::VALIGNDZ256rmikz, 0 }, 2779 { X86::VALIGNQZ256rrikz, X86::VALIGNQZ256rmikz, 0 }, 2780 { X86::VANDNPDZ256rrkz, X86::VANDNPDZ256rmkz, 0 }, 2781 { X86::VANDNPSZ256rrkz, X86::VANDNPSZ256rmkz, 0 }, 2782 { X86::VANDPDZ256rrkz, X86::VANDPDZ256rmkz, 0 }, 2783 { X86::VANDPSZ256rrkz, X86::VANDPSZ256rmkz, 0 }, 2784 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 }, 2785 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 }, 2786 { X86::VINSERTF32x4Z256rrkz, X86::VINSERTF32x4Z256rmkz, 0 }, 2787 { X86::VINSERTF64x2Z256rrkz, X86::VINSERTF64x2Z256rmkz, 0 }, 2788 { X86::VINSERTI32x4Z256rrkz, X86::VINSERTI32x4Z256rmkz, 0 }, 2789 { X86::VINSERTI64x2Z256rrkz, X86::VINSERTI64x2Z256rmkz, 0 }, 2790 { X86::VMAXCPDZ256rrkz, X86::VMAXCPDZ256rmkz, 0 }, 2791 { X86::VMAXCPSZ256rrkz, X86::VMAXCPSZ256rmkz, 0 }, 2792 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 }, 2793 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 }, 2794 { X86::VMINCPDZ256rrkz, X86::VMINCPDZ256rmkz, 0 }, 2795 { X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmkz, 0 }, 2796 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 }, 2797 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 }, 2798 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 }, 2799 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 }, 2800 { X86::VORPDZ256rrkz, X86::VORPDZ256rmkz, 0 }, 2801 { X86::VORPSZ256rrkz, X86::VORPSZ256rmkz, 0 }, 2802 { X86::VPACKSSDWZ256rrkz, X86::VPACKSSDWZ256rmkz, 0 }, 2803 { X86::VPACKSSWBZ256rrkz, X86::VPACKSSWBZ256rmkz, 0 }, 2804 { X86::VPACKUSDWZ256rrkz, X86::VPACKUSDWZ256rmkz, 0 }, 2805 { X86::VPACKUSWBZ256rrkz, X86::VPACKUSWBZ256rmkz, 0 }, 2806 { X86::VPADDBZ256rrkz, X86::VPADDBZ256rmkz, 0 }, 2807 { X86::VPADDDZ256rrkz, X86::VPADDDZ256rmkz, 0 }, 2808 { X86::VPADDQZ256rrkz, X86::VPADDQZ256rmkz, 0 }, 2809 { X86::VPADDSBZ256rrkz, X86::VPADDSBZ256rmkz, 0 }, 2810 { X86::VPADDSWZ256rrkz, X86::VPADDSWZ256rmkz, 0 }, 2811 { X86::VPADDUSBZ256rrkz, X86::VPADDUSBZ256rmkz, 0 }, 2812 { X86::VPADDUSWZ256rrkz, X86::VPADDUSWZ256rmkz, 0 }, 2813 { X86::VPADDWZ256rrkz, X86::VPADDWZ256rmkz, 0 }, 2814 { X86::VPALIGNRZ256rrikz, X86::VPALIGNRZ256rmikz, 0 }, 2815 { X86::VPANDDZ256rrkz, X86::VPANDDZ256rmkz, 0 }, 2816 { X86::VPANDNDZ256rrkz, X86::VPANDNDZ256rmkz, 0 }, 2817 { X86::VPANDNQZ256rrkz, X86::VPANDNQZ256rmkz, 0 }, 2818 { X86::VPANDQZ256rrkz, X86::VPANDQZ256rmkz, 0 }, 2819 { X86::VPAVGBZ256rrkz, X86::VPAVGBZ256rmkz, 0 }, 2820 { X86::VPAVGWZ256rrkz, X86::VPAVGWZ256rmkz, 0 }, 2821 { X86::VPERMBZ256rrkz, X86::VPERMBZ256rmkz, 0 }, 2822 { X86::VPERMDZ256rrkz, X86::VPERMDZ256rmkz, 0 }, 2823 { X86::VPERMILPDZ256rrkz, X86::VPERMILPDZ256rmkz, 0 }, 2824 { X86::VPERMILPSZ256rrkz, X86::VPERMILPSZ256rmkz, 0 }, 2825 { X86::VPERMPDZ256rrkz, X86::VPERMPDZ256rmkz, 0 }, 2826 { X86::VPERMPSZ256rrkz, X86::VPERMPSZ256rmkz, 0 }, 2827 { X86::VPERMQZ256rrkz, X86::VPERMQZ256rmkz, 0 }, 2828 { X86::VPERMWZ256rrkz, X86::VPERMWZ256rmkz, 0 }, 2829 { X86::VPMADDUBSWZ256rrkz, X86::VPMADDUBSWZ256rmkz, 0 }, 2830 { X86::VPMADDWDZ256rrkz, X86::VPMADDWDZ256rmkz, 0 }, 2831 { X86::VPMAXSBZ256rrkz, X86::VPMAXSBZ256rmkz, 0 }, 2832 { X86::VPMAXSDZ256rrkz, X86::VPMAXSDZ256rmkz, 0 }, 2833 { X86::VPMAXSQZ256rrkz, X86::VPMAXSQZ256rmkz, 0 }, 2834 { X86::VPMAXSWZ256rrkz, X86::VPMAXSWZ256rmkz, 0 }, 2835 { X86::VPMAXUBZ256rrkz, X86::VPMAXUBZ256rmkz, 0 }, 2836 { X86::VPMAXUDZ256rrkz, X86::VPMAXUDZ256rmkz, 0 }, 2837 { X86::VPMAXUQZ256rrkz, X86::VPMAXUQZ256rmkz, 0 }, 2838 { X86::VPMAXUWZ256rrkz, X86::VPMAXUWZ256rmkz, 0 }, 2839 { X86::VPMINSBZ256rrkz, X86::VPMINSBZ256rmkz, 0 }, 2840 { X86::VPMINSDZ256rrkz, X86::VPMINSDZ256rmkz, 0 }, 2841 { X86::VPMINSQZ256rrkz, X86::VPMINSQZ256rmkz, 0 }, 2842 { X86::VPMINSWZ256rrkz, X86::VPMINSWZ256rmkz, 0 }, 2843 { X86::VPMINUBZ256rrkz, X86::VPMINUBZ256rmkz, 0 }, 2844 { X86::VPMINUDZ256rrkz, X86::VPMINUDZ256rmkz, 0 }, 2845 { X86::VPMINUQZ256rrkz, X86::VPMINUQZ256rmkz, 0 }, 2846 { X86::VPMINUWZ256rrkz, X86::VPMINUWZ256rmkz, 0 }, 2847 { X86::VPMULDQZ256rrkz, X86::VPMULDQZ256rmkz, 0 }, 2848 { X86::VPMULLDZ256rrkz, X86::VPMULLDZ256rmkz, 0 }, 2849 { X86::VPMULLQZ256rrkz, X86::VPMULLQZ256rmkz, 0 }, 2850 { X86::VPMULLWZ256rrkz, X86::VPMULLWZ256rmkz, 0 }, 2851 { X86::VPMULUDQZ256rrkz, X86::VPMULUDQZ256rmkz, 0 }, 2852 { X86::VPORDZ256rrkz, X86::VPORDZ256rmkz, 0 }, 2853 { X86::VPORQZ256rrkz, X86::VPORQZ256rmkz, 0 }, 2854 { X86::VPSHUFBZ256rrkz, X86::VPSHUFBZ256rmkz, 0 }, 2855 { X86::VPSLLDZ256rrkz, X86::VPSLLDZ256rmkz, 0 }, 2856 { X86::VPSLLQZ256rrkz, X86::VPSLLQZ256rmkz, 0 }, 2857 { X86::VPSLLVDZ256rrkz, X86::VPSLLVDZ256rmkz, 0 }, 2858 { X86::VPSLLVQZ256rrkz, X86::VPSLLVQZ256rmkz, 0 }, 2859 { X86::VPSLLVWZ256rrkz, X86::VPSLLVWZ256rmkz, 0 }, 2860 { X86::VPSLLWZ256rrkz, X86::VPSLLWZ256rmkz, 0 }, 2861 { X86::VPSRADZ256rrkz, X86::VPSRADZ256rmkz, 0 }, 2862 { X86::VPSRAQZ256rrkz, X86::VPSRAQZ256rmkz, 0 }, 2863 { X86::VPSRAVDZ256rrkz, X86::VPSRAVDZ256rmkz, 0 }, 2864 { X86::VPSRAVQZ256rrkz, X86::VPSRAVQZ256rmkz, 0 }, 2865 { X86::VPSRAVWZ256rrkz, X86::VPSRAVWZ256rmkz, 0 }, 2866 { X86::VPSRAWZ256rrkz, X86::VPSRAWZ256rmkz, 0 }, 2867 { X86::VPSRLDZ256rrkz, X86::VPSRLDZ256rmkz, 0 }, 2868 { X86::VPSRLQZ256rrkz, X86::VPSRLQZ256rmkz, 0 }, 2869 { X86::VPSRLVDZ256rrkz, X86::VPSRLVDZ256rmkz, 0 }, 2870 { X86::VPSRLVQZ256rrkz, X86::VPSRLVQZ256rmkz, 0 }, 2871 { X86::VPSRLVWZ256rrkz, X86::VPSRLVWZ256rmkz, 0 }, 2872 { X86::VPSRLWZ256rrkz, X86::VPSRLWZ256rmkz, 0 }, 2873 { X86::VPSUBBZ256rrkz, X86::VPSUBBZ256rmkz, 0 }, 2874 { X86::VPSUBDZ256rrkz, X86::VPSUBDZ256rmkz, 0 }, 2875 { X86::VPSUBQZ256rrkz, X86::VPSUBQZ256rmkz, 0 }, 2876 { X86::VPSUBSBZ256rrkz, X86::VPSUBSBZ256rmkz, 0 }, 2877 { X86::VPSUBSWZ256rrkz, X86::VPSUBSWZ256rmkz, 0 }, 2878 { X86::VPSUBUSBZ256rrkz, X86::VPSUBUSBZ256rmkz, 0 }, 2879 { X86::VPSUBUSWZ256rrkz, X86::VPSUBUSWZ256rmkz, 0 }, 2880 { X86::VPSUBWZ256rrkz, X86::VPSUBWZ256rmkz, 0 }, 2881 { X86::VPUNPCKHBWZ256rrkz, X86::VPUNPCKHBWZ256rmkz, 0 }, 2882 { X86::VPUNPCKHDQZ256rrkz, X86::VPUNPCKHDQZ256rmkz, 0 }, 2883 { X86::VPUNPCKHQDQZ256rrkz, X86::VPUNPCKHQDQZ256rmkz, 0 }, 2884 { X86::VPUNPCKHWDZ256rrkz, X86::VPUNPCKHWDZ256rmkz, 0 }, 2885 { X86::VPUNPCKLBWZ256rrkz, X86::VPUNPCKLBWZ256rmkz, 0 }, 2886 { X86::VPUNPCKLDQZ256rrkz, X86::VPUNPCKLDQZ256rmkz, 0 }, 2887 { X86::VPUNPCKLQDQZ256rrkz, X86::VPUNPCKLQDQZ256rmkz, 0 }, 2888 { X86::VPUNPCKLWDZ256rrkz, X86::VPUNPCKLWDZ256rmkz, 0 }, 2889 { X86::VPXORDZ256rrkz, X86::VPXORDZ256rmkz, 0 }, 2890 { X86::VPXORQZ256rrkz, X86::VPXORQZ256rmkz, 0 }, 2891 { X86::VSHUFPDZ256rrikz, X86::VSHUFPDZ256rmikz, 0 }, 2892 { X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0 }, 2893 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 }, 2894 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 }, 2895 { X86::VUNPCKHPDZ256rrkz, X86::VUNPCKHPDZ256rmkz, 0 }, 2896 { X86::VUNPCKHPSZ256rrkz, X86::VUNPCKHPSZ256rmkz, 0 }, 2897 { X86::VUNPCKLPDZ256rrkz, X86::VUNPCKLPDZ256rmkz, 0 }, 2898 { X86::VUNPCKLPSZ256rrkz, X86::VUNPCKLPSZ256rmkz, 0 }, 2899 { X86::VXORPDZ256rrkz, X86::VXORPDZ256rmkz, 0 }, 2900 { X86::VXORPSZ256rrkz, X86::VXORPSZ256rmkz, 0 }, 2901 2902 // AVX-512{F,VL} masked arithmetic instructions 128-bit 2903 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 }, 2904 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 }, 2905 { X86::VALIGNDZ128rrikz, X86::VALIGNDZ128rmikz, 0 }, 2906 { X86::VALIGNQZ128rrikz, X86::VALIGNQZ128rmikz, 0 }, 2907 { X86::VANDNPDZ128rrkz, X86::VANDNPDZ128rmkz, 0 }, 2908 { X86::VANDNPSZ128rrkz, X86::VANDNPSZ128rmkz, 0 }, 2909 { X86::VANDPDZ128rrkz, X86::VANDPDZ128rmkz, 0 }, 2910 { X86::VANDPSZ128rrkz, X86::VANDPSZ128rmkz, 0 }, 2911 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 }, 2912 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 }, 2913 { X86::VMAXCPDZ128rrkz, X86::VMAXCPDZ128rmkz, 0 }, 2914 { X86::VMAXCPSZ128rrkz, X86::VMAXCPSZ128rmkz, 0 }, 2915 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }, 2916 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 }, 2917 { X86::VMINCPDZ128rrkz, X86::VMINCPDZ128rmkz, 0 }, 2918 { X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmkz, 0 }, 2919 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 }, 2920 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 }, 2921 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 }, 2922 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 }, 2923 { X86::VORPDZ128rrkz, X86::VORPDZ128rmkz, 0 }, 2924 { X86::VORPSZ128rrkz, X86::VORPSZ128rmkz, 0 }, 2925 { X86::VPACKSSDWZ128rrkz, X86::VPACKSSDWZ128rmkz, 0 }, 2926 { X86::VPACKSSWBZ128rrkz, X86::VPACKSSWBZ128rmkz, 0 }, 2927 { X86::VPACKUSDWZ128rrkz, X86::VPACKUSDWZ128rmkz, 0 }, 2928 { X86::VPACKUSWBZ128rrkz, X86::VPACKUSWBZ128rmkz, 0 }, 2929 { X86::VPADDBZ128rrkz, X86::VPADDBZ128rmkz, 0 }, 2930 { X86::VPADDDZ128rrkz, X86::VPADDDZ128rmkz, 0 }, 2931 { X86::VPADDQZ128rrkz, X86::VPADDQZ128rmkz, 0 }, 2932 { X86::VPADDSBZ128rrkz, X86::VPADDSBZ128rmkz, 0 }, 2933 { X86::VPADDSWZ128rrkz, X86::VPADDSWZ128rmkz, 0 }, 2934 { X86::VPADDUSBZ128rrkz, X86::VPADDUSBZ128rmkz, 0 }, 2935 { X86::VPADDUSWZ128rrkz, X86::VPADDUSWZ128rmkz, 0 }, 2936 { X86::VPADDWZ128rrkz, X86::VPADDWZ128rmkz, 0 }, 2937 { X86::VPALIGNRZ128rrikz, X86::VPALIGNRZ128rmikz, 0 }, 2938 { X86::VPANDDZ128rrkz, X86::VPANDDZ128rmkz, 0 }, 2939 { X86::VPANDNDZ128rrkz, X86::VPANDNDZ128rmkz, 0 }, 2940 { X86::VPANDNQZ128rrkz, X86::VPANDNQZ128rmkz, 0 }, 2941 { X86::VPANDQZ128rrkz, X86::VPANDQZ128rmkz, 0 }, 2942 { X86::VPAVGBZ128rrkz, X86::VPAVGBZ128rmkz, 0 }, 2943 { X86::VPAVGWZ128rrkz, X86::VPAVGWZ128rmkz, 0 }, 2944 { X86::VPERMBZ128rrkz, X86::VPERMBZ128rmkz, 0 }, 2945 { X86::VPERMILPDZ128rrkz, X86::VPERMILPDZ128rmkz, 0 }, 2946 { X86::VPERMILPSZ128rrkz, X86::VPERMILPSZ128rmkz, 0 }, 2947 { X86::VPERMWZ128rrkz, X86::VPERMWZ128rmkz, 0 }, 2948 { X86::VPMADDUBSWZ128rrkz, X86::VPMADDUBSWZ128rmkz, 0 }, 2949 { X86::VPMADDWDZ128rrkz, X86::VPMADDWDZ128rmkz, 0 }, 2950 { X86::VPMAXSBZ128rrkz, X86::VPMAXSBZ128rmkz, 0 }, 2951 { X86::VPMAXSDZ128rrkz, X86::VPMAXSDZ128rmkz, 0 }, 2952 { X86::VPMAXSQZ128rrkz, X86::VPMAXSQZ128rmkz, 0 }, 2953 { X86::VPMAXSWZ128rrkz, X86::VPMAXSWZ128rmkz, 0 }, 2954 { X86::VPMAXUBZ128rrkz, X86::VPMAXUBZ128rmkz, 0 }, 2955 { X86::VPMAXUDZ128rrkz, X86::VPMAXUDZ128rmkz, 0 }, 2956 { X86::VPMAXUQZ128rrkz, X86::VPMAXUQZ128rmkz, 0 }, 2957 { X86::VPMAXUWZ128rrkz, X86::VPMAXUWZ128rmkz, 0 }, 2958 { X86::VPMINSBZ128rrkz, X86::VPMINSBZ128rmkz, 0 }, 2959 { X86::VPMINSDZ128rrkz, X86::VPMINSDZ128rmkz, 0 }, 2960 { X86::VPMINSQZ128rrkz, X86::VPMINSQZ128rmkz, 0 }, 2961 { X86::VPMINSWZ128rrkz, X86::VPMINSWZ128rmkz, 0 }, 2962 { X86::VPMINUBZ128rrkz, X86::VPMINUBZ128rmkz, 0 }, 2963 { X86::VPMINUDZ128rrkz, X86::VPMINUDZ128rmkz, 0 }, 2964 { X86::VPMINUQZ128rrkz, X86::VPMINUQZ128rmkz, 0 }, 2965 { X86::VPMINUWZ128rrkz, X86::VPMINUWZ128rmkz, 0 }, 2966 { X86::VPMULDQZ128rrkz, X86::VPMULDQZ128rmkz, 0 }, 2967 { X86::VPMULLDZ128rrkz, X86::VPMULLDZ128rmkz, 0 }, 2968 { X86::VPMULLQZ128rrkz, X86::VPMULLQZ128rmkz, 0 }, 2969 { X86::VPMULLWZ128rrkz, X86::VPMULLWZ128rmkz, 0 }, 2970 { X86::VPMULUDQZ128rrkz, X86::VPMULUDQZ128rmkz, 0 }, 2971 { X86::VPORDZ128rrkz, X86::VPORDZ128rmkz, 0 }, 2972 { X86::VPORQZ128rrkz, X86::VPORQZ128rmkz, 0 }, 2973 { X86::VPSHUFBZ128rrkz, X86::VPSHUFBZ128rmkz, 0 }, 2974 { X86::VPSLLDZ128rrkz, X86::VPSLLDZ128rmkz, 0 }, 2975 { X86::VPSLLQZ128rrkz, X86::VPSLLQZ128rmkz, 0 }, 2976 { X86::VPSLLVDZ128rrkz, X86::VPSLLVDZ128rmkz, 0 }, 2977 { X86::VPSLLVQZ128rrkz, X86::VPSLLVQZ128rmkz, 0 }, 2978 { X86::VPSLLVWZ128rrkz, X86::VPSLLVWZ128rmkz, 0 }, 2979 { X86::VPSLLWZ128rrkz, X86::VPSLLWZ128rmkz, 0 }, 2980 { X86::VPSRADZ128rrkz, X86::VPSRADZ128rmkz, 0 }, 2981 { X86::VPSRAQZ128rrkz, X86::VPSRAQZ128rmkz, 0 }, 2982 { X86::VPSRAVDZ128rrkz, X86::VPSRAVDZ128rmkz, 0 }, 2983 { X86::VPSRAVQZ128rrkz, X86::VPSRAVQZ128rmkz, 0 }, 2984 { X86::VPSRAVWZ128rrkz, X86::VPSRAVWZ128rmkz, 0 }, 2985 { X86::VPSRAWZ128rrkz, X86::VPSRAWZ128rmkz, 0 }, 2986 { X86::VPSRLDZ128rrkz, X86::VPSRLDZ128rmkz, 0 }, 2987 { X86::VPSRLQZ128rrkz, X86::VPSRLQZ128rmkz, 0 }, 2988 { X86::VPSRLVDZ128rrkz, X86::VPSRLVDZ128rmkz, 0 }, 2989 { X86::VPSRLVQZ128rrkz, X86::VPSRLVQZ128rmkz, 0 }, 2990 { X86::VPSRLVWZ128rrkz, X86::VPSRLVWZ128rmkz, 0 }, 2991 { X86::VPSRLWZ128rrkz, X86::VPSRLWZ128rmkz, 0 }, 2992 { X86::VPSUBBZ128rrkz, X86::VPSUBBZ128rmkz, 0 }, 2993 { X86::VPSUBDZ128rrkz, X86::VPSUBDZ128rmkz, 0 }, 2994 { X86::VPSUBQZ128rrkz, X86::VPSUBQZ128rmkz, 0 }, 2995 { X86::VPSUBSBZ128rrkz, X86::VPSUBSBZ128rmkz, 0 }, 2996 { X86::VPSUBSWZ128rrkz, X86::VPSUBSWZ128rmkz, 0 }, 2997 { X86::VPSUBUSBZ128rrkz, X86::VPSUBUSBZ128rmkz, 0 }, 2998 { X86::VPSUBUSWZ128rrkz, X86::VPSUBUSWZ128rmkz, 0 }, 2999 { X86::VPSUBWZ128rrkz, X86::VPSUBWZ128rmkz, 0 }, 3000 { X86::VPUNPCKHBWZ128rrkz, X86::VPUNPCKHBWZ128rmkz, 0 }, 3001 { X86::VPUNPCKHDQZ128rrkz, X86::VPUNPCKHDQZ128rmkz, 0 }, 3002 { X86::VPUNPCKHQDQZ128rrkz, X86::VPUNPCKHQDQZ128rmkz, 0 }, 3003 { X86::VPUNPCKHWDZ128rrkz, X86::VPUNPCKHWDZ128rmkz, 0 }, 3004 { X86::VPUNPCKLBWZ128rrkz, X86::VPUNPCKLBWZ128rmkz, 0 }, 3005 { X86::VPUNPCKLDQZ128rrkz, X86::VPUNPCKLDQZ128rmkz, 0 }, 3006 { X86::VPUNPCKLQDQZ128rrkz, X86::VPUNPCKLQDQZ128rmkz, 0 }, 3007 { X86::VPUNPCKLWDZ128rrkz, X86::VPUNPCKLWDZ128rmkz, 0 }, 3008 { X86::VPXORDZ128rrkz, X86::VPXORDZ128rmkz, 0 }, 3009 { X86::VPXORQZ128rrkz, X86::VPXORQZ128rmkz, 0 }, 3010 { X86::VSHUFPDZ128rrikz, X86::VSHUFPDZ128rmikz, 0 }, 3011 { X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0 }, 3012 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 }, 3013 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 }, 3014 { X86::VUNPCKHPDZ128rrkz, X86::VUNPCKHPDZ128rmkz, 0 }, 3015 { X86::VUNPCKHPSZ128rrkz, X86::VUNPCKHPSZ128rmkz, 0 }, 3016 { X86::VUNPCKLPDZ128rrkz, X86::VUNPCKLPDZ128rmkz, 0 }, 3017 { X86::VUNPCKLPSZ128rrkz, X86::VUNPCKLPSZ128rmkz, 0 }, 3018 { X86::VXORPDZ128rrkz, X86::VXORPDZ128rmkz, 0 }, 3019 { X86::VXORPSZ128rrkz, X86::VXORPSZ128rmkz, 0 }, 3020 3021 // AVX-512 masked foldable instructions 3022 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE }, 3023 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE }, 3024 { X86::VPABSBZrrk, X86::VPABSBZrmk, 0 }, 3025 { X86::VPABSDZrrk, X86::VPABSDZrmk, 0 }, 3026 { X86::VPABSQZrrk, X86::VPABSQZrmk, 0 }, 3027 { X86::VPABSWZrrk, X86::VPABSWZrmk, 0 }, 3028 { X86::VPCONFLICTDZrrk, X86::VPCONFLICTDZrmk, 0 }, 3029 { X86::VPCONFLICTQZrrk, X86::VPCONFLICTQZrmk, 0 }, 3030 { X86::VPERMILPDZrik, X86::VPERMILPDZmik, 0 }, 3031 { X86::VPERMILPSZrik, X86::VPERMILPSZmik, 0 }, 3032 { X86::VPERMPDZrik, X86::VPERMPDZmik, 0 }, 3033 { X86::VPERMQZrik, X86::VPERMQZmik, 0 }, 3034 { X86::VPLZCNTDZrrk, X86::VPLZCNTDZrmk, 0 }, 3035 { X86::VPLZCNTQZrrk, X86::VPLZCNTQZrmk, 0 }, 3036 { X86::VPMOVSXBDZrrk, X86::VPMOVSXBDZrmk, 0 }, 3037 { X86::VPMOVSXBQZrrk, X86::VPMOVSXBQZrmk, TB_NO_REVERSE }, 3038 { X86::VPMOVSXBWZrrk, X86::VPMOVSXBWZrmk, 0 }, 3039 { X86::VPMOVSXDQZrrk, X86::VPMOVSXDQZrmk, 0 }, 3040 { X86::VPMOVSXWDZrrk, X86::VPMOVSXWDZrmk, 0 }, 3041 { X86::VPMOVSXWQZrrk, X86::VPMOVSXWQZrmk, 0 }, 3042 { X86::VPMOVZXBDZrrk, X86::VPMOVZXBDZrmk, 0 }, 3043 { X86::VPMOVZXBQZrrk, X86::VPMOVZXBQZrmk, TB_NO_REVERSE }, 3044 { X86::VPMOVZXBWZrrk, X86::VPMOVZXBWZrmk, 0 }, 3045 { X86::VPMOVZXDQZrrk, X86::VPMOVZXDQZrmk, 0 }, 3046 { X86::VPMOVZXWDZrrk, X86::VPMOVZXWDZrmk, 0 }, 3047 { X86::VPMOVZXWQZrrk, X86::VPMOVZXWQZrmk, 0 }, 3048 { X86::VPOPCNTDZrrk, X86::VPOPCNTDZrmk, 0 }, 3049 { X86::VPOPCNTQZrrk, X86::VPOPCNTQZrmk, 0 }, 3050 { X86::VPSHUFDZrik, X86::VPSHUFDZmik, 0 }, 3051 { X86::VPSHUFHWZrik, X86::VPSHUFHWZmik, 0 }, 3052 { X86::VPSHUFLWZrik, X86::VPSHUFLWZmik, 0 }, 3053 { X86::VPSLLDZrik, X86::VPSLLDZmik, 0 }, 3054 { X86::VPSLLQZrik, X86::VPSLLQZmik, 0 }, 3055 { X86::VPSLLWZrik, X86::VPSLLWZmik, 0 }, 3056 { X86::VPSRADZrik, X86::VPSRADZmik, 0 }, 3057 { X86::VPSRAQZrik, X86::VPSRAQZmik, 0 }, 3058 { X86::VPSRAWZrik, X86::VPSRAWZmik, 0 }, 3059 { X86::VPSRLDZrik, X86::VPSRLDZmik, 0 }, 3060 { X86::VPSRLQZrik, X86::VPSRLQZmik, 0 }, 3061 { X86::VPSRLWZrik, X86::VPSRLWZmik, 0 }, 3062 3063 // AVX-512VL 256-bit masked foldable instructions 3064 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE }, 3065 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE }, 3066 { X86::VPABSBZ256rrk, X86::VPABSBZ256rmk, 0 }, 3067 { X86::VPABSDZ256rrk, X86::VPABSDZ256rmk, 0 }, 3068 { X86::VPABSQZ256rrk, X86::VPABSQZ256rmk, 0 }, 3069 { X86::VPABSWZ256rrk, X86::VPABSWZ256rmk, 0 }, 3070 { X86::VPCONFLICTDZ256rrk, X86::VPCONFLICTDZ256rmk, 0 }, 3071 { X86::VPCONFLICTQZ256rrk, X86::VPCONFLICTQZ256rmk, 0 }, 3072 { X86::VPERMILPDZ256rik, X86::VPERMILPDZ256mik, 0 }, 3073 { X86::VPERMILPSZ256rik, X86::VPERMILPSZ256mik, 0 }, 3074 { X86::VPERMPDZ256rik, X86::VPERMPDZ256mik, 0 }, 3075 { X86::VPERMQZ256rik, X86::VPERMQZ256mik, 0 }, 3076 { X86::VPLZCNTDZ256rrk, X86::VPLZCNTDZ256rmk, 0 }, 3077 { X86::VPLZCNTQZ256rrk, X86::VPLZCNTQZ256rmk, 0 }, 3078 { X86::VPMOVSXBDZ256rrk, X86::VPMOVSXBDZ256rmk, TB_NO_REVERSE }, 3079 { X86::VPMOVSXBQZ256rrk, X86::VPMOVSXBQZ256rmk, TB_NO_REVERSE }, 3080 { X86::VPMOVSXBWZ256rrk, X86::VPMOVSXBWZ256rmk, 0 }, 3081 { X86::VPMOVSXDQZ256rrk, X86::VPMOVSXDQZ256rmk, 0 }, 3082 { X86::VPMOVSXWDZ256rrk, X86::VPMOVSXWDZ256rmk, 0 }, 3083 { X86::VPMOVSXWQZ256rrk, X86::VPMOVSXWQZ256rmk, TB_NO_REVERSE }, 3084 { X86::VPMOVZXBDZ256rrk, X86::VPMOVZXBDZ256rmk, TB_NO_REVERSE }, 3085 { X86::VPMOVZXBQZ256rrk, X86::VPMOVZXBQZ256rmk, TB_NO_REVERSE }, 3086 { X86::VPMOVZXBWZ256rrk, X86::VPMOVZXBWZ256rmk, 0 }, 3087 { X86::VPMOVZXDQZ256rrk, X86::VPMOVZXDQZ256rmk, 0 }, 3088 { X86::VPMOVZXWDZ256rrk, X86::VPMOVZXWDZ256rmk, 0 }, 3089 { X86::VPMOVZXWQZ256rrk, X86::VPMOVZXWQZ256rmk, TB_NO_REVERSE }, 3090 { X86::VPSHUFDZ256rik, X86::VPSHUFDZ256mik, 0 }, 3091 { X86::VPSHUFHWZ256rik, X86::VPSHUFHWZ256mik, 0 }, 3092 { X86::VPSHUFLWZ256rik, X86::VPSHUFLWZ256mik, 0 }, 3093 { X86::VPSLLDZ256rik, X86::VPSLLDZ256mik, 0 }, 3094 { X86::VPSLLQZ256rik, X86::VPSLLQZ256mik, 0 }, 3095 { X86::VPSLLWZ256rik, X86::VPSLLWZ256mik, 0 }, 3096 { X86::VPSRADZ256rik, X86::VPSRADZ256mik, 0 }, 3097 { X86::VPSRAQZ256rik, X86::VPSRAQZ256mik, 0 }, 3098 { X86::VPSRAWZ256rik, X86::VPSRAWZ256mik, 0 }, 3099 { X86::VPSRLDZ256rik, X86::VPSRLDZ256mik, 0 }, 3100 { X86::VPSRLQZ256rik, X86::VPSRLQZ256mik, 0 }, 3101 { X86::VPSRLWZ256rik, X86::VPSRLWZ256mik, 0 }, 3102 3103 // AVX-512VL 128-bit masked foldable instructions 3104 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE }, 3105 { X86::VPABSBZ128rrk, X86::VPABSBZ128rmk, 0 }, 3106 { X86::VPABSDZ128rrk, X86::VPABSDZ128rmk, 0 }, 3107 { X86::VPABSQZ128rrk, X86::VPABSQZ128rmk, 0 }, 3108 { X86::VPABSWZ128rrk, X86::VPABSWZ128rmk, 0 }, 3109 { X86::VPCONFLICTDZ128rrk, X86::VPCONFLICTDZ128rmk, 0 }, 3110 { X86::VPCONFLICTQZ128rrk, X86::VPCONFLICTQZ128rmk, 0 }, 3111 { X86::VPERMILPDZ128rik, X86::VPERMILPDZ128mik, 0 }, 3112 { X86::VPERMILPSZ128rik, X86::VPERMILPSZ128mik, 0 }, 3113 { X86::VPLZCNTDZ128rrk, X86::VPLZCNTDZ128rmk, 0 }, 3114 { X86::VPLZCNTQZ128rrk, X86::VPLZCNTQZ128rmk, 0 }, 3115 { X86::VPMOVSXBDZ128rrk, X86::VPMOVSXBDZ128rmk, TB_NO_REVERSE }, 3116 { X86::VPMOVSXBQZ128rrk, X86::VPMOVSXBQZ128rmk, TB_NO_REVERSE }, 3117 { X86::VPMOVSXBWZ128rrk, X86::VPMOVSXBWZ128rmk, TB_NO_REVERSE }, 3118 { X86::VPMOVSXDQZ128rrk, X86::VPMOVSXDQZ128rmk, TB_NO_REVERSE }, 3119 { X86::VPMOVSXWDZ128rrk, X86::VPMOVSXWDZ128rmk, TB_NO_REVERSE }, 3120 { X86::VPMOVSXWQZ128rrk, X86::VPMOVSXWQZ128rmk, TB_NO_REVERSE }, 3121 { X86::VPMOVZXBDZ128rrk, X86::VPMOVZXBDZ128rmk, TB_NO_REVERSE }, 3122 { X86::VPMOVZXBQZ128rrk, X86::VPMOVZXBQZ128rmk, TB_NO_REVERSE }, 3123 { X86::VPMOVZXBWZ128rrk, X86::VPMOVZXBWZ128rmk, TB_NO_REVERSE }, 3124 { X86::VPMOVZXDQZ128rrk, X86::VPMOVZXDQZ128rmk, TB_NO_REVERSE }, 3125 { X86::VPMOVZXWDZ128rrk, X86::VPMOVZXWDZ128rmk, TB_NO_REVERSE }, 3126 { X86::VPMOVZXWQZ128rrk, X86::VPMOVZXWQZ128rmk, TB_NO_REVERSE }, 3127 { X86::VPSHUFDZ128rik, X86::VPSHUFDZ128mik, 0 }, 3128 { X86::VPSHUFHWZ128rik, X86::VPSHUFHWZ128mik, 0 }, 3129 { X86::VPSHUFLWZ128rik, X86::VPSHUFLWZ128mik, 0 }, 3130 { X86::VPSLLDZ128rik, X86::VPSLLDZ128mik, 0 }, 3131 { X86::VPSLLQZ128rik, X86::VPSLLQZ128mik, 0 }, 3132 { X86::VPSLLWZ128rik, X86::VPSLLWZ128mik, 0 }, 3133 { X86::VPSRADZ128rik, X86::VPSRADZ128mik, 0 }, 3134 { X86::VPSRAQZ128rik, X86::VPSRAQZ128mik, 0 }, 3135 { X86::VPSRAWZ128rik, X86::VPSRAWZ128mik, 0 }, 3136 { X86::VPSRLDZ128rik, X86::VPSRLDZ128mik, 0 }, 3137 { X86::VPSRLQZ128rik, X86::VPSRLQZ128mik, 0 }, 3138 { X86::VPSRLWZ128rik, X86::VPSRLWZ128mik, 0 }, 3139 3140 // AVX-512 masked compare instructions 3141 { X86::VCMPPDZ128rrik, X86::VCMPPDZ128rmik, 0 }, 3142 { X86::VCMPPSZ128rrik, X86::VCMPPSZ128rmik, 0 }, 3143 { X86::VCMPPDZ256rrik, X86::VCMPPDZ256rmik, 0 }, 3144 { X86::VCMPPSZ256rrik, X86::VCMPPSZ256rmik, 0 }, 3145 { X86::VCMPPDZrrik, X86::VCMPPDZrmik, 0 }, 3146 { X86::VCMPPSZrrik, X86::VCMPPSZrmik, 0 }, 3147 { X86::VCMPSDZrr_Intk, X86::VCMPSDZrm_Intk, TB_NO_REVERSE }, 3148 { X86::VCMPSSZrr_Intk, X86::VCMPSSZrm_Intk, TB_NO_REVERSE }, 3149 { X86::VPCMPBZ128rrik, X86::VPCMPBZ128rmik, 0 }, 3150 { X86::VPCMPBZ256rrik, X86::VPCMPBZ256rmik, 0 }, 3151 { X86::VPCMPBZrrik, X86::VPCMPBZrmik, 0 }, 3152 { X86::VPCMPDZ128rrik, X86::VPCMPDZ128rmik, 0 }, 3153 { X86::VPCMPDZ256rrik, X86::VPCMPDZ256rmik, 0 }, 3154 { X86::VPCMPDZrrik, X86::VPCMPDZrmik, 0 }, 3155 { X86::VPCMPEQBZ128rrk, X86::VPCMPEQBZ128rmk, 0 }, 3156 { X86::VPCMPEQBZ256rrk, X86::VPCMPEQBZ256rmk, 0 }, 3157 { X86::VPCMPEQBZrrk, X86::VPCMPEQBZrmk, 0 }, 3158 { X86::VPCMPEQDZ128rrk, X86::VPCMPEQDZ128rmk, 0 }, 3159 { X86::VPCMPEQDZ256rrk, X86::VPCMPEQDZ256rmk, 0 }, 3160 { X86::VPCMPEQDZrrk, X86::VPCMPEQDZrmk, 0 }, 3161 { X86::VPCMPEQQZ128rrk, X86::VPCMPEQQZ128rmk, 0 }, 3162 { X86::VPCMPEQQZ256rrk, X86::VPCMPEQQZ256rmk, 0 }, 3163 { X86::VPCMPEQQZrrk, X86::VPCMPEQQZrmk, 0 }, 3164 { X86::VPCMPEQWZ128rrk, X86::VPCMPEQWZ128rmk, 0 }, 3165 { X86::VPCMPEQWZ256rrk, X86::VPCMPEQWZ256rmk, 0 }, 3166 { X86::VPCMPEQWZrrk, X86::VPCMPEQWZrmk, 0 }, 3167 { X86::VPCMPGTBZ128rrk, X86::VPCMPGTBZ128rmk, 0 }, 3168 { X86::VPCMPGTBZ256rrk, X86::VPCMPGTBZ256rmk, 0 }, 3169 { X86::VPCMPGTBZrrk, X86::VPCMPGTBZrmk, 0 }, 3170 { X86::VPCMPGTDZ128rrk, X86::VPCMPGTDZ128rmk, 0 }, 3171 { X86::VPCMPGTDZ256rrk, X86::VPCMPGTDZ256rmk, 0 }, 3172 { X86::VPCMPGTDZrrk, X86::VPCMPGTDZrmk, 0 }, 3173 { X86::VPCMPGTQZ128rrk, X86::VPCMPGTQZ128rmk, 0 }, 3174 { X86::VPCMPGTQZ256rrk, X86::VPCMPGTQZ256rmk, 0 }, 3175 { X86::VPCMPGTQZrrk, X86::VPCMPGTQZrmk, 0 }, 3176 { X86::VPCMPGTWZ128rrk, X86::VPCMPGTWZ128rmk, 0 }, 3177 { X86::VPCMPGTWZ256rrk, X86::VPCMPGTWZ256rmk, 0 }, 3178 { X86::VPCMPGTWZrrk, X86::VPCMPGTWZrmk, 0 }, 3179 { X86::VPCMPQZ128rrik, X86::VPCMPQZ128rmik, 0 }, 3180 { X86::VPCMPQZ256rrik, X86::VPCMPQZ256rmik, 0 }, 3181 { X86::VPCMPQZrrik, X86::VPCMPQZrmik, 0 }, 3182 { X86::VPCMPUBZ128rrik, X86::VPCMPUBZ128rmik, 0 }, 3183 { X86::VPCMPUBZ256rrik, X86::VPCMPUBZ256rmik, 0 }, 3184 { X86::VPCMPUBZrrik, X86::VPCMPUBZrmik, 0 }, 3185 { X86::VPCMPUDZ128rrik, X86::VPCMPUDZ128rmik, 0 }, 3186 { X86::VPCMPUDZ256rrik, X86::VPCMPUDZ256rmik, 0 }, 3187 { X86::VPCMPUDZrrik, X86::VPCMPUDZrmik, 0 }, 3188 { X86::VPCMPUQZ128rrik, X86::VPCMPUQZ128rmik, 0 }, 3189 { X86::VPCMPUQZ256rrik, X86::VPCMPUQZ256rmik, 0 }, 3190 { X86::VPCMPUQZrrik, X86::VPCMPUQZrmik, 0 }, 3191 { X86::VPCMPUWZ128rrik, X86::VPCMPUWZ128rmik, 0 }, 3192 { X86::VPCMPUWZ256rrik, X86::VPCMPUWZ256rmik, 0 }, 3193 { X86::VPCMPUWZrrik, X86::VPCMPUWZrmik, 0 }, 3194 { X86::VPCMPWZ128rrik, X86::VPCMPWZ128rmik, 0 }, 3195 { X86::VPCMPWZ256rrik, X86::VPCMPWZ256rmik, 0 }, 3196 { X86::VPCMPWZrrik, X86::VPCMPWZrmik, 0 }, 3197 }; 3198 3199 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) { 3200 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 3201 Entry.RegOp, Entry.MemOp, 3202 // Index 3, folded load 3203 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 3204 } 3205 auto I = X86InstrFMA3Info::rm_begin(); 3206 auto E = X86InstrFMA3Info::rm_end(); 3207 for (; I != E; ++I) { 3208 if (!I.getGroup()->isKMasked()) { 3209 // Intrinsic forms need to pass TB_NO_REVERSE. 3210 if (I.getGroup()->isIntrinsic()) { 3211 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 3212 I.getRegOpcode(), I.getMemOpcode(), 3213 TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE); 3214 } else { 3215 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 3216 I.getRegOpcode(), I.getMemOpcode(), 3217 TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD); 3218 } 3219 } 3220 } 3221 3222 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = { 3223 // AVX-512 foldable masked instructions 3224 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 }, 3225 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 }, 3226 { X86::VADDSDZrr_Intk, X86::VADDSDZrm_Intk, TB_NO_REVERSE }, 3227 { X86::VADDSSZrr_Intk, X86::VADDSSZrm_Intk, TB_NO_REVERSE }, 3228 { X86::VALIGNDZrrik, X86::VALIGNDZrmik, 0 }, 3229 { X86::VALIGNQZrrik, X86::VALIGNQZrmik, 0 }, 3230 { X86::VANDNPDZrrk, X86::VANDNPDZrmk, 0 }, 3231 { X86::VANDNPSZrrk, X86::VANDNPSZrmk, 0 }, 3232 { X86::VANDPDZrrk, X86::VANDPDZrmk, 0 }, 3233 { X86::VANDPSZrrk, X86::VANDPSZrmk, 0 }, 3234 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 }, 3235 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 }, 3236 { X86::VDIVSDZrr_Intk, X86::VDIVSDZrm_Intk, TB_NO_REVERSE }, 3237 { X86::VDIVSSZrr_Intk, X86::VDIVSSZrm_Intk, TB_NO_REVERSE }, 3238 { X86::VINSERTF32x4Zrrk, X86::VINSERTF32x4Zrmk, 0 }, 3239 { X86::VINSERTF32x8Zrrk, X86::VINSERTF32x8Zrmk, 0 }, 3240 { X86::VINSERTF64x2Zrrk, X86::VINSERTF64x2Zrmk, 0 }, 3241 { X86::VINSERTF64x4Zrrk, X86::VINSERTF64x4Zrmk, 0 }, 3242 { X86::VINSERTI32x4Zrrk, X86::VINSERTI32x4Zrmk, 0 }, 3243 { X86::VINSERTI32x8Zrrk, X86::VINSERTI32x8Zrmk, 0 }, 3244 { X86::VINSERTI64x2Zrrk, X86::VINSERTI64x2Zrmk, 0 }, 3245 { X86::VINSERTI64x4Zrrk, X86::VINSERTI64x4Zrmk, 0 }, 3246 { X86::VMAXCPDZrrk, X86::VMAXCPDZrmk, 0 }, 3247 { X86::VMAXCPSZrrk, X86::VMAXCPSZrmk, 0 }, 3248 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 }, 3249 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 }, 3250 { X86::VMAXSDZrr_Intk, X86::VMAXSDZrm_Intk, 0 }, 3251 { X86::VMAXSSZrr_Intk, X86::VMAXSSZrm_Intk, 0 }, 3252 { X86::VMINCPDZrrk, X86::VMINCPDZrmk, 0 }, 3253 { X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0 }, 3254 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 }, 3255 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 }, 3256 { X86::VMINSDZrr_Intk, X86::VMINSDZrm_Intk, 0 }, 3257 { X86::VMINSSZrr_Intk, X86::VMINSSZrm_Intk, 0 }, 3258 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 }, 3259 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 }, 3260 { X86::VMULSDZrr_Intk, X86::VMULSDZrm_Intk, TB_NO_REVERSE }, 3261 { X86::VMULSSZrr_Intk, X86::VMULSSZrm_Intk, TB_NO_REVERSE }, 3262 { X86::VORPDZrrk, X86::VORPDZrmk, 0 }, 3263 { X86::VORPSZrrk, X86::VORPSZrmk, 0 }, 3264 { X86::VPACKSSDWZrrk, X86::VPACKSSDWZrmk, 0 }, 3265 { X86::VPACKSSWBZrrk, X86::VPACKSSWBZrmk, 0 }, 3266 { X86::VPACKUSDWZrrk, X86::VPACKUSDWZrmk, 0 }, 3267 { X86::VPACKUSWBZrrk, X86::VPACKUSWBZrmk, 0 }, 3268 { X86::VPADDBZrrk, X86::VPADDBZrmk, 0 }, 3269 { X86::VPADDDZrrk, X86::VPADDDZrmk, 0 }, 3270 { X86::VPADDQZrrk, X86::VPADDQZrmk, 0 }, 3271 { X86::VPADDSBZrrk, X86::VPADDSBZrmk, 0 }, 3272 { X86::VPADDSWZrrk, X86::VPADDSWZrmk, 0 }, 3273 { X86::VPADDUSBZrrk, X86::VPADDUSBZrmk, 0 }, 3274 { X86::VPADDUSWZrrk, X86::VPADDUSWZrmk, 0 }, 3275 { X86::VPADDWZrrk, X86::VPADDWZrmk, 0 }, 3276 { X86::VPALIGNRZrrik, X86::VPALIGNRZrmik, 0 }, 3277 { X86::VPANDDZrrk, X86::VPANDDZrmk, 0 }, 3278 { X86::VPANDNDZrrk, X86::VPANDNDZrmk, 0 }, 3279 { X86::VPANDNQZrrk, X86::VPANDNQZrmk, 0 }, 3280 { X86::VPANDQZrrk, X86::VPANDQZrmk, 0 }, 3281 { X86::VPAVGBZrrk, X86::VPAVGBZrmk, 0 }, 3282 { X86::VPAVGWZrrk, X86::VPAVGWZrmk, 0 }, 3283 { X86::VPERMBZrrk, X86::VPERMBZrmk, 0 }, 3284 { X86::VPERMDZrrk, X86::VPERMDZrmk, 0 }, 3285 { X86::VPERMI2Brrk, X86::VPERMI2Brmk, 0 }, 3286 { X86::VPERMI2Drrk, X86::VPERMI2Drmk, 0 }, 3287 { X86::VPERMI2PSrrk, X86::VPERMI2PSrmk, 0 }, 3288 { X86::VPERMI2PDrrk, X86::VPERMI2PDrmk, 0 }, 3289 { X86::VPERMI2Qrrk, X86::VPERMI2Qrmk, 0 }, 3290 { X86::VPERMI2Wrrk, X86::VPERMI2Wrmk, 0 }, 3291 { X86::VPERMILPDZrrk, X86::VPERMILPDZrmk, 0 }, 3292 { X86::VPERMILPSZrrk, X86::VPERMILPSZrmk, 0 }, 3293 { X86::VPERMPDZrrk, X86::VPERMPDZrmk, 0 }, 3294 { X86::VPERMPSZrrk, X86::VPERMPSZrmk, 0 }, 3295 { X86::VPERMQZrrk, X86::VPERMQZrmk, 0 }, 3296 { X86::VPERMT2Brrk, X86::VPERMT2Brmk, 0 }, 3297 { X86::VPERMT2Drrk, X86::VPERMT2Drmk, 0 }, 3298 { X86::VPERMT2PSrrk, X86::VPERMT2PSrmk, 0 }, 3299 { X86::VPERMT2PDrrk, X86::VPERMT2PDrmk, 0 }, 3300 { X86::VPERMT2Qrrk, X86::VPERMT2Qrmk, 0 }, 3301 { X86::VPERMT2Wrrk, X86::VPERMT2Wrmk, 0 }, 3302 { X86::VPERMWZrrk, X86::VPERMWZrmk, 0 }, 3303 { X86::VPMADD52HUQZrk, X86::VPMADD52HUQZmk, 0 }, 3304 { X86::VPMADD52LUQZrk, X86::VPMADD52LUQZmk, 0 }, 3305 { X86::VPMADDUBSWZrrk, X86::VPMADDUBSWZrmk, 0 }, 3306 { X86::VPMADDWDZrrk, X86::VPMADDWDZrmk, 0 }, 3307 { X86::VPMAXSBZrrk, X86::VPMAXSBZrmk, 0 }, 3308 { X86::VPMAXSDZrrk, X86::VPMAXSDZrmk, 0 }, 3309 { X86::VPMAXSQZrrk, X86::VPMAXSQZrmk, 0 }, 3310 { X86::VPMAXSWZrrk, X86::VPMAXSWZrmk, 0 }, 3311 { X86::VPMAXUBZrrk, X86::VPMAXUBZrmk, 0 }, 3312 { X86::VPMAXUDZrrk, X86::VPMAXUDZrmk, 0 }, 3313 { X86::VPMAXUQZrrk, X86::VPMAXUQZrmk, 0 }, 3314 { X86::VPMAXUWZrrk, X86::VPMAXUWZrmk, 0 }, 3315 { X86::VPMINSBZrrk, X86::VPMINSBZrmk, 0 }, 3316 { X86::VPMINSDZrrk, X86::VPMINSDZrmk, 0 }, 3317 { X86::VPMINSQZrrk, X86::VPMINSQZrmk, 0 }, 3318 { X86::VPMINSWZrrk, X86::VPMINSWZrmk, 0 }, 3319 { X86::VPMINUBZrrk, X86::VPMINUBZrmk, 0 }, 3320 { X86::VPMINUDZrrk, X86::VPMINUDZrmk, 0 }, 3321 { X86::VPMINUQZrrk, X86::VPMINUQZrmk, 0 }, 3322 { X86::VPMINUWZrrk, X86::VPMINUWZrmk, 0 }, 3323 { X86::VPMULDQZrrk, X86::VPMULDQZrmk, 0 }, 3324 { X86::VPMULLDZrrk, X86::VPMULLDZrmk, 0 }, 3325 { X86::VPMULLQZrrk, X86::VPMULLQZrmk, 0 }, 3326 { X86::VPMULLWZrrk, X86::VPMULLWZrmk, 0 }, 3327 { X86::VPMULUDQZrrk, X86::VPMULUDQZrmk, 0 }, 3328 { X86::VPORDZrrk, X86::VPORDZrmk, 0 }, 3329 { X86::VPORQZrrk, X86::VPORQZrmk, 0 }, 3330 { X86::VPSHUFBZrrk, X86::VPSHUFBZrmk, 0 }, 3331 { X86::VPSLLDZrrk, X86::VPSLLDZrmk, 0 }, 3332 { X86::VPSLLQZrrk, X86::VPSLLQZrmk, 0 }, 3333 { X86::VPSLLVDZrrk, X86::VPSLLVDZrmk, 0 }, 3334 { X86::VPSLLVQZrrk, X86::VPSLLVQZrmk, 0 }, 3335 { X86::VPSLLVWZrrk, X86::VPSLLVWZrmk, 0 }, 3336 { X86::VPSLLWZrrk, X86::VPSLLWZrmk, 0 }, 3337 { X86::VPSRADZrrk, X86::VPSRADZrmk, 0 }, 3338 { X86::VPSRAQZrrk, X86::VPSRAQZrmk, 0 }, 3339 { X86::VPSRAVDZrrk, X86::VPSRAVDZrmk, 0 }, 3340 { X86::VPSRAVQZrrk, X86::VPSRAVQZrmk, 0 }, 3341 { X86::VPSRAVWZrrk, X86::VPSRAVWZrmk, 0 }, 3342 { X86::VPSRAWZrrk, X86::VPSRAWZrmk, 0 }, 3343 { X86::VPSRLDZrrk, X86::VPSRLDZrmk, 0 }, 3344 { X86::VPSRLQZrrk, X86::VPSRLQZrmk, 0 }, 3345 { X86::VPSRLVDZrrk, X86::VPSRLVDZrmk, 0 }, 3346 { X86::VPSRLVQZrrk, X86::VPSRLVQZrmk, 0 }, 3347 { X86::VPSRLVWZrrk, X86::VPSRLVWZrmk, 0 }, 3348 { X86::VPSRLWZrrk, X86::VPSRLWZrmk, 0 }, 3349 { X86::VPSUBBZrrk, X86::VPSUBBZrmk, 0 }, 3350 { X86::VPSUBDZrrk, X86::VPSUBDZrmk, 0 }, 3351 { X86::VPSUBQZrrk, X86::VPSUBQZrmk, 0 }, 3352 { X86::VPSUBSBZrrk, X86::VPSUBSBZrmk, 0 }, 3353 { X86::VPSUBSWZrrk, X86::VPSUBSWZrmk, 0 }, 3354 { X86::VPSUBUSBZrrk, X86::VPSUBUSBZrmk, 0 }, 3355 { X86::VPSUBUSWZrrk, X86::VPSUBUSWZrmk, 0 }, 3356 { X86::VPTERNLOGDZrrik, X86::VPTERNLOGDZrmik, 0 }, 3357 { X86::VPTERNLOGQZrrik, X86::VPTERNLOGQZrmik, 0 }, 3358 { X86::VPUNPCKHBWZrrk, X86::VPUNPCKHBWZrmk, 0 }, 3359 { X86::VPUNPCKHDQZrrk, X86::VPUNPCKHDQZrmk, 0 }, 3360 { X86::VPUNPCKHQDQZrrk, X86::VPUNPCKHQDQZrmk, 0 }, 3361 { X86::VPUNPCKHWDZrrk, X86::VPUNPCKHWDZrmk, 0 }, 3362 { X86::VPUNPCKLBWZrrk, X86::VPUNPCKLBWZrmk, 0 }, 3363 { X86::VPUNPCKLDQZrrk, X86::VPUNPCKLDQZrmk, 0 }, 3364 { X86::VPUNPCKLQDQZrrk, X86::VPUNPCKLQDQZrmk, 0 }, 3365 { X86::VPUNPCKLWDZrrk, X86::VPUNPCKLWDZrmk, 0 }, 3366 { X86::VPXORDZrrk, X86::VPXORDZrmk, 0 }, 3367 { X86::VPXORQZrrk, X86::VPXORQZrmk, 0 }, 3368 { X86::VSHUFPDZrrik, X86::VSHUFPDZrmik, 0 }, 3369 { X86::VSHUFPSZrrik, X86::VSHUFPSZrmik, 0 }, 3370 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 }, 3371 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 }, 3372 { X86::VSUBSDZrr_Intk, X86::VSUBSDZrm_Intk, TB_NO_REVERSE }, 3373 { X86::VSUBSSZrr_Intk, X86::VSUBSSZrm_Intk, TB_NO_REVERSE }, 3374 { X86::VUNPCKHPDZrrk, X86::VUNPCKHPDZrmk, 0 }, 3375 { X86::VUNPCKHPSZrrk, X86::VUNPCKHPSZrmk, 0 }, 3376 { X86::VUNPCKLPDZrrk, X86::VUNPCKLPDZrmk, 0 }, 3377 { X86::VUNPCKLPSZrrk, X86::VUNPCKLPSZrmk, 0 }, 3378 { X86::VXORPDZrrk, X86::VXORPDZrmk, 0 }, 3379 { X86::VXORPSZrrk, X86::VXORPSZrmk, 0 }, 3380 3381 // AVX-512{F,VL} foldable masked instructions 256-bit 3382 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 }, 3383 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 }, 3384 { X86::VALIGNDZ256rrik, X86::VALIGNDZ256rmik, 0 }, 3385 { X86::VALIGNQZ256rrik, X86::VALIGNQZ256rmik, 0 }, 3386 { X86::VANDNPDZ256rrk, X86::VANDNPDZ256rmk, 0 }, 3387 { X86::VANDNPSZ256rrk, X86::VANDNPSZ256rmk, 0 }, 3388 { X86::VANDPDZ256rrk, X86::VANDPDZ256rmk, 0 }, 3389 { X86::VANDPSZ256rrk, X86::VANDPSZ256rmk, 0 }, 3390 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 }, 3391 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 }, 3392 { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk, 0 }, 3393 { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk, 0 }, 3394 { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk, 0 }, 3395 { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk, 0 }, 3396 { X86::VMAXCPDZ256rrk, X86::VMAXCPDZ256rmk, 0 }, 3397 { X86::VMAXCPSZ256rrk, X86::VMAXCPSZ256rmk, 0 }, 3398 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 }, 3399 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 }, 3400 { X86::VMINCPDZ256rrk, X86::VMINCPDZ256rmk, 0 }, 3401 { X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmk, 0 }, 3402 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 }, 3403 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 }, 3404 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 }, 3405 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 }, 3406 { X86::VORPDZ256rrk, X86::VORPDZ256rmk, 0 }, 3407 { X86::VORPSZ256rrk, X86::VORPSZ256rmk, 0 }, 3408 { X86::VPACKSSDWZ256rrk, X86::VPACKSSDWZ256rmk, 0 }, 3409 { X86::VPACKSSWBZ256rrk, X86::VPACKSSWBZ256rmk, 0 }, 3410 { X86::VPACKUSDWZ256rrk, X86::VPACKUSDWZ256rmk, 0 }, 3411 { X86::VPACKUSWBZ256rrk, X86::VPACKUSWBZ256rmk, 0 }, 3412 { X86::VPADDBZ256rrk, X86::VPADDBZ256rmk, 0 }, 3413 { X86::VPADDDZ256rrk, X86::VPADDDZ256rmk, 0 }, 3414 { X86::VPADDQZ256rrk, X86::VPADDQZ256rmk, 0 }, 3415 { X86::VPADDSBZ256rrk, X86::VPADDSBZ256rmk, 0 }, 3416 { X86::VPADDSWZ256rrk, X86::VPADDSWZ256rmk, 0 }, 3417 { X86::VPADDUSBZ256rrk, X86::VPADDUSBZ256rmk, 0 }, 3418 { X86::VPADDUSWZ256rrk, X86::VPADDUSWZ256rmk, 0 }, 3419 { X86::VPADDWZ256rrk, X86::VPADDWZ256rmk, 0 }, 3420 { X86::VPALIGNRZ256rrik, X86::VPALIGNRZ256rmik, 0 }, 3421 { X86::VPANDDZ256rrk, X86::VPANDDZ256rmk, 0 }, 3422 { X86::VPANDNDZ256rrk, X86::VPANDNDZ256rmk, 0 }, 3423 { X86::VPANDNQZ256rrk, X86::VPANDNQZ256rmk, 0 }, 3424 { X86::VPANDQZ256rrk, X86::VPANDQZ256rmk, 0 }, 3425 { X86::VPAVGBZ256rrk, X86::VPAVGBZ256rmk, 0 }, 3426 { X86::VPAVGWZ256rrk, X86::VPAVGWZ256rmk, 0 }, 3427 { X86::VPERMBZ256rrk, X86::VPERMBZ256rmk, 0 }, 3428 { X86::VPERMDZ256rrk, X86::VPERMDZ256rmk, 0 }, 3429 { X86::VPERMI2B256rrk, X86::VPERMI2B256rmk, 0 }, 3430 { X86::VPERMI2D256rrk, X86::VPERMI2D256rmk, 0 }, 3431 { X86::VPERMI2PD256rrk, X86::VPERMI2PD256rmk, 0 }, 3432 { X86::VPERMI2PS256rrk, X86::VPERMI2PS256rmk, 0 }, 3433 { X86::VPERMI2Q256rrk, X86::VPERMI2Q256rmk, 0 }, 3434 { X86::VPERMI2W256rrk, X86::VPERMI2W256rmk, 0 }, 3435 { X86::VPERMILPDZ256rrk, X86::VPERMILPDZ256rmk, 0 }, 3436 { X86::VPERMILPSZ256rrk, X86::VPERMILPSZ256rmk, 0 }, 3437 { X86::VPERMPDZ256rrk, X86::VPERMPDZ256rmk, 0 }, 3438 { X86::VPERMPSZ256rrk, X86::VPERMPSZ256rmk, 0 }, 3439 { X86::VPERMQZ256rrk, X86::VPERMQZ256rmk, 0 }, 3440 { X86::VPERMT2B256rrk, X86::VPERMT2B256rmk, 0 }, 3441 { X86::VPERMT2D256rrk, X86::VPERMT2D256rmk, 0 }, 3442 { X86::VPERMT2PD256rrk, X86::VPERMT2PD256rmk, 0 }, 3443 { X86::VPERMT2PS256rrk, X86::VPERMT2PS256rmk, 0 }, 3444 { X86::VPERMT2Q256rrk, X86::VPERMT2Q256rmk, 0 }, 3445 { X86::VPERMT2W256rrk, X86::VPERMT2W256rmk, 0 }, 3446 { X86::VPERMWZ256rrk, X86::VPERMWZ256rmk, 0 }, 3447 { X86::VPMADD52HUQZ256rk, X86::VPMADD52HUQZ256mk, 0 }, 3448 { X86::VPMADD52LUQZ256rk, X86::VPMADD52LUQZ256mk, 0 }, 3449 { X86::VPMADDUBSWZ256rrk, X86::VPMADDUBSWZ256rmk, 0 }, 3450 { X86::VPMADDWDZ256rrk, X86::VPMADDWDZ256rmk, 0 }, 3451 { X86::VPMAXSBZ256rrk, X86::VPMAXSBZ256rmk, 0 }, 3452 { X86::VPMAXSDZ256rrk, X86::VPMAXSDZ256rmk, 0 }, 3453 { X86::VPMAXSQZ256rrk, X86::VPMAXSQZ256rmk, 0 }, 3454 { X86::VPMAXSWZ256rrk, X86::VPMAXSWZ256rmk, 0 }, 3455 { X86::VPMAXUBZ256rrk, X86::VPMAXUBZ256rmk, 0 }, 3456 { X86::VPMAXUDZ256rrk, X86::VPMAXUDZ256rmk, 0 }, 3457 { X86::VPMAXUQZ256rrk, X86::VPMAXUQZ256rmk, 0 }, 3458 { X86::VPMAXUWZ256rrk, X86::VPMAXUWZ256rmk, 0 }, 3459 { X86::VPMINSBZ256rrk, X86::VPMINSBZ256rmk, 0 }, 3460 { X86::VPMINSDZ256rrk, X86::VPMINSDZ256rmk, 0 }, 3461 { X86::VPMINSQZ256rrk, X86::VPMINSQZ256rmk, 0 }, 3462 { X86::VPMINSWZ256rrk, X86::VPMINSWZ256rmk, 0 }, 3463 { X86::VPMINUBZ256rrk, X86::VPMINUBZ256rmk, 0 }, 3464 { X86::VPMINUDZ256rrk, X86::VPMINUDZ256rmk, 0 }, 3465 { X86::VPMINUQZ256rrk, X86::VPMINUQZ256rmk, 0 }, 3466 { X86::VPMINUWZ256rrk, X86::VPMINUWZ256rmk, 0 }, 3467 { X86::VPMULDQZ256rrk, X86::VPMULDQZ256rmk, 0 }, 3468 { X86::VPMULLDZ256rrk, X86::VPMULLDZ256rmk, 0 }, 3469 { X86::VPMULLQZ256rrk, X86::VPMULLQZ256rmk, 0 }, 3470 { X86::VPMULLWZ256rrk, X86::VPMULLWZ256rmk, 0 }, 3471 { X86::VPMULUDQZ256rrk, X86::VPMULUDQZ256rmk, 0 }, 3472 { X86::VPORDZ256rrk, X86::VPORDZ256rmk, 0 }, 3473 { X86::VPORQZ256rrk, X86::VPORQZ256rmk, 0 }, 3474 { X86::VPSHUFBZ256rrk, X86::VPSHUFBZ256rmk, 0 }, 3475 { X86::VPSLLDZ256rrk, X86::VPSLLDZ256rmk, 0 }, 3476 { X86::VPSLLQZ256rrk, X86::VPSLLQZ256rmk, 0 }, 3477 { X86::VPSLLVDZ256rrk, X86::VPSLLVDZ256rmk, 0 }, 3478 { X86::VPSLLVQZ256rrk, X86::VPSLLVQZ256rmk, 0 }, 3479 { X86::VPSLLVWZ256rrk, X86::VPSLLVWZ256rmk, 0 }, 3480 { X86::VPSLLWZ256rrk, X86::VPSLLWZ256rmk, 0 }, 3481 { X86::VPSRADZ256rrk, X86::VPSRADZ256rmk, 0 }, 3482 { X86::VPSRAQZ256rrk, X86::VPSRAQZ256rmk, 0 }, 3483 { X86::VPSRAVDZ256rrk, X86::VPSRAVDZ256rmk, 0 }, 3484 { X86::VPSRAVQZ256rrk, X86::VPSRAVQZ256rmk, 0 }, 3485 { X86::VPSRAVWZ256rrk, X86::VPSRAVWZ256rmk, 0 }, 3486 { X86::VPSRAWZ256rrk, X86::VPSRAWZ256rmk, 0 }, 3487 { X86::VPSRLDZ256rrk, X86::VPSRLDZ256rmk, 0 }, 3488 { X86::VPSRLQZ256rrk, X86::VPSRLQZ256rmk, 0 }, 3489 { X86::VPSRLVDZ256rrk, X86::VPSRLVDZ256rmk, 0 }, 3490 { X86::VPSRLVQZ256rrk, X86::VPSRLVQZ256rmk, 0 }, 3491 { X86::VPSRLVWZ256rrk, X86::VPSRLVWZ256rmk, 0 }, 3492 { X86::VPSRLWZ256rrk, X86::VPSRLWZ256rmk, 0 }, 3493 { X86::VPSUBBZ256rrk, X86::VPSUBBZ256rmk, 0 }, 3494 { X86::VPSUBDZ256rrk, X86::VPSUBDZ256rmk, 0 }, 3495 { X86::VPSUBQZ256rrk, X86::VPSUBQZ256rmk, 0 }, 3496 { X86::VPSUBSBZ256rrk, X86::VPSUBSBZ256rmk, 0 }, 3497 { X86::VPSUBSWZ256rrk, X86::VPSUBSWZ256rmk, 0 }, 3498 { X86::VPSUBUSBZ256rrk, X86::VPSUBUSBZ256rmk, 0 }, 3499 { X86::VPSUBUSWZ256rrk, X86::VPSUBUSWZ256rmk, 0 }, 3500 { X86::VPSUBWZ256rrk, X86::VPSUBWZ256rmk, 0 }, 3501 { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik, 0 }, 3502 { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik, 0 }, 3503 { X86::VPUNPCKHBWZ256rrk, X86::VPUNPCKHBWZ256rmk, 0 }, 3504 { X86::VPUNPCKHDQZ256rrk, X86::VPUNPCKHDQZ256rmk, 0 }, 3505 { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk, 0 }, 3506 { X86::VPUNPCKHWDZ256rrk, X86::VPUNPCKHWDZ256rmk, 0 }, 3507 { X86::VPUNPCKLBWZ256rrk, X86::VPUNPCKLBWZ256rmk, 0 }, 3508 { X86::VPUNPCKLDQZ256rrk, X86::VPUNPCKLDQZ256rmk, 0 }, 3509 { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk, 0 }, 3510 { X86::VPUNPCKLWDZ256rrk, X86::VPUNPCKLWDZ256rmk, 0 }, 3511 { X86::VPXORDZ256rrk, X86::VPXORDZ256rmk, 0 }, 3512 { X86::VPXORQZ256rrk, X86::VPXORQZ256rmk, 0 }, 3513 { X86::VSHUFPDZ256rrik, X86::VSHUFPDZ256rmik, 0 }, 3514 { X86::VSHUFPSZ256rrik, X86::VSHUFPSZ256rmik, 0 }, 3515 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 }, 3516 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 }, 3517 { X86::VUNPCKHPDZ256rrk, X86::VUNPCKHPDZ256rmk, 0 }, 3518 { X86::VUNPCKHPSZ256rrk, X86::VUNPCKHPSZ256rmk, 0 }, 3519 { X86::VUNPCKLPDZ256rrk, X86::VUNPCKLPDZ256rmk, 0 }, 3520 { X86::VUNPCKLPSZ256rrk, X86::VUNPCKLPSZ256rmk, 0 }, 3521 { X86::VXORPDZ256rrk, X86::VXORPDZ256rmk, 0 }, 3522 { X86::VXORPSZ256rrk, X86::VXORPSZ256rmk, 0 }, 3523 3524 // AVX-512{F,VL} foldable instructions 128-bit 3525 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 }, 3526 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 }, 3527 { X86::VALIGNDZ128rrik, X86::VALIGNDZ128rmik, 0 }, 3528 { X86::VALIGNQZ128rrik, X86::VALIGNQZ128rmik, 0 }, 3529 { X86::VANDNPDZ128rrk, X86::VANDNPDZ128rmk, 0 }, 3530 { X86::VANDNPSZ128rrk, X86::VANDNPSZ128rmk, 0 }, 3531 { X86::VANDPDZ128rrk, X86::VANDPDZ128rmk, 0 }, 3532 { X86::VANDPSZ128rrk, X86::VANDPSZ128rmk, 0 }, 3533 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 }, 3534 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 }, 3535 { X86::VMAXCPDZ128rrk, X86::VMAXCPDZ128rmk, 0 }, 3536 { X86::VMAXCPSZ128rrk, X86::VMAXCPSZ128rmk, 0 }, 3537 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }, 3538 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 }, 3539 { X86::VMINCPDZ128rrk, X86::VMINCPDZ128rmk, 0 }, 3540 { X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmk, 0 }, 3541 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 }, 3542 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 }, 3543 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 }, 3544 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 }, 3545 { X86::VORPDZ128rrk, X86::VORPDZ128rmk, 0 }, 3546 { X86::VORPSZ128rrk, X86::VORPSZ128rmk, 0 }, 3547 { X86::VPACKSSDWZ128rrk, X86::VPACKSSDWZ128rmk, 0 }, 3548 { X86::VPACKSSWBZ128rrk, X86::VPACKSSWBZ128rmk, 0 }, 3549 { X86::VPACKUSDWZ128rrk, X86::VPACKUSDWZ128rmk, 0 }, 3550 { X86::VPACKUSWBZ128rrk, X86::VPACKUSWBZ128rmk, 0 }, 3551 { X86::VPADDBZ128rrk, X86::VPADDBZ128rmk, 0 }, 3552 { X86::VPADDDZ128rrk, X86::VPADDDZ128rmk, 0 }, 3553 { X86::VPADDQZ128rrk, X86::VPADDQZ128rmk, 0 }, 3554 { X86::VPADDSBZ128rrk, X86::VPADDSBZ128rmk, 0 }, 3555 { X86::VPADDSWZ128rrk, X86::VPADDSWZ128rmk, 0 }, 3556 { X86::VPADDUSBZ128rrk, X86::VPADDUSBZ128rmk, 0 }, 3557 { X86::VPADDUSWZ128rrk, X86::VPADDUSWZ128rmk, 0 }, 3558 { X86::VPADDWZ128rrk, X86::VPADDWZ128rmk, 0 }, 3559 { X86::VPALIGNRZ128rrik, X86::VPALIGNRZ128rmik, 0 }, 3560 { X86::VPANDDZ128rrk, X86::VPANDDZ128rmk, 0 }, 3561 { X86::VPANDNDZ128rrk, X86::VPANDNDZ128rmk, 0 }, 3562 { X86::VPANDNQZ128rrk, X86::VPANDNQZ128rmk, 0 }, 3563 { X86::VPANDQZ128rrk, X86::VPANDQZ128rmk, 0 }, 3564 { X86::VPAVGBZ128rrk, X86::VPAVGBZ128rmk, 0 }, 3565 { X86::VPAVGWZ128rrk, X86::VPAVGWZ128rmk, 0 }, 3566 { X86::VPERMBZ128rrk, X86::VPERMBZ128rmk, 0 }, 3567 { X86::VPERMI2B128rrk, X86::VPERMI2B128rmk, 0 }, 3568 { X86::VPERMI2D128rrk, X86::VPERMI2D128rmk, 0 }, 3569 { X86::VPERMI2PD128rrk, X86::VPERMI2PD128rmk, 0 }, 3570 { X86::VPERMI2PS128rrk, X86::VPERMI2PS128rmk, 0 }, 3571 { X86::VPERMI2Q128rrk, X86::VPERMI2Q128rmk, 0 }, 3572 { X86::VPERMI2W128rrk, X86::VPERMI2W128rmk, 0 }, 3573 { X86::VPERMILPDZ128rrk, X86::VPERMILPDZ128rmk, 0 }, 3574 { X86::VPERMILPSZ128rrk, X86::VPERMILPSZ128rmk, 0 }, 3575 { X86::VPERMT2B128rrk, X86::VPERMT2B128rmk, 0 }, 3576 { X86::VPERMT2D128rrk, X86::VPERMT2D128rmk, 0 }, 3577 { X86::VPERMT2PD128rrk, X86::VPERMT2PD128rmk, 0 }, 3578 { X86::VPERMT2PS128rrk, X86::VPERMT2PS128rmk, 0 }, 3579 { X86::VPERMT2Q128rrk, X86::VPERMT2Q128rmk, 0 }, 3580 { X86::VPERMT2W128rrk, X86::VPERMT2W128rmk, 0 }, 3581 { X86::VPERMWZ128rrk, X86::VPERMWZ128rmk, 0 }, 3582 { X86::VPMADD52HUQZ128rk, X86::VPMADD52HUQZ128mk, 0 }, 3583 { X86::VPMADD52LUQZ128rk, X86::VPMADD52LUQZ128mk, 0 }, 3584 { X86::VPMADDUBSWZ128rrk, X86::VPMADDUBSWZ128rmk, 0 }, 3585 { X86::VPMADDWDZ128rrk, X86::VPMADDWDZ128rmk, 0 }, 3586 { X86::VPMAXSBZ128rrk, X86::VPMAXSBZ128rmk, 0 }, 3587 { X86::VPMAXSDZ128rrk, X86::VPMAXSDZ128rmk, 0 }, 3588 { X86::VPMAXSQZ128rrk, X86::VPMAXSQZ128rmk, 0 }, 3589 { X86::VPMAXSWZ128rrk, X86::VPMAXSWZ128rmk, 0 }, 3590 { X86::VPMAXUBZ128rrk, X86::VPMAXUBZ128rmk, 0 }, 3591 { X86::VPMAXUDZ128rrk, X86::VPMAXUDZ128rmk, 0 }, 3592 { X86::VPMAXUQZ128rrk, X86::VPMAXUQZ128rmk, 0 }, 3593 { X86::VPMAXUWZ128rrk, X86::VPMAXUWZ128rmk, 0 }, 3594 { X86::VPMINSBZ128rrk, X86::VPMINSBZ128rmk, 0 }, 3595 { X86::VPMINSDZ128rrk, X86::VPMINSDZ128rmk, 0 }, 3596 { X86::VPMINSQZ128rrk, X86::VPMINSQZ128rmk, 0 }, 3597 { X86::VPMINSWZ128rrk, X86::VPMINSWZ128rmk, 0 }, 3598 { X86::VPMINUBZ128rrk, X86::VPMINUBZ128rmk, 0 }, 3599 { X86::VPMINUDZ128rrk, X86::VPMINUDZ128rmk, 0 }, 3600 { X86::VPMINUQZ128rrk, X86::VPMINUQZ128rmk, 0 }, 3601 { X86::VPMINUWZ128rrk, X86::VPMINUWZ128rmk, 0 }, 3602 { X86::VPMULDQZ128rrk, X86::VPMULDQZ128rmk, 0 }, 3603 { X86::VPMULLDZ128rrk, X86::VPMULLDZ128rmk, 0 }, 3604 { X86::VPMULLQZ128rrk, X86::VPMULLQZ128rmk, 0 }, 3605 { X86::VPMULLWZ128rrk, X86::VPMULLWZ128rmk, 0 }, 3606 { X86::VPMULUDQZ128rrk, X86::VPMULUDQZ128rmk, 0 }, 3607 { X86::VPORDZ128rrk, X86::VPORDZ128rmk, 0 }, 3608 { X86::VPORQZ128rrk, X86::VPORQZ128rmk, 0 }, 3609 { X86::VPSHUFBZ128rrk, X86::VPSHUFBZ128rmk, 0 }, 3610 { X86::VPSLLDZ128rrk, X86::VPSLLDZ128rmk, 0 }, 3611 { X86::VPSLLQZ128rrk, X86::VPSLLQZ128rmk, 0 }, 3612 { X86::VPSLLVDZ128rrk, X86::VPSLLVDZ128rmk, 0 }, 3613 { X86::VPSLLVQZ128rrk, X86::VPSLLVQZ128rmk, 0 }, 3614 { X86::VPSLLVWZ128rrk, X86::VPSLLVWZ128rmk, 0 }, 3615 { X86::VPSLLWZ128rrk, X86::VPSLLWZ128rmk, 0 }, 3616 { X86::VPSRADZ128rrk, X86::VPSRADZ128rmk, 0 }, 3617 { X86::VPSRAQZ128rrk, X86::VPSRAQZ128rmk, 0 }, 3618 { X86::VPSRAVDZ128rrk, X86::VPSRAVDZ128rmk, 0 }, 3619 { X86::VPSRAVQZ128rrk, X86::VPSRAVQZ128rmk, 0 }, 3620 { X86::VPSRAVWZ128rrk, X86::VPSRAVWZ128rmk, 0 }, 3621 { X86::VPSRAWZ128rrk, X86::VPSRAWZ128rmk, 0 }, 3622 { X86::VPSRLDZ128rrk, X86::VPSRLDZ128rmk, 0 }, 3623 { X86::VPSRLQZ128rrk, X86::VPSRLQZ128rmk, 0 }, 3624 { X86::VPSRLVDZ128rrk, X86::VPSRLVDZ128rmk, 0 }, 3625 { X86::VPSRLVQZ128rrk, X86::VPSRLVQZ128rmk, 0 }, 3626 { X86::VPSRLVWZ128rrk, X86::VPSRLVWZ128rmk, 0 }, 3627 { X86::VPSRLWZ128rrk, X86::VPSRLWZ128rmk, 0 }, 3628 { X86::VPSUBBZ128rrk, X86::VPSUBBZ128rmk, 0 }, 3629 { X86::VPSUBDZ128rrk, X86::VPSUBDZ128rmk, 0 }, 3630 { X86::VPSUBQZ128rrk, X86::VPSUBQZ128rmk, 0 }, 3631 { X86::VPSUBSBZ128rrk, X86::VPSUBSBZ128rmk, 0 }, 3632 { X86::VPSUBSWZ128rrk, X86::VPSUBSWZ128rmk, 0 }, 3633 { X86::VPSUBUSBZ128rrk, X86::VPSUBUSBZ128rmk, 0 }, 3634 { X86::VPSUBUSWZ128rrk, X86::VPSUBUSWZ128rmk, 0 }, 3635 { X86::VPSUBWZ128rrk, X86::VPSUBWZ128rmk, 0 }, 3636 { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik, 0 }, 3637 { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik, 0 }, 3638 { X86::VPUNPCKHBWZ128rrk, X86::VPUNPCKHBWZ128rmk, 0 }, 3639 { X86::VPUNPCKHDQZ128rrk, X86::VPUNPCKHDQZ128rmk, 0 }, 3640 { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk, 0 }, 3641 { X86::VPUNPCKHWDZ128rrk, X86::VPUNPCKHWDZ128rmk, 0 }, 3642 { X86::VPUNPCKLBWZ128rrk, X86::VPUNPCKLBWZ128rmk, 0 }, 3643 { X86::VPUNPCKLDQZ128rrk, X86::VPUNPCKLDQZ128rmk, 0 }, 3644 { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk, 0 }, 3645 { X86::VPUNPCKLWDZ128rrk, X86::VPUNPCKLWDZ128rmk, 0 }, 3646 { X86::VPXORDZ128rrk, X86::VPXORDZ128rmk, 0 }, 3647 { X86::VPXORQZ128rrk, X86::VPXORQZ128rmk, 0 }, 3648 { X86::VSHUFPDZ128rrik, X86::VSHUFPDZ128rmik, 0 }, 3649 { X86::VSHUFPSZ128rrik, X86::VSHUFPSZ128rmik, 0 }, 3650 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 }, 3651 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 }, 3652 { X86::VUNPCKHPDZ128rrk, X86::VUNPCKHPDZ128rmk, 0 }, 3653 { X86::VUNPCKHPSZ128rrk, X86::VUNPCKHPSZ128rmk, 0 }, 3654 { X86::VUNPCKLPDZ128rrk, X86::VUNPCKLPDZ128rmk, 0 }, 3655 { X86::VUNPCKLPSZ128rrk, X86::VUNPCKLPSZ128rmk, 0 }, 3656 { X86::VXORPDZ128rrk, X86::VXORPDZ128rmk, 0 }, 3657 { X86::VXORPSZ128rrk, X86::VXORPSZ128rmk, 0 }, 3658 3659 // 512-bit three source instructions with zero masking. 3660 { X86::VPERMI2Brrkz, X86::VPERMI2Brmkz, 0 }, 3661 { X86::VPERMI2Drrkz, X86::VPERMI2Drmkz, 0 }, 3662 { X86::VPERMI2PSrrkz, X86::VPERMI2PSrmkz, 0 }, 3663 { X86::VPERMI2PDrrkz, X86::VPERMI2PDrmkz, 0 }, 3664 { X86::VPERMI2Qrrkz, X86::VPERMI2Qrmkz, 0 }, 3665 { X86::VPERMI2Wrrkz, X86::VPERMI2Wrmkz, 0 }, 3666 { X86::VPERMT2Brrkz, X86::VPERMT2Brmkz, 0 }, 3667 { X86::VPERMT2Drrkz, X86::VPERMT2Drmkz, 0 }, 3668 { X86::VPERMT2PSrrkz, X86::VPERMT2PSrmkz, 0 }, 3669 { X86::VPERMT2PDrrkz, X86::VPERMT2PDrmkz, 0 }, 3670 { X86::VPERMT2Qrrkz, X86::VPERMT2Qrmkz, 0 }, 3671 { X86::VPERMT2Wrrkz, X86::VPERMT2Wrmkz, 0 }, 3672 { X86::VPMADD52HUQZrkz, X86::VPMADD52HUQZmkz, 0 }, 3673 { X86::VPMADD52LUQZrkz, X86::VPMADD52LUQZmkz, 0 }, 3674 { X86::VPTERNLOGDZrrikz, X86::VPTERNLOGDZrmikz, 0 }, 3675 { X86::VPTERNLOGQZrrikz, X86::VPTERNLOGQZrmikz, 0 }, 3676 3677 // 256-bit three source instructions with zero masking. 3678 { X86::VPERMI2B256rrkz, X86::VPERMI2B256rmkz, 0 }, 3679 { X86::VPERMI2D256rrkz, X86::VPERMI2D256rmkz, 0 }, 3680 { X86::VPERMI2PD256rrkz, X86::VPERMI2PD256rmkz, 0 }, 3681 { X86::VPERMI2PS256rrkz, X86::VPERMI2PS256rmkz, 0 }, 3682 { X86::VPERMI2Q256rrkz, X86::VPERMI2Q256rmkz, 0 }, 3683 { X86::VPERMI2W256rrkz, X86::VPERMI2W256rmkz, 0 }, 3684 { X86::VPERMT2B256rrkz, X86::VPERMT2B256rmkz, 0 }, 3685 { X86::VPERMT2D256rrkz, X86::VPERMT2D256rmkz, 0 }, 3686 { X86::VPERMT2PD256rrkz, X86::VPERMT2PD256rmkz, 0 }, 3687 { X86::VPERMT2PS256rrkz, X86::VPERMT2PS256rmkz, 0 }, 3688 { X86::VPERMT2Q256rrkz, X86::VPERMT2Q256rmkz, 0 }, 3689 { X86::VPERMT2W256rrkz, X86::VPERMT2W256rmkz, 0 }, 3690 { X86::VPMADD52HUQZ256rkz, X86::VPMADD52HUQZ256mkz, 0 }, 3691 { X86::VPMADD52LUQZ256rkz, X86::VPMADD52LUQZ256mkz, 0 }, 3692 { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz, 0 }, 3693 { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz, 0 }, 3694 3695 // 128-bit three source instructions with zero masking. 3696 { X86::VPERMI2B128rrkz, X86::VPERMI2B128rmkz, 0 }, 3697 { X86::VPERMI2D128rrkz, X86::VPERMI2D128rmkz, 0 }, 3698 { X86::VPERMI2PD128rrkz, X86::VPERMI2PD128rmkz, 0 }, 3699 { X86::VPERMI2PS128rrkz, X86::VPERMI2PS128rmkz, 0 }, 3700 { X86::VPERMI2Q128rrkz, X86::VPERMI2Q128rmkz, 0 }, 3701 { X86::VPERMI2W128rrkz, X86::VPERMI2W128rmkz, 0 }, 3702 { X86::VPERMT2B128rrkz, X86::VPERMT2B128rmkz, 0 }, 3703 { X86::VPERMT2D128rrkz, X86::VPERMT2D128rmkz, 0 }, 3704 { X86::VPERMT2PD128rrkz, X86::VPERMT2PD128rmkz, 0 }, 3705 { X86::VPERMT2PS128rrkz, X86::VPERMT2PS128rmkz, 0 }, 3706 { X86::VPERMT2Q128rrkz, X86::VPERMT2Q128rmkz, 0 }, 3707 { X86::VPERMT2W128rrkz, X86::VPERMT2W128rmkz, 0 }, 3708 { X86::VPMADD52HUQZ128rkz, X86::VPMADD52HUQZ128mkz, 0 }, 3709 { X86::VPMADD52LUQZ128rkz, X86::VPMADD52LUQZ128mkz, 0 }, 3710 { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz, 0 }, 3711 { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz, 0 }, 3712 }; 3713 3714 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) { 3715 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable, 3716 Entry.RegOp, Entry.MemOp, 3717 // Index 4, folded load 3718 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD); 3719 } 3720 for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) { 3721 if (I.getGroup()->isKMasked()) { 3722 // Intrinsics need to pass TB_NO_REVERSE. 3723 if (I.getGroup()->isIntrinsic()) { 3724 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable, 3725 I.getRegOpcode(), I.getMemOpcode(), 3726 TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE); 3727 } else { 3728 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable, 3729 I.getRegOpcode(), I.getMemOpcode(), 3730 TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD); 3731 } 3732 } 3733 } 3734} 3735 3736void 3737X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 3738 MemOp2RegOpTableType &M2RTable, 3739 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) { 3740 if ((Flags & TB_NO_FORWARD) == 0) { 3741 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 3742 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 3743 } 3744 if ((Flags & TB_NO_REVERSE) == 0) { 3745 assert(!M2RTable.count(MemOp) && 3746 "Duplicated entries in unfolding maps?"); 3747 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 3748 } 3749} 3750 3751bool 3752X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 3753 unsigned &SrcReg, unsigned &DstReg, 3754 unsigned &SubIdx) const { 3755 switch (MI.getOpcode()) { 3756 default: break; 3757 case X86::MOVSX16rr8: 3758 case X86::MOVZX16rr8: 3759 case X86::MOVSX32rr8: 3760 case X86::MOVZX32rr8: 3761 case X86::MOVSX64rr8: 3762 if (!Subtarget.is64Bit()) 3763 // It's not always legal to reference the low 8-bit of the larger 3764 // register in 32-bit mode. 3765 return false; 3766 LLVM_FALLTHROUGH; 3767 case X86::MOVSX32rr16: 3768 case X86::MOVZX32rr16: 3769 case X86::MOVSX64rr16: 3770 case X86::MOVSX64rr32: { 3771 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 3772 // Be conservative. 3773 return false; 3774 SrcReg = MI.getOperand(1).getReg(); 3775 DstReg = MI.getOperand(0).getReg(); 3776 switch (MI.getOpcode()) { 3777 default: llvm_unreachable("Unreachable!"); 3778 case X86::MOVSX16rr8: 3779 case X86::MOVZX16rr8: 3780 case X86::MOVSX32rr8: 3781 case X86::MOVZX32rr8: 3782 case X86::MOVSX64rr8: 3783 SubIdx = X86::sub_8bit; 3784 break; 3785 case X86::MOVSX32rr16: 3786 case X86::MOVZX32rr16: 3787 case X86::MOVSX64rr16: 3788 SubIdx = X86::sub_16bit; 3789 break; 3790 case X86::MOVSX64rr32: 3791 SubIdx = X86::sub_32bit; 3792 break; 3793 } 3794 return true; 3795 } 3796 } 3797 return false; 3798} 3799 3800int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const { 3801 const MachineFunction *MF = MI.getParent()->getParent(); 3802 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); 3803 3804 if (isFrameInstr(MI)) { 3805 unsigned StackAlign = TFI->getStackAlignment(); 3806 int SPAdj = alignTo(getFrameSize(MI), StackAlign); 3807 SPAdj -= getFrameAdjustment(MI); 3808 if (!isFrameSetup(MI)) 3809 SPAdj = -SPAdj; 3810 return SPAdj; 3811 } 3812 3813 // To know whether a call adjusts the stack, we need information 3814 // that is bound to the following ADJCALLSTACKUP pseudo. 3815 // Look for the next ADJCALLSTACKUP that follows the call. 3816 if (MI.isCall()) { 3817 const MachineBasicBlock *MBB = MI.getParent(); 3818 auto I = ++MachineBasicBlock::const_iterator(MI); 3819 for (auto E = MBB->end(); I != E; ++I) { 3820 if (I->getOpcode() == getCallFrameDestroyOpcode() || 3821 I->isCall()) 3822 break; 3823 } 3824 3825 // If we could not find a frame destroy opcode, then it has already 3826 // been simplified, so we don't care. 3827 if (I->getOpcode() != getCallFrameDestroyOpcode()) 3828 return 0; 3829 3830 return -(I->getOperand(1).getImm()); 3831 } 3832 3833 // Currently handle only PUSHes we can reasonably expect to see 3834 // in call sequences 3835 switch (MI.getOpcode()) { 3836 default: 3837 return 0; 3838 case X86::PUSH32i8: 3839 case X86::PUSH32r: 3840 case X86::PUSH32rmm: 3841 case X86::PUSH32rmr: 3842 case X86::PUSHi32: 3843 return 4; 3844 case X86::PUSH64i8: 3845 case X86::PUSH64r: 3846 case X86::PUSH64rmm: 3847 case X86::PUSH64rmr: 3848 case X86::PUSH64i32: 3849 return 8; 3850 } 3851} 3852 3853/// Return true and the FrameIndex if the specified 3854/// operand and follow operands form a reference to the stack frame. 3855bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op, 3856 int &FrameIndex) const { 3857 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() && 3858 MI.getOperand(Op + X86::AddrScaleAmt).isImm() && 3859 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 3860 MI.getOperand(Op + X86::AddrDisp).isImm() && 3861 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 && 3862 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && 3863 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) { 3864 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex(); 3865 return true; 3866 } 3867 return false; 3868} 3869 3870static bool isFrameLoadOpcode(int Opcode) { 3871 switch (Opcode) { 3872 default: 3873 return false; 3874 case X86::MOV8rm: 3875 case X86::MOV16rm: 3876 case X86::MOV32rm: 3877 case X86::MOV64rm: 3878 case X86::LD_Fp64m: 3879 case X86::MOVSSrm: 3880 case X86::MOVSDrm: 3881 case X86::MOVAPSrm: 3882 case X86::MOVUPSrm: 3883 case X86::MOVAPDrm: 3884 case X86::MOVUPDrm: 3885 case X86::MOVDQArm: 3886 case X86::MOVDQUrm: 3887 case X86::VMOVSSrm: 3888 case X86::VMOVSDrm: 3889 case X86::VMOVAPSrm: 3890 case X86::VMOVUPSrm: 3891 case X86::VMOVAPDrm: 3892 case X86::VMOVUPDrm: 3893 case X86::VMOVDQArm: 3894 case X86::VMOVDQUrm: 3895 case X86::VMOVUPSYrm: 3896 case X86::VMOVAPSYrm: 3897 case X86::VMOVUPDYrm: 3898 case X86::VMOVAPDYrm: 3899 case X86::VMOVDQUYrm: 3900 case X86::VMOVDQAYrm: 3901 case X86::MMX_MOVD64rm: 3902 case X86::MMX_MOVQ64rm: 3903 case X86::VMOVSSZrm: 3904 case X86::VMOVSDZrm: 3905 case X86::VMOVAPSZrm: 3906 case X86::VMOVAPSZ128rm: 3907 case X86::VMOVAPSZ256rm: 3908 case X86::VMOVAPSZ128rm_NOVLX: 3909 case X86::VMOVAPSZ256rm_NOVLX: 3910 case X86::VMOVUPSZrm: 3911 case X86::VMOVUPSZ128rm: 3912 case X86::VMOVUPSZ256rm: 3913 case X86::VMOVUPSZ128rm_NOVLX: 3914 case X86::VMOVUPSZ256rm_NOVLX: 3915 case X86::VMOVAPDZrm: 3916 case X86::VMOVAPDZ128rm: 3917 case X86::VMOVAPDZ256rm: 3918 case X86::VMOVUPDZrm: 3919 case X86::VMOVUPDZ128rm: 3920 case X86::VMOVUPDZ256rm: 3921 case X86::VMOVDQA32Zrm: 3922 case X86::VMOVDQA32Z128rm: 3923 case X86::VMOVDQA32Z256rm: 3924 case X86::VMOVDQU32Zrm: 3925 case X86::VMOVDQU32Z128rm: 3926 case X86::VMOVDQU32Z256rm: 3927 case X86::VMOVDQA64Zrm: 3928 case X86::VMOVDQA64Z128rm: 3929 case X86::VMOVDQA64Z256rm: 3930 case X86::VMOVDQU64Zrm: 3931 case X86::VMOVDQU64Z128rm: 3932 case X86::VMOVDQU64Z256rm: 3933 case X86::VMOVDQU8Zrm: 3934 case X86::VMOVDQU8Z128rm: 3935 case X86::VMOVDQU8Z256rm: 3936 case X86::VMOVDQU16Zrm: 3937 case X86::VMOVDQU16Z128rm: 3938 case X86::VMOVDQU16Z256rm: 3939 case X86::KMOVBkm: 3940 case X86::KMOVWkm: 3941 case X86::KMOVDkm: 3942 case X86::KMOVQkm: 3943 return true; 3944 } 3945} 3946 3947static bool isFrameStoreOpcode(int Opcode) { 3948 switch (Opcode) { 3949 default: break; 3950 case X86::MOV8mr: 3951 case X86::MOV16mr: 3952 case X86::MOV32mr: 3953 case X86::MOV64mr: 3954 case X86::ST_FpP64m: 3955 case X86::MOVSSmr: 3956 case X86::MOVSDmr: 3957 case X86::MOVAPSmr: 3958 case X86::MOVUPSmr: 3959 case X86::MOVAPDmr: 3960 case X86::MOVUPDmr: 3961 case X86::MOVDQAmr: 3962 case X86::MOVDQUmr: 3963 case X86::VMOVSSmr: 3964 case X86::VMOVSDmr: 3965 case X86::VMOVAPSmr: 3966 case X86::VMOVUPSmr: 3967 case X86::VMOVAPDmr: 3968 case X86::VMOVUPDmr: 3969 case X86::VMOVDQAmr: 3970 case X86::VMOVDQUmr: 3971 case X86::VMOVUPSYmr: 3972 case X86::VMOVAPSYmr: 3973 case X86::VMOVUPDYmr: 3974 case X86::VMOVAPDYmr: 3975 case X86::VMOVDQUYmr: 3976 case X86::VMOVDQAYmr: 3977 case X86::VMOVSSZmr: 3978 case X86::VMOVSDZmr: 3979 case X86::VMOVUPSZmr: 3980 case X86::VMOVUPSZ128mr: 3981 case X86::VMOVUPSZ256mr: 3982 case X86::VMOVUPSZ128mr_NOVLX: 3983 case X86::VMOVUPSZ256mr_NOVLX: 3984 case X86::VMOVAPSZmr: 3985 case X86::VMOVAPSZ128mr: 3986 case X86::VMOVAPSZ256mr: 3987 case X86::VMOVAPSZ128mr_NOVLX: 3988 case X86::VMOVAPSZ256mr_NOVLX: 3989 case X86::VMOVUPDZmr: 3990 case X86::VMOVUPDZ128mr: 3991 case X86::VMOVUPDZ256mr: 3992 case X86::VMOVAPDZmr: 3993 case X86::VMOVAPDZ128mr: 3994 case X86::VMOVAPDZ256mr: 3995 case X86::VMOVDQA32Zmr: 3996 case X86::VMOVDQA32Z128mr: 3997 case X86::VMOVDQA32Z256mr: 3998 case X86::VMOVDQU32Zmr: 3999 case X86::VMOVDQU32Z128mr: 4000 case X86::VMOVDQU32Z256mr: 4001 case X86::VMOVDQA64Zmr: 4002 case X86::VMOVDQA64Z128mr: 4003 case X86::VMOVDQA64Z256mr: 4004 case X86::VMOVDQU64Zmr: 4005 case X86::VMOVDQU64Z128mr: 4006 case X86::VMOVDQU64Z256mr: 4007 case X86::VMOVDQU8Zmr: 4008 case X86::VMOVDQU8Z128mr: 4009 case X86::VMOVDQU8Z256mr: 4010 case X86::VMOVDQU16Zmr: 4011 case X86::VMOVDQU16Z128mr: 4012 case X86::VMOVDQU16Z256mr: 4013 case X86::MMX_MOVD64mr: 4014 case X86::MMX_MOVQ64mr: 4015 case X86::MMX_MOVNTQmr: 4016 case X86::KMOVBmk: 4017 case X86::KMOVWmk: 4018 case X86::KMOVDmk: 4019 case X86::KMOVQmk: 4020 return true; 4021 } 4022 return false; 4023} 4024 4025unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 4026 int &FrameIndex) const { 4027 if (isFrameLoadOpcode(MI.getOpcode())) 4028 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 4029 return MI.getOperand(0).getReg(); 4030 return 0; 4031} 4032 4033unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, 4034 int &FrameIndex) const { 4035 if (isFrameLoadOpcode(MI.getOpcode())) { 4036 unsigned Reg; 4037 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 4038 return Reg; 4039 // Check for post-frame index elimination operations 4040 const MachineMemOperand *Dummy; 4041 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 4042 } 4043 return 0; 4044} 4045 4046unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI, 4047 int &FrameIndex) const { 4048 if (isFrameStoreOpcode(MI.getOpcode())) 4049 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 && 4050 isFrameOperand(MI, 0, FrameIndex)) 4051 return MI.getOperand(X86::AddrNumOperands).getReg(); 4052 return 0; 4053} 4054 4055unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, 4056 int &FrameIndex) const { 4057 if (isFrameStoreOpcode(MI.getOpcode())) { 4058 unsigned Reg; 4059 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 4060 return Reg; 4061 // Check for post-frame index elimination operations 4062 const MachineMemOperand *Dummy; 4063 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 4064 } 4065 return 0; 4066} 4067 4068/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. 4069static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 4070 // Don't waste compile time scanning use-def chains of physregs. 4071 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 4072 return false; 4073 bool isPICBase = false; 4074 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), 4075 E = MRI.def_instr_end(); I != E; ++I) { 4076 MachineInstr *DefMI = &*I; 4077 if (DefMI->getOpcode() != X86::MOVPC32r) 4078 return false; 4079 assert(!isPICBase && "More than one PIC base?"); 4080 isPICBase = true; 4081 } 4082 return isPICBase; 4083} 4084 4085bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, 4086 AliasAnalysis *AA) const { 4087 switch (MI.getOpcode()) { 4088 default: break; 4089 case X86::MOV8rm: 4090 case X86::MOV8rm_NOREX: 4091 case X86::MOV16rm: 4092 case X86::MOV32rm: 4093 case X86::MOV64rm: 4094 case X86::LD_Fp64m: 4095 case X86::MOVSSrm: 4096 case X86::MOVSDrm: 4097 case X86::MOVAPSrm: 4098 case X86::MOVUPSrm: 4099 case X86::MOVAPDrm: 4100 case X86::MOVUPDrm: 4101 case X86::MOVDQArm: 4102 case X86::MOVDQUrm: 4103 case X86::VMOVSSrm: 4104 case X86::VMOVSDrm: 4105 case X86::VMOVAPSrm: 4106 case X86::VMOVUPSrm: 4107 case X86::VMOVAPDrm: 4108 case X86::VMOVUPDrm: 4109 case X86::VMOVDQArm: 4110 case X86::VMOVDQUrm: 4111 case X86::VMOVAPSYrm: 4112 case X86::VMOVUPSYrm: 4113 case X86::VMOVAPDYrm: 4114 case X86::VMOVUPDYrm: 4115 case X86::VMOVDQAYrm: 4116 case X86::VMOVDQUYrm: 4117 case X86::MMX_MOVD64rm: 4118 case X86::MMX_MOVQ64rm: 4119 // AVX-512 4120 case X86::VMOVSSZrm: 4121 case X86::VMOVSDZrm: 4122 case X86::VMOVAPDZ128rm: 4123 case X86::VMOVAPDZ256rm: 4124 case X86::VMOVAPDZrm: 4125 case X86::VMOVAPSZ128rm: 4126 case X86::VMOVAPSZ256rm: 4127 case X86::VMOVAPSZ128rm_NOVLX: 4128 case X86::VMOVAPSZ256rm_NOVLX: 4129 case X86::VMOVAPSZrm: 4130 case X86::VMOVDQA32Z128rm: 4131 case X86::VMOVDQA32Z256rm: 4132 case X86::VMOVDQA32Zrm: 4133 case X86::VMOVDQA64Z128rm: 4134 case X86::VMOVDQA64Z256rm: 4135 case X86::VMOVDQA64Zrm: 4136 case X86::VMOVDQU16Z128rm: 4137 case X86::VMOVDQU16Z256rm: 4138 case X86::VMOVDQU16Zrm: 4139 case X86::VMOVDQU32Z128rm: 4140 case X86::VMOVDQU32Z256rm: 4141 case X86::VMOVDQU32Zrm: 4142 case X86::VMOVDQU64Z128rm: 4143 case X86::VMOVDQU64Z256rm: 4144 case X86::VMOVDQU64Zrm: 4145 case X86::VMOVDQU8Z128rm: 4146 case X86::VMOVDQU8Z256rm: 4147 case X86::VMOVDQU8Zrm: 4148 case X86::VMOVUPDZ128rm: 4149 case X86::VMOVUPDZ256rm: 4150 case X86::VMOVUPDZrm: 4151 case X86::VMOVUPSZ128rm: 4152 case X86::VMOVUPSZ256rm: 4153 case X86::VMOVUPSZ128rm_NOVLX: 4154 case X86::VMOVUPSZ256rm_NOVLX: 4155 case X86::VMOVUPSZrm: { 4156 // Loads from constant pools are trivially rematerializable. 4157 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && 4158 MI.getOperand(1 + X86::AddrScaleAmt).isImm() && 4159 MI.getOperand(1 + X86::AddrIndexReg).isReg() && 4160 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && 4161 MI.isDereferenceableInvariantLoad(AA)) { 4162 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); 4163 if (BaseReg == 0 || BaseReg == X86::RIP) 4164 return true; 4165 // Allow re-materialization of PIC load. 4166 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal()) 4167 return false; 4168 const MachineFunction &MF = *MI.getParent()->getParent(); 4169 const MachineRegisterInfo &MRI = MF.getRegInfo(); 4170 return regIsPICBase(BaseReg, MRI); 4171 } 4172 return false; 4173 } 4174 4175 case X86::LEA32r: 4176 case X86::LEA64r: { 4177 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() && 4178 MI.getOperand(1 + X86::AddrIndexReg).isReg() && 4179 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && 4180 !MI.getOperand(1 + X86::AddrDisp).isReg()) { 4181 // lea fi#, lea GV, etc. are all rematerializable. 4182 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) 4183 return true; 4184 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); 4185 if (BaseReg == 0) 4186 return true; 4187 // Allow re-materialization of lea PICBase + x. 4188 const MachineFunction &MF = *MI.getParent()->getParent(); 4189 const MachineRegisterInfo &MRI = MF.getRegInfo(); 4190 return regIsPICBase(BaseReg, MRI); 4191 } 4192 return false; 4193 } 4194 } 4195 4196 // All other instructions marked M_REMATERIALIZABLE are always trivially 4197 // rematerializable. 4198 return true; 4199} 4200 4201bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 4202 MachineBasicBlock::iterator I) const { 4203 MachineBasicBlock::iterator E = MBB.end(); 4204 4205 // For compile time consideration, if we are not able to determine the 4206 // safety after visiting 4 instructions in each direction, we will assume 4207 // it's not safe. 4208 MachineBasicBlock::iterator Iter = I; 4209 for (unsigned i = 0; Iter != E && i < 4; ++i) { 4210 bool SeenDef = false; 4211 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 4212 MachineOperand &MO = Iter->getOperand(j); 4213 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 4214 SeenDef = true; 4215 if (!MO.isReg()) 4216 continue; 4217 if (MO.getReg() == X86::EFLAGS) { 4218 if (MO.isUse()) 4219 return false; 4220 SeenDef = true; 4221 } 4222 } 4223 4224 if (SeenDef) 4225 // This instruction defines EFLAGS, no need to look any further. 4226 return true; 4227 ++Iter; 4228 // Skip over DBG_VALUE. 4229 while (Iter != E && Iter->isDebugValue()) 4230 ++Iter; 4231 } 4232 4233 // It is safe to clobber EFLAGS at the end of a block of no successor has it 4234 // live in. 4235 if (Iter == E) { 4236 for (MachineBasicBlock *S : MBB.successors()) 4237 if (S->isLiveIn(X86::EFLAGS)) 4238 return false; 4239 return true; 4240 } 4241 4242 MachineBasicBlock::iterator B = MBB.begin(); 4243 Iter = I; 4244 for (unsigned i = 0; i < 4; ++i) { 4245 // If we make it to the beginning of the block, it's safe to clobber 4246 // EFLAGS iff EFLAGS is not live-in. 4247 if (Iter == B) 4248 return !MBB.isLiveIn(X86::EFLAGS); 4249 4250 --Iter; 4251 // Skip over DBG_VALUE. 4252 while (Iter != B && Iter->isDebugValue()) 4253 --Iter; 4254 4255 bool SawKill = false; 4256 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 4257 MachineOperand &MO = Iter->getOperand(j); 4258 // A register mask may clobber EFLAGS, but we should still look for a 4259 // live EFLAGS def. 4260 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 4261 SawKill = true; 4262 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 4263 if (MO.isDef()) return MO.isDead(); 4264 if (MO.isKill()) SawKill = true; 4265 } 4266 } 4267 4268 if (SawKill) 4269 // This instruction kills EFLAGS and doesn't redefine it, so 4270 // there's no need to look further. 4271 return true; 4272 } 4273 4274 // Conservative answer. 4275 return false; 4276} 4277 4278void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 4279 MachineBasicBlock::iterator I, 4280 unsigned DestReg, unsigned SubIdx, 4281 const MachineInstr &Orig, 4282 const TargetRegisterInfo &TRI) const { 4283 bool ClobbersEFLAGS = false; 4284 for (const MachineOperand &MO : Orig.operands()) { 4285 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) { 4286 ClobbersEFLAGS = true; 4287 break; 4288 } 4289 } 4290 4291 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) { 4292 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side 4293 // effects. 4294 int Value; 4295 switch (Orig.getOpcode()) { 4296 case X86::MOV32r0: Value = 0; break; 4297 case X86::MOV32r1: Value = 1; break; 4298 case X86::MOV32r_1: Value = -1; break; 4299 default: 4300 llvm_unreachable("Unexpected instruction!"); 4301 } 4302 4303 const DebugLoc &DL = Orig.getDebugLoc(); 4304 BuildMI(MBB, I, DL, get(X86::MOV32ri)) 4305 .add(Orig.getOperand(0)) 4306 .addImm(Value); 4307 } else { 4308 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig); 4309 MBB.insert(I, MI); 4310 } 4311 4312 MachineInstr &NewMI = *std::prev(I); 4313 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI); 4314} 4315 4316/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead. 4317bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const { 4318 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 4319 MachineOperand &MO = MI.getOperand(i); 4320 if (MO.isReg() && MO.isDef() && 4321 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 4322 return true; 4323 } 4324 } 4325 return false; 4326} 4327 4328/// Check whether the shift count for a machine operand is non-zero. 4329inline static unsigned getTruncatedShiftCount(MachineInstr &MI, 4330 unsigned ShiftAmtOperandIdx) { 4331 // The shift count is six bits with the REX.W prefix and five bits without. 4332 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31; 4333 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm(); 4334 return Imm & ShiftCountMask; 4335} 4336 4337/// Check whether the given shift count is appropriate 4338/// can be represented by a LEA instruction. 4339inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) { 4340 // Left shift instructions can be transformed into load-effective-address 4341 // instructions if we can encode them appropriately. 4342 // A LEA instruction utilizes a SIB byte to encode its scale factor. 4343 // The SIB.scale field is two bits wide which means that we can encode any 4344 // shift amount less than 4. 4345 return ShAmt < 4 && ShAmt > 0; 4346} 4347 4348bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, 4349 unsigned Opc, bool AllowSP, unsigned &NewSrc, 4350 bool &isKill, bool &isUndef, 4351 MachineOperand &ImplicitOp, 4352 LiveVariables *LV) const { 4353 MachineFunction &MF = *MI.getParent()->getParent(); 4354 const TargetRegisterClass *RC; 4355 if (AllowSP) { 4356 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 4357 } else { 4358 RC = Opc != X86::LEA32r ? 4359 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; 4360 } 4361 unsigned SrcReg = Src.getReg(); 4362 4363 // For both LEA64 and LEA32 the register already has essentially the right 4364 // type (32-bit or 64-bit) we may just need to forbid SP. 4365 if (Opc != X86::LEA64_32r) { 4366 NewSrc = SrcReg; 4367 isKill = Src.isKill(); 4368 isUndef = Src.isUndef(); 4369 4370 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && 4371 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 4372 return false; 4373 4374 return true; 4375 } 4376 4377 // This is for an LEA64_32r and incoming registers are 32-bit. One way or 4378 // another we need to add 64-bit registers to the final MI. 4379 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 4380 ImplicitOp = Src; 4381 ImplicitOp.setImplicit(); 4382 4383 NewSrc = getX86SubSuperRegister(Src.getReg(), 64); 4384 isKill = Src.isKill(); 4385 isUndef = Src.isUndef(); 4386 } else { 4387 // Virtual register of the wrong class, we have to create a temporary 64-bit 4388 // vreg to feed into the LEA. 4389 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 4390 MachineInstr *Copy = 4391 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY)) 4392 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) 4393 .add(Src); 4394 4395 // Which is obviously going to be dead after we're done with it. 4396 isKill = true; 4397 isUndef = false; 4398 4399 if (LV) 4400 LV->replaceKillInstruction(SrcReg, MI, *Copy); 4401 } 4402 4403 // We've set all the parameters without issue. 4404 return true; 4405} 4406 4407/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit 4408/// LEA to form 3-address code by promoting to a 32-bit superregister and then 4409/// truncating back down to a 16-bit subregister. 4410MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA( 4411 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI, 4412 LiveVariables *LV) const { 4413 MachineBasicBlock::iterator MBBI = MI.getIterator(); 4414 unsigned Dest = MI.getOperand(0).getReg(); 4415 unsigned Src = MI.getOperand(1).getReg(); 4416 bool isDead = MI.getOperand(0).isDead(); 4417 bool isKill = MI.getOperand(1).isKill(); 4418 4419 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 4420 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4421 unsigned Opc, leaInReg; 4422 if (Subtarget.is64Bit()) { 4423 Opc = X86::LEA64_32r; 4424 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 4425 } else { 4426 Opc = X86::LEA32r; 4427 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4428 } 4429 4430 // Build and insert into an implicit UNDEF value. This is OK because 4431 // well be shifting and then extracting the lower 16-bits. 4432 // This has the potential to cause partial register stall. e.g. 4433 // movw (%rbp,%rcx,2), %dx 4434 // leal -65(%rdx), %esi 4435 // But testing has shown this *does* help performance in 64-bit mode (at 4436 // least on modern x86 machines). 4437 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 4438 MachineInstr *InsMI = 4439 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY)) 4440 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 4441 .addReg(Src, getKillRegState(isKill)); 4442 4443 MachineInstrBuilder MIB = 4444 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg); 4445 switch (MIOpc) { 4446 default: llvm_unreachable("Unreachable!"); 4447 case X86::SHL16ri: { 4448 unsigned ShAmt = MI.getOperand(2).getImm(); 4449 MIB.addReg(0).addImm(1ULL << ShAmt) 4450 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 4451 break; 4452 } 4453 case X86::INC16r: 4454 addRegOffset(MIB, leaInReg, true, 1); 4455 break; 4456 case X86::DEC16r: 4457 addRegOffset(MIB, leaInReg, true, -1); 4458 break; 4459 case X86::ADD16ri: 4460 case X86::ADD16ri8: 4461 case X86::ADD16ri_DB: 4462 case X86::ADD16ri8_DB: 4463 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm()); 4464 break; 4465 case X86::ADD16rr: 4466 case X86::ADD16rr_DB: { 4467 unsigned Src2 = MI.getOperand(2).getReg(); 4468 bool isKill2 = MI.getOperand(2).isKill(); 4469 unsigned leaInReg2 = 0; 4470 MachineInstr *InsMI2 = nullptr; 4471 if (Src == Src2) { 4472 // ADD16rr killed %reg1028, %reg1028 4473 // just a single insert_subreg. 4474 addRegReg(MIB, leaInReg, true, leaInReg, false); 4475 } else { 4476 if (Subtarget.is64Bit()) 4477 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 4478 else 4479 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4480 // Build and insert into an implicit UNDEF value. This is OK because 4481 // well be shifting and then extracting the lower 16-bits. 4482 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 4483 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY)) 4484 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 4485 .addReg(Src2, getKillRegState(isKill2)); 4486 addRegReg(MIB, leaInReg, true, leaInReg2, true); 4487 } 4488 if (LV && isKill2 && InsMI2) 4489 LV->replaceKillInstruction(Src2, MI, *InsMI2); 4490 break; 4491 } 4492 } 4493 4494 MachineInstr *NewMI = MIB; 4495 MachineInstr *ExtMI = 4496 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY)) 4497 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 4498 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 4499 4500 if (LV) { 4501 // Update live variables 4502 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 4503 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 4504 if (isKill) 4505 LV->replaceKillInstruction(Src, MI, *InsMI); 4506 if (isDead) 4507 LV->replaceKillInstruction(Dest, MI, *ExtMI); 4508 } 4509 4510 return ExtMI; 4511} 4512 4513/// This method must be implemented by targets that 4514/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 4515/// may be able to convert a two-address instruction into a true 4516/// three-address instruction on demand. This allows the X86 target (for 4517/// example) to convert ADD and SHL instructions into LEA instructions if they 4518/// would require register copies due to two-addressness. 4519/// 4520/// This method returns a null pointer if the transformation cannot be 4521/// performed, otherwise it returns the new instruction. 4522/// 4523MachineInstr * 4524X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 4525 MachineInstr &MI, LiveVariables *LV) const { 4526 // The following opcodes also sets the condition code register(s). Only 4527 // convert them to equivalent lea if the condition code register def's 4528 // are dead! 4529 if (hasLiveCondCodeDef(MI)) 4530 return nullptr; 4531 4532 MachineFunction &MF = *MI.getParent()->getParent(); 4533 // All instructions input are two-addr instructions. Get the known operands. 4534 const MachineOperand &Dest = MI.getOperand(0); 4535 const MachineOperand &Src = MI.getOperand(1); 4536 4537 MachineInstr *NewMI = nullptr; 4538 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 4539 // we have better subtarget support, enable the 16-bit LEA generation here. 4540 // 16-bit LEA is also slow on Core2. 4541 bool DisableLEA16 = true; 4542 bool is64Bit = Subtarget.is64Bit(); 4543 4544 unsigned MIOpc = MI.getOpcode(); 4545 switch (MIOpc) { 4546 default: return nullptr; 4547 case X86::SHL64ri: { 4548 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); 4549 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 4550 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 4551 4552 // LEA can't handle RSP. 4553 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 4554 !MF.getRegInfo().constrainRegClass(Src.getReg(), 4555 &X86::GR64_NOSPRegClass)) 4556 return nullptr; 4557 4558 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)) 4559 .add(Dest) 4560 .addReg(0) 4561 .addImm(1ULL << ShAmt) 4562 .add(Src) 4563 .addImm(0) 4564 .addReg(0); 4565 break; 4566 } 4567 case X86::SHL32ri: { 4568 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); 4569 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 4570 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 4571 4572 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 4573 4574 // LEA can't handle ESP. 4575 bool isKill, isUndef; 4576 unsigned SrcReg; 4577 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 4578 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 4579 SrcReg, isKill, isUndef, ImplicitOp, LV)) 4580 return nullptr; 4581 4582 MachineInstrBuilder MIB = 4583 BuildMI(MF, MI.getDebugLoc(), get(Opc)) 4584 .add(Dest) 4585 .addReg(0) 4586 .addImm(1ULL << ShAmt) 4587 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 4588 .addImm(0) 4589 .addReg(0); 4590 if (ImplicitOp.getReg() != 0) 4591 MIB.add(ImplicitOp); 4592 NewMI = MIB; 4593 4594 break; 4595 } 4596 case X86::SHL16ri: { 4597 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); 4598 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 4599 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 4600 4601 if (DisableLEA16) 4602 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV) 4603 : nullptr; 4604 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)) 4605 .add(Dest) 4606 .addReg(0) 4607 .addImm(1ULL << ShAmt) 4608 .add(Src) 4609 .addImm(0) 4610 .addReg(0); 4611 break; 4612 } 4613 case X86::INC64r: 4614 case X86::INC32r: { 4615 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!"); 4616 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 4617 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 4618 bool isKill, isUndef; 4619 unsigned SrcReg; 4620 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 4621 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 4622 SrcReg, isKill, isUndef, ImplicitOp, LV)) 4623 return nullptr; 4624 4625 MachineInstrBuilder MIB = 4626 BuildMI(MF, MI.getDebugLoc(), get(Opc)) 4627 .add(Dest) 4628 .addReg(SrcReg, 4629 getKillRegState(isKill) | getUndefRegState(isUndef)); 4630 if (ImplicitOp.getReg() != 0) 4631 MIB.add(ImplicitOp); 4632 4633 NewMI = addOffset(MIB, 1); 4634 break; 4635 } 4636 case X86::INC16r: 4637 if (DisableLEA16) 4638 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV) 4639 : nullptr; 4640 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!"); 4641 NewMI = addOffset( 4642 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 1); 4643 break; 4644 case X86::DEC64r: 4645 case X86::DEC32r: { 4646 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!"); 4647 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 4648 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 4649 4650 bool isKill, isUndef; 4651 unsigned SrcReg; 4652 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 4653 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 4654 SrcReg, isKill, isUndef, ImplicitOp, LV)) 4655 return nullptr; 4656 4657 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 4658 .add(Dest) 4659 .addReg(SrcReg, getUndefRegState(isUndef) | 4660 getKillRegState(isKill)); 4661 if (ImplicitOp.getReg() != 0) 4662 MIB.add(ImplicitOp); 4663 4664 NewMI = addOffset(MIB, -1); 4665 4666 break; 4667 } 4668 case X86::DEC16r: 4669 if (DisableLEA16) 4670 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV) 4671 : nullptr; 4672 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!"); 4673 NewMI = addOffset( 4674 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), -1); 4675 break; 4676 case X86::ADD64rr: 4677 case X86::ADD64rr_DB: 4678 case X86::ADD32rr: 4679 case X86::ADD32rr_DB: { 4680 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 4681 unsigned Opc; 4682 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) 4683 Opc = X86::LEA64r; 4684 else 4685 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 4686 4687 bool isKill, isUndef; 4688 unsigned SrcReg; 4689 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 4690 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 4691 SrcReg, isKill, isUndef, ImplicitOp, LV)) 4692 return nullptr; 4693 4694 const MachineOperand &Src2 = MI.getOperand(2); 4695 bool isKill2, isUndef2; 4696 unsigned SrcReg2; 4697 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false); 4698 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 4699 SrcReg2, isKill2, isUndef2, ImplicitOp2, LV)) 4700 return nullptr; 4701 4702 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest); 4703 if (ImplicitOp.getReg() != 0) 4704 MIB.add(ImplicitOp); 4705 if (ImplicitOp2.getReg() != 0) 4706 MIB.add(ImplicitOp2); 4707 4708 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); 4709 4710 // Preserve undefness of the operands. 4711 NewMI->getOperand(1).setIsUndef(isUndef); 4712 NewMI->getOperand(3).setIsUndef(isUndef2); 4713 4714 if (LV && Src2.isKill()) 4715 LV->replaceKillInstruction(SrcReg2, MI, *NewMI); 4716 break; 4717 } 4718 case X86::ADD16rr: 4719 case X86::ADD16rr_DB: { 4720 if (DisableLEA16) 4721 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV) 4722 : nullptr; 4723 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 4724 unsigned Src2 = MI.getOperand(2).getReg(); 4725 bool isKill2 = MI.getOperand(2).isKill(); 4726 NewMI = addRegReg(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest), 4727 Src.getReg(), Src.isKill(), Src2, isKill2); 4728 4729 // Preserve undefness of the operands. 4730 bool isUndef = MI.getOperand(1).isUndef(); 4731 bool isUndef2 = MI.getOperand(2).isUndef(); 4732 NewMI->getOperand(1).setIsUndef(isUndef); 4733 NewMI->getOperand(3).setIsUndef(isUndef2); 4734 4735 if (LV && isKill2) 4736 LV->replaceKillInstruction(Src2, MI, *NewMI); 4737 break; 4738 } 4739 case X86::ADD64ri32: 4740 case X86::ADD64ri8: 4741 case X86::ADD64ri32_DB: 4742 case X86::ADD64ri8_DB: 4743 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 4744 NewMI = addOffset( 4745 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src), 4746 MI.getOperand(2)); 4747 break; 4748 case X86::ADD32ri: 4749 case X86::ADD32ri8: 4750 case X86::ADD32ri_DB: 4751 case X86::ADD32ri8_DB: { 4752 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 4753 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 4754 4755 bool isKill, isUndef; 4756 unsigned SrcReg; 4757 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 4758 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 4759 SrcReg, isKill, isUndef, ImplicitOp, LV)) 4760 return nullptr; 4761 4762 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 4763 .add(Dest) 4764 .addReg(SrcReg, getUndefRegState(isUndef) | 4765 getKillRegState(isKill)); 4766 if (ImplicitOp.getReg() != 0) 4767 MIB.add(ImplicitOp); 4768 4769 NewMI = addOffset(MIB, MI.getOperand(2)); 4770 break; 4771 } 4772 case X86::ADD16ri: 4773 case X86::ADD16ri8: 4774 case X86::ADD16ri_DB: 4775 case X86::ADD16ri8_DB: 4776 if (DisableLEA16) 4777 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV) 4778 : nullptr; 4779 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 4780 NewMI = addOffset( 4781 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 4782 MI.getOperand(2)); 4783 break; 4784 4785 case X86::VMOVDQU8Z128rmk: 4786 case X86::VMOVDQU8Z256rmk: 4787 case X86::VMOVDQU8Zrmk: 4788 case X86::VMOVDQU16Z128rmk: 4789 case X86::VMOVDQU16Z256rmk: 4790 case X86::VMOVDQU16Zrmk: 4791 case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk: 4792 case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk: 4793 case X86::VMOVDQU32Zrmk: case X86::VMOVDQA32Zrmk: 4794 case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk: 4795 case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk: 4796 case X86::VMOVDQU64Zrmk: case X86::VMOVDQA64Zrmk: 4797 case X86::VMOVUPDZ128rmk: case X86::VMOVAPDZ128rmk: 4798 case X86::VMOVUPDZ256rmk: case X86::VMOVAPDZ256rmk: 4799 case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk: 4800 case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk: 4801 case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk: 4802 case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: { 4803 unsigned Opc; 4804 switch (MIOpc) { 4805 default: llvm_unreachable("Unreachable!"); 4806 case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break; 4807 case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break; 4808 case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break; 4809 case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break; 4810 case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break; 4811 case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break; 4812 case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break; 4813 case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break; 4814 case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break; 4815 case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break; 4816 case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break; 4817 case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break; 4818 case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break; 4819 case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break; 4820 case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break; 4821 case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break; 4822 case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break; 4823 case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break; 4824 case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break; 4825 case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break; 4826 case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break; 4827 case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break; 4828 case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break; 4829 case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break; 4830 case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break; 4831 case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break; 4832 case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break; 4833 case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break; 4834 case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break; 4835 case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break; 4836 } 4837 4838 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 4839 .add(Dest) 4840 .add(MI.getOperand(2)) 4841 .add(Src) 4842 .add(MI.getOperand(3)) 4843 .add(MI.getOperand(4)) 4844 .add(MI.getOperand(5)) 4845 .add(MI.getOperand(6)) 4846 .add(MI.getOperand(7)); 4847 break; 4848 } 4849 case X86::VMOVDQU8Z128rrk: 4850 case X86::VMOVDQU8Z256rrk: 4851 case X86::VMOVDQU8Zrrk: 4852 case X86::VMOVDQU16Z128rrk: 4853 case X86::VMOVDQU16Z256rrk: 4854 case X86::VMOVDQU16Zrrk: 4855 case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk: 4856 case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk: 4857 case X86::VMOVDQU32Zrrk: case X86::VMOVDQA32Zrrk: 4858 case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk: 4859 case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk: 4860 case X86::VMOVDQU64Zrrk: case X86::VMOVDQA64Zrrk: 4861 case X86::VMOVUPDZ128rrk: case X86::VMOVAPDZ128rrk: 4862 case X86::VMOVUPDZ256rrk: case X86::VMOVAPDZ256rrk: 4863 case X86::VMOVUPDZrrk: case X86::VMOVAPDZrrk: 4864 case X86::VMOVUPSZ128rrk: case X86::VMOVAPSZ128rrk: 4865 case X86::VMOVUPSZ256rrk: case X86::VMOVAPSZ256rrk: 4866 case X86::VMOVUPSZrrk: case X86::VMOVAPSZrrk: { 4867 unsigned Opc; 4868 switch (MIOpc) { 4869 default: llvm_unreachable("Unreachable!"); 4870 case X86::VMOVDQU8Z128rrk: Opc = X86::VPBLENDMBZ128rrk; break; 4871 case X86::VMOVDQU8Z256rrk: Opc = X86::VPBLENDMBZ256rrk; break; 4872 case X86::VMOVDQU8Zrrk: Opc = X86::VPBLENDMBZrrk; break; 4873 case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break; 4874 case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break; 4875 case X86::VMOVDQU16Zrrk: Opc = X86::VPBLENDMWZrrk; break; 4876 case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break; 4877 case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break; 4878 case X86::VMOVDQU32Zrrk: Opc = X86::VPBLENDMDZrrk; break; 4879 case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break; 4880 case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break; 4881 case X86::VMOVDQU64Zrrk: Opc = X86::VPBLENDMQZrrk; break; 4882 case X86::VMOVUPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break; 4883 case X86::VMOVUPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break; 4884 case X86::VMOVUPDZrrk: Opc = X86::VBLENDMPDZrrk; break; 4885 case X86::VMOVUPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break; 4886 case X86::VMOVUPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break; 4887 case X86::VMOVUPSZrrk: Opc = X86::VBLENDMPSZrrk; break; 4888 case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break; 4889 case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break; 4890 case X86::VMOVDQA32Zrrk: Opc = X86::VPBLENDMDZrrk; break; 4891 case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break; 4892 case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break; 4893 case X86::VMOVDQA64Zrrk: Opc = X86::VPBLENDMQZrrk; break; 4894 case X86::VMOVAPDZ128rrk: Opc = X86::VBLENDMPDZ128rrk; break; 4895 case X86::VMOVAPDZ256rrk: Opc = X86::VBLENDMPDZ256rrk; break; 4896 case X86::VMOVAPDZrrk: Opc = X86::VBLENDMPDZrrk; break; 4897 case X86::VMOVAPSZ128rrk: Opc = X86::VBLENDMPSZ128rrk; break; 4898 case X86::VMOVAPSZ256rrk: Opc = X86::VBLENDMPSZ256rrk; break; 4899 case X86::VMOVAPSZrrk: Opc = X86::VBLENDMPSZrrk; break; 4900 } 4901 4902 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 4903 .add(Dest) 4904 .add(MI.getOperand(2)) 4905 .add(Src) 4906 .add(MI.getOperand(3)); 4907 break; 4908 } 4909 } 4910 4911 if (!NewMI) return nullptr; 4912 4913 if (LV) { // Update live variables 4914 if (Src.isKill()) 4915 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI); 4916 if (Dest.isDead()) 4917 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI); 4918 } 4919 4920 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst 4921 return NewMI; 4922} 4923 4924/// This determines which of three possible cases of a three source commute 4925/// the source indexes correspond to taking into account any mask operands. 4926/// All prevents commuting a passthru operand. Returns -1 if the commute isn't 4927/// possible. 4928/// Case 0 - Possible to commute the first and second operands. 4929/// Case 1 - Possible to commute the first and third operands. 4930/// Case 2 - Possible to commute the second and third operands. 4931static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1, 4932 unsigned SrcOpIdx2) { 4933 // Put the lowest index to SrcOpIdx1 to simplify the checks below. 4934 if (SrcOpIdx1 > SrcOpIdx2) 4935 std::swap(SrcOpIdx1, SrcOpIdx2); 4936 4937 unsigned Op1 = 1, Op2 = 2, Op3 = 3; 4938 if (X86II::isKMasked(TSFlags)) { 4939 // The k-mask operand cannot be commuted. 4940 if (SrcOpIdx1 == 2) 4941 return -1; 4942 4943 // For k-zero-masked operations it is Ok to commute the first vector 4944 // operand. 4945 // For regular k-masked operations a conservative choice is done as the 4946 // elements of the first vector operand, for which the corresponding bit 4947 // in the k-mask operand is set to 0, are copied to the result of the 4948 // instruction. 4949 // TODO/FIXME: The commute still may be legal if it is known that the 4950 // k-mask operand is set to either all ones or all zeroes. 4951 // It is also Ok to commute the 1st operand if all users of MI use only 4952 // the elements enabled by the k-mask operand. For example, 4953 // v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i] 4954 // : v1[i]; 4955 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 -> 4956 // // Ok, to commute v1 in FMADD213PSZrk. 4957 if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1) 4958 return -1; 4959 Op2++; 4960 Op3++; 4961 } 4962 4963 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2) 4964 return 0; 4965 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3) 4966 return 1; 4967 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3) 4968 return 2; 4969 return -1; 4970} 4971 4972unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands( 4973 const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, 4974 const X86InstrFMA3Group &FMA3Group) const { 4975 4976 unsigned Opc = MI.getOpcode(); 4977 4978 // Put the lowest index to SrcOpIdx1 to simplify the checks below. 4979 if (SrcOpIdx1 > SrcOpIdx2) 4980 std::swap(SrcOpIdx1, SrcOpIdx2); 4981 4982 // TODO: Commuting the 1st operand of FMA*_Int requires some additional 4983 // analysis. The commute optimization is legal only if all users of FMA*_Int 4984 // use only the lowest element of the FMA*_Int instruction. Such analysis are 4985 // not implemented yet. So, just return 0 in that case. 4986 // When such analysis are available this place will be the right place for 4987 // calling it. 4988 if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1) 4989 return 0; 4990 4991 // Determine which case this commute is or if it can't be done. 4992 int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2); 4993 if (Case < 0) 4994 return 0; 4995 4996 // Define the FMA forms mapping array that helps to map input FMA form 4997 // to output FMA form to preserve the operation semantics after 4998 // commuting the operands. 4999 const unsigned Form132Index = 0; 5000 const unsigned Form213Index = 1; 5001 const unsigned Form231Index = 2; 5002 static const unsigned FormMapping[][3] = { 5003 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2; 5004 // FMA132 A, C, b; ==> FMA231 C, A, b; 5005 // FMA213 B, A, c; ==> FMA213 A, B, c; 5006 // FMA231 C, A, b; ==> FMA132 A, C, b; 5007 { Form231Index, Form213Index, Form132Index }, 5008 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3; 5009 // FMA132 A, c, B; ==> FMA132 B, c, A; 5010 // FMA213 B, a, C; ==> FMA231 C, a, B; 5011 // FMA231 C, a, B; ==> FMA213 B, a, C; 5012 { Form132Index, Form231Index, Form213Index }, 5013 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3; 5014 // FMA132 a, C, B; ==> FMA213 a, B, C; 5015 // FMA213 b, A, C; ==> FMA132 b, C, A; 5016 // FMA231 c, A, B; ==> FMA231 c, B, A; 5017 { Form213Index, Form132Index, Form231Index } 5018 }; 5019 5020 unsigned FMAForms[3]; 5021 if (FMA3Group.isRegOpcodeFromGroup(Opc)) { 5022 FMAForms[0] = FMA3Group.getReg132Opcode(); 5023 FMAForms[1] = FMA3Group.getReg213Opcode(); 5024 FMAForms[2] = FMA3Group.getReg231Opcode(); 5025 } else { 5026 FMAForms[0] = FMA3Group.getMem132Opcode(); 5027 FMAForms[1] = FMA3Group.getMem213Opcode(); 5028 FMAForms[2] = FMA3Group.getMem231Opcode(); 5029 } 5030 unsigned FormIndex; 5031 for (FormIndex = 0; FormIndex < 3; FormIndex++) 5032 if (Opc == FMAForms[FormIndex]) 5033 break; 5034 5035 // Everything is ready, just adjust the FMA opcode and return it. 5036 FormIndex = FormMapping[Case][FormIndex]; 5037 return FMAForms[FormIndex]; 5038} 5039 5040static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1, 5041 unsigned SrcOpIdx2) { 5042 uint64_t TSFlags = MI.getDesc().TSFlags; 5043 5044 // Determine which case this commute is or if it can't be done. 5045 int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2); 5046 if (Case < 0) 5047 return false; 5048 5049 // For each case we need to swap two pairs of bits in the final immediate. 5050 static const uint8_t SwapMasks[3][4] = { 5051 { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5. 5052 { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6. 5053 { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6. 5054 }; 5055 5056 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm(); 5057 // Clear out the bits we are swapping. 5058 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] | 5059 SwapMasks[Case][2] | SwapMasks[Case][3]); 5060 // If the immediate had a bit of the pair set, then set the opposite bit. 5061 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1]; 5062 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0]; 5063 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3]; 5064 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2]; 5065 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm); 5066 5067 return true; 5068} 5069 5070// Returns true if this is a VPERMI2 or VPERMT2 instrution that can be 5071// commuted. 5072static bool isCommutableVPERMV3Instruction(unsigned Opcode) { 5073#define VPERM_CASES(Suffix) \ 5074 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \ 5075 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \ 5076 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \ 5077 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \ 5078 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \ 5079 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \ 5080 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \ 5081 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \ 5082 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \ 5083 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \ 5084 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \ 5085 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz: 5086 5087#define VPERM_CASES_BROADCAST(Suffix) \ 5088 VPERM_CASES(Suffix) \ 5089 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \ 5090 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \ 5091 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \ 5092 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \ 5093 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \ 5094 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz: 5095 5096 switch (Opcode) { 5097 default: return false; 5098 VPERM_CASES(B) 5099 VPERM_CASES_BROADCAST(D) 5100 VPERM_CASES_BROADCAST(PD) 5101 VPERM_CASES_BROADCAST(PS) 5102 VPERM_CASES_BROADCAST(Q) 5103 VPERM_CASES(W) 5104 return true; 5105 } 5106#undef VPERM_CASES_BROADCAST 5107#undef VPERM_CASES 5108} 5109 5110// Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching 5111// from the I opcod to the T opcode and vice versa. 5112static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) { 5113#define VPERM_CASES(Orig, New) \ 5114 case X86::Orig##128rr: return X86::New##128rr; \ 5115 case X86::Orig##128rrkz: return X86::New##128rrkz; \ 5116 case X86::Orig##128rm: return X86::New##128rm; \ 5117 case X86::Orig##128rmkz: return X86::New##128rmkz; \ 5118 case X86::Orig##256rr: return X86::New##256rr; \ 5119 case X86::Orig##256rrkz: return X86::New##256rrkz; \ 5120 case X86::Orig##256rm: return X86::New##256rm; \ 5121 case X86::Orig##256rmkz: return X86::New##256rmkz; \ 5122 case X86::Orig##rr: return X86::New##rr; \ 5123 case X86::Orig##rrkz: return X86::New##rrkz; \ 5124 case X86::Orig##rm: return X86::New##rm; \ 5125 case X86::Orig##rmkz: return X86::New##rmkz; 5126 5127#define VPERM_CASES_BROADCAST(Orig, New) \ 5128 VPERM_CASES(Orig, New) \ 5129 case X86::Orig##128rmb: return X86::New##128rmb; \ 5130 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \ 5131 case X86::Orig##256rmb: return X86::New##256rmb; \ 5132 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \ 5133 case X86::Orig##rmb: return X86::New##rmb; \ 5134 case X86::Orig##rmbkz: return X86::New##rmbkz; 5135 5136 switch (Opcode) { 5137 VPERM_CASES(VPERMI2B, VPERMT2B) 5138 VPERM_CASES_BROADCAST(VPERMI2D, VPERMT2D) 5139 VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD) 5140 VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS) 5141 VPERM_CASES_BROADCAST(VPERMI2Q, VPERMT2Q) 5142 VPERM_CASES(VPERMI2W, VPERMT2W) 5143 VPERM_CASES(VPERMT2B, VPERMI2B) 5144 VPERM_CASES_BROADCAST(VPERMT2D, VPERMI2D) 5145 VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD) 5146 VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS) 5147 VPERM_CASES_BROADCAST(VPERMT2Q, VPERMI2Q) 5148 VPERM_CASES(VPERMT2W, VPERMI2W) 5149 } 5150 5151 llvm_unreachable("Unreachable!"); 5152#undef VPERM_CASES_BROADCAST 5153#undef VPERM_CASES 5154} 5155 5156MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, 5157 unsigned OpIdx1, 5158 unsigned OpIdx2) const { 5159 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & { 5160 if (NewMI) 5161 return *MI.getParent()->getParent()->CloneMachineInstr(&MI); 5162 return MI; 5163 }; 5164 5165 switch (MI.getOpcode()) { 5166 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 5167 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 5168 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 5169 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 5170 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 5171 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 5172 unsigned Opc; 5173 unsigned Size; 5174 switch (MI.getOpcode()) { 5175 default: llvm_unreachable("Unreachable!"); 5176 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 5177 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 5178 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 5179 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 5180 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 5181 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 5182 } 5183 unsigned Amt = MI.getOperand(3).getImm(); 5184 auto &WorkingMI = cloneIfNew(MI); 5185 WorkingMI.setDesc(get(Opc)); 5186 WorkingMI.getOperand(3).setImm(Size - Amt); 5187 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5188 OpIdx1, OpIdx2); 5189 } 5190 case X86::PFSUBrr: 5191 case X86::PFSUBRrr: { 5192 // PFSUB x, y: x = x - y 5193 // PFSUBR x, y: x = y - x 5194 unsigned Opc = 5195 (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr); 5196 auto &WorkingMI = cloneIfNew(MI); 5197 WorkingMI.setDesc(get(Opc)); 5198 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5199 OpIdx1, OpIdx2); 5200 } 5201 case X86::BLENDPDrri: 5202 case X86::BLENDPSrri: 5203 case X86::PBLENDWrri: 5204 case X86::VBLENDPDrri: 5205 case X86::VBLENDPSrri: 5206 case X86::VBLENDPDYrri: 5207 case X86::VBLENDPSYrri: 5208 case X86::VPBLENDDrri: 5209 case X86::VPBLENDWrri: 5210 case X86::VPBLENDDYrri: 5211 case X86::VPBLENDWYrri:{ 5212 unsigned Mask; 5213 switch (MI.getOpcode()) { 5214 default: llvm_unreachable("Unreachable!"); 5215 case X86::BLENDPDrri: Mask = 0x03; break; 5216 case X86::BLENDPSrri: Mask = 0x0F; break; 5217 case X86::PBLENDWrri: Mask = 0xFF; break; 5218 case X86::VBLENDPDrri: Mask = 0x03; break; 5219 case X86::VBLENDPSrri: Mask = 0x0F; break; 5220 case X86::VBLENDPDYrri: Mask = 0x0F; break; 5221 case X86::VBLENDPSYrri: Mask = 0xFF; break; 5222 case X86::VPBLENDDrri: Mask = 0x0F; break; 5223 case X86::VPBLENDWrri: Mask = 0xFF; break; 5224 case X86::VPBLENDDYrri: Mask = 0xFF; break; 5225 case X86::VPBLENDWYrri: Mask = 0xFF; break; 5226 } 5227 // Only the least significant bits of Imm are used. 5228 unsigned Imm = MI.getOperand(3).getImm() & Mask; 5229 auto &WorkingMI = cloneIfNew(MI); 5230 WorkingMI.getOperand(3).setImm(Mask ^ Imm); 5231 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5232 OpIdx1, OpIdx2); 5233 } 5234 case X86::MOVSDrr: 5235 case X86::MOVSSrr: 5236 case X86::VMOVSDrr: 5237 case X86::VMOVSSrr:{ 5238 // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD. 5239 if (!Subtarget.hasSSE41()) 5240 return nullptr; 5241 5242 unsigned Mask, Opc; 5243 switch (MI.getOpcode()) { 5244 default: llvm_unreachable("Unreachable!"); 5245 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02; break; 5246 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E; break; 5247 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break; 5248 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break; 5249 } 5250 5251 auto &WorkingMI = cloneIfNew(MI); 5252 WorkingMI.setDesc(get(Opc)); 5253 WorkingMI.addOperand(MachineOperand::CreateImm(Mask)); 5254 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5255 OpIdx1, OpIdx2); 5256 } 5257 case X86::PCLMULQDQrr: 5258 case X86::VPCLMULQDQrr: 5259 case X86::VPCLMULQDQYrr: 5260 case X86::VPCLMULQDQZrr: 5261 case X86::VPCLMULQDQZ128rr: 5262 case X86::VPCLMULQDQZ256rr: { 5263 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0] 5264 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0] 5265 unsigned Imm = MI.getOperand(3).getImm(); 5266 unsigned Src1Hi = Imm & 0x01; 5267 unsigned Src2Hi = Imm & 0x10; 5268 auto &WorkingMI = cloneIfNew(MI); 5269 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4)); 5270 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5271 OpIdx1, OpIdx2); 5272 } 5273 case X86::CMPSDrr: 5274 case X86::CMPSSrr: 5275 case X86::CMPPDrri: 5276 case X86::CMPPSrri: 5277 case X86::VCMPSDrr: 5278 case X86::VCMPSSrr: 5279 case X86::VCMPPDrri: 5280 case X86::VCMPPSrri: 5281 case X86::VCMPPDYrri: 5282 case X86::VCMPPSYrri: 5283 case X86::VCMPSDZrr: 5284 case X86::VCMPSSZrr: 5285 case X86::VCMPPDZrri: 5286 case X86::VCMPPSZrri: 5287 case X86::VCMPPDZ128rri: 5288 case X86::VCMPPSZ128rri: 5289 case X86::VCMPPDZ256rri: 5290 case X86::VCMPPSZ256rri: { 5291 // Float comparison can be safely commuted for 5292 // Ordered/Unordered/Equal/NotEqual tests 5293 unsigned Imm = MI.getOperand(3).getImm() & 0x7; 5294 switch (Imm) { 5295 case 0x00: // EQUAL 5296 case 0x03: // UNORDERED 5297 case 0x04: // NOT EQUAL 5298 case 0x07: // ORDERED 5299 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 5300 default: 5301 return nullptr; 5302 } 5303 } 5304 case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri: 5305 case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri: 5306 case X86::VPCMPBZrri: case X86::VPCMPUBZrri: 5307 case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri: 5308 case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri: 5309 case X86::VPCMPDZrri: case X86::VPCMPUDZrri: 5310 case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri: 5311 case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri: 5312 case X86::VPCMPQZrri: case X86::VPCMPUQZrri: 5313 case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri: 5314 case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri: 5315 case X86::VPCMPWZrri: case X86::VPCMPUWZrri: 5316 case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik: 5317 case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik: 5318 case X86::VPCMPBZrrik: case X86::VPCMPUBZrrik: 5319 case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik: 5320 case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik: 5321 case X86::VPCMPDZrrik: case X86::VPCMPUDZrrik: 5322 case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik: 5323 case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik: 5324 case X86::VPCMPQZrrik: case X86::VPCMPUQZrrik: 5325 case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik: 5326 case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik: 5327 case X86::VPCMPWZrrik: case X86::VPCMPUWZrrik: { 5328 // Flip comparison mode immediate (if necessary). 5329 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7; 5330 switch (Imm) { 5331 default: llvm_unreachable("Unreachable!"); 5332 case 0x01: Imm = 0x06; break; // LT -> NLE 5333 case 0x02: Imm = 0x05; break; // LE -> NLT 5334 case 0x05: Imm = 0x02; break; // NLT -> LE 5335 case 0x06: Imm = 0x01; break; // NLE -> LT 5336 case 0x00: // EQ 5337 case 0x03: // FALSE 5338 case 0x04: // NE 5339 case 0x07: // TRUE 5340 break; 5341 } 5342 auto &WorkingMI = cloneIfNew(MI); 5343 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm); 5344 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5345 OpIdx1, OpIdx2); 5346 } 5347 case X86::VPCOMBri: case X86::VPCOMUBri: 5348 case X86::VPCOMDri: case X86::VPCOMUDri: 5349 case X86::VPCOMQri: case X86::VPCOMUQri: 5350 case X86::VPCOMWri: case X86::VPCOMUWri: { 5351 // Flip comparison mode immediate (if necessary). 5352 unsigned Imm = MI.getOperand(3).getImm() & 0x7; 5353 switch (Imm) { 5354 default: llvm_unreachable("Unreachable!"); 5355 case 0x00: Imm = 0x02; break; // LT -> GT 5356 case 0x01: Imm = 0x03; break; // LE -> GE 5357 case 0x02: Imm = 0x00; break; // GT -> LT 5358 case 0x03: Imm = 0x01; break; // GE -> LE 5359 case 0x04: // EQ 5360 case 0x05: // NE 5361 case 0x06: // FALSE 5362 case 0x07: // TRUE 5363 break; 5364 } 5365 auto &WorkingMI = cloneIfNew(MI); 5366 WorkingMI.getOperand(3).setImm(Imm); 5367 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5368 OpIdx1, OpIdx2); 5369 } 5370 case X86::VPERM2F128rr: 5371 case X86::VPERM2I128rr: { 5372 // Flip permute source immediate. 5373 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi. 5374 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi. 5375 unsigned Imm = MI.getOperand(3).getImm() & 0xFF; 5376 auto &WorkingMI = cloneIfNew(MI); 5377 WorkingMI.getOperand(3).setImm(Imm ^ 0x22); 5378 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5379 OpIdx1, OpIdx2); 5380 } 5381 case X86::MOVHLPSrr: 5382 case X86::UNPCKHPDrr: { 5383 if (!Subtarget.hasSSE2()) 5384 return nullptr; 5385 5386 unsigned Opc = MI.getOpcode(); 5387 switch (Opc) { 5388 default: llvm_unreachable("Unreachable!"); 5389 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break; 5390 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break; 5391 } 5392 auto &WorkingMI = cloneIfNew(MI); 5393 WorkingMI.setDesc(get(Opc)); 5394 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5395 OpIdx1, OpIdx2); 5396 } 5397 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 5398 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 5399 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 5400 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 5401 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 5402 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 5403 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 5404 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 5405 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 5406 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 5407 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 5408 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 5409 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 5410 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 5411 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 5412 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 5413 unsigned Opc; 5414 switch (MI.getOpcode()) { 5415 default: llvm_unreachable("Unreachable!"); 5416 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 5417 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 5418 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 5419 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 5420 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 5421 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 5422 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 5423 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 5424 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 5425 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 5426 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 5427 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 5428 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 5429 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 5430 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 5431 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 5432 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 5433 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 5434 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 5435 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 5436 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 5437 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 5438 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 5439 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 5440 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 5441 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 5442 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 5443 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 5444 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 5445 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 5446 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 5447 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 5448 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 5449 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 5450 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 5451 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 5452 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 5453 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 5454 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 5455 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 5456 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 5457 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 5458 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 5459 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 5460 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 5461 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 5462 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 5463 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 5464 } 5465 auto &WorkingMI = cloneIfNew(MI); 5466 WorkingMI.setDesc(get(Opc)); 5467 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5468 OpIdx1, OpIdx2); 5469 } 5470 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi: 5471 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi: 5472 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi: 5473 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi: 5474 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi: 5475 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi: 5476 case X86::VPTERNLOGDZrrik: 5477 case X86::VPTERNLOGDZ128rrik: 5478 case X86::VPTERNLOGDZ256rrik: 5479 case X86::VPTERNLOGQZrrik: 5480 case X86::VPTERNLOGQZ128rrik: 5481 case X86::VPTERNLOGQZ256rrik: 5482 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz: 5483 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz: 5484 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz: 5485 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz: 5486 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz: 5487 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: 5488 case X86::VPTERNLOGDZ128rmbi: 5489 case X86::VPTERNLOGDZ256rmbi: 5490 case X86::VPTERNLOGDZrmbi: 5491 case X86::VPTERNLOGQZ128rmbi: 5492 case X86::VPTERNLOGQZ256rmbi: 5493 case X86::VPTERNLOGQZrmbi: 5494 case X86::VPTERNLOGDZ128rmbikz: 5495 case X86::VPTERNLOGDZ256rmbikz: 5496 case X86::VPTERNLOGDZrmbikz: 5497 case X86::VPTERNLOGQZ128rmbikz: 5498 case X86::VPTERNLOGQZ256rmbikz: 5499 case X86::VPTERNLOGQZrmbikz: { 5500 auto &WorkingMI = cloneIfNew(MI); 5501 if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2)) 5502 return nullptr; 5503 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5504 OpIdx1, OpIdx2); 5505 } 5506 default: { 5507 if (isCommutableVPERMV3Instruction(MI.getOpcode())) { 5508 unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode()); 5509 auto &WorkingMI = cloneIfNew(MI); 5510 WorkingMI.setDesc(get(Opc)); 5511 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5512 OpIdx1, OpIdx2); 5513 } 5514 5515 const X86InstrFMA3Group *FMA3Group = 5516 X86InstrFMA3Info::getFMA3Group(MI.getOpcode()); 5517 if (FMA3Group) { 5518 unsigned Opc = 5519 getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group); 5520 if (Opc == 0) 5521 return nullptr; 5522 auto &WorkingMI = cloneIfNew(MI); 5523 WorkingMI.setDesc(get(Opc)); 5524 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false, 5525 OpIdx1, OpIdx2); 5526 } 5527 5528 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 5529 } 5530 } 5531} 5532 5533bool X86InstrInfo::findFMA3CommutedOpIndices( 5534 const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, 5535 const X86InstrFMA3Group &FMA3Group) const { 5536 5537 if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2)) 5538 return false; 5539 5540 // Check if we can adjust the opcode to preserve the semantics when 5541 // commute the register operands. 5542 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0; 5543} 5544 5545bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI, 5546 unsigned &SrcOpIdx1, 5547 unsigned &SrcOpIdx2) const { 5548 uint64_t TSFlags = MI.getDesc().TSFlags; 5549 5550 unsigned FirstCommutableVecOp = 1; 5551 unsigned LastCommutableVecOp = 3; 5552 unsigned KMaskOp = 0; 5553 if (X86II::isKMasked(TSFlags)) { 5554 // The k-mask operand has index = 2 for masked and zero-masked operations. 5555 KMaskOp = 2; 5556 5557 // The operand with index = 1 is used as a source for those elements for 5558 // which the corresponding bit in the k-mask is set to 0. 5559 if (X86II::isKMergeMasked(TSFlags)) 5560 FirstCommutableVecOp = 3; 5561 5562 LastCommutableVecOp++; 5563 } 5564 5565 if (isMem(MI, LastCommutableVecOp)) 5566 LastCommutableVecOp--; 5567 5568 // Only the first RegOpsNum operands are commutable. 5569 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means 5570 // that the operand is not specified/fixed. 5571 if (SrcOpIdx1 != CommuteAnyOperandIndex && 5572 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || 5573 SrcOpIdx1 == KMaskOp)) 5574 return false; 5575 if (SrcOpIdx2 != CommuteAnyOperandIndex && 5576 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || 5577 SrcOpIdx2 == KMaskOp)) 5578 return false; 5579 5580 // Look for two different register operands assumed to be commutable 5581 // regardless of the FMA opcode. The FMA opcode is adjusted later. 5582 if (SrcOpIdx1 == CommuteAnyOperandIndex || 5583 SrcOpIdx2 == CommuteAnyOperandIndex) { 5584 unsigned CommutableOpIdx1 = SrcOpIdx1; 5585 unsigned CommutableOpIdx2 = SrcOpIdx2; 5586 5587 // At least one of operands to be commuted is not specified and 5588 // this method is free to choose appropriate commutable operands. 5589 if (SrcOpIdx1 == SrcOpIdx2) 5590 // Both of operands are not fixed. By default set one of commutable 5591 // operands to the last register operand of the instruction. 5592 CommutableOpIdx2 = LastCommutableVecOp; 5593 else if (SrcOpIdx2 == CommuteAnyOperandIndex) 5594 // Only one of operands is not fixed. 5595 CommutableOpIdx2 = SrcOpIdx1; 5596 5597 // CommutableOpIdx2 is well defined now. Let's choose another commutable 5598 // operand and assign its index to CommutableOpIdx1. 5599 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg(); 5600 for (CommutableOpIdx1 = LastCommutableVecOp; 5601 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) { 5602 // Just ignore and skip the k-mask operand. 5603 if (CommutableOpIdx1 == KMaskOp) 5604 continue; 5605 5606 // The commuted operands must have different registers. 5607 // Otherwise, the commute transformation does not change anything and 5608 // is useless then. 5609 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg()) 5610 break; 5611 } 5612 5613 // No appropriate commutable operands were found. 5614 if (CommutableOpIdx1 < FirstCommutableVecOp) 5615 return false; 5616 5617 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2 5618 // to return those values. 5619 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 5620 CommutableOpIdx1, CommutableOpIdx2)) 5621 return false; 5622 } 5623 5624 return true; 5625} 5626 5627bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, 5628 unsigned &SrcOpIdx2) const { 5629 const MCInstrDesc &Desc = MI.getDesc(); 5630 if (!Desc.isCommutable()) 5631 return false; 5632 5633 switch (MI.getOpcode()) { 5634 case X86::CMPSDrr: 5635 case X86::CMPSSrr: 5636 case X86::CMPPDrri: 5637 case X86::CMPPSrri: 5638 case X86::VCMPSDrr: 5639 case X86::VCMPSSrr: 5640 case X86::VCMPPDrri: 5641 case X86::VCMPPSrri: 5642 case X86::VCMPPDYrri: 5643 case X86::VCMPPSYrri: 5644 case X86::VCMPSDZrr: 5645 case X86::VCMPSSZrr: 5646 case X86::VCMPPDZrri: 5647 case X86::VCMPPSZrri: 5648 case X86::VCMPPDZ128rri: 5649 case X86::VCMPPSZ128rri: 5650 case X86::VCMPPDZ256rri: 5651 case X86::VCMPPSZ256rri: { 5652 // Float comparison can be safely commuted for 5653 // Ordered/Unordered/Equal/NotEqual tests 5654 unsigned Imm = MI.getOperand(3).getImm() & 0x7; 5655 switch (Imm) { 5656 case 0x00: // EQUAL 5657 case 0x03: // UNORDERED 5658 case 0x04: // NOT EQUAL 5659 case 0x07: // ORDERED 5660 // The indices of the commutable operands are 1 and 2. 5661 // Assign them to the returned operand indices here. 5662 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2); 5663 } 5664 return false; 5665 } 5666 case X86::MOVSDrr: 5667 case X86::MOVSSrr: 5668 case X86::VMOVSDrr: 5669 case X86::VMOVSSrr: { 5670 if (Subtarget.hasSSE41()) 5671 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 5672 return false; 5673 } 5674 case X86::VPTERNLOGDZrri: case X86::VPTERNLOGDZrmi: 5675 case X86::VPTERNLOGDZ128rri: case X86::VPTERNLOGDZ128rmi: 5676 case X86::VPTERNLOGDZ256rri: case X86::VPTERNLOGDZ256rmi: 5677 case X86::VPTERNLOGQZrri: case X86::VPTERNLOGQZrmi: 5678 case X86::VPTERNLOGQZ128rri: case X86::VPTERNLOGQZ128rmi: 5679 case X86::VPTERNLOGQZ256rri: case X86::VPTERNLOGQZ256rmi: 5680 case X86::VPTERNLOGDZrrik: 5681 case X86::VPTERNLOGDZ128rrik: 5682 case X86::VPTERNLOGDZ256rrik: 5683 case X86::VPTERNLOGQZrrik: 5684 case X86::VPTERNLOGQZ128rrik: 5685 case X86::VPTERNLOGQZ256rrik: 5686 case X86::VPTERNLOGDZrrikz: case X86::VPTERNLOGDZrmikz: 5687 case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz: 5688 case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz: 5689 case X86::VPTERNLOGQZrrikz: case X86::VPTERNLOGQZrmikz: 5690 case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz: 5691 case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: 5692 case X86::VPTERNLOGDZ128rmbi: 5693 case X86::VPTERNLOGDZ256rmbi: 5694 case X86::VPTERNLOGDZrmbi: 5695 case X86::VPTERNLOGQZ128rmbi: 5696 case X86::VPTERNLOGQZ256rmbi: 5697 case X86::VPTERNLOGQZrmbi: 5698 case X86::VPTERNLOGDZ128rmbikz: 5699 case X86::VPTERNLOGDZ256rmbikz: 5700 case X86::VPTERNLOGDZrmbikz: 5701 case X86::VPTERNLOGQZ128rmbikz: 5702 case X86::VPTERNLOGQZ256rmbikz: 5703 case X86::VPTERNLOGQZrmbikz: 5704 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 5705 case X86::VPMADD52HUQZ128r: 5706 case X86::VPMADD52HUQZ128rk: 5707 case X86::VPMADD52HUQZ128rkz: 5708 case X86::VPMADD52HUQZ256r: 5709 case X86::VPMADD52HUQZ256rk: 5710 case X86::VPMADD52HUQZ256rkz: 5711 case X86::VPMADD52HUQZr: 5712 case X86::VPMADD52HUQZrk: 5713 case X86::VPMADD52HUQZrkz: 5714 case X86::VPMADD52LUQZ128r: 5715 case X86::VPMADD52LUQZ128rk: 5716 case X86::VPMADD52LUQZ128rkz: 5717 case X86::VPMADD52LUQZ256r: 5718 case X86::VPMADD52LUQZ256rk: 5719 case X86::VPMADD52LUQZ256rkz: 5720 case X86::VPMADD52LUQZr: 5721 case X86::VPMADD52LUQZrk: 5722 case X86::VPMADD52LUQZrkz: { 5723 unsigned CommutableOpIdx1 = 2; 5724 unsigned CommutableOpIdx2 = 3; 5725 if (Desc.TSFlags & X86II::EVEX_K) { 5726 // Skip the mask register. 5727 ++CommutableOpIdx1; 5728 ++CommutableOpIdx2; 5729 } 5730 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 5731 CommutableOpIdx1, CommutableOpIdx2)) 5732 return false; 5733 if (!MI.getOperand(SrcOpIdx1).isReg() || 5734 !MI.getOperand(SrcOpIdx2).isReg()) 5735 // No idea. 5736 return false; 5737 return true; 5738 } 5739 5740 default: 5741 const X86InstrFMA3Group *FMA3Group = 5742 X86InstrFMA3Info::getFMA3Group(MI.getOpcode()); 5743 if (FMA3Group) 5744 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group); 5745 5746 // Handled masked instructions since we need to skip over the mask input 5747 // and the preserved input. 5748 if (Desc.TSFlags & X86II::EVEX_K) { 5749 // First assume that the first input is the mask operand and skip past it. 5750 unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1; 5751 unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2; 5752 // Check if the first input is tied. If there isn't one then we only 5753 // need to skip the mask operand which we did above. 5754 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(), 5755 MCOI::TIED_TO) != -1)) { 5756 // If this is zero masking instruction with a tied operand, we need to 5757 // move the first index back to the first input since this must 5758 // be a 3 input instruction and we want the first two non-mask inputs. 5759 // Otherwise this is a 2 input instruction with a preserved input and 5760 // mask, so we need to move the indices to skip one more input. 5761 if (Desc.TSFlags & X86II::EVEX_Z) 5762 --CommutableOpIdx1; 5763 else { 5764 ++CommutableOpIdx1; 5765 ++CommutableOpIdx2; 5766 } 5767 } 5768 5769 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 5770 CommutableOpIdx1, CommutableOpIdx2)) 5771 return false; 5772 5773 if (!MI.getOperand(SrcOpIdx1).isReg() || 5774 !MI.getOperand(SrcOpIdx2).isReg()) 5775 // No idea. 5776 return false; 5777 return true; 5778 } 5779 5780 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 5781 } 5782 return false; 5783} 5784 5785X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) { 5786 switch (BrOpc) { 5787 default: return X86::COND_INVALID; 5788 case X86::JE_1: return X86::COND_E; 5789 case X86::JNE_1: return X86::COND_NE; 5790 case X86::JL_1: return X86::COND_L; 5791 case X86::JLE_1: return X86::COND_LE; 5792 case X86::JG_1: return X86::COND_G; 5793 case X86::JGE_1: return X86::COND_GE; 5794 case X86::JB_1: return X86::COND_B; 5795 case X86::JBE_1: return X86::COND_BE; 5796 case X86::JA_1: return X86::COND_A; 5797 case X86::JAE_1: return X86::COND_AE; 5798 case X86::JS_1: return X86::COND_S; 5799 case X86::JNS_1: return X86::COND_NS; 5800 case X86::JP_1: return X86::COND_P; 5801 case X86::JNP_1: return X86::COND_NP; 5802 case X86::JO_1: return X86::COND_O; 5803 case X86::JNO_1: return X86::COND_NO; 5804 } 5805} 5806 5807/// Return condition code of a SET opcode. 5808X86::CondCode X86::getCondFromSETOpc(unsigned Opc) { 5809 switch (Opc) { 5810 default: return X86::COND_INVALID; 5811 case X86::SETAr: case X86::SETAm: return X86::COND_A; 5812 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 5813 case X86::SETBr: case X86::SETBm: return X86::COND_B; 5814 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 5815 case X86::SETEr: case X86::SETEm: return X86::COND_E; 5816 case X86::SETGr: case X86::SETGm: return X86::COND_G; 5817 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 5818 case X86::SETLr: case X86::SETLm: return X86::COND_L; 5819 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 5820 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 5821 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 5822 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 5823 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 5824 case X86::SETOr: case X86::SETOm: return X86::COND_O; 5825 case X86::SETPr: case X86::SETPm: return X86::COND_P; 5826 case X86::SETSr: case X86::SETSm: return X86::COND_S; 5827 } 5828} 5829 5830/// Return condition code of a CMov opcode. 5831X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 5832 switch (Opc) { 5833 default: return X86::COND_INVALID; 5834 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 5835 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 5836 return X86::COND_A; 5837 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 5838 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 5839 return X86::COND_AE; 5840 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 5841 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 5842 return X86::COND_B; 5843 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 5844 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 5845 return X86::COND_BE; 5846 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 5847 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 5848 return X86::COND_E; 5849 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 5850 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 5851 return X86::COND_G; 5852 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 5853 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 5854 return X86::COND_GE; 5855 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 5856 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 5857 return X86::COND_L; 5858 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 5859 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 5860 return X86::COND_LE; 5861 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 5862 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 5863 return X86::COND_NE; 5864 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 5865 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 5866 return X86::COND_NO; 5867 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 5868 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 5869 return X86::COND_NP; 5870 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 5871 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 5872 return X86::COND_NS; 5873 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 5874 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 5875 return X86::COND_O; 5876 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 5877 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 5878 return X86::COND_P; 5879 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 5880 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 5881 return X86::COND_S; 5882 } 5883} 5884 5885unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 5886 switch (CC) { 5887 default: llvm_unreachable("Illegal condition code!"); 5888 case X86::COND_E: return X86::JE_1; 5889 case X86::COND_NE: return X86::JNE_1; 5890 case X86::COND_L: return X86::JL_1; 5891 case X86::COND_LE: return X86::JLE_1; 5892 case X86::COND_G: return X86::JG_1; 5893 case X86::COND_GE: return X86::JGE_1; 5894 case X86::COND_B: return X86::JB_1; 5895 case X86::COND_BE: return X86::JBE_1; 5896 case X86::COND_A: return X86::JA_1; 5897 case X86::COND_AE: return X86::JAE_1; 5898 case X86::COND_S: return X86::JS_1; 5899 case X86::COND_NS: return X86::JNS_1; 5900 case X86::COND_P: return X86::JP_1; 5901 case X86::COND_NP: return X86::JNP_1; 5902 case X86::COND_O: return X86::JO_1; 5903 case X86::COND_NO: return X86::JNO_1; 5904 } 5905} 5906 5907/// Return the inverse of the specified condition, 5908/// e.g. turning COND_E to COND_NE. 5909X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 5910 switch (CC) { 5911 default: llvm_unreachable("Illegal condition code!"); 5912 case X86::COND_E: return X86::COND_NE; 5913 case X86::COND_NE: return X86::COND_E; 5914 case X86::COND_L: return X86::COND_GE; 5915 case X86::COND_LE: return X86::COND_G; 5916 case X86::COND_G: return X86::COND_LE; 5917 case X86::COND_GE: return X86::COND_L; 5918 case X86::COND_B: return X86::COND_AE; 5919 case X86::COND_BE: return X86::COND_A; 5920 case X86::COND_A: return X86::COND_BE; 5921 case X86::COND_AE: return X86::COND_B; 5922 case X86::COND_S: return X86::COND_NS; 5923 case X86::COND_NS: return X86::COND_S; 5924 case X86::COND_P: return X86::COND_NP; 5925 case X86::COND_NP: return X86::COND_P; 5926 case X86::COND_O: return X86::COND_NO; 5927 case X86::COND_NO: return X86::COND_O; 5928 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP; 5929 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P; 5930 } 5931} 5932 5933/// Assuming the flags are set by MI(a,b), return the condition code if we 5934/// modify the instructions such that flags are set by MI(b,a). 5935static X86::CondCode getSwappedCondition(X86::CondCode CC) { 5936 switch (CC) { 5937 default: return X86::COND_INVALID; 5938 case X86::COND_E: return X86::COND_E; 5939 case X86::COND_NE: return X86::COND_NE; 5940 case X86::COND_L: return X86::COND_G; 5941 case X86::COND_LE: return X86::COND_GE; 5942 case X86::COND_G: return X86::COND_L; 5943 case X86::COND_GE: return X86::COND_LE; 5944 case X86::COND_B: return X86::COND_A; 5945 case X86::COND_BE: return X86::COND_AE; 5946 case X86::COND_A: return X86::COND_B; 5947 case X86::COND_AE: return X86::COND_BE; 5948 } 5949} 5950 5951std::pair<X86::CondCode, bool> 5952X86::getX86ConditionCode(CmpInst::Predicate Predicate) { 5953 X86::CondCode CC = X86::COND_INVALID; 5954 bool NeedSwap = false; 5955 switch (Predicate) { 5956 default: break; 5957 // Floating-point Predicates 5958 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break; 5959 case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH; 5960 case CmpInst::FCMP_OGT: CC = X86::COND_A; break; 5961 case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH; 5962 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break; 5963 case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH; 5964 case CmpInst::FCMP_ULT: CC = X86::COND_B; break; 5965 case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH; 5966 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break; 5967 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break; 5968 case CmpInst::FCMP_UNO: CC = X86::COND_P; break; 5969 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break; 5970 case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH; 5971 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break; 5972 5973 // Integer Predicates 5974 case CmpInst::ICMP_EQ: CC = X86::COND_E; break; 5975 case CmpInst::ICMP_NE: CC = X86::COND_NE; break; 5976 case CmpInst::ICMP_UGT: CC = X86::COND_A; break; 5977 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break; 5978 case CmpInst::ICMP_ULT: CC = X86::COND_B; break; 5979 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break; 5980 case CmpInst::ICMP_SGT: CC = X86::COND_G; break; 5981 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break; 5982 case CmpInst::ICMP_SLT: CC = X86::COND_L; break; 5983 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break; 5984 } 5985 5986 return std::make_pair(CC, NeedSwap); 5987} 5988 5989/// Return a set opcode for the given condition and 5990/// whether it has memory operand. 5991unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) { 5992 static const uint16_t Opc[16][2] = { 5993 { X86::SETAr, X86::SETAm }, 5994 { X86::SETAEr, X86::SETAEm }, 5995 { X86::SETBr, X86::SETBm }, 5996 { X86::SETBEr, X86::SETBEm }, 5997 { X86::SETEr, X86::SETEm }, 5998 { X86::SETGr, X86::SETGm }, 5999 { X86::SETGEr, X86::SETGEm }, 6000 { X86::SETLr, X86::SETLm }, 6001 { X86::SETLEr, X86::SETLEm }, 6002 { X86::SETNEr, X86::SETNEm }, 6003 { X86::SETNOr, X86::SETNOm }, 6004 { X86::SETNPr, X86::SETNPm }, 6005 { X86::SETNSr, X86::SETNSm }, 6006 { X86::SETOr, X86::SETOm }, 6007 { X86::SETPr, X86::SETPm }, 6008 { X86::SETSr, X86::SETSm } 6009 }; 6010 6011 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes"); 6012 return Opc[CC][HasMemoryOperand ? 1 : 0]; 6013} 6014 6015/// Return a cmov opcode for the given condition, 6016/// register size in bytes, and operand type. 6017unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, 6018 bool HasMemoryOperand) { 6019 static const uint16_t Opc[32][3] = { 6020 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 6021 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 6022 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 6023 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 6024 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 6025 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 6026 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 6027 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 6028 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 6029 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 6030 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 6031 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 6032 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 6033 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 6034 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 6035 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 6036 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 6037 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 6038 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 6039 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 6040 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 6041 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 6042 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 6043 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 6044 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 6045 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 6046 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 6047 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 6048 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 6049 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 6050 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 6051 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 6052 }; 6053 6054 assert(CC < 16 && "Can only handle standard cond codes"); 6055 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 6056 switch(RegBytes) { 6057 default: llvm_unreachable("Illegal register size!"); 6058 case 2: return Opc[Idx][0]; 6059 case 4: return Opc[Idx][1]; 6060 case 8: return Opc[Idx][2]; 6061 } 6062} 6063 6064bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const { 6065 if (!MI.isTerminator()) return false; 6066 6067 // Conditional branch is a special case. 6068 if (MI.isBranch() && !MI.isBarrier()) 6069 return true; 6070 if (!MI.isPredicable()) 6071 return true; 6072 return !isPredicated(MI); 6073} 6074 6075bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const { 6076 switch (MI.getOpcode()) { 6077 case X86::TCRETURNdi: 6078 case X86::TCRETURNri: 6079 case X86::TCRETURNmi: 6080 case X86::TCRETURNdi64: 6081 case X86::TCRETURNri64: 6082 case X86::TCRETURNmi64: 6083 return true; 6084 default: 6085 return false; 6086 } 6087} 6088 6089bool X86InstrInfo::canMakeTailCallConditional( 6090 SmallVectorImpl<MachineOperand> &BranchCond, 6091 const MachineInstr &TailCall) const { 6092 if (TailCall.getOpcode() != X86::TCRETURNdi && 6093 TailCall.getOpcode() != X86::TCRETURNdi64) { 6094 // Only direct calls can be done with a conditional branch. 6095 return false; 6096 } 6097 6098 const MachineFunction *MF = TailCall.getParent()->getParent(); 6099 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) { 6100 // Conditional tail calls confuse the Win64 unwinder. 6101 return false; 6102 } 6103 6104 assert(BranchCond.size() == 1); 6105 if (BranchCond[0].getImm() > X86::LAST_VALID_COND) { 6106 // Can't make a conditional tail call with this condition. 6107 return false; 6108 } 6109 6110 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 6111 if (X86FI->getTCReturnAddrDelta() != 0 || 6112 TailCall.getOperand(1).getImm() != 0) { 6113 // A conditional tail call cannot do any stack adjustment. 6114 return false; 6115 } 6116 6117 return true; 6118} 6119 6120void X86InstrInfo::replaceBranchWithTailCall( 6121 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond, 6122 const MachineInstr &TailCall) const { 6123 assert(canMakeTailCallConditional(BranchCond, TailCall)); 6124 6125 MachineBasicBlock::iterator I = MBB.end(); 6126 while (I != MBB.begin()) { 6127 --I; 6128 if (I->isDebugValue()) 6129 continue; 6130 if (!I->isBranch()) 6131 assert(0 && "Can't find the branch to replace!"); 6132 6133 X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode()); 6134 assert(BranchCond.size() == 1); 6135 if (CC != BranchCond[0].getImm()) 6136 continue; 6137 6138 break; 6139 } 6140 6141 unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc 6142 : X86::TCRETURNdi64cc; 6143 6144 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc)); 6145 MIB->addOperand(TailCall.getOperand(0)); // Destination. 6146 MIB.addImm(0); // Stack offset (not used). 6147 MIB->addOperand(BranchCond[0]); // Condition. 6148 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters. 6149 6150 // Add implicit uses and defs of all live regs potentially clobbered by the 6151 // call. This way they still appear live across the call. 6152 LivePhysRegs LiveRegs(getRegisterInfo()); 6153 LiveRegs.addLiveOuts(MBB); 6154 SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers; 6155 LiveRegs.stepForward(*MIB, Clobbers); 6156 for (const auto &C : Clobbers) { 6157 MIB.addReg(C.first, RegState::Implicit); 6158 MIB.addReg(C.first, RegState::Implicit | RegState::Define); 6159 } 6160 6161 I->eraseFromParent(); 6162} 6163 6164// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may 6165// not be a fallthrough MBB now due to layout changes). Return nullptr if the 6166// fallthrough MBB cannot be identified. 6167static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB, 6168 MachineBasicBlock *TBB) { 6169 // Look for non-EHPad successors other than TBB. If we find exactly one, it 6170 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB 6171 // and fallthrough MBB. If we find more than one, we cannot identify the 6172 // fallthrough MBB and should return nullptr. 6173 MachineBasicBlock *FallthroughBB = nullptr; 6174 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) { 6175 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB)) 6176 continue; 6177 // Return a nullptr if we found more than one fallthrough successor. 6178 if (FallthroughBB && FallthroughBB != TBB) 6179 return nullptr; 6180 FallthroughBB = *SI; 6181 } 6182 return FallthroughBB; 6183} 6184 6185bool X86InstrInfo::AnalyzeBranchImpl( 6186 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 6187 SmallVectorImpl<MachineOperand> &Cond, 6188 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const { 6189 6190 // Start from the bottom of the block and work up, examining the 6191 // terminator instructions. 6192 MachineBasicBlock::iterator I = MBB.end(); 6193 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 6194 while (I != MBB.begin()) { 6195 --I; 6196 if (I->isDebugValue()) 6197 continue; 6198 6199 // Working from the bottom, when we see a non-terminator instruction, we're 6200 // done. 6201 if (!isUnpredicatedTerminator(*I)) 6202 break; 6203 6204 // A terminator that isn't a branch can't easily be handled by this 6205 // analysis. 6206 if (!I->isBranch()) 6207 return true; 6208 6209 // Handle unconditional branches. 6210 if (I->getOpcode() == X86::JMP_1) { 6211 UnCondBrIter = I; 6212 6213 if (!AllowModify) { 6214 TBB = I->getOperand(0).getMBB(); 6215 continue; 6216 } 6217 6218 // If the block has any instructions after a JMP, delete them. 6219 while (std::next(I) != MBB.end()) 6220 std::next(I)->eraseFromParent(); 6221 6222 Cond.clear(); 6223 FBB = nullptr; 6224 6225 // Delete the JMP if it's equivalent to a fall-through. 6226 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 6227 TBB = nullptr; 6228 I->eraseFromParent(); 6229 I = MBB.end(); 6230 UnCondBrIter = MBB.end(); 6231 continue; 6232 } 6233 6234 // TBB is used to indicate the unconditional destination. 6235 TBB = I->getOperand(0).getMBB(); 6236 continue; 6237 } 6238 6239 // Handle conditional branches. 6240 X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode()); 6241 if (BranchCode == X86::COND_INVALID) 6242 return true; // Can't handle indirect branch. 6243 6244 // Working from the bottom, handle the first conditional branch. 6245 if (Cond.empty()) { 6246 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 6247 if (AllowModify && UnCondBrIter != MBB.end() && 6248 MBB.isLayoutSuccessor(TargetBB)) { 6249 // If we can modify the code and it ends in something like: 6250 // 6251 // jCC L1 6252 // jmp L2 6253 // L1: 6254 // ... 6255 // L2: 6256 // 6257 // Then we can change this to: 6258 // 6259 // jnCC L2 6260 // L1: 6261 // ... 6262 // L2: 6263 // 6264 // Which is a bit more efficient. 6265 // We conditionally jump to the fall-through block. 6266 BranchCode = GetOppositeBranchCondition(BranchCode); 6267 unsigned JNCC = GetCondBranchFromCond(BranchCode); 6268 MachineBasicBlock::iterator OldInst = I; 6269 6270 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 6271 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 6272 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1)) 6273 .addMBB(TargetBB); 6274 6275 OldInst->eraseFromParent(); 6276 UnCondBrIter->eraseFromParent(); 6277 6278 // Restart the analysis. 6279 UnCondBrIter = MBB.end(); 6280 I = MBB.end(); 6281 continue; 6282 } 6283 6284 FBB = TBB; 6285 TBB = I->getOperand(0).getMBB(); 6286 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 6287 CondBranches.push_back(&*I); 6288 continue; 6289 } 6290 6291 // Handle subsequent conditional branches. Only handle the case where all 6292 // conditional branches branch to the same destination and their condition 6293 // opcodes fit one of the special multi-branch idioms. 6294 assert(Cond.size() == 1); 6295 assert(TBB); 6296 6297 // If the conditions are the same, we can leave them alone. 6298 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 6299 auto NewTBB = I->getOperand(0).getMBB(); 6300 if (OldBranchCode == BranchCode && TBB == NewTBB) 6301 continue; 6302 6303 // If they differ, see if they fit one of the known patterns. Theoretically, 6304 // we could handle more patterns here, but we shouldn't expect to see them 6305 // if instruction selection has done a reasonable job. 6306 if (TBB == NewTBB && 6307 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) || 6308 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) { 6309 BranchCode = X86::COND_NE_OR_P; 6310 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) || 6311 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) { 6312 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB))) 6313 return true; 6314 6315 // X86::COND_E_AND_NP usually has two different branch destinations. 6316 // 6317 // JP B1 6318 // JE B2 6319 // JMP B1 6320 // B1: 6321 // B2: 6322 // 6323 // Here this condition branches to B2 only if NP && E. It has another 6324 // equivalent form: 6325 // 6326 // JNE B1 6327 // JNP B2 6328 // JMP B1 6329 // B1: 6330 // B2: 6331 // 6332 // Similarly it branches to B2 only if E && NP. That is why this condition 6333 // is named with COND_E_AND_NP. 6334 BranchCode = X86::COND_E_AND_NP; 6335 } else 6336 return true; 6337 6338 // Update the MachineOperand. 6339 Cond[0].setImm(BranchCode); 6340 CondBranches.push_back(&*I); 6341 } 6342 6343 return false; 6344} 6345 6346bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB, 6347 MachineBasicBlock *&TBB, 6348 MachineBasicBlock *&FBB, 6349 SmallVectorImpl<MachineOperand> &Cond, 6350 bool AllowModify) const { 6351 SmallVector<MachineInstr *, 4> CondBranches; 6352 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify); 6353} 6354 6355bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, 6356 MachineBranchPredicate &MBP, 6357 bool AllowModify) const { 6358 using namespace std::placeholders; 6359 6360 SmallVector<MachineOperand, 4> Cond; 6361 SmallVector<MachineInstr *, 4> CondBranches; 6362 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches, 6363 AllowModify)) 6364 return true; 6365 6366 if (Cond.size() != 1) 6367 return true; 6368 6369 assert(MBP.TrueDest && "expected!"); 6370 6371 if (!MBP.FalseDest) 6372 MBP.FalseDest = MBB.getNextNode(); 6373 6374 const TargetRegisterInfo *TRI = &getRegisterInfo(); 6375 6376 MachineInstr *ConditionDef = nullptr; 6377 bool SingleUseCondition = true; 6378 6379 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) { 6380 if (I->modifiesRegister(X86::EFLAGS, TRI)) { 6381 ConditionDef = &*I; 6382 break; 6383 } 6384 6385 if (I->readsRegister(X86::EFLAGS, TRI)) 6386 SingleUseCondition = false; 6387 } 6388 6389 if (!ConditionDef) 6390 return true; 6391 6392 if (SingleUseCondition) { 6393 for (auto *Succ : MBB.successors()) 6394 if (Succ->isLiveIn(X86::EFLAGS)) 6395 SingleUseCondition = false; 6396 } 6397 6398 MBP.ConditionDef = ConditionDef; 6399 MBP.SingleUseCondition = SingleUseCondition; 6400 6401 // Currently we only recognize the simple pattern: 6402 // 6403 // test %reg, %reg 6404 // je %label 6405 // 6406 const unsigned TestOpcode = 6407 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr; 6408 6409 if (ConditionDef->getOpcode() == TestOpcode && 6410 ConditionDef->getNumOperands() == 3 && 6411 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) && 6412 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) { 6413 MBP.LHS = ConditionDef->getOperand(0); 6414 MBP.RHS = MachineOperand::CreateImm(0); 6415 MBP.Predicate = Cond[0].getImm() == X86::COND_NE 6416 ? MachineBranchPredicate::PRED_NE 6417 : MachineBranchPredicate::PRED_EQ; 6418 return false; 6419 } 6420 6421 return true; 6422} 6423 6424unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, 6425 int *BytesRemoved) const { 6426 assert(!BytesRemoved && "code size not handled"); 6427 6428 MachineBasicBlock::iterator I = MBB.end(); 6429 unsigned Count = 0; 6430 6431 while (I != MBB.begin()) { 6432 --I; 6433 if (I->isDebugValue()) 6434 continue; 6435 if (I->getOpcode() != X86::JMP_1 && 6436 X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 6437 break; 6438 // Remove the branch. 6439 I->eraseFromParent(); 6440 I = MBB.end(); 6441 ++Count; 6442 } 6443 6444 return Count; 6445} 6446 6447unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB, 6448 MachineBasicBlock *TBB, 6449 MachineBasicBlock *FBB, 6450 ArrayRef<MachineOperand> Cond, 6451 const DebugLoc &DL, 6452 int *BytesAdded) const { 6453 // Shouldn't be a fall through. 6454 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 6455 assert((Cond.size() == 1 || Cond.size() == 0) && 6456 "X86 branch conditions have one component!"); 6457 assert(!BytesAdded && "code size not handled"); 6458 6459 if (Cond.empty()) { 6460 // Unconditional branch? 6461 assert(!FBB && "Unconditional branch with multiple successors!"); 6462 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB); 6463 return 1; 6464 } 6465 6466 // If FBB is null, it is implied to be a fall-through block. 6467 bool FallThru = FBB == nullptr; 6468 6469 // Conditional branch. 6470 unsigned Count = 0; 6471 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 6472 switch (CC) { 6473 case X86::COND_NE_OR_P: 6474 // Synthesize NE_OR_P with two branches. 6475 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB); 6476 ++Count; 6477 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB); 6478 ++Count; 6479 break; 6480 case X86::COND_E_AND_NP: 6481 // Use the next block of MBB as FBB if it is null. 6482 if (FBB == nullptr) { 6483 FBB = getFallThroughMBB(&MBB, TBB); 6484 assert(FBB && "MBB cannot be the last block in function when the false " 6485 "body is a fall-through."); 6486 } 6487 // Synthesize COND_E_AND_NP with two branches. 6488 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB); 6489 ++Count; 6490 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB); 6491 ++Count; 6492 break; 6493 default: { 6494 unsigned Opc = GetCondBranchFromCond(CC); 6495 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 6496 ++Count; 6497 } 6498 } 6499 if (!FallThru) { 6500 // Two-way Conditional branch. Insert the second branch. 6501 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB); 6502 ++Count; 6503 } 6504 return Count; 6505} 6506 6507bool X86InstrInfo:: 6508canInsertSelect(const MachineBasicBlock &MBB, 6509 ArrayRef<MachineOperand> Cond, 6510 unsigned TrueReg, unsigned FalseReg, 6511 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 6512 // Not all subtargets have cmov instructions. 6513 if (!Subtarget.hasCMov()) 6514 return false; 6515 if (Cond.size() != 1) 6516 return false; 6517 // We cannot do the composite conditions, at least not in SSA form. 6518 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 6519 return false; 6520 6521 // Check register classes. 6522 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 6523 const TargetRegisterClass *RC = 6524 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 6525 if (!RC) 6526 return false; 6527 6528 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 6529 if (X86::GR16RegClass.hasSubClassEq(RC) || 6530 X86::GR32RegClass.hasSubClassEq(RC) || 6531 X86::GR64RegClass.hasSubClassEq(RC)) { 6532 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 6533 // Bridge. Probably Ivy Bridge as well. 6534 CondCycles = 2; 6535 TrueCycles = 2; 6536 FalseCycles = 2; 6537 return true; 6538 } 6539 6540 // Can't do vectors. 6541 return false; 6542} 6543 6544void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 6545 MachineBasicBlock::iterator I, 6546 const DebugLoc &DL, unsigned DstReg, 6547 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 6548 unsigned FalseReg) const { 6549 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 6550 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); 6551 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg); 6552 assert(Cond.size() == 1 && "Invalid Cond array"); 6553 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 6554 TRI.getRegSizeInBits(RC) / 8, 6555 false /*HasMemoryOperand*/); 6556 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 6557} 6558 6559/// Test if the given register is a physical h register. 6560static bool isHReg(unsigned Reg) { 6561 return X86::GR8_ABCD_HRegClass.contains(Reg); 6562} 6563 6564// Try and copy between VR128/VR64 and GR64 registers. 6565static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg, 6566 const X86Subtarget &Subtarget) { 6567 bool HasAVX = Subtarget.hasAVX(); 6568 bool HasAVX512 = Subtarget.hasAVX512(); 6569 6570 // SrcReg(MaskReg) -> DestReg(GR64) 6571 // SrcReg(MaskReg) -> DestReg(GR32) 6572 6573 // All KMASK RegClasses hold the same k registers, can be tested against anyone. 6574 if (X86::VK16RegClass.contains(SrcReg)) { 6575 if (X86::GR64RegClass.contains(DestReg)) { 6576 assert(Subtarget.hasBWI()); 6577 return X86::KMOVQrk; 6578 } 6579 if (X86::GR32RegClass.contains(DestReg)) 6580 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk; 6581 } 6582 6583 // SrcReg(GR64) -> DestReg(MaskReg) 6584 // SrcReg(GR32) -> DestReg(MaskReg) 6585 6586 // All KMASK RegClasses hold the same k registers, can be tested against anyone. 6587 if (X86::VK16RegClass.contains(DestReg)) { 6588 if (X86::GR64RegClass.contains(SrcReg)) { 6589 assert(Subtarget.hasBWI()); 6590 return X86::KMOVQkr; 6591 } 6592 if (X86::GR32RegClass.contains(SrcReg)) 6593 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr; 6594 } 6595 6596 6597 // SrcReg(VR128) -> DestReg(GR64) 6598 // SrcReg(VR64) -> DestReg(GR64) 6599 // SrcReg(GR64) -> DestReg(VR128) 6600 // SrcReg(GR64) -> DestReg(VR64) 6601 6602 if (X86::GR64RegClass.contains(DestReg)) { 6603 if (X86::VR128XRegClass.contains(SrcReg)) 6604 // Copy from a VR128 register to a GR64 register. 6605 return HasAVX512 ? X86::VMOVPQIto64Zrr : 6606 HasAVX ? X86::VMOVPQIto64rr : 6607 X86::MOVPQIto64rr; 6608 if (X86::VR64RegClass.contains(SrcReg)) 6609 // Copy from a VR64 register to a GR64 register. 6610 return X86::MMX_MOVD64from64rr; 6611 } else if (X86::GR64RegClass.contains(SrcReg)) { 6612 // Copy from a GR64 register to a VR128 register. 6613 if (X86::VR128XRegClass.contains(DestReg)) 6614 return HasAVX512 ? X86::VMOV64toPQIZrr : 6615 HasAVX ? X86::VMOV64toPQIrr : 6616 X86::MOV64toPQIrr; 6617 // Copy from a GR64 register to a VR64 register. 6618 if (X86::VR64RegClass.contains(DestReg)) 6619 return X86::MMX_MOVD64to64rr; 6620 } 6621 6622 // SrcReg(FR32) -> DestReg(GR32) 6623 // SrcReg(GR32) -> DestReg(FR32) 6624 6625 if (X86::GR32RegClass.contains(DestReg) && 6626 X86::FR32XRegClass.contains(SrcReg)) 6627 // Copy from a FR32 register to a GR32 register. 6628 return HasAVX512 ? X86::VMOVSS2DIZrr : 6629 HasAVX ? X86::VMOVSS2DIrr : 6630 X86::MOVSS2DIrr; 6631 6632 if (X86::FR32XRegClass.contains(DestReg) && 6633 X86::GR32RegClass.contains(SrcReg)) 6634 // Copy from a GR32 register to a FR32 register. 6635 return HasAVX512 ? X86::VMOVDI2SSZrr : 6636 HasAVX ? X86::VMOVDI2SSrr : 6637 X86::MOVDI2SSrr; 6638 return 0; 6639} 6640 6641void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 6642 MachineBasicBlock::iterator MI, 6643 const DebugLoc &DL, unsigned DestReg, 6644 unsigned SrcReg, bool KillSrc) const { 6645 // First deal with the normal symmetric copies. 6646 bool HasAVX = Subtarget.hasAVX(); 6647 bool HasVLX = Subtarget.hasVLX(); 6648 unsigned Opc = 0; 6649 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 6650 Opc = X86::MOV64rr; 6651 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 6652 Opc = X86::MOV32rr; 6653 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 6654 Opc = X86::MOV16rr; 6655 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 6656 // Copying to or from a physical H register on x86-64 requires a NOREX 6657 // move. Otherwise use a normal move. 6658 if ((isHReg(DestReg) || isHReg(SrcReg)) && 6659 Subtarget.is64Bit()) { 6660 Opc = X86::MOV8rr_NOREX; 6661 // Both operands must be encodable without an REX prefix. 6662 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 6663 "8-bit H register can not be copied outside GR8_NOREX"); 6664 } else 6665 Opc = X86::MOV8rr; 6666 } 6667 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 6668 Opc = X86::MMX_MOVQ64rr; 6669 else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) { 6670 if (HasVLX) 6671 Opc = X86::VMOVAPSZ128rr; 6672 else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 6673 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 6674 else { 6675 // If this an extended register and we don't have VLX we need to use a 6676 // 512-bit move. 6677 Opc = X86::VMOVAPSZrr; 6678 const TargetRegisterInfo *TRI = &getRegisterInfo(); 6679 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, 6680 &X86::VR512RegClass); 6681 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, 6682 &X86::VR512RegClass); 6683 } 6684 } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) { 6685 if (HasVLX) 6686 Opc = X86::VMOVAPSZ256rr; 6687 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 6688 Opc = X86::VMOVAPSYrr; 6689 else { 6690 // If this an extended register and we don't have VLX we need to use a 6691 // 512-bit move. 6692 Opc = X86::VMOVAPSZrr; 6693 const TargetRegisterInfo *TRI = &getRegisterInfo(); 6694 DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, 6695 &X86::VR512RegClass); 6696 SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, 6697 &X86::VR512RegClass); 6698 } 6699 } else if (X86::VR512RegClass.contains(DestReg, SrcReg)) 6700 Opc = X86::VMOVAPSZrr; 6701 // All KMASK RegClasses hold the same k registers, can be tested against anyone. 6702 else if (X86::VK16RegClass.contains(DestReg, SrcReg)) 6703 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk; 6704 if (!Opc) 6705 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget); 6706 6707 if (Opc) { 6708 BuildMI(MBB, MI, DL, get(Opc), DestReg) 6709 .addReg(SrcReg, getKillRegState(KillSrc)); 6710 return; 6711 } 6712 6713 if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) { 6714 // FIXME: We use a fatal error here because historically LLVM has tried 6715 // lower some of these physreg copies and we want to ensure we get 6716 // reasonable bug reports if someone encounters a case no other testing 6717 // found. This path should be removed after the LLVM 7 release. 6718 report_fatal_error("Unable to copy EFLAGS physical register!"); 6719 } 6720 6721 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 6722 << " to " << RI.getName(DestReg) << '\n'); 6723 llvm_unreachable("Cannot emit physreg copy instruction"); 6724} 6725 6726static unsigned getLoadStoreRegOpcode(unsigned Reg, 6727 const TargetRegisterClass *RC, 6728 bool isStackAligned, 6729 const X86Subtarget &STI, 6730 bool load) { 6731 bool HasAVX = STI.hasAVX(); 6732 bool HasAVX512 = STI.hasAVX512(); 6733 bool HasVLX = STI.hasVLX(); 6734 6735 switch (STI.getRegisterInfo()->getSpillSize(*RC)) { 6736 default: 6737 llvm_unreachable("Unknown spill size"); 6738 case 1: 6739 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 6740 if (STI.is64Bit()) 6741 // Copying to or from a physical H register on x86-64 requires a NOREX 6742 // move. Otherwise use a normal move. 6743 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 6744 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 6745 return load ? X86::MOV8rm : X86::MOV8mr; 6746 case 2: 6747 if (X86::VK16RegClass.hasSubClassEq(RC)) 6748 return load ? X86::KMOVWkm : X86::KMOVWmk; 6749 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 6750 return load ? X86::MOV16rm : X86::MOV16mr; 6751 case 4: 6752 if (X86::GR32RegClass.hasSubClassEq(RC)) 6753 return load ? X86::MOV32rm : X86::MOV32mr; 6754 if (X86::FR32XRegClass.hasSubClassEq(RC)) 6755 return load ? 6756 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 6757 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 6758 if (X86::RFP32RegClass.hasSubClassEq(RC)) 6759 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 6760 if (X86::VK32RegClass.hasSubClassEq(RC)) 6761 return load ? X86::KMOVDkm : X86::KMOVDmk; 6762 llvm_unreachable("Unknown 4-byte regclass"); 6763 case 8: 6764 if (X86::GR64RegClass.hasSubClassEq(RC)) 6765 return load ? X86::MOV64rm : X86::MOV64mr; 6766 if (X86::FR64XRegClass.hasSubClassEq(RC)) 6767 return load ? 6768 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 6769 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 6770 if (X86::VR64RegClass.hasSubClassEq(RC)) 6771 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 6772 if (X86::RFP64RegClass.hasSubClassEq(RC)) 6773 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 6774 if (X86::VK64RegClass.hasSubClassEq(RC)) 6775 return load ? X86::KMOVQkm : X86::KMOVQmk; 6776 llvm_unreachable("Unknown 8-byte regclass"); 6777 case 10: 6778 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 6779 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 6780 case 16: { 6781 if (X86::VR128XRegClass.hasSubClassEq(RC)) { 6782 // If stack is realigned we can use aligned stores. 6783 if (isStackAligned) 6784 return load ? 6785 (HasVLX ? X86::VMOVAPSZ128rm : 6786 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX : 6787 HasAVX ? X86::VMOVAPSrm : 6788 X86::MOVAPSrm): 6789 (HasVLX ? X86::VMOVAPSZ128mr : 6790 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX : 6791 HasAVX ? X86::VMOVAPSmr : 6792 X86::MOVAPSmr); 6793 else 6794 return load ? 6795 (HasVLX ? X86::VMOVUPSZ128rm : 6796 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX : 6797 HasAVX ? X86::VMOVUPSrm : 6798 X86::MOVUPSrm): 6799 (HasVLX ? X86::VMOVUPSZ128mr : 6800 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX : 6801 HasAVX ? X86::VMOVUPSmr : 6802 X86::MOVUPSmr); 6803 } 6804 if (X86::BNDRRegClass.hasSubClassEq(RC)) { 6805 if (STI.is64Bit()) 6806 return load ? X86::BNDMOVRM64rm : X86::BNDMOVMR64mr; 6807 else 6808 return load ? X86::BNDMOVRM32rm : X86::BNDMOVMR32mr; 6809 } 6810 llvm_unreachable("Unknown 16-byte regclass"); 6811 } 6812 case 32: 6813 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 6814 // If stack is realigned we can use aligned stores. 6815 if (isStackAligned) 6816 return load ? 6817 (HasVLX ? X86::VMOVAPSZ256rm : 6818 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX : 6819 X86::VMOVAPSYrm) : 6820 (HasVLX ? X86::VMOVAPSZ256mr : 6821 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX : 6822 X86::VMOVAPSYmr); 6823 else 6824 return load ? 6825 (HasVLX ? X86::VMOVUPSZ256rm : 6826 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX : 6827 X86::VMOVUPSYrm) : 6828 (HasVLX ? X86::VMOVUPSZ256mr : 6829 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX : 6830 X86::VMOVUPSYmr); 6831 case 64: 6832 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); 6833 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512"); 6834 if (isStackAligned) 6835 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; 6836 else 6837 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 6838 } 6839} 6840 6841bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg, 6842 int64_t &Offset, 6843 const TargetRegisterInfo *TRI) const { 6844 const MCInstrDesc &Desc = MemOp.getDesc(); 6845 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags); 6846 if (MemRefBegin < 0) 6847 return false; 6848 6849 MemRefBegin += X86II::getOperandBias(Desc); 6850 6851 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); 6852 if (!BaseMO.isReg()) // Can be an MO_FrameIndex 6853 return false; 6854 6855 BaseReg = BaseMO.getReg(); 6856 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1) 6857 return false; 6858 6859 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != 6860 X86::NoRegister) 6861 return false; 6862 6863 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp); 6864 6865 // Displacement can be symbolic 6866 if (!DispMO.isImm()) 6867 return false; 6868 6869 Offset = DispMO.getImm(); 6870 6871 return true; 6872} 6873 6874static unsigned getStoreRegOpcode(unsigned SrcReg, 6875 const TargetRegisterClass *RC, 6876 bool isStackAligned, 6877 const X86Subtarget &STI) { 6878 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false); 6879} 6880 6881 6882static unsigned getLoadRegOpcode(unsigned DestReg, 6883 const TargetRegisterClass *RC, 6884 bool isStackAligned, 6885 const X86Subtarget &STI) { 6886 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true); 6887} 6888 6889void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 6890 MachineBasicBlock::iterator MI, 6891 unsigned SrcReg, bool isKill, int FrameIdx, 6892 const TargetRegisterClass *RC, 6893 const TargetRegisterInfo *TRI) const { 6894 const MachineFunction &MF = *MBB.getParent(); 6895 assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && 6896 "Stack slot too small for store"); 6897 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); 6898 bool isAligned = 6899 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) || 6900 RI.canRealignStack(MF); 6901 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 6902 DebugLoc DL = MBB.findDebugLoc(MI); 6903 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 6904 .addReg(SrcReg, getKillRegState(isKill)); 6905} 6906 6907void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 6908 bool isKill, 6909 SmallVectorImpl<MachineOperand> &Addr, 6910 const TargetRegisterClass *RC, 6911 MachineInstr::mmo_iterator MMOBegin, 6912 MachineInstr::mmo_iterator MMOEnd, 6913 SmallVectorImpl<MachineInstr*> &NewMIs) const { 6914 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 6915 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); 6916 bool isAligned = MMOBegin != MMOEnd && 6917 (*MMOBegin)->getAlignment() >= Alignment; 6918 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 6919 DebugLoc DL; 6920 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 6921 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 6922 MIB.add(Addr[i]); 6923 MIB.addReg(SrcReg, getKillRegState(isKill)); 6924 (*MIB).setMemRefs(MMOBegin, MMOEnd); 6925 NewMIs.push_back(MIB); 6926} 6927 6928 6929void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 6930 MachineBasicBlock::iterator MI, 6931 unsigned DestReg, int FrameIdx, 6932 const TargetRegisterClass *RC, 6933 const TargetRegisterInfo *TRI) const { 6934 const MachineFunction &MF = *MBB.getParent(); 6935 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); 6936 bool isAligned = 6937 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) || 6938 RI.canRealignStack(MF); 6939 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 6940 DebugLoc DL = MBB.findDebugLoc(MI); 6941 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 6942} 6943 6944void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 6945 SmallVectorImpl<MachineOperand> &Addr, 6946 const TargetRegisterClass *RC, 6947 MachineInstr::mmo_iterator MMOBegin, 6948 MachineInstr::mmo_iterator MMOEnd, 6949 SmallVectorImpl<MachineInstr*> &NewMIs) const { 6950 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 6951 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); 6952 bool isAligned = MMOBegin != MMOEnd && 6953 (*MMOBegin)->getAlignment() >= Alignment; 6954 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 6955 DebugLoc DL; 6956 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 6957 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 6958 MIB.add(Addr[i]); 6959 (*MIB).setMemRefs(MMOBegin, MMOEnd); 6960 NewMIs.push_back(MIB); 6961} 6962 6963bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 6964 unsigned &SrcReg2, int &CmpMask, 6965 int &CmpValue) const { 6966 switch (MI.getOpcode()) { 6967 default: break; 6968 case X86::CMP64ri32: 6969 case X86::CMP64ri8: 6970 case X86::CMP32ri: 6971 case X86::CMP32ri8: 6972 case X86::CMP16ri: 6973 case X86::CMP16ri8: 6974 case X86::CMP8ri: 6975 SrcReg = MI.getOperand(0).getReg(); 6976 SrcReg2 = 0; 6977 if (MI.getOperand(1).isImm()) { 6978 CmpMask = ~0; 6979 CmpValue = MI.getOperand(1).getImm(); 6980 } else { 6981 CmpMask = CmpValue = 0; 6982 } 6983 return true; 6984 // A SUB can be used to perform comparison. 6985 case X86::SUB64rm: 6986 case X86::SUB32rm: 6987 case X86::SUB16rm: 6988 case X86::SUB8rm: 6989 SrcReg = MI.getOperand(1).getReg(); 6990 SrcReg2 = 0; 6991 CmpMask = 0; 6992 CmpValue = 0; 6993 return true; 6994 case X86::SUB64rr: 6995 case X86::SUB32rr: 6996 case X86::SUB16rr: 6997 case X86::SUB8rr: 6998 SrcReg = MI.getOperand(1).getReg(); 6999 SrcReg2 = MI.getOperand(2).getReg(); 7000 CmpMask = 0; 7001 CmpValue = 0; 7002 return true; 7003 case X86::SUB64ri32: 7004 case X86::SUB64ri8: 7005 case X86::SUB32ri: 7006 case X86::SUB32ri8: 7007 case X86::SUB16ri: 7008 case X86::SUB16ri8: 7009 case X86::SUB8ri: 7010 SrcReg = MI.getOperand(1).getReg(); 7011 SrcReg2 = 0; 7012 if (MI.getOperand(2).isImm()) { 7013 CmpMask = ~0; 7014 CmpValue = MI.getOperand(2).getImm(); 7015 } else { 7016 CmpMask = CmpValue = 0; 7017 } 7018 return true; 7019 case X86::CMP64rr: 7020 case X86::CMP32rr: 7021 case X86::CMP16rr: 7022 case X86::CMP8rr: 7023 SrcReg = MI.getOperand(0).getReg(); 7024 SrcReg2 = MI.getOperand(1).getReg(); 7025 CmpMask = 0; 7026 CmpValue = 0; 7027 return true; 7028 case X86::TEST8rr: 7029 case X86::TEST16rr: 7030 case X86::TEST32rr: 7031 case X86::TEST64rr: 7032 SrcReg = MI.getOperand(0).getReg(); 7033 if (MI.getOperand(1).getReg() != SrcReg) 7034 return false; 7035 // Compare against zero. 7036 SrcReg2 = 0; 7037 CmpMask = ~0; 7038 CmpValue = 0; 7039 return true; 7040 } 7041 return false; 7042} 7043 7044/// Check whether the first instruction, whose only 7045/// purpose is to update flags, can be made redundant. 7046/// CMPrr can be made redundant by SUBrr if the operands are the same. 7047/// This function can be extended later on. 7048/// SrcReg, SrcRegs: register operands for FlagI. 7049/// ImmValue: immediate for FlagI if it takes an immediate. 7050inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg, 7051 unsigned SrcReg2, int ImmMask, 7052 int ImmValue, MachineInstr &OI) { 7053 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) || 7054 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) || 7055 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) || 7056 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) && 7057 ((OI.getOperand(1).getReg() == SrcReg && 7058 OI.getOperand(2).getReg() == SrcReg2) || 7059 (OI.getOperand(1).getReg() == SrcReg2 && 7060 OI.getOperand(2).getReg() == SrcReg))) 7061 return true; 7062 7063 if (ImmMask != 0 && 7064 ((FlagI.getOpcode() == X86::CMP64ri32 && 7065 OI.getOpcode() == X86::SUB64ri32) || 7066 (FlagI.getOpcode() == X86::CMP64ri8 && 7067 OI.getOpcode() == X86::SUB64ri8) || 7068 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) || 7069 (FlagI.getOpcode() == X86::CMP32ri8 && 7070 OI.getOpcode() == X86::SUB32ri8) || 7071 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) || 7072 (FlagI.getOpcode() == X86::CMP16ri8 && 7073 OI.getOpcode() == X86::SUB16ri8) || 7074 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) && 7075 OI.getOperand(1).getReg() == SrcReg && 7076 OI.getOperand(2).getImm() == ImmValue) 7077 return true; 7078 return false; 7079} 7080 7081/// Check whether the definition can be converted 7082/// to remove a comparison against zero. 7083inline static bool isDefConvertible(MachineInstr &MI) { 7084 switch (MI.getOpcode()) { 7085 default: return false; 7086 7087 // The shift instructions only modify ZF if their shift count is non-zero. 7088 // N.B.: The processor truncates the shift count depending on the encoding. 7089 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri: 7090 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri: 7091 return getTruncatedShiftCount(MI, 2) != 0; 7092 7093 // Some left shift instructions can be turned into LEA instructions but only 7094 // if their flags aren't used. Avoid transforming such instructions. 7095 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{ 7096 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 7097 if (isTruncatedShiftCountForLEA(ShAmt)) return false; 7098 return ShAmt != 0; 7099 } 7100 7101 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8: 7102 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8: 7103 return getTruncatedShiftCount(MI, 3) != 0; 7104 7105 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 7106 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 7107 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 7108 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 7109 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 7110 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 7111 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 7112 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 7113 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 7114 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 7115 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 7116 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 7117 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 7118 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 7119 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 7120 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 7121 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 7122 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 7123 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 7124 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 7125 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 7126 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 7127 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 7128 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 7129 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 7130 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 7131 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 7132 case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri: 7133 case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8: 7134 case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr: 7135 case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm: 7136 case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm: 7137 case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri: 7138 case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8: 7139 case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr: 7140 case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm: 7141 case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm: 7142 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: 7143 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1: 7144 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1: 7145 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1: 7146 case X86::ANDN32rr: case X86::ANDN32rm: 7147 case X86::ANDN64rr: case X86::ANDN64rm: 7148 case X86::BEXTR32rr: case X86::BEXTR64rr: 7149 case X86::BEXTR32rm: case X86::BEXTR64rm: 7150 case X86::BLSI32rr: case X86::BLSI32rm: 7151 case X86::BLSI64rr: case X86::BLSI64rm: 7152 case X86::BLSMSK32rr:case X86::BLSMSK32rm: 7153 case X86::BLSMSK64rr:case X86::BLSMSK64rm: 7154 case X86::BLSR32rr: case X86::BLSR32rm: 7155 case X86::BLSR64rr: case X86::BLSR64rm: 7156 case X86::BZHI32rr: case X86::BZHI32rm: 7157 case X86::BZHI64rr: case X86::BZHI64rm: 7158 case X86::LZCNT16rr: case X86::LZCNT16rm: 7159 case X86::LZCNT32rr: case X86::LZCNT32rm: 7160 case X86::LZCNT64rr: case X86::LZCNT64rm: 7161 case X86::POPCNT16rr:case X86::POPCNT16rm: 7162 case X86::POPCNT32rr:case X86::POPCNT32rm: 7163 case X86::POPCNT64rr:case X86::POPCNT64rm: 7164 case X86::TZCNT16rr: case X86::TZCNT16rm: 7165 case X86::TZCNT32rr: case X86::TZCNT32rm: 7166 case X86::TZCNT64rr: case X86::TZCNT64rm: 7167 case X86::BEXTRI32ri: case X86::BEXTRI32mi: 7168 case X86::BEXTRI64ri: case X86::BEXTRI64mi: 7169 case X86::BLCFILL32rr: case X86::BLCFILL32rm: 7170 case X86::BLCFILL64rr: case X86::BLCFILL64rm: 7171 case X86::BLCI32rr: case X86::BLCI32rm: 7172 case X86::BLCI64rr: case X86::BLCI64rm: 7173 case X86::BLCIC32rr: case X86::BLCIC32rm: 7174 case X86::BLCIC64rr: case X86::BLCIC64rm: 7175 case X86::BLCMSK32rr: case X86::BLCMSK32rm: 7176 case X86::BLCMSK64rr: case X86::BLCMSK64rm: 7177 case X86::BLCS32rr: case X86::BLCS32rm: 7178 case X86::BLCS64rr: case X86::BLCS64rm: 7179 case X86::BLSFILL32rr: case X86::BLSFILL32rm: 7180 case X86::BLSFILL64rr: case X86::BLSFILL64rm: 7181 case X86::BLSIC32rr: case X86::BLSIC32rm: 7182 case X86::BLSIC64rr: case X86::BLSIC64rm: 7183 return true; 7184 } 7185} 7186 7187/// Check whether the use can be converted to remove a comparison against zero. 7188static X86::CondCode isUseDefConvertible(MachineInstr &MI) { 7189 switch (MI.getOpcode()) { 7190 default: return X86::COND_INVALID; 7191 case X86::LZCNT16rr: case X86::LZCNT16rm: 7192 case X86::LZCNT32rr: case X86::LZCNT32rm: 7193 case X86::LZCNT64rr: case X86::LZCNT64rm: 7194 return X86::COND_B; 7195 case X86::POPCNT16rr:case X86::POPCNT16rm: 7196 case X86::POPCNT32rr:case X86::POPCNT32rm: 7197 case X86::POPCNT64rr:case X86::POPCNT64rm: 7198 return X86::COND_E; 7199 case X86::TZCNT16rr: case X86::TZCNT16rm: 7200 case X86::TZCNT32rr: case X86::TZCNT32rm: 7201 case X86::TZCNT64rr: case X86::TZCNT64rm: 7202 return X86::COND_B; 7203 } 7204} 7205 7206/// Check if there exists an earlier instruction that 7207/// operates on the same source operands and sets flags in the same way as 7208/// Compare; remove Compare if possible. 7209bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 7210 unsigned SrcReg2, int CmpMask, 7211 int CmpValue, 7212 const MachineRegisterInfo *MRI) const { 7213 // Check whether we can replace SUB with CMP. 7214 unsigned NewOpcode = 0; 7215 switch (CmpInstr.getOpcode()) { 7216 default: break; 7217 case X86::SUB64ri32: 7218 case X86::SUB64ri8: 7219 case X86::SUB32ri: 7220 case X86::SUB32ri8: 7221 case X86::SUB16ri: 7222 case X86::SUB16ri8: 7223 case X86::SUB8ri: 7224 case X86::SUB64rm: 7225 case X86::SUB32rm: 7226 case X86::SUB16rm: 7227 case X86::SUB8rm: 7228 case X86::SUB64rr: 7229 case X86::SUB32rr: 7230 case X86::SUB16rr: 7231 case X86::SUB8rr: { 7232 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg())) 7233 return false; 7234 // There is no use of the destination register, we can replace SUB with CMP. 7235 switch (CmpInstr.getOpcode()) { 7236 default: llvm_unreachable("Unreachable!"); 7237 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 7238 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 7239 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 7240 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 7241 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 7242 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 7243 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 7244 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 7245 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 7246 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 7247 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 7248 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 7249 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 7250 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 7251 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 7252 } 7253 CmpInstr.setDesc(get(NewOpcode)); 7254 CmpInstr.RemoveOperand(0); 7255 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 7256 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 7257 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 7258 return false; 7259 } 7260 } 7261 7262 // Get the unique definition of SrcReg. 7263 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 7264 if (!MI) return false; 7265 7266 // CmpInstr is the first instruction of the BB. 7267 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 7268 7269 // If we are comparing against zero, check whether we can use MI to update 7270 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 7271 bool IsCmpZero = (CmpMask != 0 && CmpValue == 0); 7272 if (IsCmpZero && MI->getParent() != CmpInstr.getParent()) 7273 return false; 7274 7275 // If we have a use of the source register between the def and our compare 7276 // instruction we can eliminate the compare iff the use sets EFLAGS in the 7277 // right way. 7278 bool ShouldUpdateCC = false; 7279 X86::CondCode NewCC = X86::COND_INVALID; 7280 if (IsCmpZero && !isDefConvertible(*MI)) { 7281 // Scan forward from the use until we hit the use we're looking for or the 7282 // compare instruction. 7283 for (MachineBasicBlock::iterator J = MI;; ++J) { 7284 // Do we have a convertible instruction? 7285 NewCC = isUseDefConvertible(*J); 7286 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() && 7287 J->getOperand(1).getReg() == SrcReg) { 7288 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"); 7289 ShouldUpdateCC = true; // Update CC later on. 7290 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going 7291 // with the new def. 7292 Def = J; 7293 MI = &*Def; 7294 break; 7295 } 7296 7297 if (J == I) 7298 return false; 7299 } 7300 } 7301 7302 // We are searching for an earlier instruction that can make CmpInstr 7303 // redundant and that instruction will be saved in Sub. 7304 MachineInstr *Sub = nullptr; 7305 const TargetRegisterInfo *TRI = &getRegisterInfo(); 7306 7307 // We iterate backward, starting from the instruction before CmpInstr and 7308 // stop when reaching the definition of a source register or done with the BB. 7309 // RI points to the instruction before CmpInstr. 7310 // If the definition is in this basic block, RE points to the definition; 7311 // otherwise, RE is the rend of the basic block. 7312 MachineBasicBlock::reverse_iterator 7313 RI = ++I.getReverse(), 7314 RE = CmpInstr.getParent() == MI->getParent() 7315 ? Def.getReverse() /* points to MI */ 7316 : CmpInstr.getParent()->rend(); 7317 MachineInstr *Movr0Inst = nullptr; 7318 for (; RI != RE; ++RI) { 7319 MachineInstr &Instr = *RI; 7320 // Check whether CmpInstr can be made redundant by the current instruction. 7321 if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, 7322 CmpValue, Instr)) { 7323 Sub = &Instr; 7324 break; 7325 } 7326 7327 if (Instr.modifiesRegister(X86::EFLAGS, TRI) || 7328 Instr.readsRegister(X86::EFLAGS, TRI)) { 7329 // This instruction modifies or uses EFLAGS. 7330 7331 // MOV32r0 etc. are implemented with xor which clobbers condition code. 7332 // They are safe to move up, if the definition to EFLAGS is dead and 7333 // earlier instructions do not read or write EFLAGS. 7334 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 && 7335 Instr.registerDefIsDead(X86::EFLAGS, TRI)) { 7336 Movr0Inst = &Instr; 7337 continue; 7338 } 7339 7340 // We can't remove CmpInstr. 7341 return false; 7342 } 7343 } 7344 7345 // Return false if no candidates exist. 7346 if (!IsCmpZero && !Sub) 7347 return false; 7348 7349 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 7350 Sub->getOperand(2).getReg() == SrcReg); 7351 7352 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 7353 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 7354 // If we are done with the basic block, we need to check whether EFLAGS is 7355 // live-out. 7356 bool IsSafe = false; 7357 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 7358 MachineBasicBlock::iterator E = CmpInstr.getParent()->end(); 7359 for (++I; I != E; ++I) { 7360 const MachineInstr &Instr = *I; 7361 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 7362 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 7363 // We should check the usage if this instruction uses and updates EFLAGS. 7364 if (!UseEFLAGS && ModifyEFLAGS) { 7365 // It is safe to remove CmpInstr if EFLAGS is updated again. 7366 IsSafe = true; 7367 break; 7368 } 7369 if (!UseEFLAGS && !ModifyEFLAGS) 7370 continue; 7371 7372 // EFLAGS is used by this instruction. 7373 X86::CondCode OldCC = X86::COND_INVALID; 7374 bool OpcIsSET = false; 7375 if (IsCmpZero || IsSwapped) { 7376 // We decode the condition code from opcode. 7377 if (Instr.isBranch()) 7378 OldCC = X86::getCondFromBranchOpc(Instr.getOpcode()); 7379 else { 7380 OldCC = X86::getCondFromSETOpc(Instr.getOpcode()); 7381 if (OldCC != X86::COND_INVALID) 7382 OpcIsSET = true; 7383 else 7384 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 7385 } 7386 if (OldCC == X86::COND_INVALID) return false; 7387 } 7388 X86::CondCode ReplacementCC = X86::COND_INVALID; 7389 if (IsCmpZero) { 7390 switch (OldCC) { 7391 default: break; 7392 case X86::COND_A: case X86::COND_AE: 7393 case X86::COND_B: case X86::COND_BE: 7394 case X86::COND_G: case X86::COND_GE: 7395 case X86::COND_L: case X86::COND_LE: 7396 case X86::COND_O: case X86::COND_NO: 7397 // CF and OF are used, we can't perform this optimization. 7398 return false; 7399 } 7400 7401 // If we're updating the condition code check if we have to reverse the 7402 // condition. 7403 if (ShouldUpdateCC) 7404 switch (OldCC) { 7405 default: 7406 return false; 7407 case X86::COND_E: 7408 ReplacementCC = NewCC; 7409 break; 7410 case X86::COND_NE: 7411 ReplacementCC = GetOppositeBranchCondition(NewCC); 7412 break; 7413 } 7414 } else if (IsSwapped) { 7415 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 7416 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 7417 // We swap the condition code and synthesize the new opcode. 7418 ReplacementCC = getSwappedCondition(OldCC); 7419 if (ReplacementCC == X86::COND_INVALID) return false; 7420 } 7421 7422 if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) { 7423 // Synthesize the new opcode. 7424 bool HasMemoryOperand = Instr.hasOneMemOperand(); 7425 unsigned NewOpc; 7426 if (Instr.isBranch()) 7427 NewOpc = GetCondBranchFromCond(ReplacementCC); 7428 else if(OpcIsSET) 7429 NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand); 7430 else { 7431 unsigned DstReg = Instr.getOperand(0).getReg(); 7432 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 7433 NewOpc = getCMovFromCond(ReplacementCC, TRI->getRegSizeInBits(*DstRC)/8, 7434 HasMemoryOperand); 7435 } 7436 7437 // Push the MachineInstr to OpsToUpdate. 7438 // If it is safe to remove CmpInstr, the condition code of these 7439 // instructions will be modified. 7440 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 7441 } 7442 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 7443 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 7444 IsSafe = true; 7445 break; 7446 } 7447 } 7448 7449 // If EFLAGS is not killed nor re-defined, we should check whether it is 7450 // live-out. If it is live-out, do not optimize. 7451 if ((IsCmpZero || IsSwapped) && !IsSafe) { 7452 MachineBasicBlock *MBB = CmpInstr.getParent(); 7453 for (MachineBasicBlock *Successor : MBB->successors()) 7454 if (Successor->isLiveIn(X86::EFLAGS)) 7455 return false; 7456 } 7457 7458 // The instruction to be updated is either Sub or MI. 7459 Sub = IsCmpZero ? MI : Sub; 7460 // Move Movr0Inst to the appropriate place before Sub. 7461 if (Movr0Inst) { 7462 // Look backwards until we find a def that doesn't use the current EFLAGS. 7463 Def = Sub; 7464 MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(), 7465 InsertE = Sub->getParent()->rend(); 7466 for (; InsertI != InsertE; ++InsertI) { 7467 MachineInstr *Instr = &*InsertI; 7468 if (!Instr->readsRegister(X86::EFLAGS, TRI) && 7469 Instr->modifiesRegister(X86::EFLAGS, TRI)) { 7470 Sub->getParent()->remove(Movr0Inst); 7471 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr), 7472 Movr0Inst); 7473 break; 7474 } 7475 } 7476 if (InsertI == InsertE) 7477 return false; 7478 } 7479 7480 // Make sure Sub instruction defines EFLAGS and mark the def live. 7481 unsigned i = 0, e = Sub->getNumOperands(); 7482 for (; i != e; ++i) { 7483 MachineOperand &MO = Sub->getOperand(i); 7484 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) { 7485 MO.setIsDead(false); 7486 break; 7487 } 7488 } 7489 assert(i != e && "Unable to locate a def EFLAGS operand"); 7490 7491 CmpInstr.eraseFromParent(); 7492 7493 // Modify the condition code of instructions in OpsToUpdate. 7494 for (auto &Op : OpsToUpdate) 7495 Op.first->setDesc(get(Op.second)); 7496 return true; 7497} 7498 7499/// Try to remove the load by folding it to a register 7500/// operand at the use. We fold the load instructions if load defines a virtual 7501/// register, the virtual register is used once in the same BB, and the 7502/// instructions in-between do not load or store, and have no side effects. 7503MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI, 7504 const MachineRegisterInfo *MRI, 7505 unsigned &FoldAsLoadDefReg, 7506 MachineInstr *&DefMI) const { 7507 // Check whether we can move DefMI here. 7508 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 7509 assert(DefMI); 7510 bool SawStore = false; 7511 if (!DefMI->isSafeToMove(nullptr, SawStore)) 7512 return nullptr; 7513 7514 // Collect information about virtual register operands of MI. 7515 SmallVector<unsigned, 1> SrcOperandIds; 7516 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 7517 MachineOperand &MO = MI.getOperand(i); 7518 if (!MO.isReg()) 7519 continue; 7520 unsigned Reg = MO.getReg(); 7521 if (Reg != FoldAsLoadDefReg) 7522 continue; 7523 // Do not fold if we have a subreg use or a def. 7524 if (MO.getSubReg() || MO.isDef()) 7525 return nullptr; 7526 SrcOperandIds.push_back(i); 7527 } 7528 if (SrcOperandIds.empty()) 7529 return nullptr; 7530 7531 // Check whether we can fold the def into SrcOperandId. 7532 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) { 7533 FoldAsLoadDefReg = 0; 7534 return FoldMI; 7535 } 7536 7537 return nullptr; 7538} 7539 7540/// Expand a single-def pseudo instruction to a two-addr 7541/// instruction with two undef reads of the register being defined. 7542/// This is used for mapping: 7543/// %xmm4 = V_SET0 7544/// to: 7545/// %xmm4 = PXORrr undef %xmm4, undef %xmm4 7546/// 7547static bool Expand2AddrUndef(MachineInstrBuilder &MIB, 7548 const MCInstrDesc &Desc) { 7549 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 7550 unsigned Reg = MIB->getOperand(0).getReg(); 7551 MIB->setDesc(Desc); 7552 7553 // MachineInstr::addOperand() will insert explicit operands before any 7554 // implicit operands. 7555 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 7556 // But we don't trust that. 7557 assert(MIB->getOperand(1).getReg() == Reg && 7558 MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 7559 return true; 7560} 7561 7562/// Expand a single-def pseudo instruction to a two-addr 7563/// instruction with two %k0 reads. 7564/// This is used for mapping: 7565/// %k4 = K_SET1 7566/// to: 7567/// %k4 = KXNORrr %k0, %k0 7568static bool Expand2AddrKreg(MachineInstrBuilder &MIB, 7569 const MCInstrDesc &Desc, unsigned Reg) { 7570 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 7571 MIB->setDesc(Desc); 7572 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 7573 return true; 7574} 7575 7576static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, 7577 bool MinusOne) { 7578 MachineBasicBlock &MBB = *MIB->getParent(); 7579 DebugLoc DL = MIB->getDebugLoc(); 7580 unsigned Reg = MIB->getOperand(0).getReg(); 7581 7582 // Insert the XOR. 7583 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg) 7584 .addReg(Reg, RegState::Undef) 7585 .addReg(Reg, RegState::Undef); 7586 7587 // Turn the pseudo into an INC or DEC. 7588 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r)); 7589 MIB.addReg(Reg); 7590 7591 return true; 7592} 7593 7594static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, 7595 const TargetInstrInfo &TII, 7596 const X86Subtarget &Subtarget) { 7597 MachineBasicBlock &MBB = *MIB->getParent(); 7598 DebugLoc DL = MIB->getDebugLoc(); 7599 int64_t Imm = MIB->getOperand(1).getImm(); 7600 assert(Imm != 0 && "Using push/pop for 0 is not efficient."); 7601 MachineBasicBlock::iterator I = MIB.getInstr(); 7602 7603 int StackAdjustment; 7604 7605 if (Subtarget.is64Bit()) { 7606 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 || 7607 MIB->getOpcode() == X86::MOV32ImmSExti8); 7608 7609 // Can't use push/pop lowering if the function might write to the red zone. 7610 X86MachineFunctionInfo *X86FI = 7611 MBB.getParent()->getInfo<X86MachineFunctionInfo>(); 7612 if (X86FI->getUsesRedZone()) { 7613 MIB->setDesc(TII.get(MIB->getOpcode() == 7614 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri)); 7615 return true; 7616 } 7617 7618 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and 7619 // widen the register if necessary. 7620 StackAdjustment = 8; 7621 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm); 7622 MIB->setDesc(TII.get(X86::POP64r)); 7623 MIB->getOperand(0) 7624 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64)); 7625 } else { 7626 assert(MIB->getOpcode() == X86::MOV32ImmSExti8); 7627 StackAdjustment = 4; 7628 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm); 7629 MIB->setDesc(TII.get(X86::POP32r)); 7630 } 7631 7632 // Build CFI if necessary. 7633 MachineFunction &MF = *MBB.getParent(); 7634 const X86FrameLowering *TFL = Subtarget.getFrameLowering(); 7635 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI(); 7636 bool NeedsDwarfCFI = 7637 !IsWin64Prologue && 7638 (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry()); 7639 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI; 7640 if (EmitCFI) { 7641 TFL->BuildCFI(MBB, I, DL, 7642 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment)); 7643 TFL->BuildCFI(MBB, std::next(I), DL, 7644 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment)); 7645 } 7646 7647 return true; 7648} 7649 7650// LoadStackGuard has so far only been implemented for 64-bit MachO. Different 7651// code sequence is needed for other targets. 7652static void expandLoadStackGuard(MachineInstrBuilder &MIB, 7653 const TargetInstrInfo &TII) { 7654 MachineBasicBlock &MBB = *MIB->getParent(); 7655 DebugLoc DL = MIB->getDebugLoc(); 7656 unsigned Reg = MIB->getOperand(0).getReg(); 7657 const GlobalValue *GV = 7658 cast<GlobalValue>((*MIB->memoperands_begin())->getValue()); 7659 auto Flags = MachineMemOperand::MOLoad | 7660 MachineMemOperand::MODereferenceable | 7661 MachineMemOperand::MOInvariant; 7662 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand( 7663 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8); 7664 MachineBasicBlock::iterator I = MIB.getInstr(); 7665 7666 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1) 7667 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0) 7668 .addMemOperand(MMO); 7669 MIB->setDebugLoc(DL); 7670 MIB->setDesc(TII.get(X86::MOV64rm)); 7671 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0); 7672} 7673 7674static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) { 7675 MachineBasicBlock &MBB = *MIB->getParent(); 7676 MachineFunction &MF = *MBB.getParent(); 7677 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); 7678 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo(); 7679 unsigned XorOp = 7680 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr; 7681 MIB->setDesc(TII.get(XorOp)); 7682 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef); 7683 return true; 7684} 7685 7686// This is used to handle spills for 128/256-bit registers when we have AVX512, 7687// but not VLX. If it uses an extended register we need to use an instruction 7688// that loads the lower 128/256-bit, but is available with only AVX512F. 7689static bool expandNOVLXLoad(MachineInstrBuilder &MIB, 7690 const TargetRegisterInfo *TRI, 7691 const MCInstrDesc &LoadDesc, 7692 const MCInstrDesc &BroadcastDesc, 7693 unsigned SubIdx) { 7694 unsigned DestReg = MIB->getOperand(0).getReg(); 7695 // Check if DestReg is XMM16-31 or YMM16-31. 7696 if (TRI->getEncodingValue(DestReg) < 16) { 7697 // We can use a normal VEX encoded load. 7698 MIB->setDesc(LoadDesc); 7699 } else { 7700 // Use a 128/256-bit VBROADCAST instruction. 7701 MIB->setDesc(BroadcastDesc); 7702 // Change the destination to a 512-bit register. 7703 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass); 7704 MIB->getOperand(0).setReg(DestReg); 7705 } 7706 return true; 7707} 7708 7709// This is used to handle spills for 128/256-bit registers when we have AVX512, 7710// but not VLX. If it uses an extended register we need to use an instruction 7711// that stores the lower 128/256-bit, but is available with only AVX512F. 7712static bool expandNOVLXStore(MachineInstrBuilder &MIB, 7713 const TargetRegisterInfo *TRI, 7714 const MCInstrDesc &StoreDesc, 7715 const MCInstrDesc &ExtractDesc, 7716 unsigned SubIdx) { 7717 unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg(); 7718 // Check if DestReg is XMM16-31 or YMM16-31. 7719 if (TRI->getEncodingValue(SrcReg) < 16) { 7720 // We can use a normal VEX encoded store. 7721 MIB->setDesc(StoreDesc); 7722 } else { 7723 // Use a VEXTRACTF instruction. 7724 MIB->setDesc(ExtractDesc); 7725 // Change the destination to a 512-bit register. 7726 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass); 7727 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg); 7728 MIB.addImm(0x0); // Append immediate to extract from the lower bits. 7729 } 7730 7731 return true; 7732} 7733bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 7734 bool HasAVX = Subtarget.hasAVX(); 7735 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); 7736 switch (MI.getOpcode()) { 7737 case X86::MOV32r0: 7738 return Expand2AddrUndef(MIB, get(X86::XOR32rr)); 7739 case X86::MOV32r1: 7740 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false); 7741 case X86::MOV32r_1: 7742 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true); 7743 case X86::MOV32ImmSExti8: 7744 case X86::MOV64ImmSExti8: 7745 return ExpandMOVImmSExti8(MIB, *this, Subtarget); 7746 case X86::SETB_C8r: 7747 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 7748 case X86::SETB_C16r: 7749 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 7750 case X86::SETB_C32r: 7751 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 7752 case X86::SETB_C64r: 7753 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 7754 case X86::V_SET0: 7755 case X86::FsFLD0SS: 7756 case X86::FsFLD0SD: 7757 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 7758 case X86::AVX_SET0: { 7759 assert(HasAVX && "AVX not supported"); 7760 const TargetRegisterInfo *TRI = &getRegisterInfo(); 7761 unsigned SrcReg = MIB->getOperand(0).getReg(); 7762 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); 7763 MIB->getOperand(0).setReg(XReg); 7764 Expand2AddrUndef(MIB, get(X86::VXORPSrr)); 7765 MIB.addReg(SrcReg, RegState::ImplicitDefine); 7766 return true; 7767 } 7768 case X86::AVX512_128_SET0: 7769 case X86::AVX512_FsFLD0SS: 7770 case X86::AVX512_FsFLD0SD: { 7771 bool HasVLX = Subtarget.hasVLX(); 7772 unsigned SrcReg = MIB->getOperand(0).getReg(); 7773 const TargetRegisterInfo *TRI = &getRegisterInfo(); 7774 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) 7775 return Expand2AddrUndef(MIB, 7776 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); 7777 // Extended register without VLX. Use a larger XOR. 7778 SrcReg = 7779 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); 7780 MIB->getOperand(0).setReg(SrcReg); 7781 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 7782 } 7783 case X86::AVX512_256_SET0: 7784 case X86::AVX512_512_SET0: { 7785 bool HasVLX = Subtarget.hasVLX(); 7786 unsigned SrcReg = MIB->getOperand(0).getReg(); 7787 const TargetRegisterInfo *TRI = &getRegisterInfo(); 7788 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) { 7789 unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); 7790 MIB->getOperand(0).setReg(XReg); 7791 Expand2AddrUndef(MIB, 7792 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); 7793 MIB.addReg(SrcReg, RegState::ImplicitDefine); 7794 return true; 7795 } 7796 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 7797 } 7798 case X86::V_SETALLONES: 7799 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 7800 case X86::AVX2_SETALLONES: 7801 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 7802 case X86::AVX1_SETALLONES: { 7803 unsigned Reg = MIB->getOperand(0).getReg(); 7804 // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS. 7805 MIB->setDesc(get(X86::VCMPPSYrri)); 7806 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf); 7807 return true; 7808 } 7809 case X86::AVX512_512_SETALLONES: { 7810 unsigned Reg = MIB->getOperand(0).getReg(); 7811 MIB->setDesc(get(X86::VPTERNLOGDZrri)); 7812 // VPTERNLOGD needs 3 register inputs and an immediate. 7813 // 0xff will return 1s for any input. 7814 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef) 7815 .addReg(Reg, RegState::Undef).addImm(0xff); 7816 return true; 7817 } 7818 case X86::AVX512_512_SEXT_MASK_32: 7819 case X86::AVX512_512_SEXT_MASK_64: { 7820 unsigned Reg = MIB->getOperand(0).getReg(); 7821 unsigned MaskReg = MIB->getOperand(1).getReg(); 7822 unsigned MaskState = getRegState(MIB->getOperand(1)); 7823 unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ? 7824 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz; 7825 MI.RemoveOperand(1); 7826 MIB->setDesc(get(Opc)); 7827 // VPTERNLOG needs 3 register inputs and an immediate. 7828 // 0xff will return 1s for any input. 7829 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) 7830 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff); 7831 return true; 7832 } 7833 case X86::VMOVAPSZ128rm_NOVLX: 7834 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm), 7835 get(X86::VBROADCASTF32X4rm), X86::sub_xmm); 7836 case X86::VMOVUPSZ128rm_NOVLX: 7837 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm), 7838 get(X86::VBROADCASTF32X4rm), X86::sub_xmm); 7839 case X86::VMOVAPSZ256rm_NOVLX: 7840 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm), 7841 get(X86::VBROADCASTF64X4rm), X86::sub_ymm); 7842 case X86::VMOVUPSZ256rm_NOVLX: 7843 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm), 7844 get(X86::VBROADCASTF64X4rm), X86::sub_ymm); 7845 case X86::VMOVAPSZ128mr_NOVLX: 7846 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr), 7847 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm); 7848 case X86::VMOVUPSZ128mr_NOVLX: 7849 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr), 7850 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm); 7851 case X86::VMOVAPSZ256mr_NOVLX: 7852 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr), 7853 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm); 7854 case X86::VMOVUPSZ256mr_NOVLX: 7855 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr), 7856 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm); 7857 case X86::TEST8ri_NOREX: 7858 MI.setDesc(get(X86::TEST8ri)); 7859 return true; 7860 case X86::MOV32ri64: 7861 MI.setDesc(get(X86::MOV32ri)); 7862 return true; 7863 7864 // KNL does not recognize dependency-breaking idioms for mask registers, 7865 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1. 7866 // Using %k0 as the undef input register is a performance heuristic based 7867 // on the assumption that %k0 is used less frequently than the other mask 7868 // registers, since it is not usable as a write mask. 7869 // FIXME: A more advanced approach would be to choose the best input mask 7870 // register based on context. 7871 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0); 7872 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0); 7873 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0); 7874 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0); 7875 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0); 7876 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0); 7877 case TargetOpcode::LOAD_STACK_GUARD: 7878 expandLoadStackGuard(MIB, *this); 7879 return true; 7880 case X86::XOR64_FP: 7881 case X86::XOR32_FP: 7882 return expandXorFP(MIB, *this); 7883 } 7884 return false; 7885} 7886 7887/// Return true for all instructions that only update 7888/// the first 32 or 64-bits of the destination register and leave the rest 7889/// unmodified. This can be used to avoid folding loads if the instructions 7890/// only update part of the destination register, and the non-updated part is 7891/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 7892/// instructions breaks the partial register dependency and it can improve 7893/// performance. e.g.: 7894/// 7895/// movss (%rdi), %xmm0 7896/// cvtss2sd %xmm0, %xmm0 7897/// 7898/// Instead of 7899/// cvtss2sd (%rdi), %xmm0 7900/// 7901/// FIXME: This should be turned into a TSFlags. 7902/// 7903static bool hasPartialRegUpdate(unsigned Opcode) { 7904 switch (Opcode) { 7905 case X86::CVTSI2SSrr: 7906 case X86::CVTSI2SSrm: 7907 case X86::CVTSI642SSrr: 7908 case X86::CVTSI642SSrm: 7909 case X86::CVTSI2SDrr: 7910 case X86::CVTSI2SDrm: 7911 case X86::CVTSI642SDrr: 7912 case X86::CVTSI642SDrm: 7913 case X86::CVTSD2SSrr: 7914 case X86::CVTSD2SSrm: 7915 case X86::CVTSS2SDrr: 7916 case X86::CVTSS2SDrm: 7917 case X86::MOVHPDrm: 7918 case X86::MOVHPSrm: 7919 case X86::MOVLPDrm: 7920 case X86::MOVLPSrm: 7921 case X86::RCPSSr: 7922 case X86::RCPSSm: 7923 case X86::RCPSSr_Int: 7924 case X86::RCPSSm_Int: 7925 case X86::ROUNDSDr: 7926 case X86::ROUNDSDm: 7927 case X86::ROUNDSSr: 7928 case X86::ROUNDSSm: 7929 case X86::RSQRTSSr: 7930 case X86::RSQRTSSm: 7931 case X86::RSQRTSSr_Int: 7932 case X86::RSQRTSSm_Int: 7933 case X86::SQRTSSr: 7934 case X86::SQRTSSm: 7935 case X86::SQRTSSr_Int: 7936 case X86::SQRTSSm_Int: 7937 case X86::SQRTSDr: 7938 case X86::SQRTSDm: 7939 case X86::SQRTSDr_Int: 7940 case X86::SQRTSDm_Int: 7941 return true; 7942 } 7943 7944 return false; 7945} 7946 7947/// Inform the ExecutionDepsFix pass how many idle 7948/// instructions we would like before a partial register update. 7949unsigned X86InstrInfo::getPartialRegUpdateClearance( 7950 const MachineInstr &MI, unsigned OpNum, 7951 const TargetRegisterInfo *TRI) const { 7952 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode())) 7953 return 0; 7954 7955 // If MI is marked as reading Reg, the partial register update is wanted. 7956 const MachineOperand &MO = MI.getOperand(0); 7957 unsigned Reg = MO.getReg(); 7958 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 7959 if (MO.readsReg() || MI.readsVirtualRegister(Reg)) 7960 return 0; 7961 } else { 7962 if (MI.readsRegister(Reg, TRI)) 7963 return 0; 7964 } 7965 7966 // If any instructions in the clearance range are reading Reg, insert a 7967 // dependency breaking instruction, which is inexpensive and is likely to 7968 // be hidden in other instruction's cycles. 7969 return PartialRegUpdateClearance; 7970} 7971 7972// Return true for any instruction the copies the high bits of the first source 7973// operand into the unused high bits of the destination operand. 7974static bool hasUndefRegUpdate(unsigned Opcode) { 7975 switch (Opcode) { 7976 case X86::VCVTSI2SSrr: 7977 case X86::VCVTSI2SSrm: 7978 case X86::VCVTSI2SSrr_Int: 7979 case X86::VCVTSI2SSrm_Int: 7980 case X86::VCVTSI642SSrr: 7981 case X86::VCVTSI642SSrm: 7982 case X86::VCVTSI642SSrr_Int: 7983 case X86::VCVTSI642SSrm_Int: 7984 case X86::VCVTSI2SDrr: 7985 case X86::VCVTSI2SDrm: 7986 case X86::VCVTSI2SDrr_Int: 7987 case X86::VCVTSI2SDrm_Int: 7988 case X86::VCVTSI642SDrr: 7989 case X86::VCVTSI642SDrm: 7990 case X86::VCVTSI642SDrr_Int: 7991 case X86::VCVTSI642SDrm_Int: 7992 case X86::VCVTSD2SSrr: 7993 case X86::VCVTSD2SSrm: 7994 case X86::VCVTSD2SSrr_Int: 7995 case X86::VCVTSD2SSrm_Int: 7996 case X86::VCVTSS2SDrr: 7997 case X86::VCVTSS2SDrm: 7998 case X86::VCVTSS2SDrr_Int: 7999 case X86::VCVTSS2SDrm_Int: 8000 case X86::VRCPSSr: 8001 case X86::VRCPSSr_Int: 8002 case X86::VRCPSSm: 8003 case X86::VRCPSSm_Int: 8004 case X86::VROUNDSDr: 8005 case X86::VROUNDSDm: 8006 case X86::VROUNDSDr_Int: 8007 case X86::VROUNDSDm_Int: 8008 case X86::VROUNDSSr: 8009 case X86::VROUNDSSm: 8010 case X86::VROUNDSSr_Int: 8011 case X86::VROUNDSSm_Int: 8012 case X86::VRSQRTSSr: 8013 case X86::VRSQRTSSr_Int: 8014 case X86::VRSQRTSSm: 8015 case X86::VRSQRTSSm_Int: 8016 case X86::VSQRTSSr: 8017 case X86::VSQRTSSr_Int: 8018 case X86::VSQRTSSm: 8019 case X86::VSQRTSSm_Int: 8020 case X86::VSQRTSDr: 8021 case X86::VSQRTSDr_Int: 8022 case X86::VSQRTSDm: 8023 case X86::VSQRTSDm_Int: 8024 // AVX-512 8025 case X86::VCVTSI2SSZrr: 8026 case X86::VCVTSI2SSZrm: 8027 case X86::VCVTSI2SSZrr_Int: 8028 case X86::VCVTSI2SSZrrb_Int: 8029 case X86::VCVTSI2SSZrm_Int: 8030 case X86::VCVTSI642SSZrr: 8031 case X86::VCVTSI642SSZrm: 8032 case X86::VCVTSI642SSZrr_Int: 8033 case X86::VCVTSI642SSZrrb_Int: 8034 case X86::VCVTSI642SSZrm_Int: 8035 case X86::VCVTSI2SDZrr: 8036 case X86::VCVTSI2SDZrm: 8037 case X86::VCVTSI2SDZrr_Int: 8038 case X86::VCVTSI2SDZrrb_Int: 8039 case X86::VCVTSI2SDZrm_Int: 8040 case X86::VCVTSI642SDZrr: 8041 case X86::VCVTSI642SDZrm: 8042 case X86::VCVTSI642SDZrr_Int: 8043 case X86::VCVTSI642SDZrrb_Int: 8044 case X86::VCVTSI642SDZrm_Int: 8045 case X86::VCVTUSI2SSZrr: 8046 case X86::VCVTUSI2SSZrm: 8047 case X86::VCVTUSI2SSZrr_Int: 8048 case X86::VCVTUSI2SSZrrb_Int: 8049 case X86::VCVTUSI2SSZrm_Int: 8050 case X86::VCVTUSI642SSZrr: 8051 case X86::VCVTUSI642SSZrm: 8052 case X86::VCVTUSI642SSZrr_Int: 8053 case X86::VCVTUSI642SSZrrb_Int: 8054 case X86::VCVTUSI642SSZrm_Int: 8055 case X86::VCVTUSI2SDZrr: 8056 case X86::VCVTUSI2SDZrm: 8057 case X86::VCVTUSI2SDZrr_Int: 8058 case X86::VCVTUSI2SDZrm_Int: 8059 case X86::VCVTUSI642SDZrr: 8060 case X86::VCVTUSI642SDZrm: 8061 case X86::VCVTUSI642SDZrr_Int: 8062 case X86::VCVTUSI642SDZrrb_Int: 8063 case X86::VCVTUSI642SDZrm_Int: 8064 case X86::VCVTSD2SSZrr: 8065 case X86::VCVTSD2SSZrr_Int: 8066 case X86::VCVTSD2SSZrrb_Int: 8067 case X86::VCVTSD2SSZrm: 8068 case X86::VCVTSD2SSZrm_Int: 8069 case X86::VCVTSS2SDZrr: 8070 case X86::VCVTSS2SDZrr_Int: 8071 case X86::VCVTSS2SDZrrb_Int: 8072 case X86::VCVTSS2SDZrm: 8073 case X86::VCVTSS2SDZrm_Int: 8074 case X86::VRNDSCALESDr: 8075 case X86::VRNDSCALESDr_Int: 8076 case X86::VRNDSCALESDrb_Int: 8077 case X86::VRNDSCALESDm: 8078 case X86::VRNDSCALESDm_Int: 8079 case X86::VRNDSCALESSr: 8080 case X86::VRNDSCALESSr_Int: 8081 case X86::VRNDSCALESSrb_Int: 8082 case X86::VRNDSCALESSm: 8083 case X86::VRNDSCALESSm_Int: 8084 case X86::VRCP14SSrr: 8085 case X86::VRCP14SSrm: 8086 case X86::VRSQRT14SSrr: 8087 case X86::VRSQRT14SSrm: 8088 case X86::VSQRTSSZr: 8089 case X86::VSQRTSSZr_Int: 8090 case X86::VSQRTSSZrb_Int: 8091 case X86::VSQRTSSZm: 8092 case X86::VSQRTSSZm_Int: 8093 case X86::VSQRTSDZr: 8094 case X86::VSQRTSDZr_Int: 8095 case X86::VSQRTSDZrb_Int: 8096 case X86::VSQRTSDZm: 8097 case X86::VSQRTSDZm_Int: 8098 return true; 8099 } 8100 8101 return false; 8102} 8103 8104/// Inform the ExecutionDepsFix pass how many idle instructions we would like 8105/// before certain undef register reads. 8106/// 8107/// This catches the VCVTSI2SD family of instructions: 8108/// 8109/// vcvtsi2sdq %rax, undef %xmm0, %xmm14 8110/// 8111/// We should to be careful *not* to catch VXOR idioms which are presumably 8112/// handled specially in the pipeline: 8113/// 8114/// vxorps undef %xmm1, undef %xmm1, %xmm1 8115/// 8116/// Like getPartialRegUpdateClearance, this makes a strong assumption that the 8117/// high bits that are passed-through are not live. 8118unsigned 8119X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, 8120 const TargetRegisterInfo *TRI) const { 8121 if (!hasUndefRegUpdate(MI.getOpcode())) 8122 return 0; 8123 8124 // Set the OpNum parameter to the first source operand. 8125 OpNum = 1; 8126 8127 const MachineOperand &MO = MI.getOperand(OpNum); 8128 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { 8129 return UndefRegClearance; 8130 } 8131 return 0; 8132} 8133 8134void X86InstrInfo::breakPartialRegDependency( 8135 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const { 8136 unsigned Reg = MI.getOperand(OpNum).getReg(); 8137 // If MI kills this register, the false dependence is already broken. 8138 if (MI.killsRegister(Reg, TRI)) 8139 return; 8140 8141 if (X86::VR128RegClass.contains(Reg)) { 8142 // These instructions are all floating point domain, so xorps is the best 8143 // choice. 8144 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr; 8145 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg) 8146 .addReg(Reg, RegState::Undef) 8147 .addReg(Reg, RegState::Undef); 8148 MI.addRegisterKilled(Reg, TRI, true); 8149 } else if (X86::VR256RegClass.contains(Reg)) { 8150 // Use vxorps to clear the full ymm register. 8151 // It wants to read and write the xmm sub-register. 8152 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 8153 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg) 8154 .addReg(XReg, RegState::Undef) 8155 .addReg(XReg, RegState::Undef) 8156 .addReg(Reg, RegState::ImplicitDefine); 8157 MI.addRegisterKilled(Reg, TRI, true); 8158 } 8159} 8160 8161static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs, 8162 int PtrOffset = 0) { 8163 unsigned NumAddrOps = MOs.size(); 8164 8165 if (NumAddrOps < 4) { 8166 // FrameIndex only - add an immediate offset (whether its zero or not). 8167 for (unsigned i = 0; i != NumAddrOps; ++i) 8168 MIB.add(MOs[i]); 8169 addOffset(MIB, PtrOffset); 8170 } else { 8171 // General Memory Addressing - we need to add any offset to an existing 8172 // offset. 8173 assert(MOs.size() == 5 && "Unexpected memory operand list length"); 8174 for (unsigned i = 0; i != NumAddrOps; ++i) { 8175 const MachineOperand &MO = MOs[i]; 8176 if (i == 3 && PtrOffset != 0) { 8177 MIB.addDisp(MO, PtrOffset); 8178 } else { 8179 MIB.add(MO); 8180 } 8181 } 8182 } 8183} 8184 8185static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 8186 ArrayRef<MachineOperand> MOs, 8187 MachineBasicBlock::iterator InsertPt, 8188 MachineInstr &MI, 8189 const TargetInstrInfo &TII) { 8190 // Create the base instruction with the memory operand as the first part. 8191 // Omit the implicit operands, something BuildMI can't do. 8192 MachineInstr *NewMI = 8193 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true); 8194 MachineInstrBuilder MIB(MF, NewMI); 8195 addOperands(MIB, MOs); 8196 8197 // Loop over the rest of the ri operands, converting them over. 8198 unsigned NumOps = MI.getDesc().getNumOperands() - 2; 8199 for (unsigned i = 0; i != NumOps; ++i) { 8200 MachineOperand &MO = MI.getOperand(i + 2); 8201 MIB.add(MO); 8202 } 8203 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) { 8204 MachineOperand &MO = MI.getOperand(i); 8205 MIB.add(MO); 8206 } 8207 8208 MachineBasicBlock *MBB = InsertPt->getParent(); 8209 MBB->insert(InsertPt, NewMI); 8210 8211 return MIB; 8212} 8213 8214static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode, 8215 unsigned OpNo, ArrayRef<MachineOperand> MOs, 8216 MachineBasicBlock::iterator InsertPt, 8217 MachineInstr &MI, const TargetInstrInfo &TII, 8218 int PtrOffset = 0) { 8219 // Omit the implicit operands, something BuildMI can't do. 8220 MachineInstr *NewMI = 8221 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true); 8222 MachineInstrBuilder MIB(MF, NewMI); 8223 8224 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 8225 MachineOperand &MO = MI.getOperand(i); 8226 if (i == OpNo) { 8227 assert(MO.isReg() && "Expected to fold into reg operand!"); 8228 addOperands(MIB, MOs, PtrOffset); 8229 } else { 8230 MIB.add(MO); 8231 } 8232 } 8233 8234 MachineBasicBlock *MBB = InsertPt->getParent(); 8235 MBB->insert(InsertPt, NewMI); 8236 8237 return MIB; 8238} 8239 8240static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 8241 ArrayRef<MachineOperand> MOs, 8242 MachineBasicBlock::iterator InsertPt, 8243 MachineInstr &MI) { 8244 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt, 8245 MI.getDebugLoc(), TII.get(Opcode)); 8246 addOperands(MIB, MOs); 8247 return MIB.addImm(0); 8248} 8249 8250MachineInstr *X86InstrInfo::foldMemoryOperandCustom( 8251 MachineFunction &MF, MachineInstr &MI, unsigned OpNum, 8252 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt, 8253 unsigned Size, unsigned Align) const { 8254 switch (MI.getOpcode()) { 8255 case X86::INSERTPSrr: 8256 case X86::VINSERTPSrr: 8257 case X86::VINSERTPSZrr: 8258 // Attempt to convert the load of inserted vector into a fold load 8259 // of a single float. 8260 if (OpNum == 2) { 8261 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm(); 8262 unsigned ZMask = Imm & 15; 8263 unsigned DstIdx = (Imm >> 4) & 3; 8264 unsigned SrcIdx = (Imm >> 6) & 3; 8265 8266 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8267 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF); 8268 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8; 8269 if (Size <= RCSize && 4 <= Align) { 8270 int PtrOffset = SrcIdx * 4; 8271 unsigned NewImm = (DstIdx << 4) | ZMask; 8272 unsigned NewOpCode = 8273 (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm : 8274 (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm : 8275 X86::INSERTPSrm; 8276 MachineInstr *NewMI = 8277 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset); 8278 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm); 8279 return NewMI; 8280 } 8281 } 8282 break; 8283 case X86::MOVHLPSrr: 8284 case X86::VMOVHLPSrr: 8285 case X86::VMOVHLPSZrr: 8286 // Move the upper 64-bits of the second operand to the lower 64-bits. 8287 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS. 8288 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement. 8289 if (OpNum == 2) { 8290 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8291 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF); 8292 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8; 8293 if (Size <= RCSize && 8 <= Align) { 8294 unsigned NewOpCode = 8295 (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm : 8296 (MI.getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm : 8297 X86::MOVLPSrm; 8298 MachineInstr *NewMI = 8299 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8); 8300 return NewMI; 8301 } 8302 } 8303 break; 8304 }; 8305 8306 return nullptr; 8307} 8308 8309MachineInstr *X86InstrInfo::foldMemoryOperandImpl( 8310 MachineFunction &MF, MachineInstr &MI, unsigned OpNum, 8311 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt, 8312 unsigned Size, unsigned Align, bool AllowCommute) const { 8313 const DenseMap<unsigned, 8314 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr; 8315 bool isSlowTwoMemOps = Subtarget.slowTwoMemOps(); 8316 bool isTwoAddrFold = false; 8317 8318 // For CPUs that favor the register form of a call or push, 8319 // do not fold loads into calls or pushes, unless optimizing for size 8320 // aggressively. 8321 if (isSlowTwoMemOps && !MF.getFunction().optForMinSize() && 8322 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r || 8323 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r || 8324 MI.getOpcode() == X86::PUSH64r)) 8325 return nullptr; 8326 8327 // Avoid partial register update stalls unless optimizing for size. 8328 // TODO: we should block undef reg update as well. 8329 if (!MF.getFunction().optForSize() && hasPartialRegUpdate(MI.getOpcode())) 8330 return nullptr; 8331 8332 unsigned NumOps = MI.getDesc().getNumOperands(); 8333 bool isTwoAddr = 8334 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 8335 8336 // FIXME: AsmPrinter doesn't know how to handle 8337 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 8338 if (MI.getOpcode() == X86::ADD32ri && 8339 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 8340 return nullptr; 8341 8342 MachineInstr *NewMI = nullptr; 8343 8344 // Attempt to fold any custom cases we have. 8345 if (MachineInstr *CustomMI = 8346 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align)) 8347 return CustomMI; 8348 8349 // Folding a memory location into the two-address part of a two-address 8350 // instruction is different than folding it other places. It requires 8351 // replacing the *two* registers with the memory location. 8352 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() && 8353 MI.getOperand(1).isReg() && 8354 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { 8355 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 8356 isTwoAddrFold = true; 8357 } else if (OpNum == 0) { 8358 if (MI.getOpcode() == X86::MOV32r0) { 8359 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI); 8360 if (NewMI) 8361 return NewMI; 8362 } 8363 8364 OpcodeTablePtr = &RegOp2MemOpTable0; 8365 } else if (OpNum == 1) { 8366 OpcodeTablePtr = &RegOp2MemOpTable1; 8367 } else if (OpNum == 2) { 8368 OpcodeTablePtr = &RegOp2MemOpTable2; 8369 } else if (OpNum == 3) { 8370 OpcodeTablePtr = &RegOp2MemOpTable3; 8371 } else if (OpNum == 4) { 8372 OpcodeTablePtr = &RegOp2MemOpTable4; 8373 } 8374 8375 // If table selected... 8376 if (OpcodeTablePtr) { 8377 // Find the Opcode to fuse 8378 auto I = OpcodeTablePtr->find(MI.getOpcode()); 8379 if (I != OpcodeTablePtr->end()) { 8380 unsigned Opcode = I->second.first; 8381 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 8382 if (Align < MinAlign) 8383 return nullptr; 8384 bool NarrowToMOV32rm = false; 8385 if (Size) { 8386 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8387 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, 8388 &RI, MF); 8389 unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8; 8390 if (Size < RCSize) { 8391 // Check if it's safe to fold the load. If the size of the object is 8392 // narrower than the load width, then it's not. 8393 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 8394 return nullptr; 8395 // If this is a 64-bit load, but the spill slot is 32, then we can do 8396 // a 32-bit load which is implicitly zero-extended. This likely is 8397 // due to live interval analysis remat'ing a load from stack slot. 8398 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 8399 return nullptr; 8400 Opcode = X86::MOV32rm; 8401 NarrowToMOV32rm = true; 8402 } 8403 } 8404 8405 if (isTwoAddrFold) 8406 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this); 8407 else 8408 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this); 8409 8410 if (NarrowToMOV32rm) { 8411 // If this is the special case where we use a MOV32rm to load a 32-bit 8412 // value and zero-extend the top bits. Change the destination register 8413 // to a 32-bit one. 8414 unsigned DstReg = NewMI->getOperand(0).getReg(); 8415 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 8416 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit)); 8417 else 8418 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 8419 } 8420 return NewMI; 8421 } 8422 } 8423 8424 // If the instruction and target operand are commutable, commute the 8425 // instruction and try again. 8426 if (AllowCommute) { 8427 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex; 8428 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) { 8429 bool HasDef = MI.getDesc().getNumDefs(); 8430 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0; 8431 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg(); 8432 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg(); 8433 bool Tied1 = 8434 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); 8435 bool Tied2 = 8436 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); 8437 8438 // If either of the commutable operands are tied to the destination 8439 // then we can not commute + fold. 8440 if ((HasDef && Reg0 == Reg1 && Tied1) || 8441 (HasDef && Reg0 == Reg2 && Tied2)) 8442 return nullptr; 8443 8444 MachineInstr *CommutedMI = 8445 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2); 8446 if (!CommutedMI) { 8447 // Unable to commute. 8448 return nullptr; 8449 } 8450 if (CommutedMI != &MI) { 8451 // New instruction. We can't fold from this. 8452 CommutedMI->eraseFromParent(); 8453 return nullptr; 8454 } 8455 8456 // Attempt to fold with the commuted version of the instruction. 8457 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, 8458 Size, Align, /*AllowCommute=*/false); 8459 if (NewMI) 8460 return NewMI; 8461 8462 // Folding failed again - undo the commute before returning. 8463 MachineInstr *UncommutedMI = 8464 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2); 8465 if (!UncommutedMI) { 8466 // Unable to commute. 8467 return nullptr; 8468 } 8469 if (UncommutedMI != &MI) { 8470 // New instruction. It doesn't need to be kept. 8471 UncommutedMI->eraseFromParent(); 8472 return nullptr; 8473 } 8474 8475 // Return here to prevent duplicate fuse failure report. 8476 return nullptr; 8477 } 8478 } 8479 8480 // No fusion 8481 if (PrintFailedFusing && !MI.isCopy()) 8482 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI; 8483 return nullptr; 8484} 8485 8486MachineInstr * 8487X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 8488 ArrayRef<unsigned> Ops, 8489 MachineBasicBlock::iterator InsertPt, 8490 int FrameIndex, LiveIntervals *LIS) const { 8491 // Check switch flag 8492 if (NoFusing) 8493 return nullptr; 8494 8495 // Unless optimizing for size, don't fold to avoid partial 8496 // register update stalls 8497 // TODO: we should block undef reg update as well. 8498 if (!MF.getFunction().optForSize() && hasPartialRegUpdate(MI.getOpcode())) 8499 return nullptr; 8500 8501 // Don't fold subreg spills, or reloads that use a high subreg. 8502 for (auto Op : Ops) { 8503 MachineOperand &MO = MI.getOperand(Op); 8504 auto SubReg = MO.getSubReg(); 8505 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi)) 8506 return nullptr; 8507 } 8508 8509 const MachineFrameInfo &MFI = MF.getFrameInfo(); 8510 unsigned Size = MFI.getObjectSize(FrameIndex); 8511 unsigned Alignment = MFI.getObjectAlignment(FrameIndex); 8512 // If the function stack isn't realigned we don't want to fold instructions 8513 // that need increased alignment. 8514 if (!RI.needsStackRealignment(MF)) 8515 Alignment = 8516 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment()); 8517 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 8518 unsigned NewOpc = 0; 8519 unsigned RCSize = 0; 8520 switch (MI.getOpcode()) { 8521 default: return nullptr; 8522 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 8523 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 8524 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 8525 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 8526 } 8527 // Check if it's safe to fold the load. If the size of the object is 8528 // narrower than the load width, then it's not. 8529 if (Size < RCSize) 8530 return nullptr; 8531 // Change to CMPXXri r, 0 first. 8532 MI.setDesc(get(NewOpc)); 8533 MI.getOperand(1).ChangeToImmediate(0); 8534 } else if (Ops.size() != 1) 8535 return nullptr; 8536 8537 return foldMemoryOperandImpl(MF, MI, Ops[0], 8538 MachineOperand::CreateFI(FrameIndex), InsertPt, 8539 Size, Alignment, /*AllowCommute=*/true); 8540} 8541 8542/// Check if \p LoadMI is a partial register load that we can't fold into \p MI 8543/// because the latter uses contents that wouldn't be defined in the folded 8544/// version. For instance, this transformation isn't legal: 8545/// movss (%rdi), %xmm0 8546/// addps %xmm0, %xmm0 8547/// -> 8548/// addps (%rdi), %xmm0 8549/// 8550/// But this one is: 8551/// movss (%rdi), %xmm0 8552/// addss %xmm0, %xmm0 8553/// -> 8554/// addss (%rdi), %xmm0 8555/// 8556static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, 8557 const MachineInstr &UserMI, 8558 const MachineFunction &MF) { 8559 unsigned Opc = LoadMI.getOpcode(); 8560 unsigned UserOpc = UserMI.getOpcode(); 8561 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8562 const TargetRegisterClass *RC = 8563 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg()); 8564 unsigned RegSize = TRI.getRegSizeInBits(*RC); 8565 8566 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) && 8567 RegSize > 32) { 8568 // These instructions only load 32 bits, we can't fold them if the 8569 // destination register is wider than 32 bits (4 bytes), and its user 8570 // instruction isn't scalar (SS). 8571 switch (UserOpc) { 8572 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int: 8573 case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int: 8574 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int: 8575 case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int: 8576 case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int: 8577 case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int: 8578 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int: 8579 case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz: 8580 case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz: 8581 case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz: 8582 case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz: 8583 case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz: 8584 case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz: 8585 case X86::VFMADDSS4rr_Int: case X86::VFNMADDSS4rr_Int: 8586 case X86::VFMSUBSS4rr_Int: case X86::VFNMSUBSS4rr_Int: 8587 case X86::VFMADD132SSr_Int: case X86::VFNMADD132SSr_Int: 8588 case X86::VFMADD213SSr_Int: case X86::VFNMADD213SSr_Int: 8589 case X86::VFMADD231SSr_Int: case X86::VFNMADD231SSr_Int: 8590 case X86::VFMSUB132SSr_Int: case X86::VFNMSUB132SSr_Int: 8591 case X86::VFMSUB213SSr_Int: case X86::VFNMSUB213SSr_Int: 8592 case X86::VFMSUB231SSr_Int: case X86::VFNMSUB231SSr_Int: 8593 case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int: 8594 case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int: 8595 case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int: 8596 case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int: 8597 case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int: 8598 case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int: 8599 case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk: 8600 case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk: 8601 case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk: 8602 case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk: 8603 case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk: 8604 case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk: 8605 case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz: 8606 case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz: 8607 case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz: 8608 case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz: 8609 case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz: 8610 case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz: 8611 return false; 8612 default: 8613 return true; 8614 } 8615 } 8616 8617 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) && 8618 RegSize > 64) { 8619 // These instructions only load 64 bits, we can't fold them if the 8620 // destination register is wider than 64 bits (8 bytes), and its user 8621 // instruction isn't scalar (SD). 8622 switch (UserOpc) { 8623 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int: 8624 case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int: 8625 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int: 8626 case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int: 8627 case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int: 8628 case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int: 8629 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int: 8630 case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz: 8631 case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz: 8632 case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz: 8633 case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz: 8634 case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz: 8635 case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz: 8636 case X86::VFMADDSD4rr_Int: case X86::VFNMADDSD4rr_Int: 8637 case X86::VFMSUBSD4rr_Int: case X86::VFNMSUBSD4rr_Int: 8638 case X86::VFMADD132SDr_Int: case X86::VFNMADD132SDr_Int: 8639 case X86::VFMADD213SDr_Int: case X86::VFNMADD213SDr_Int: 8640 case X86::VFMADD231SDr_Int: case X86::VFNMADD231SDr_Int: 8641 case X86::VFMSUB132SDr_Int: case X86::VFNMSUB132SDr_Int: 8642 case X86::VFMSUB213SDr_Int: case X86::VFNMSUB213SDr_Int: 8643 case X86::VFMSUB231SDr_Int: case X86::VFNMSUB231SDr_Int: 8644 case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int: 8645 case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int: 8646 case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int: 8647 case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int: 8648 case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int: 8649 case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int: 8650 case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk: 8651 case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk: 8652 case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk: 8653 case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk: 8654 case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk: 8655 case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk: 8656 case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz: 8657 case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz: 8658 case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz: 8659 case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz: 8660 case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz: 8661 case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz: 8662 return false; 8663 default: 8664 return true; 8665 } 8666 } 8667 8668 return false; 8669} 8670 8671MachineInstr *X86InstrInfo::foldMemoryOperandImpl( 8672 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 8673 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 8674 LiveIntervals *LIS) const { 8675 8676 // TODO: Support the case where LoadMI loads a wide register, but MI 8677 // only uses a subreg. 8678 for (auto Op : Ops) { 8679 if (MI.getOperand(Op).getSubReg()) 8680 return nullptr; 8681 } 8682 8683 // If loading from a FrameIndex, fold directly from the FrameIndex. 8684 unsigned NumOps = LoadMI.getDesc().getNumOperands(); 8685 int FrameIndex; 8686 if (isLoadFromStackSlot(LoadMI, FrameIndex)) { 8687 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF)) 8688 return nullptr; 8689 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS); 8690 } 8691 8692 // Check switch flag 8693 if (NoFusing) return nullptr; 8694 8695 // Avoid partial register update stalls unless optimizing for size. 8696 // TODO: we should block undef reg update as well. 8697 if (!MF.getFunction().optForSize() && hasPartialRegUpdate(MI.getOpcode())) 8698 return nullptr; 8699 8700 // Determine the alignment of the load. 8701 unsigned Alignment = 0; 8702 if (LoadMI.hasOneMemOperand()) 8703 Alignment = (*LoadMI.memoperands_begin())->getAlignment(); 8704 else 8705 switch (LoadMI.getOpcode()) { 8706 case X86::AVX512_512_SET0: 8707 case X86::AVX512_512_SETALLONES: 8708 Alignment = 64; 8709 break; 8710 case X86::AVX2_SETALLONES: 8711 case X86::AVX1_SETALLONES: 8712 case X86::AVX_SET0: 8713 case X86::AVX512_256_SET0: 8714 Alignment = 32; 8715 break; 8716 case X86::V_SET0: 8717 case X86::V_SETALLONES: 8718 case X86::AVX512_128_SET0: 8719 Alignment = 16; 8720 break; 8721 case X86::FsFLD0SD: 8722 case X86::AVX512_FsFLD0SD: 8723 Alignment = 8; 8724 break; 8725 case X86::FsFLD0SS: 8726 case X86::AVX512_FsFLD0SS: 8727 Alignment = 4; 8728 break; 8729 default: 8730 return nullptr; 8731 } 8732 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 8733 unsigned NewOpc = 0; 8734 switch (MI.getOpcode()) { 8735 default: return nullptr; 8736 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 8737 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 8738 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 8739 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 8740 } 8741 // Change to CMPXXri r, 0 first. 8742 MI.setDesc(get(NewOpc)); 8743 MI.getOperand(1).ChangeToImmediate(0); 8744 } else if (Ops.size() != 1) 8745 return nullptr; 8746 8747 // Make sure the subregisters match. 8748 // Otherwise we risk changing the size of the load. 8749 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg()) 8750 return nullptr; 8751 8752 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 8753 switch (LoadMI.getOpcode()) { 8754 case X86::V_SET0: 8755 case X86::V_SETALLONES: 8756 case X86::AVX2_SETALLONES: 8757 case X86::AVX1_SETALLONES: 8758 case X86::AVX_SET0: 8759 case X86::AVX512_128_SET0: 8760 case X86::AVX512_256_SET0: 8761 case X86::AVX512_512_SET0: 8762 case X86::AVX512_512_SETALLONES: 8763 case X86::FsFLD0SD: 8764 case X86::AVX512_FsFLD0SD: 8765 case X86::FsFLD0SS: 8766 case X86::AVX512_FsFLD0SS: { 8767 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 8768 // Create a constant-pool entry and operands to load from it. 8769 8770 // Medium and large mode can't fold loads this way. 8771 if (MF.getTarget().getCodeModel() != CodeModel::Small && 8772 MF.getTarget().getCodeModel() != CodeModel::Kernel) 8773 return nullptr; 8774 8775 // x86-32 PIC requires a PIC base register for constant pools. 8776 unsigned PICBase = 0; 8777 if (MF.getTarget().isPositionIndependent()) { 8778 if (Subtarget.is64Bit()) 8779 PICBase = X86::RIP; 8780 else 8781 // FIXME: PICBase = getGlobalBaseReg(&MF); 8782 // This doesn't work for several reasons. 8783 // 1. GlobalBaseReg may have been spilled. 8784 // 2. It may not be live at MI. 8785 return nullptr; 8786 } 8787 8788 // Create a constant-pool entry. 8789 MachineConstantPool &MCP = *MF.getConstantPool(); 8790 Type *Ty; 8791 unsigned Opc = LoadMI.getOpcode(); 8792 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS) 8793 Ty = Type::getFloatTy(MF.getFunction().getContext()); 8794 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD) 8795 Ty = Type::getDoubleTy(MF.getFunction().getContext()); 8796 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES) 8797 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16); 8798 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 || 8799 Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES) 8800 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8); 8801 else 8802 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4); 8803 8804 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES || 8805 Opc == X86::AVX512_512_SETALLONES || 8806 Opc == X86::AVX1_SETALLONES); 8807 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 8808 Constant::getNullValue(Ty); 8809 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 8810 8811 // Create operands to load from the constant pool entry. 8812 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 8813 MOs.push_back(MachineOperand::CreateImm(1)); 8814 MOs.push_back(MachineOperand::CreateReg(0, false)); 8815 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 8816 MOs.push_back(MachineOperand::CreateReg(0, false)); 8817 break; 8818 } 8819 default: { 8820 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF)) 8821 return nullptr; 8822 8823 // Folding a normal load. Just copy the load's address operands. 8824 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, 8825 LoadMI.operands_begin() + NumOps); 8826 break; 8827 } 8828 } 8829 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt, 8830 /*Size=*/0, Alignment, /*AllowCommute=*/true); 8831} 8832 8833bool X86InstrInfo::unfoldMemoryOperand( 8834 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, 8835 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const { 8836 auto I = MemOp2RegOpTable.find(MI.getOpcode()); 8837 if (I == MemOp2RegOpTable.end()) 8838 return false; 8839 unsigned Opc = I->second.first; 8840 unsigned Index = I->second.second & TB_INDEX_MASK; 8841 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 8842 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 8843 if (UnfoldLoad && !FoldedLoad) 8844 return false; 8845 UnfoldLoad &= FoldedLoad; 8846 if (UnfoldStore && !FoldedStore) 8847 return false; 8848 UnfoldStore &= FoldedStore; 8849 8850 const MCInstrDesc &MCID = get(Opc); 8851 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 8852 // TODO: Check if 32-byte or greater accesses are slow too? 8853 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass && 8854 Subtarget.isUnalignedMem16Slow()) 8855 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 8856 // conservatively assume the address is unaligned. That's bad for 8857 // performance. 8858 return false; 8859 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 8860 SmallVector<MachineOperand,2> BeforeOps; 8861 SmallVector<MachineOperand,2> AfterOps; 8862 SmallVector<MachineOperand,4> ImpOps; 8863 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 8864 MachineOperand &Op = MI.getOperand(i); 8865 if (i >= Index && i < Index + X86::AddrNumOperands) 8866 AddrOps.push_back(Op); 8867 else if (Op.isReg() && Op.isImplicit()) 8868 ImpOps.push_back(Op); 8869 else if (i < Index) 8870 BeforeOps.push_back(Op); 8871 else if (i > Index) 8872 AfterOps.push_back(Op); 8873 } 8874 8875 // Emit the load instruction. 8876 if (UnfoldLoad) { 8877 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs = 8878 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 8879 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 8880 if (UnfoldStore) { 8881 // Address operands cannot be marked isKill. 8882 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 8883 MachineOperand &MO = NewMIs[0]->getOperand(i); 8884 if (MO.isReg()) 8885 MO.setIsKill(false); 8886 } 8887 } 8888 } 8889 8890 // Emit the data processing instruction. 8891 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true); 8892 MachineInstrBuilder MIB(MF, DataMI); 8893 8894 if (FoldedStore) 8895 MIB.addReg(Reg, RegState::Define); 8896 for (MachineOperand &BeforeOp : BeforeOps) 8897 MIB.add(BeforeOp); 8898 if (FoldedLoad) 8899 MIB.addReg(Reg); 8900 for (MachineOperand &AfterOp : AfterOps) 8901 MIB.add(AfterOp); 8902 for (MachineOperand &ImpOp : ImpOps) { 8903 MIB.addReg(ImpOp.getReg(), 8904 getDefRegState(ImpOp.isDef()) | 8905 RegState::Implicit | 8906 getKillRegState(ImpOp.isKill()) | 8907 getDeadRegState(ImpOp.isDead()) | 8908 getUndefRegState(ImpOp.isUndef())); 8909 } 8910 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 8911 switch (DataMI->getOpcode()) { 8912 default: break; 8913 case X86::CMP64ri32: 8914 case X86::CMP64ri8: 8915 case X86::CMP32ri: 8916 case X86::CMP32ri8: 8917 case X86::CMP16ri: 8918 case X86::CMP16ri8: 8919 case X86::CMP8ri: { 8920 MachineOperand &MO0 = DataMI->getOperand(0); 8921 MachineOperand &MO1 = DataMI->getOperand(1); 8922 if (MO1.getImm() == 0) { 8923 unsigned NewOpc; 8924 switch (DataMI->getOpcode()) { 8925 default: llvm_unreachable("Unreachable!"); 8926 case X86::CMP64ri8: 8927 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 8928 case X86::CMP32ri8: 8929 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 8930 case X86::CMP16ri8: 8931 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 8932 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 8933 } 8934 DataMI->setDesc(get(NewOpc)); 8935 MO1.ChangeToRegister(MO0.getReg(), false); 8936 } 8937 } 8938 } 8939 NewMIs.push_back(DataMI); 8940 8941 // Emit the store instruction. 8942 if (UnfoldStore) { 8943 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 8944 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs = 8945 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 8946 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 8947 } 8948 8949 return true; 8950} 8951 8952bool 8953X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 8954 SmallVectorImpl<SDNode*> &NewNodes) const { 8955 if (!N->isMachineOpcode()) 8956 return false; 8957 8958 auto I = MemOp2RegOpTable.find(N->getMachineOpcode()); 8959 if (I == MemOp2RegOpTable.end()) 8960 return false; 8961 unsigned Opc = I->second.first; 8962 unsigned Index = I->second.second & TB_INDEX_MASK; 8963 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 8964 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 8965 const MCInstrDesc &MCID = get(Opc); 8966 MachineFunction &MF = DAG.getMachineFunction(); 8967 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 8968 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 8969 unsigned NumDefs = MCID.NumDefs; 8970 std::vector<SDValue> AddrOps; 8971 std::vector<SDValue> BeforeOps; 8972 std::vector<SDValue> AfterOps; 8973 SDLoc dl(N); 8974 unsigned NumOps = N->getNumOperands(); 8975 for (unsigned i = 0; i != NumOps-1; ++i) { 8976 SDValue Op = N->getOperand(i); 8977 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 8978 AddrOps.push_back(Op); 8979 else if (i < Index-NumDefs) 8980 BeforeOps.push_back(Op); 8981 else if (i > Index-NumDefs) 8982 AfterOps.push_back(Op); 8983 } 8984 SDValue Chain = N->getOperand(NumOps-1); 8985 AddrOps.push_back(Chain); 8986 8987 // Emit the load instruction. 8988 SDNode *Load = nullptr; 8989 if (FoldedLoad) { 8990 EVT VT = *TRI.legalclasstypes_begin(*RC); 8991 std::pair<MachineInstr::mmo_iterator, 8992 MachineInstr::mmo_iterator> MMOs = 8993 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 8994 cast<MachineSDNode>(N)->memoperands_end()); 8995 if (!(*MMOs.first) && 8996 RC == &X86::VR128RegClass && 8997 Subtarget.isUnalignedMem16Slow()) 8998 // Do not introduce a slow unaligned load. 8999 return false; 9000 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte 9001 // memory access is slow above. 9002 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); 9003 bool isAligned = (*MMOs.first) && 9004 (*MMOs.first)->getAlignment() >= Alignment; 9005 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl, 9006 VT, MVT::Other, AddrOps); 9007 NewNodes.push_back(Load); 9008 9009 // Preserve memory reference information. 9010 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 9011 } 9012 9013 // Emit the data processing instruction. 9014 std::vector<EVT> VTs; 9015 const TargetRegisterClass *DstRC = nullptr; 9016 if (MCID.getNumDefs() > 0) { 9017 DstRC = getRegClass(MCID, 0, &RI, MF); 9018 VTs.push_back(*TRI.legalclasstypes_begin(*DstRC)); 9019 } 9020 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 9021 EVT VT = N->getValueType(i); 9022 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 9023 VTs.push_back(VT); 9024 } 9025 if (Load) 9026 BeforeOps.push_back(SDValue(Load, 0)); 9027 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end()); 9028 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 9029 NewNodes.push_back(NewNode); 9030 9031 // Emit the store instruction. 9032 if (FoldedStore) { 9033 AddrOps.pop_back(); 9034 AddrOps.push_back(SDValue(NewNode, 0)); 9035 AddrOps.push_back(Chain); 9036 std::pair<MachineInstr::mmo_iterator, 9037 MachineInstr::mmo_iterator> MMOs = 9038 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 9039 cast<MachineSDNode>(N)->memoperands_end()); 9040 if (!(*MMOs.first) && 9041 RC == &X86::VR128RegClass && 9042 Subtarget.isUnalignedMem16Slow()) 9043 // Do not introduce a slow unaligned store. 9044 return false; 9045 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte 9046 // memory access is slow above. 9047 unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16); 9048 bool isAligned = (*MMOs.first) && 9049 (*MMOs.first)->getAlignment() >= Alignment; 9050 SDNode *Store = 9051 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget), 9052 dl, MVT::Other, AddrOps); 9053 NewNodes.push_back(Store); 9054 9055 // Preserve memory reference information. 9056 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second); 9057 } 9058 9059 return true; 9060} 9061 9062unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 9063 bool UnfoldLoad, bool UnfoldStore, 9064 unsigned *LoadRegIndex) const { 9065 auto I = MemOp2RegOpTable.find(Opc); 9066 if (I == MemOp2RegOpTable.end()) 9067 return 0; 9068 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 9069 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 9070 if (UnfoldLoad && !FoldedLoad) 9071 return 0; 9072 if (UnfoldStore && !FoldedStore) 9073 return 0; 9074 if (LoadRegIndex) 9075 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 9076 return I->second.first; 9077} 9078 9079bool 9080X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 9081 int64_t &Offset1, int64_t &Offset2) const { 9082 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 9083 return false; 9084 unsigned Opc1 = Load1->getMachineOpcode(); 9085 unsigned Opc2 = Load2->getMachineOpcode(); 9086 switch (Opc1) { 9087 default: return false; 9088 case X86::MOV8rm: 9089 case X86::MOV16rm: 9090 case X86::MOV32rm: 9091 case X86::MOV64rm: 9092 case X86::LD_Fp32m: 9093 case X86::LD_Fp64m: 9094 case X86::LD_Fp80m: 9095 case X86::MOVSSrm: 9096 case X86::MOVSDrm: 9097 case X86::MMX_MOVD64rm: 9098 case X86::MMX_MOVQ64rm: 9099 case X86::MOVAPSrm: 9100 case X86::MOVUPSrm: 9101 case X86::MOVAPDrm: 9102 case X86::MOVUPDrm: 9103 case X86::MOVDQArm: 9104 case X86::MOVDQUrm: 9105 // AVX load instructions 9106 case X86::VMOVSSrm: 9107 case X86::VMOVSDrm: 9108 case X86::VMOVAPSrm: 9109 case X86::VMOVUPSrm: 9110 case X86::VMOVAPDrm: 9111 case X86::VMOVUPDrm: 9112 case X86::VMOVDQArm: 9113 case X86::VMOVDQUrm: 9114 case X86::VMOVAPSYrm: 9115 case X86::VMOVUPSYrm: 9116 case X86::VMOVAPDYrm: 9117 case X86::VMOVUPDYrm: 9118 case X86::VMOVDQAYrm: 9119 case X86::VMOVDQUYrm: 9120 // AVX512 load instructions 9121 case X86::VMOVSSZrm: 9122 case X86::VMOVSDZrm: 9123 case X86::VMOVAPSZ128rm: 9124 case X86::VMOVUPSZ128rm: 9125 case X86::VMOVAPSZ128rm_NOVLX: 9126 case X86::VMOVUPSZ128rm_NOVLX: 9127 case X86::VMOVAPDZ128rm: 9128 case X86::VMOVUPDZ128rm: 9129 case X86::VMOVDQU8Z128rm: 9130 case X86::VMOVDQU16Z128rm: 9131 case X86::VMOVDQA32Z128rm: 9132 case X86::VMOVDQU32Z128rm: 9133 case X86::VMOVDQA64Z128rm: 9134 case X86::VMOVDQU64Z128rm: 9135 case X86::VMOVAPSZ256rm: 9136 case X86::VMOVUPSZ256rm: 9137 case X86::VMOVAPSZ256rm_NOVLX: 9138 case X86::VMOVUPSZ256rm_NOVLX: 9139 case X86::VMOVAPDZ256rm: 9140 case X86::VMOVUPDZ256rm: 9141 case X86::VMOVDQU8Z256rm: 9142 case X86::VMOVDQU16Z256rm: 9143 case X86::VMOVDQA32Z256rm: 9144 case X86::VMOVDQU32Z256rm: 9145 case X86::VMOVDQA64Z256rm: 9146 case X86::VMOVDQU64Z256rm: 9147 case X86::VMOVAPSZrm: 9148 case X86::VMOVUPSZrm: 9149 case X86::VMOVAPDZrm: 9150 case X86::VMOVUPDZrm: 9151 case X86::VMOVDQU8Zrm: 9152 case X86::VMOVDQU16Zrm: 9153 case X86::VMOVDQA32Zrm: 9154 case X86::VMOVDQU32Zrm: 9155 case X86::VMOVDQA64Zrm: 9156 case X86::VMOVDQU64Zrm: 9157 case X86::KMOVBkm: 9158 case X86::KMOVWkm: 9159 case X86::KMOVDkm: 9160 case X86::KMOVQkm: 9161 break; 9162 } 9163 switch (Opc2) { 9164 default: return false; 9165 case X86::MOV8rm: 9166 case X86::MOV16rm: 9167 case X86::MOV32rm: 9168 case X86::MOV64rm: 9169 case X86::LD_Fp32m: 9170 case X86::LD_Fp64m: 9171 case X86::LD_Fp80m: 9172 case X86::MOVSSrm: 9173 case X86::MOVSDrm: 9174 case X86::MMX_MOVD64rm: 9175 case X86::MMX_MOVQ64rm: 9176 case X86::MOVAPSrm: 9177 case X86::MOVUPSrm: 9178 case X86::MOVAPDrm: 9179 case X86::MOVUPDrm: 9180 case X86::MOVDQArm: 9181 case X86::MOVDQUrm: 9182 // AVX load instructions 9183 case X86::VMOVSSrm: 9184 case X86::VMOVSDrm: 9185 case X86::VMOVAPSrm: 9186 case X86::VMOVUPSrm: 9187 case X86::VMOVAPDrm: 9188 case X86::VMOVUPDrm: 9189 case X86::VMOVDQArm: 9190 case X86::VMOVDQUrm: 9191 case X86::VMOVAPSYrm: 9192 case X86::VMOVUPSYrm: 9193 case X86::VMOVAPDYrm: 9194 case X86::VMOVUPDYrm: 9195 case X86::VMOVDQAYrm: 9196 case X86::VMOVDQUYrm: 9197 // AVX512 load instructions 9198 case X86::VMOVSSZrm: 9199 case X86::VMOVSDZrm: 9200 case X86::VMOVAPSZ128rm: 9201 case X86::VMOVUPSZ128rm: 9202 case X86::VMOVAPSZ128rm_NOVLX: 9203 case X86::VMOVUPSZ128rm_NOVLX: 9204 case X86::VMOVAPDZ128rm: 9205 case X86::VMOVUPDZ128rm: 9206 case X86::VMOVDQU8Z128rm: 9207 case X86::VMOVDQU16Z128rm: 9208 case X86::VMOVDQA32Z128rm: 9209 case X86::VMOVDQU32Z128rm: 9210 case X86::VMOVDQA64Z128rm: 9211 case X86::VMOVDQU64Z128rm: 9212 case X86::VMOVAPSZ256rm: 9213 case X86::VMOVUPSZ256rm: 9214 case X86::VMOVAPSZ256rm_NOVLX: 9215 case X86::VMOVUPSZ256rm_NOVLX: 9216 case X86::VMOVAPDZ256rm: 9217 case X86::VMOVUPDZ256rm: 9218 case X86::VMOVDQU8Z256rm: 9219 case X86::VMOVDQU16Z256rm: 9220 case X86::VMOVDQA32Z256rm: 9221 case X86::VMOVDQU32Z256rm: 9222 case X86::VMOVDQA64Z256rm: 9223 case X86::VMOVDQU64Z256rm: 9224 case X86::VMOVAPSZrm: 9225 case X86::VMOVUPSZrm: 9226 case X86::VMOVAPDZrm: 9227 case X86::VMOVUPDZrm: 9228 case X86::VMOVDQU8Zrm: 9229 case X86::VMOVDQU16Zrm: 9230 case X86::VMOVDQA32Zrm: 9231 case X86::VMOVDQU32Zrm: 9232 case X86::VMOVDQA64Zrm: 9233 case X86::VMOVDQU64Zrm: 9234 case X86::KMOVBkm: 9235 case X86::KMOVWkm: 9236 case X86::KMOVDkm: 9237 case X86::KMOVQkm: 9238 break; 9239 } 9240 9241 // Lambda to check if both the loads have the same value for an operand index. 9242 auto HasSameOp = [&](int I) { 9243 return Load1->getOperand(I) == Load2->getOperand(I); 9244 }; 9245 9246 // All operands except the displacement should match. 9247 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) || 9248 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg)) 9249 return false; 9250 9251 // Chain Operand must be the same. 9252 if (!HasSameOp(5)) 9253 return false; 9254 9255 // Now let's examine if the displacements are constants. 9256 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp)); 9257 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp)); 9258 if (!Disp1 || !Disp2) 9259 return false; 9260 9261 Offset1 = Disp1->getSExtValue(); 9262 Offset2 = Disp2->getSExtValue(); 9263 return true; 9264} 9265 9266bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 9267 int64_t Offset1, int64_t Offset2, 9268 unsigned NumLoads) const { 9269 assert(Offset2 > Offset1); 9270 if ((Offset2 - Offset1) / 8 > 64) 9271 return false; 9272 9273 unsigned Opc1 = Load1->getMachineOpcode(); 9274 unsigned Opc2 = Load2->getMachineOpcode(); 9275 if (Opc1 != Opc2) 9276 return false; // FIXME: overly conservative? 9277 9278 switch (Opc1) { 9279 default: break; 9280 case X86::LD_Fp32m: 9281 case X86::LD_Fp64m: 9282 case X86::LD_Fp80m: 9283 case X86::MMX_MOVD64rm: 9284 case X86::MMX_MOVQ64rm: 9285 return false; 9286 } 9287 9288 EVT VT = Load1->getValueType(0); 9289 switch (VT.getSimpleVT().SimpleTy) { 9290 default: 9291 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 9292 // have 16 of them to play with. 9293 if (Subtarget.is64Bit()) { 9294 if (NumLoads >= 3) 9295 return false; 9296 } else if (NumLoads) { 9297 return false; 9298 } 9299 break; 9300 case MVT::i8: 9301 case MVT::i16: 9302 case MVT::i32: 9303 case MVT::i64: 9304 case MVT::f32: 9305 case MVT::f64: 9306 if (NumLoads) 9307 return false; 9308 break; 9309 } 9310 9311 return true; 9312} 9313 9314bool X86InstrInfo:: 9315reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 9316 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 9317 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 9318 Cond[0].setImm(GetOppositeBranchCondition(CC)); 9319 return false; 9320} 9321 9322bool X86InstrInfo:: 9323isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 9324 // FIXME: Return false for x87 stack register classes for now. We can't 9325 // allow any loads of these registers before FpGet_ST0_80. 9326 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass || 9327 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass || 9328 RC == &X86::RFP80RegClass); 9329} 9330 9331/// Return a virtual register initialized with the 9332/// the global base register value. Output instructions required to 9333/// initialize the register in the function entry block, if necessary. 9334/// 9335/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 9336/// 9337unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 9338 assert(!Subtarget.is64Bit() && 9339 "X86-64 PIC uses RIP relative addressing"); 9340 9341 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 9342 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 9343 if (GlobalBaseReg != 0) 9344 return GlobalBaseReg; 9345 9346 // Create the register. The code to initialize it is inserted 9347 // later, by the CGBR pass (below). 9348 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 9349 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 9350 X86FI->setGlobalBaseReg(GlobalBaseReg); 9351 return GlobalBaseReg; 9352} 9353 9354// These are the replaceable SSE instructions. Some of these have Int variants 9355// that we don't include here. We don't want to replace instructions selected 9356// by intrinsics. 9357static const uint16_t ReplaceableInstrs[][3] = { 9358 //PackedSingle PackedDouble PackedInt 9359 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 9360 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 9361 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 9362 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 9363 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 9364 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr }, 9365 { X86::MOVSDmr, X86::MOVSDmr, X86::MOVPQI2QImr }, 9366 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr }, 9367 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm }, 9368 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm }, 9369 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 9370 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 9371 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 9372 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 9373 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 9374 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 9375 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 9376 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 9377 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 9378 { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm }, 9379 { X86::MOVLHPSrr, X86::UNPCKLPDrr, X86::PUNPCKLQDQrr }, 9380 { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm }, 9381 { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr }, 9382 { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm }, 9383 { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr }, 9384 { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm }, 9385 { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr }, 9386 { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr }, 9387 { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr }, 9388 // AVX 128-bit support 9389 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 9390 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 9391 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 9392 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 9393 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 9394 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr }, 9395 { X86::VMOVSDmr, X86::VMOVSDmr, X86::VMOVPQI2QImr }, 9396 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr }, 9397 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm }, 9398 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm }, 9399 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 9400 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 9401 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 9402 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 9403 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 9404 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 9405 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 9406 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 9407 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 9408 { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm }, 9409 { X86::VMOVLHPSrr, X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr }, 9410 { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm }, 9411 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr }, 9412 { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm }, 9413 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr }, 9414 { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm }, 9415 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr }, 9416 { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr }, 9417 { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr }, 9418 // AVX 256-bit support 9419 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 9420 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 9421 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 9422 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 9423 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 9424 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }, 9425 { X86::VPERMPSYrm, X86::VPERMPSYrm, X86::VPERMDYrm }, 9426 { X86::VPERMPSYrr, X86::VPERMPSYrr, X86::VPERMDYrr }, 9427 { X86::VPERMPDYmi, X86::VPERMPDYmi, X86::VPERMQYmi }, 9428 { X86::VPERMPDYri, X86::VPERMPDYri, X86::VPERMQYri }, 9429 // AVX512 support 9430 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr }, 9431 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr }, 9432 { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr }, 9433 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr }, 9434 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr }, 9435 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr }, 9436 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm }, 9437 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm }, 9438 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r }, 9439 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m }, 9440 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r }, 9441 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m }, 9442 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr }, 9443 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm }, 9444 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r }, 9445 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m }, 9446 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr }, 9447 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm }, 9448 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrr, X86::VINSERTI32x4Zrr }, 9449 { X86::VINSERTF32x4Zrm, X86::VINSERTF32x4Zrm, X86::VINSERTI32x4Zrm }, 9450 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrr, X86::VINSERTI32x8Zrr }, 9451 { X86::VINSERTF32x8Zrm, X86::VINSERTF32x8Zrm, X86::VINSERTI32x8Zrm }, 9452 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrr, X86::VINSERTI64x2Zrr }, 9453 { X86::VINSERTF64x2Zrm, X86::VINSERTF64x2Zrm, X86::VINSERTI64x2Zrm }, 9454 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrr, X86::VINSERTI64x4Zrr }, 9455 { X86::VINSERTF64x4Zrm, X86::VINSERTF64x4Zrm, X86::VINSERTI64x4Zrm }, 9456 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr }, 9457 { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm }, 9458 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr }, 9459 { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm }, 9460 { X86::VEXTRACTF32x4Zrr, X86::VEXTRACTF32x4Zrr, X86::VEXTRACTI32x4Zrr }, 9461 { X86::VEXTRACTF32x4Zmr, X86::VEXTRACTF32x4Zmr, X86::VEXTRACTI32x4Zmr }, 9462 { X86::VEXTRACTF32x8Zrr, X86::VEXTRACTF32x8Zrr, X86::VEXTRACTI32x8Zrr }, 9463 { X86::VEXTRACTF32x8Zmr, X86::VEXTRACTF32x8Zmr, X86::VEXTRACTI32x8Zmr }, 9464 { X86::VEXTRACTF64x2Zrr, X86::VEXTRACTF64x2Zrr, X86::VEXTRACTI64x2Zrr }, 9465 { X86::VEXTRACTF64x2Zmr, X86::VEXTRACTF64x2Zmr, X86::VEXTRACTI64x2Zmr }, 9466 { X86::VEXTRACTF64x4Zrr, X86::VEXTRACTF64x4Zrr, X86::VEXTRACTI64x4Zrr }, 9467 { X86::VEXTRACTF64x4Zmr, X86::VEXTRACTF64x4Zmr, X86::VEXTRACTI64x4Zmr }, 9468 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr }, 9469 { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr }, 9470 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr }, 9471 { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr }, 9472 { X86::VPERMILPSmi, X86::VPERMILPSmi, X86::VPSHUFDmi }, 9473 { X86::VPERMILPSri, X86::VPERMILPSri, X86::VPSHUFDri }, 9474 { X86::VPERMILPSZ128mi, X86::VPERMILPSZ128mi, X86::VPSHUFDZ128mi }, 9475 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128ri, X86::VPSHUFDZ128ri }, 9476 { X86::VPERMILPSZ256mi, X86::VPERMILPSZ256mi, X86::VPSHUFDZ256mi }, 9477 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256ri, X86::VPSHUFDZ256ri }, 9478 { X86::VPERMILPSZmi, X86::VPERMILPSZmi, X86::VPSHUFDZmi }, 9479 { X86::VPERMILPSZri, X86::VPERMILPSZri, X86::VPSHUFDZri }, 9480 { X86::VPERMPSZ256rm, X86::VPERMPSZ256rm, X86::VPERMDZ256rm }, 9481 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rr, X86::VPERMDZ256rr }, 9482 { X86::VPERMPDZ256mi, X86::VPERMPDZ256mi, X86::VPERMQZ256mi }, 9483 { X86::VPERMPDZ256ri, X86::VPERMPDZ256ri, X86::VPERMQZ256ri }, 9484 { X86::VPERMPDZ256rm, X86::VPERMPDZ256rm, X86::VPERMQZ256rm }, 9485 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rr, X86::VPERMQZ256rr }, 9486 { X86::VPERMPSZrm, X86::VPERMPSZrm, X86::VPERMDZrm }, 9487 { X86::VPERMPSZrr, X86::VPERMPSZrr, X86::VPERMDZrr }, 9488 { X86::VPERMPDZmi, X86::VPERMPDZmi, X86::VPERMQZmi }, 9489 { X86::VPERMPDZri, X86::VPERMPDZri, X86::VPERMQZri }, 9490 { X86::VPERMPDZrm, X86::VPERMPDZrm, X86::VPERMQZrm }, 9491 { X86::VPERMPDZrr, X86::VPERMPDZrr, X86::VPERMQZrr }, 9492 { X86::VUNPCKLPDZ256rm, X86::VUNPCKLPDZ256rm, X86::VPUNPCKLQDQZ256rm }, 9493 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rr, X86::VPUNPCKLQDQZ256rr }, 9494 { X86::VUNPCKHPDZ256rm, X86::VUNPCKHPDZ256rm, X86::VPUNPCKHQDQZ256rm }, 9495 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rr, X86::VPUNPCKHQDQZ256rr }, 9496 { X86::VUNPCKLPSZ256rm, X86::VUNPCKLPSZ256rm, X86::VPUNPCKLDQZ256rm }, 9497 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rr, X86::VPUNPCKLDQZ256rr }, 9498 { X86::VUNPCKHPSZ256rm, X86::VUNPCKHPSZ256rm, X86::VPUNPCKHDQZ256rm }, 9499 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rr, X86::VPUNPCKHDQZ256rr }, 9500 { X86::VUNPCKLPDZ128rm, X86::VUNPCKLPDZ128rm, X86::VPUNPCKLQDQZ128rm }, 9501 { X86::VMOVLHPSZrr, X86::VUNPCKLPDZ128rr, X86::VPUNPCKLQDQZ128rr }, 9502 { X86::VUNPCKHPDZ128rm, X86::VUNPCKHPDZ128rm, X86::VPUNPCKHQDQZ128rm }, 9503 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rr, X86::VPUNPCKHQDQZ128rr }, 9504 { X86::VUNPCKLPSZ128rm, X86::VUNPCKLPSZ128rm, X86::VPUNPCKLDQZ128rm }, 9505 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rr, X86::VPUNPCKLDQZ128rr }, 9506 { X86::VUNPCKHPSZ128rm, X86::VUNPCKHPSZ128rm, X86::VPUNPCKHDQZ128rm }, 9507 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rr, X86::VPUNPCKHDQZ128rr }, 9508 { X86::VUNPCKLPDZrm, X86::VUNPCKLPDZrm, X86::VPUNPCKLQDQZrm }, 9509 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrr, X86::VPUNPCKLQDQZrr }, 9510 { X86::VUNPCKHPDZrm, X86::VUNPCKHPDZrm, X86::VPUNPCKHQDQZrm }, 9511 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrr, X86::VPUNPCKHQDQZrr }, 9512 { X86::VUNPCKLPSZrm, X86::VUNPCKLPSZrm, X86::VPUNPCKLDQZrm }, 9513 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrr, X86::VPUNPCKLDQZrr }, 9514 { X86::VUNPCKHPSZrm, X86::VUNPCKHPSZrm, X86::VPUNPCKHDQZrm }, 9515 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrr, X86::VPUNPCKHDQZrr }, 9516 { X86::VEXTRACTPSZmr, X86::VEXTRACTPSZmr, X86::VPEXTRDZmr }, 9517 { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZrr, X86::VPEXTRDZrr }, 9518}; 9519 9520static const uint16_t ReplaceableInstrsAVX2[][3] = { 9521 //PackedSingle PackedDouble PackedInt 9522 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 9523 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 9524 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 9525 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 9526 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 9527 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 9528 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 9529 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 9530 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 9531 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }, 9532 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm}, 9533 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr}, 9534 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr}, 9535 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm}, 9536 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr}, 9537 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}, 9538 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 }, 9539 { X86::VBLENDPSrri, X86::VBLENDPSrri, X86::VPBLENDDrri }, 9540 { X86::VBLENDPSrmi, X86::VBLENDPSrmi, X86::VPBLENDDrmi }, 9541 { X86::VBLENDPSYrri, X86::VBLENDPSYrri, X86::VPBLENDDYrri }, 9542 { X86::VBLENDPSYrmi, X86::VBLENDPSYrmi, X86::VPBLENDDYrmi }, 9543 { X86::VPERMILPSYmi, X86::VPERMILPSYmi, X86::VPSHUFDYmi }, 9544 { X86::VPERMILPSYri, X86::VPERMILPSYri, X86::VPSHUFDYri }, 9545 { X86::VUNPCKLPDYrm, X86::VUNPCKLPDYrm, X86::VPUNPCKLQDQYrm }, 9546 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrr, X86::VPUNPCKLQDQYrr }, 9547 { X86::VUNPCKHPDYrm, X86::VUNPCKHPDYrm, X86::VPUNPCKHQDQYrm }, 9548 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrr, X86::VPUNPCKHQDQYrr }, 9549 { X86::VUNPCKLPSYrm, X86::VUNPCKLPSYrm, X86::VPUNPCKLDQYrm }, 9550 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrr, X86::VPUNPCKLDQYrr }, 9551 { X86::VUNPCKHPSYrm, X86::VUNPCKHPSYrm, X86::VPUNPCKHDQYrm }, 9552 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrr, X86::VPUNPCKHDQYrr }, 9553}; 9554 9555static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = { 9556 //PackedSingle PackedDouble PackedInt 9557 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 9558 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 9559 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 9560 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 9561}; 9562 9563static const uint16_t ReplaceableInstrsAVX512[][4] = { 9564 // Two integer columns for 64-bit and 32-bit elements. 9565 //PackedSingle PackedDouble PackedInt PackedInt 9566 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr }, 9567 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm }, 9568 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr }, 9569 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr }, 9570 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm }, 9571 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr }, 9572 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm }, 9573 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr }, 9574 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr }, 9575 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm }, 9576 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr }, 9577 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm }, 9578 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr }, 9579 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr }, 9580 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm }, 9581}; 9582 9583static const uint16_t ReplaceableInstrsAVX512DQ[][4] = { 9584 // Two integer columns for 64-bit and 32-bit elements. 9585 //PackedSingle PackedDouble PackedInt PackedInt 9586 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm }, 9587 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr }, 9588 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm }, 9589 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr }, 9590 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm }, 9591 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr }, 9592 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm }, 9593 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr }, 9594 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm }, 9595 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr }, 9596 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm }, 9597 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr }, 9598 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm }, 9599 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr }, 9600 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm }, 9601 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr }, 9602 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm }, 9603 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr }, 9604 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm }, 9605 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr }, 9606 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm }, 9607 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr }, 9608 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm }, 9609 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr }, 9610}; 9611 9612static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = { 9613 // Two integer columns for 64-bit and 32-bit elements. 9614 //PackedSingle PackedDouble 9615 //PackedInt PackedInt 9616 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk, 9617 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk }, 9618 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz, 9619 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz }, 9620 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk, 9621 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk }, 9622 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz, 9623 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz }, 9624 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk, 9625 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk }, 9626 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz, 9627 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz }, 9628 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk, 9629 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk }, 9630 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz, 9631 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz }, 9632 { X86::VORPSZ128rmk, X86::VORPDZ128rmk, 9633 X86::VPORQZ128rmk, X86::VPORDZ128rmk }, 9634 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz, 9635 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz }, 9636 { X86::VORPSZ128rrk, X86::VORPDZ128rrk, 9637 X86::VPORQZ128rrk, X86::VPORDZ128rrk }, 9638 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz, 9639 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz }, 9640 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk, 9641 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk }, 9642 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz, 9643 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz }, 9644 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk, 9645 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk }, 9646 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz, 9647 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz }, 9648 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk, 9649 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk }, 9650 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz, 9651 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz }, 9652 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk, 9653 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk }, 9654 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz, 9655 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz }, 9656 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk, 9657 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk }, 9658 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz, 9659 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz }, 9660 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk, 9661 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk }, 9662 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz, 9663 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz }, 9664 { X86::VORPSZ256rmk, X86::VORPDZ256rmk, 9665 X86::VPORQZ256rmk, X86::VPORDZ256rmk }, 9666 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz, 9667 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz }, 9668 { X86::VORPSZ256rrk, X86::VORPDZ256rrk, 9669 X86::VPORQZ256rrk, X86::VPORDZ256rrk }, 9670 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz, 9671 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz }, 9672 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk, 9673 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk }, 9674 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz, 9675 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz }, 9676 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk, 9677 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk }, 9678 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz, 9679 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz }, 9680 { X86::VANDNPSZrmk, X86::VANDNPDZrmk, 9681 X86::VPANDNQZrmk, X86::VPANDNDZrmk }, 9682 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz, 9683 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz }, 9684 { X86::VANDNPSZrrk, X86::VANDNPDZrrk, 9685 X86::VPANDNQZrrk, X86::VPANDNDZrrk }, 9686 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz, 9687 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz }, 9688 { X86::VANDPSZrmk, X86::VANDPDZrmk, 9689 X86::VPANDQZrmk, X86::VPANDDZrmk }, 9690 { X86::VANDPSZrmkz, X86::VANDPDZrmkz, 9691 X86::VPANDQZrmkz, X86::VPANDDZrmkz }, 9692 { X86::VANDPSZrrk, X86::VANDPDZrrk, 9693 X86::VPANDQZrrk, X86::VPANDDZrrk }, 9694 { X86::VANDPSZrrkz, X86::VANDPDZrrkz, 9695 X86::VPANDQZrrkz, X86::VPANDDZrrkz }, 9696 { X86::VORPSZrmk, X86::VORPDZrmk, 9697 X86::VPORQZrmk, X86::VPORDZrmk }, 9698 { X86::VORPSZrmkz, X86::VORPDZrmkz, 9699 X86::VPORQZrmkz, X86::VPORDZrmkz }, 9700 { X86::VORPSZrrk, X86::VORPDZrrk, 9701 X86::VPORQZrrk, X86::VPORDZrrk }, 9702 { X86::VORPSZrrkz, X86::VORPDZrrkz, 9703 X86::VPORQZrrkz, X86::VPORDZrrkz }, 9704 { X86::VXORPSZrmk, X86::VXORPDZrmk, 9705 X86::VPXORQZrmk, X86::VPXORDZrmk }, 9706 { X86::VXORPSZrmkz, X86::VXORPDZrmkz, 9707 X86::VPXORQZrmkz, X86::VPXORDZrmkz }, 9708 { X86::VXORPSZrrk, X86::VXORPDZrrk, 9709 X86::VPXORQZrrk, X86::VPXORDZrrk }, 9710 { X86::VXORPSZrrkz, X86::VXORPDZrrkz, 9711 X86::VPXORQZrrkz, X86::VPXORDZrrkz }, 9712 // Broadcast loads can be handled the same as masked operations to avoid 9713 // changing element size. 9714 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb, 9715 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb }, 9716 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb, 9717 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb }, 9718 { X86::VORPSZ128rmb, X86::VORPDZ128rmb, 9719 X86::VPORQZ128rmb, X86::VPORDZ128rmb }, 9720 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb, 9721 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb }, 9722 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb, 9723 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb }, 9724 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb, 9725 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb }, 9726 { X86::VORPSZ256rmb, X86::VORPDZ256rmb, 9727 X86::VPORQZ256rmb, X86::VPORDZ256rmb }, 9728 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb, 9729 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb }, 9730 { X86::VANDNPSZrmb, X86::VANDNPDZrmb, 9731 X86::VPANDNQZrmb, X86::VPANDNDZrmb }, 9732 { X86::VANDPSZrmb, X86::VANDPDZrmb, 9733 X86::VPANDQZrmb, X86::VPANDDZrmb }, 9734 { X86::VANDPSZrmb, X86::VANDPDZrmb, 9735 X86::VPANDQZrmb, X86::VPANDDZrmb }, 9736 { X86::VORPSZrmb, X86::VORPDZrmb, 9737 X86::VPORQZrmb, X86::VPORDZrmb }, 9738 { X86::VXORPSZrmb, X86::VXORPDZrmb, 9739 X86::VPXORQZrmb, X86::VPXORDZrmb }, 9740 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk, 9741 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk }, 9742 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk, 9743 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk }, 9744 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk, 9745 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk }, 9746 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk, 9747 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk }, 9748 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk, 9749 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk }, 9750 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk, 9751 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk }, 9752 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk, 9753 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk }, 9754 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk, 9755 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk }, 9756 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk, 9757 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk }, 9758 { X86::VANDPSZrmbk, X86::VANDPDZrmbk, 9759 X86::VPANDQZrmbk, X86::VPANDDZrmbk }, 9760 { X86::VANDPSZrmbk, X86::VANDPDZrmbk, 9761 X86::VPANDQZrmbk, X86::VPANDDZrmbk }, 9762 { X86::VORPSZrmbk, X86::VORPDZrmbk, 9763 X86::VPORQZrmbk, X86::VPORDZrmbk }, 9764 { X86::VXORPSZrmbk, X86::VXORPDZrmbk, 9765 X86::VPXORQZrmbk, X86::VPXORDZrmbk }, 9766 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz, 9767 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz}, 9768 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz, 9769 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz }, 9770 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz, 9771 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz }, 9772 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz, 9773 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz }, 9774 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz, 9775 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz}, 9776 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz, 9777 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz }, 9778 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz, 9779 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz }, 9780 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz, 9781 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz }, 9782 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz, 9783 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz }, 9784 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz, 9785 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz }, 9786 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz, 9787 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz }, 9788 { X86::VORPSZrmbkz, X86::VORPDZrmbkz, 9789 X86::VPORQZrmbkz, X86::VPORDZrmbkz }, 9790 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz, 9791 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz }, 9792}; 9793 9794// FIXME: Some shuffle and unpack instructions have equivalents in different 9795// domains, but they require a bit more work than just switching opcodes. 9796 9797static const uint16_t *lookup(unsigned opcode, unsigned domain, 9798 ArrayRef<uint16_t[3]> Table) { 9799 for (const uint16_t (&Row)[3] : Table) 9800 if (Row[domain-1] == opcode) 9801 return Row; 9802 return nullptr; 9803} 9804 9805static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain, 9806 ArrayRef<uint16_t[4]> Table) { 9807 // If this is the integer domain make sure to check both integer columns. 9808 for (const uint16_t (&Row)[4] : Table) 9809 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode)) 9810 return Row; 9811 return nullptr; 9812} 9813 9814std::pair<uint16_t, uint16_t> 9815X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const { 9816 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 9817 unsigned opcode = MI.getOpcode(); 9818 uint16_t validDomains = 0; 9819 if (domain) { 9820 if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) { 9821 validDomains = 0xe; 9822 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) { 9823 validDomains = Subtarget.hasAVX2() ? 0xe : 0x6; 9824 } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) { 9825 // Insert/extract instructions should only effect domain if AVX2 9826 // is enabled. 9827 if (!Subtarget.hasAVX2()) 9828 return std::make_pair(0, 0); 9829 validDomains = 0xe; 9830 } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) { 9831 validDomains = 0xe; 9832 } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain, 9833 ReplaceableInstrsAVX512DQ)) { 9834 validDomains = 0xe; 9835 } else if (Subtarget.hasDQI()) { 9836 if (const uint16_t *table = lookupAVX512(opcode, domain, 9837 ReplaceableInstrsAVX512DQMasked)) { 9838 if (domain == 1 || (domain == 3 && table[3] == opcode)) 9839 validDomains = 0xa; 9840 else 9841 validDomains = 0xc; 9842 } 9843 } 9844 } 9845 return std::make_pair(domain, validDomains); 9846} 9847 9848void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const { 9849 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 9850 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 9851 assert(dom && "Not an SSE instruction"); 9852 const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs); 9853 if (!table) { // try the other table 9854 assert((Subtarget.hasAVX2() || Domain < 3) && 9855 "256-bit vector operations only available in AVX2"); 9856 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2); 9857 } 9858 if (!table) { // try the other table 9859 assert(Subtarget.hasAVX2() && 9860 "256-bit insert/extract only available in AVX2"); 9861 table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract); 9862 } 9863 if (!table) { // try the AVX512 table 9864 assert(Subtarget.hasAVX512() && "Requires AVX-512"); 9865 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512); 9866 // Don't change integer Q instructions to D instructions. 9867 if (table && Domain == 3 && table[3] == MI.getOpcode()) 9868 Domain = 4; 9869 } 9870 if (!table) { // try the AVX512DQ table 9871 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ"); 9872 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ); 9873 // Don't change integer Q instructions to D instructions and 9874 // use D intructions if we started with a PS instruction. 9875 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode())) 9876 Domain = 4; 9877 } 9878 if (!table) { // try the AVX512DQMasked table 9879 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ"); 9880 table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked); 9881 if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode())) 9882 Domain = 4; 9883 } 9884 assert(table && "Cannot change domain"); 9885 MI.setDesc(get(table[Domain - 1])); 9886} 9887 9888/// Return the noop instruction to use for a noop. 9889void X86InstrInfo::getNoop(MCInst &NopInst) const { 9890 NopInst.setOpcode(X86::NOOP); 9891} 9892 9893bool X86InstrInfo::isHighLatencyDef(int opc) const { 9894 switch (opc) { 9895 default: return false; 9896 case X86::DIVPDrm: 9897 case X86::DIVPDrr: 9898 case X86::DIVPSrm: 9899 case X86::DIVPSrr: 9900 case X86::DIVSDrm: 9901 case X86::DIVSDrm_Int: 9902 case X86::DIVSDrr: 9903 case X86::DIVSDrr_Int: 9904 case X86::DIVSSrm: 9905 case X86::DIVSSrm_Int: 9906 case X86::DIVSSrr: 9907 case X86::DIVSSrr_Int: 9908 case X86::SQRTPDm: 9909 case X86::SQRTPDr: 9910 case X86::SQRTPSm: 9911 case X86::SQRTPSr: 9912 case X86::SQRTSDm: 9913 case X86::SQRTSDm_Int: 9914 case X86::SQRTSDr: 9915 case X86::SQRTSDr_Int: 9916 case X86::SQRTSSm: 9917 case X86::SQRTSSm_Int: 9918 case X86::SQRTSSr: 9919 case X86::SQRTSSr_Int: 9920 // AVX instructions with high latency 9921 case X86::VDIVPDrm: 9922 case X86::VDIVPDrr: 9923 case X86::VDIVPDYrm: 9924 case X86::VDIVPDYrr: 9925 case X86::VDIVPSrm: 9926 case X86::VDIVPSrr: 9927 case X86::VDIVPSYrm: 9928 case X86::VDIVPSYrr: 9929 case X86::VDIVSDrm: 9930 case X86::VDIVSDrm_Int: 9931 case X86::VDIVSDrr: 9932 case X86::VDIVSDrr_Int: 9933 case X86::VDIVSSrm: 9934 case X86::VDIVSSrm_Int: 9935 case X86::VDIVSSrr: 9936 case X86::VDIVSSrr_Int: 9937 case X86::VSQRTPDm: 9938 case X86::VSQRTPDr: 9939 case X86::VSQRTPDYm: 9940 case X86::VSQRTPDYr: 9941 case X86::VSQRTPSm: 9942 case X86::VSQRTPSr: 9943 case X86::VSQRTPSYm: 9944 case X86::VSQRTPSYr: 9945 case X86::VSQRTSDm: 9946 case X86::VSQRTSDm_Int: 9947 case X86::VSQRTSDr: 9948 case X86::VSQRTSDr_Int: 9949 case X86::VSQRTSSm: 9950 case X86::VSQRTSSm_Int: 9951 case X86::VSQRTSSr: 9952 case X86::VSQRTSSr_Int: 9953 // AVX512 instructions with high latency 9954 case X86::VDIVPDZ128rm: 9955 case X86::VDIVPDZ128rmb: 9956 case X86::VDIVPDZ128rmbk: 9957 case X86::VDIVPDZ128rmbkz: 9958 case X86::VDIVPDZ128rmk: 9959 case X86::VDIVPDZ128rmkz: 9960 case X86::VDIVPDZ128rr: 9961 case X86::VDIVPDZ128rrk: 9962 case X86::VDIVPDZ128rrkz: 9963 case X86::VDIVPDZ256rm: 9964 case X86::VDIVPDZ256rmb: 9965 case X86::VDIVPDZ256rmbk: 9966 case X86::VDIVPDZ256rmbkz: 9967 case X86::VDIVPDZ256rmk: 9968 case X86::VDIVPDZ256rmkz: 9969 case X86::VDIVPDZ256rr: 9970 case X86::VDIVPDZ256rrk: 9971 case X86::VDIVPDZ256rrkz: 9972 case X86::VDIVPDZrrb: 9973 case X86::VDIVPDZrrbk: 9974 case X86::VDIVPDZrrbkz: 9975 case X86::VDIVPDZrm: 9976 case X86::VDIVPDZrmb: 9977 case X86::VDIVPDZrmbk: 9978 case X86::VDIVPDZrmbkz: 9979 case X86::VDIVPDZrmk: 9980 case X86::VDIVPDZrmkz: 9981 case X86::VDIVPDZrr: 9982 case X86::VDIVPDZrrk: 9983 case X86::VDIVPDZrrkz: 9984 case X86::VDIVPSZ128rm: 9985 case X86::VDIVPSZ128rmb: 9986 case X86::VDIVPSZ128rmbk: 9987 case X86::VDIVPSZ128rmbkz: 9988 case X86::VDIVPSZ128rmk: 9989 case X86::VDIVPSZ128rmkz: 9990 case X86::VDIVPSZ128rr: 9991 case X86::VDIVPSZ128rrk: 9992 case X86::VDIVPSZ128rrkz: 9993 case X86::VDIVPSZ256rm: 9994 case X86::VDIVPSZ256rmb: 9995 case X86::VDIVPSZ256rmbk: 9996 case X86::VDIVPSZ256rmbkz: 9997 case X86::VDIVPSZ256rmk: 9998 case X86::VDIVPSZ256rmkz: 9999 case X86::VDIVPSZ256rr: 10000 case X86::VDIVPSZ256rrk: 10001 case X86::VDIVPSZ256rrkz: 10002 case X86::VDIVPSZrrb: 10003 case X86::VDIVPSZrrbk: 10004 case X86::VDIVPSZrrbkz: 10005 case X86::VDIVPSZrm: 10006 case X86::VDIVPSZrmb: 10007 case X86::VDIVPSZrmbk: 10008 case X86::VDIVPSZrmbkz: 10009 case X86::VDIVPSZrmk: 10010 case X86::VDIVPSZrmkz: 10011 case X86::VDIVPSZrr: 10012 case X86::VDIVPSZrrk: 10013 case X86::VDIVPSZrrkz: 10014 case X86::VDIVSDZrm: 10015 case X86::VDIVSDZrr: 10016 case X86::VDIVSDZrm_Int: 10017 case X86::VDIVSDZrm_Intk: 10018 case X86::VDIVSDZrm_Intkz: 10019 case X86::VDIVSDZrr_Int: 10020 case X86::VDIVSDZrr_Intk: 10021 case X86::VDIVSDZrr_Intkz: 10022 case X86::VDIVSDZrrb_Int: 10023 case X86::VDIVSDZrrb_Intk: 10024 case X86::VDIVSDZrrb_Intkz: 10025 case X86::VDIVSSZrm: 10026 case X86::VDIVSSZrr: 10027 case X86::VDIVSSZrm_Int: 10028 case X86::VDIVSSZrm_Intk: 10029 case X86::VDIVSSZrm_Intkz: 10030 case X86::VDIVSSZrr_Int: 10031 case X86::VDIVSSZrr_Intk: 10032 case X86::VDIVSSZrr_Intkz: 10033 case X86::VDIVSSZrrb_Int: 10034 case X86::VDIVSSZrrb_Intk: 10035 case X86::VDIVSSZrrb_Intkz: 10036 case X86::VSQRTPDZ128m: 10037 case X86::VSQRTPDZ128mb: 10038 case X86::VSQRTPDZ128mbk: 10039 case X86::VSQRTPDZ128mbkz: 10040 case X86::VSQRTPDZ128mk: 10041 case X86::VSQRTPDZ128mkz: 10042 case X86::VSQRTPDZ128r: 10043 case X86::VSQRTPDZ128rk: 10044 case X86::VSQRTPDZ128rkz: 10045 case X86::VSQRTPDZ256m: 10046 case X86::VSQRTPDZ256mb: 10047 case X86::VSQRTPDZ256mbk: 10048 case X86::VSQRTPDZ256mbkz: 10049 case X86::VSQRTPDZ256mk: 10050 case X86::VSQRTPDZ256mkz: 10051 case X86::VSQRTPDZ256r: 10052 case X86::VSQRTPDZ256rk: 10053 case X86::VSQRTPDZ256rkz: 10054 case X86::VSQRTPDZm: 10055 case X86::VSQRTPDZmb: 10056 case X86::VSQRTPDZmbk: 10057 case X86::VSQRTPDZmbkz: 10058 case X86::VSQRTPDZmk: 10059 case X86::VSQRTPDZmkz: 10060 case X86::VSQRTPDZr: 10061 case X86::VSQRTPDZrb: 10062 case X86::VSQRTPDZrbk: 10063 case X86::VSQRTPDZrbkz: 10064 case X86::VSQRTPDZrk: 10065 case X86::VSQRTPDZrkz: 10066 case X86::VSQRTPSZ128m: 10067 case X86::VSQRTPSZ128mb: 10068 case X86::VSQRTPSZ128mbk: 10069 case X86::VSQRTPSZ128mbkz: 10070 case X86::VSQRTPSZ128mk: 10071 case X86::VSQRTPSZ128mkz: 10072 case X86::VSQRTPSZ128r: 10073 case X86::VSQRTPSZ128rk: 10074 case X86::VSQRTPSZ128rkz: 10075 case X86::VSQRTPSZ256m: 10076 case X86::VSQRTPSZ256mb: 10077 case X86::VSQRTPSZ256mbk: 10078 case X86::VSQRTPSZ256mbkz: 10079 case X86::VSQRTPSZ256mk: 10080 case X86::VSQRTPSZ256mkz: 10081 case X86::VSQRTPSZ256r: 10082 case X86::VSQRTPSZ256rk: 10083 case X86::VSQRTPSZ256rkz: 10084 case X86::VSQRTPSZm: 10085 case X86::VSQRTPSZmb: 10086 case X86::VSQRTPSZmbk: 10087 case X86::VSQRTPSZmbkz: 10088 case X86::VSQRTPSZmk: 10089 case X86::VSQRTPSZmkz: 10090 case X86::VSQRTPSZr: 10091 case X86::VSQRTPSZrb: 10092 case X86::VSQRTPSZrbk: 10093 case X86::VSQRTPSZrbkz: 10094 case X86::VSQRTPSZrk: 10095 case X86::VSQRTPSZrkz: 10096 case X86::VSQRTSDZm: 10097 case X86::VSQRTSDZm_Int: 10098 case X86::VSQRTSDZm_Intk: 10099 case X86::VSQRTSDZm_Intkz: 10100 case X86::VSQRTSDZr: 10101 case X86::VSQRTSDZr_Int: 10102 case X86::VSQRTSDZr_Intk: 10103 case X86::VSQRTSDZr_Intkz: 10104 case X86::VSQRTSDZrb_Int: 10105 case X86::VSQRTSDZrb_Intk: 10106 case X86::VSQRTSDZrb_Intkz: 10107 case X86::VSQRTSSZm: 10108 case X86::VSQRTSSZm_Int: 10109 case X86::VSQRTSSZm_Intk: 10110 case X86::VSQRTSSZm_Intkz: 10111 case X86::VSQRTSSZr: 10112 case X86::VSQRTSSZr_Int: 10113 case X86::VSQRTSSZr_Intk: 10114 case X86::VSQRTSSZr_Intkz: 10115 case X86::VSQRTSSZrb_Int: 10116 case X86::VSQRTSSZrb_Intk: 10117 case X86::VSQRTSSZrb_Intkz: 10118 10119 case X86::VGATHERDPDYrm: 10120 case X86::VGATHERDPDZ128rm: 10121 case X86::VGATHERDPDZ256rm: 10122 case X86::VGATHERDPDZrm: 10123 case X86::VGATHERDPDrm: 10124 case X86::VGATHERDPSYrm: 10125 case X86::VGATHERDPSZ128rm: 10126 case X86::VGATHERDPSZ256rm: 10127 case X86::VGATHERDPSZrm: 10128 case X86::VGATHERDPSrm: 10129 case X86::VGATHERPF0DPDm: 10130 case X86::VGATHERPF0DPSm: 10131 case X86::VGATHERPF0QPDm: 10132 case X86::VGATHERPF0QPSm: 10133 case X86::VGATHERPF1DPDm: 10134 case X86::VGATHERPF1DPSm: 10135 case X86::VGATHERPF1QPDm: 10136 case X86::VGATHERPF1QPSm: 10137 case X86::VGATHERQPDYrm: 10138 case X86::VGATHERQPDZ128rm: 10139 case X86::VGATHERQPDZ256rm: 10140 case X86::VGATHERQPDZrm: 10141 case X86::VGATHERQPDrm: 10142 case X86::VGATHERQPSYrm: 10143 case X86::VGATHERQPSZ128rm: 10144 case X86::VGATHERQPSZ256rm: 10145 case X86::VGATHERQPSZrm: 10146 case X86::VGATHERQPSrm: 10147 case X86::VPGATHERDDYrm: 10148 case X86::VPGATHERDDZ128rm: 10149 case X86::VPGATHERDDZ256rm: 10150 case X86::VPGATHERDDZrm: 10151 case X86::VPGATHERDDrm: 10152 case X86::VPGATHERDQYrm: 10153 case X86::VPGATHERDQZ128rm: 10154 case X86::VPGATHERDQZ256rm: 10155 case X86::VPGATHERDQZrm: 10156 case X86::VPGATHERDQrm: 10157 case X86::VPGATHERQDYrm: 10158 case X86::VPGATHERQDZ128rm: 10159 case X86::VPGATHERQDZ256rm: 10160 case X86::VPGATHERQDZrm: 10161 case X86::VPGATHERQDrm: 10162 case X86::VPGATHERQQYrm: 10163 case X86::VPGATHERQQZ128rm: 10164 case X86::VPGATHERQQZ256rm: 10165 case X86::VPGATHERQQZrm: 10166 case X86::VPGATHERQQrm: 10167 case X86::VSCATTERDPDZ128mr: 10168 case X86::VSCATTERDPDZ256mr: 10169 case X86::VSCATTERDPDZmr: 10170 case X86::VSCATTERDPSZ128mr: 10171 case X86::VSCATTERDPSZ256mr: 10172 case X86::VSCATTERDPSZmr: 10173 case X86::VSCATTERPF0DPDm: 10174 case X86::VSCATTERPF0DPSm: 10175 case X86::VSCATTERPF0QPDm: 10176 case X86::VSCATTERPF0QPSm: 10177 case X86::VSCATTERPF1DPDm: 10178 case X86::VSCATTERPF1DPSm: 10179 case X86::VSCATTERPF1QPDm: 10180 case X86::VSCATTERPF1QPSm: 10181 case X86::VSCATTERQPDZ128mr: 10182 case X86::VSCATTERQPDZ256mr: 10183 case X86::VSCATTERQPDZmr: 10184 case X86::VSCATTERQPSZ128mr: 10185 case X86::VSCATTERQPSZ256mr: 10186 case X86::VSCATTERQPSZmr: 10187 case X86::VPSCATTERDDZ128mr: 10188 case X86::VPSCATTERDDZ256mr: 10189 case X86::VPSCATTERDDZmr: 10190 case X86::VPSCATTERDQZ128mr: 10191 case X86::VPSCATTERDQZ256mr: 10192 case X86::VPSCATTERDQZmr: 10193 case X86::VPSCATTERQDZ128mr: 10194 case X86::VPSCATTERQDZ256mr: 10195 case X86::VPSCATTERQDZmr: 10196 case X86::VPSCATTERQQZ128mr: 10197 case X86::VPSCATTERQQZ256mr: 10198 case X86::VPSCATTERQQZmr: 10199 return true; 10200 } 10201} 10202 10203bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel, 10204 const MachineRegisterInfo *MRI, 10205 const MachineInstr &DefMI, 10206 unsigned DefIdx, 10207 const MachineInstr &UseMI, 10208 unsigned UseIdx) const { 10209 return isHighLatencyDef(DefMI.getOpcode()); 10210} 10211 10212bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst, 10213 const MachineBasicBlock *MBB) const { 10214 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) && 10215 "Reassociation needs binary operators"); 10216 10217 // Integer binary math/logic instructions have a third source operand: 10218 // the EFLAGS register. That operand must be both defined here and never 10219 // used; ie, it must be dead. If the EFLAGS operand is live, then we can 10220 // not change anything because rearranging the operands could affect other 10221 // instructions that depend on the exact status flags (zero, sign, etc.) 10222 // that are set by using these particular operands with this operation. 10223 if (Inst.getNumOperands() == 4) { 10224 assert(Inst.getOperand(3).isReg() && 10225 Inst.getOperand(3).getReg() == X86::EFLAGS && 10226 "Unexpected operand in reassociable instruction"); 10227 if (!Inst.getOperand(3).isDead()) 10228 return false; 10229 } 10230 10231 return TargetInstrInfo::hasReassociableOperands(Inst, MBB); 10232} 10233 10234// TODO: There are many more machine instruction opcodes to match: 10235// 1. Other data types (integer, vectors) 10236// 2. Other math / logic operations (xor, or) 10237// 3. Other forms of the same operation (intrinsics and other variants) 10238bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const { 10239 switch (Inst.getOpcode()) { 10240 case X86::AND8rr: 10241 case X86::AND16rr: 10242 case X86::AND32rr: 10243 case X86::AND64rr: 10244 case X86::OR8rr: 10245 case X86::OR16rr: 10246 case X86::OR32rr: 10247 case X86::OR64rr: 10248 case X86::XOR8rr: 10249 case X86::XOR16rr: 10250 case X86::XOR32rr: 10251 case X86::XOR64rr: 10252 case X86::IMUL16rr: 10253 case X86::IMUL32rr: 10254 case X86::IMUL64rr: 10255 case X86::PANDrr: 10256 case X86::PORrr: 10257 case X86::PXORrr: 10258 case X86::ANDPDrr: 10259 case X86::ANDPSrr: 10260 case X86::ORPDrr: 10261 case X86::ORPSrr: 10262 case X86::XORPDrr: 10263 case X86::XORPSrr: 10264 case X86::PADDBrr: 10265 case X86::PADDWrr: 10266 case X86::PADDDrr: 10267 case X86::PADDQrr: 10268 case X86::VPANDrr: 10269 case X86::VPANDYrr: 10270 case X86::VPANDDZ128rr: 10271 case X86::VPANDDZ256rr: 10272 case X86::VPANDDZrr: 10273 case X86::VPANDQZ128rr: 10274 case X86::VPANDQZ256rr: 10275 case X86::VPANDQZrr: 10276 case X86::VPORrr: 10277 case X86::VPORYrr: 10278 case X86::VPORDZ128rr: 10279 case X86::VPORDZ256rr: 10280 case X86::VPORDZrr: 10281 case X86::VPORQZ128rr: 10282 case X86::VPORQZ256rr: 10283 case X86::VPORQZrr: 10284 case X86::VPXORrr: 10285 case X86::VPXORYrr: 10286 case X86::VPXORDZ128rr: 10287 case X86::VPXORDZ256rr: 10288 case X86::VPXORDZrr: 10289 case X86::VPXORQZ128rr: 10290 case X86::VPXORQZ256rr: 10291 case X86::VPXORQZrr: 10292 case X86::VANDPDrr: 10293 case X86::VANDPSrr: 10294 case X86::VANDPDYrr: 10295 case X86::VANDPSYrr: 10296 case X86::VANDPDZ128rr: 10297 case X86::VANDPSZ128rr: 10298 case X86::VANDPDZ256rr: 10299 case X86::VANDPSZ256rr: 10300 case X86::VANDPDZrr: 10301 case X86::VANDPSZrr: 10302 case X86::VORPDrr: 10303 case X86::VORPSrr: 10304 case X86::VORPDYrr: 10305 case X86::VORPSYrr: 10306 case X86::VORPDZ128rr: 10307 case X86::VORPSZ128rr: 10308 case X86::VORPDZ256rr: 10309 case X86::VORPSZ256rr: 10310 case X86::VORPDZrr: 10311 case X86::VORPSZrr: 10312 case X86::VXORPDrr: 10313 case X86::VXORPSrr: 10314 case X86::VXORPDYrr: 10315 case X86::VXORPSYrr: 10316 case X86::VXORPDZ128rr: 10317 case X86::VXORPSZ128rr: 10318 case X86::VXORPDZ256rr: 10319 case X86::VXORPSZ256rr: 10320 case X86::VXORPDZrr: 10321 case X86::VXORPSZrr: 10322 case X86::KADDBrr: 10323 case X86::KADDWrr: 10324 case X86::KADDDrr: 10325 case X86::KADDQrr: 10326 case X86::KANDBrr: 10327 case X86::KANDWrr: 10328 case X86::KANDDrr: 10329 case X86::KANDQrr: 10330 case X86::KORBrr: 10331 case X86::KORWrr: 10332 case X86::KORDrr: 10333 case X86::KORQrr: 10334 case X86::KXORBrr: 10335 case X86::KXORWrr: 10336 case X86::KXORDrr: 10337 case X86::KXORQrr: 10338 case X86::VPADDBrr: 10339 case X86::VPADDWrr: 10340 case X86::VPADDDrr: 10341 case X86::VPADDQrr: 10342 case X86::VPADDBYrr: 10343 case X86::VPADDWYrr: 10344 case X86::VPADDDYrr: 10345 case X86::VPADDQYrr: 10346 case X86::VPADDBZ128rr: 10347 case X86::VPADDWZ128rr: 10348 case X86::VPADDDZ128rr: 10349 case X86::VPADDQZ128rr: 10350 case X86::VPADDBZ256rr: 10351 case X86::VPADDWZ256rr: 10352 case X86::VPADDDZ256rr: 10353 case X86::VPADDQZ256rr: 10354 case X86::VPADDBZrr: 10355 case X86::VPADDWZrr: 10356 case X86::VPADDDZrr: 10357 case X86::VPADDQZrr: 10358 case X86::VPMULLWrr: 10359 case X86::VPMULLWYrr: 10360 case X86::VPMULLWZ128rr: 10361 case X86::VPMULLWZ256rr: 10362 case X86::VPMULLWZrr: 10363 case X86::VPMULLDrr: 10364 case X86::VPMULLDYrr: 10365 case X86::VPMULLDZ128rr: 10366 case X86::VPMULLDZ256rr: 10367 case X86::VPMULLDZrr: 10368 case X86::VPMULLQZ128rr: 10369 case X86::VPMULLQZ256rr: 10370 case X86::VPMULLQZrr: 10371 // Normal min/max instructions are not commutative because of NaN and signed 10372 // zero semantics, but these are. Thus, there's no need to check for global 10373 // relaxed math; the instructions themselves have the properties we need. 10374 case X86::MAXCPDrr: 10375 case X86::MAXCPSrr: 10376 case X86::MAXCSDrr: 10377 case X86::MAXCSSrr: 10378 case X86::MINCPDrr: 10379 case X86::MINCPSrr: 10380 case X86::MINCSDrr: 10381 case X86::MINCSSrr: 10382 case X86::VMAXCPDrr: 10383 case X86::VMAXCPSrr: 10384 case X86::VMAXCPDYrr: 10385 case X86::VMAXCPSYrr: 10386 case X86::VMAXCPDZ128rr: 10387 case X86::VMAXCPSZ128rr: 10388 case X86::VMAXCPDZ256rr: 10389 case X86::VMAXCPSZ256rr: 10390 case X86::VMAXCPDZrr: 10391 case X86::VMAXCPSZrr: 10392 case X86::VMAXCSDrr: 10393 case X86::VMAXCSSrr: 10394 case X86::VMAXCSDZrr: 10395 case X86::VMAXCSSZrr: 10396 case X86::VMINCPDrr: 10397 case X86::VMINCPSrr: 10398 case X86::VMINCPDYrr: 10399 case X86::VMINCPSYrr: 10400 case X86::VMINCPDZ128rr: 10401 case X86::VMINCPSZ128rr: 10402 case X86::VMINCPDZ256rr: 10403 case X86::VMINCPSZ256rr: 10404 case X86::VMINCPDZrr: 10405 case X86::VMINCPSZrr: 10406 case X86::VMINCSDrr: 10407 case X86::VMINCSSrr: 10408 case X86::VMINCSDZrr: 10409 case X86::VMINCSSZrr: 10410 return true; 10411 case X86::ADDPDrr: 10412 case X86::ADDPSrr: 10413 case X86::ADDSDrr: 10414 case X86::ADDSSrr: 10415 case X86::MULPDrr: 10416 case X86::MULPSrr: 10417 case X86::MULSDrr: 10418 case X86::MULSSrr: 10419 case X86::VADDPDrr: 10420 case X86::VADDPSrr: 10421 case X86::VADDPDYrr: 10422 case X86::VADDPSYrr: 10423 case X86::VADDPDZ128rr: 10424 case X86::VADDPSZ128rr: 10425 case X86::VADDPDZ256rr: 10426 case X86::VADDPSZ256rr: 10427 case X86::VADDPDZrr: 10428 case X86::VADDPSZrr: 10429 case X86::VADDSDrr: 10430 case X86::VADDSSrr: 10431 case X86::VADDSDZrr: 10432 case X86::VADDSSZrr: 10433 case X86::VMULPDrr: 10434 case X86::VMULPSrr: 10435 case X86::VMULPDYrr: 10436 case X86::VMULPSYrr: 10437 case X86::VMULPDZ128rr: 10438 case X86::VMULPSZ128rr: 10439 case X86::VMULPDZ256rr: 10440 case X86::VMULPSZ256rr: 10441 case X86::VMULPDZrr: 10442 case X86::VMULPSZrr: 10443 case X86::VMULSDrr: 10444 case X86::VMULSSrr: 10445 case X86::VMULSDZrr: 10446 case X86::VMULSSZrr: 10447 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath; 10448 default: 10449 return false; 10450 } 10451} 10452 10453/// This is an architecture-specific helper function of reassociateOps. 10454/// Set special operand attributes for new instructions after reassociation. 10455void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1, 10456 MachineInstr &OldMI2, 10457 MachineInstr &NewMI1, 10458 MachineInstr &NewMI2) const { 10459 // Integer instructions define an implicit EFLAGS source register operand as 10460 // the third source (fourth total) operand. 10461 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4) 10462 return; 10463 10464 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 && 10465 "Unexpected instruction type for reassociation"); 10466 10467 MachineOperand &OldOp1 = OldMI1.getOperand(3); 10468 MachineOperand &OldOp2 = OldMI2.getOperand(3); 10469 MachineOperand &NewOp1 = NewMI1.getOperand(3); 10470 MachineOperand &NewOp2 = NewMI2.getOperand(3); 10471 10472 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() && 10473 "Must have dead EFLAGS operand in reassociable instruction"); 10474 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() && 10475 "Must have dead EFLAGS operand in reassociable instruction"); 10476 10477 (void)OldOp1; 10478 (void)OldOp2; 10479 10480 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS && 10481 "Unexpected operand in reassociable instruction"); 10482 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS && 10483 "Unexpected operand in reassociable instruction"); 10484 10485 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations 10486 // of this pass or other passes. The EFLAGS operands must be dead in these new 10487 // instructions because the EFLAGS operands in the original instructions must 10488 // be dead in order for reassociation to occur. 10489 NewOp1.setIsDead(); 10490 NewOp2.setIsDead(); 10491} 10492 10493std::pair<unsigned, unsigned> 10494X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { 10495 return std::make_pair(TF, 0u); 10496} 10497 10498ArrayRef<std::pair<unsigned, const char *>> 10499X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const { 10500 using namespace X86II; 10501 static const std::pair<unsigned, const char *> TargetFlags[] = { 10502 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"}, 10503 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"}, 10504 {MO_GOT, "x86-got"}, 10505 {MO_GOTOFF, "x86-gotoff"}, 10506 {MO_GOTPCREL, "x86-gotpcrel"}, 10507 {MO_PLT, "x86-plt"}, 10508 {MO_TLSGD, "x86-tlsgd"}, 10509 {MO_TLSLD, "x86-tlsld"}, 10510 {MO_TLSLDM, "x86-tlsldm"}, 10511 {MO_GOTTPOFF, "x86-gottpoff"}, 10512 {MO_INDNTPOFF, "x86-indntpoff"}, 10513 {MO_TPOFF, "x86-tpoff"}, 10514 {MO_DTPOFF, "x86-dtpoff"}, 10515 {MO_NTPOFF, "x86-ntpoff"}, 10516 {MO_GOTNTPOFF, "x86-gotntpoff"}, 10517 {MO_DLLIMPORT, "x86-dllimport"}, 10518 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"}, 10519 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"}, 10520 {MO_TLVP, "x86-tlvp"}, 10521 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"}, 10522 {MO_SECREL, "x86-secrel"}}; 10523 return makeArrayRef(TargetFlags); 10524} 10525 10526namespace { 10527 /// Create Global Base Reg pass. This initializes the PIC 10528 /// global base register for x86-32. 10529 struct CGBR : public MachineFunctionPass { 10530 static char ID; 10531 CGBR() : MachineFunctionPass(ID) {} 10532 10533 bool runOnMachineFunction(MachineFunction &MF) override { 10534 const X86TargetMachine *TM = 10535 static_cast<const X86TargetMachine *>(&MF.getTarget()); 10536 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>(); 10537 10538 // Don't do anything if this is 64-bit as 64-bit PIC 10539 // uses RIP relative addressing. 10540 if (STI.is64Bit()) 10541 return false; 10542 10543 // Only emit a global base reg in PIC mode. 10544 if (!TM->isPositionIndependent()) 10545 return false; 10546 10547 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 10548 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 10549 10550 // If we didn't need a GlobalBaseReg, don't insert code. 10551 if (GlobalBaseReg == 0) 10552 return false; 10553 10554 // Insert the set of GlobalBaseReg into the first MBB of the function 10555 MachineBasicBlock &FirstMBB = MF.front(); 10556 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 10557 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 10558 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 10559 const X86InstrInfo *TII = STI.getInstrInfo(); 10560 10561 unsigned PC; 10562 if (STI.isPICStyleGOT()) 10563 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 10564 else 10565 PC = GlobalBaseReg; 10566 10567 // Operand of MovePCtoStack is completely ignored by asm printer. It's 10568 // only used in JIT code emission as displacement to pc. 10569 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 10570 10571 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 10572 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 10573 if (STI.isPICStyleGOT()) { 10574 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 10575 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 10576 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 10577 X86II::MO_GOT_ABSOLUTE_ADDRESS); 10578 } 10579 10580 return true; 10581 } 10582 10583 StringRef getPassName() const override { 10584 return "X86 PIC Global Base Reg Initialization"; 10585 } 10586 10587 void getAnalysisUsage(AnalysisUsage &AU) const override { 10588 AU.setPreservesCFG(); 10589 MachineFunctionPass::getAnalysisUsage(AU); 10590 } 10591 }; 10592} 10593 10594char CGBR::ID = 0; 10595FunctionPass* 10596llvm::createX86GlobalBaseRegPass() { return new CGBR(); } 10597 10598namespace { 10599 struct LDTLSCleanup : public MachineFunctionPass { 10600 static char ID; 10601 LDTLSCleanup() : MachineFunctionPass(ID) {} 10602 10603 bool runOnMachineFunction(MachineFunction &MF) override { 10604 if (skipFunction(MF.getFunction())) 10605 return false; 10606 10607 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>(); 10608 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 10609 // No point folding accesses if there isn't at least two. 10610 return false; 10611 } 10612 10613 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 10614 return VisitNode(DT->getRootNode(), 0); 10615 } 10616 10617 // Visit the dominator subtree rooted at Node in pre-order. 10618 // If TLSBaseAddrReg is non-null, then use that to replace any 10619 // TLS_base_addr instructions. Otherwise, create the register 10620 // when the first such instruction is seen, and then use it 10621 // as we encounter more instructions. 10622 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 10623 MachineBasicBlock *BB = Node->getBlock(); 10624 bool Changed = false; 10625 10626 // Traverse the current block. 10627 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 10628 ++I) { 10629 switch (I->getOpcode()) { 10630 case X86::TLS_base_addr32: 10631 case X86::TLS_base_addr64: 10632 if (TLSBaseAddrReg) 10633 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg); 10634 else 10635 I = SetRegister(*I, &TLSBaseAddrReg); 10636 Changed = true; 10637 break; 10638 default: 10639 break; 10640 } 10641 } 10642 10643 // Visit the children of this block in the dominator tree. 10644 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 10645 I != E; ++I) { 10646 Changed |= VisitNode(*I, TLSBaseAddrReg); 10647 } 10648 10649 return Changed; 10650 } 10651 10652 // Replace the TLS_base_addr instruction I with a copy from 10653 // TLSBaseAddrReg, returning the new instruction. 10654 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I, 10655 unsigned TLSBaseAddrReg) { 10656 MachineFunction *MF = I.getParent()->getParent(); 10657 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>(); 10658 const bool is64Bit = STI.is64Bit(); 10659 const X86InstrInfo *TII = STI.getInstrInfo(); 10660 10661 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 10662 MachineInstr *Copy = 10663 BuildMI(*I.getParent(), I, I.getDebugLoc(), 10664 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX) 10665 .addReg(TLSBaseAddrReg); 10666 10667 // Erase the TLS_base_addr instruction. 10668 I.eraseFromParent(); 10669 10670 return Copy; 10671 } 10672 10673 // Create a virtual register in *TLSBaseAddrReg, and populate it by 10674 // inserting a copy instruction after I. Returns the new instruction. 10675 MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) { 10676 MachineFunction *MF = I.getParent()->getParent(); 10677 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>(); 10678 const bool is64Bit = STI.is64Bit(); 10679 const X86InstrInfo *TII = STI.getInstrInfo(); 10680 10681 // Create a virtual register for the TLS base address. 10682 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 10683 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 10684 ? &X86::GR64RegClass 10685 : &X86::GR32RegClass); 10686 10687 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 10688 MachineInstr *Next = I.getNextNode(); 10689 MachineInstr *Copy = 10690 BuildMI(*I.getParent(), Next, I.getDebugLoc(), 10691 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg) 10692 .addReg(is64Bit ? X86::RAX : X86::EAX); 10693 10694 return Copy; 10695 } 10696 10697 StringRef getPassName() const override { 10698 return "Local Dynamic TLS Access Clean-up"; 10699 } 10700 10701 void getAnalysisUsage(AnalysisUsage &AU) const override { 10702 AU.setPreservesCFG(); 10703 AU.addRequired<MachineDominatorTree>(); 10704 MachineFunctionPass::getAnalysisUsage(AU); 10705 } 10706 }; 10707} 10708 10709char LDTLSCleanup::ID = 0; 10710FunctionPass* 10711llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 10712 10713/// Constants defining how certain sequences should be outlined. 10714/// 10715/// \p MachineOutlinerDefault implies that the function is called with a call 10716/// instruction, and a return must be emitted for the outlined function frame. 10717/// 10718/// That is, 10719/// 10720/// I1 OUTLINED_FUNCTION: 10721/// I2 --> call OUTLINED_FUNCTION I1 10722/// I3 I2 10723/// I3 10724/// ret 10725/// 10726/// * Call construction overhead: 1 (call instruction) 10727/// * Frame construction overhead: 1 (return instruction) 10728/// 10729/// \p MachineOutlinerTailCall implies that the function is being tail called. 10730/// A jump is emitted instead of a call, and the return is already present in 10731/// the outlined sequence. That is, 10732/// 10733/// I1 OUTLINED_FUNCTION: 10734/// I2 --> jmp OUTLINED_FUNCTION I1 10735/// ret I2 10736/// ret 10737/// 10738/// * Call construction overhead: 1 (jump instruction) 10739/// * Frame construction overhead: 0 (don't need to return) 10740/// 10741enum MachineOutlinerClass { 10742 MachineOutlinerDefault, 10743 MachineOutlinerTailCall 10744}; 10745 10746X86GenInstrInfo::MachineOutlinerInfo 10747X86InstrInfo::getOutlininingCandidateInfo( 10748 std::vector< 10749 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>> 10750 &RepeatedSequenceLocs) const { 10751 10752 if (RepeatedSequenceLocs[0].second->isTerminator()) 10753 return MachineOutlinerInfo(1, // Number of instructions to emit call. 10754 0, // Number of instructions to emit frame. 10755 MachineOutlinerTailCall, // Type of call. 10756 MachineOutlinerTailCall // Type of frame. 10757 ); 10758 10759 return MachineOutlinerInfo(1, 1, MachineOutlinerDefault, 10760 MachineOutlinerDefault); 10761} 10762 10763bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF, 10764 bool OutlineFromLinkOnceODRs) const { 10765 const Function &F = MF.getFunction(); 10766 10767 // Does the function use a red zone? If it does, then we can't risk messing 10768 // with the stack. 10769 if (!F.hasFnAttribute(Attribute::NoRedZone)) 10770 return false; 10771 10772 // If we *don't* want to outline from things that could potentially be deduped 10773 // then return false. 10774 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage()) 10775 return false; 10776 10777 // This function is viable for outlining, so return true. 10778 return true; 10779} 10780 10781X86GenInstrInfo::MachineOutlinerInstrType 10782X86InstrInfo::getOutliningType(MachineInstr &MI) const { 10783 10784 // Don't allow debug values to impact outlining type. 10785 if (MI.isDebugValue() || MI.isIndirectDebugValue()) 10786 return MachineOutlinerInstrType::Invisible; 10787 10788 // Is this a tail call? If yes, we can outline as a tail call. 10789 if (isTailCall(MI)) 10790 return MachineOutlinerInstrType::Legal; 10791 10792 // Is this the terminator of a basic block? 10793 if (MI.isTerminator() || MI.isReturn()) { 10794 10795 // Does its parent have any successors in its MachineFunction? 10796 if (MI.getParent()->succ_empty()) 10797 return MachineOutlinerInstrType::Legal; 10798 10799 // It does, so we can't tail call it. 10800 return MachineOutlinerInstrType::Illegal; 10801 } 10802 10803 // Don't outline anything that modifies or reads from the stack pointer. 10804 // 10805 // FIXME: There are instructions which are being manually built without 10806 // explicit uses/defs so we also have to check the MCInstrDesc. We should be 10807 // able to remove the extra checks once those are fixed up. For example, 10808 // sometimes we might get something like %rax = POP64r 1. This won't be 10809 // caught by modifiesRegister or readsRegister even though the instruction 10810 // really ought to be formed so that modifiesRegister/readsRegister would 10811 // catch it. 10812 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) || 10813 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) || 10814 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) 10815 return MachineOutlinerInstrType::Illegal; 10816 10817 // Outlined calls change the instruction pointer, so don't read from it. 10818 if (MI.readsRegister(X86::RIP, &RI) || 10819 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) || 10820 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP)) 10821 return MachineOutlinerInstrType::Illegal; 10822 10823 // Positions can't safely be outlined. 10824 if (MI.isPosition()) 10825 return MachineOutlinerInstrType::Illegal; 10826 10827 // Make sure none of the operands of this instruction do anything tricky. 10828 for (const MachineOperand &MOP : MI.operands()) 10829 if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() || 10830 MOP.isTargetIndex()) 10831 return MachineOutlinerInstrType::Illegal; 10832 10833 return MachineOutlinerInstrType::Legal; 10834} 10835 10836void X86InstrInfo::insertOutlinerEpilogue(MachineBasicBlock &MBB, 10837 MachineFunction &MF, 10838 const MachineOutlinerInfo &MInfo) 10839 const { 10840 // If we're a tail call, we already have a return, so don't do anything. 10841 if (MInfo.FrameConstructionID == MachineOutlinerTailCall) 10842 return; 10843 10844 // We're a normal call, so our sequence doesn't have a return instruction. 10845 // Add it in. 10846 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ)); 10847 MBB.insert(MBB.end(), retq); 10848} 10849 10850void X86InstrInfo::insertOutlinerPrologue(MachineBasicBlock &MBB, 10851 MachineFunction &MF, 10852 const MachineOutlinerInfo &MInfo) 10853 const {} 10854 10855MachineBasicBlock::iterator 10856X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB, 10857 MachineBasicBlock::iterator &It, 10858 MachineFunction &MF, 10859 const MachineOutlinerInfo &MInfo) const { 10860 // Is it a tail call? 10861 if (MInfo.CallConstructionID == MachineOutlinerTailCall) { 10862 // Yes, just insert a JMP. 10863 It = MBB.insert(It, 10864 BuildMI(MF, DebugLoc(), get(X86::JMP_1)) 10865 .addGlobalAddress(M.getNamedValue(MF.getName()))); 10866 } else { 10867 // No, insert a call. 10868 It = MBB.insert(It, 10869 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32)) 10870 .addGlobalAddress(M.getNamedValue(MF.getName()))); 10871 } 10872 10873 return It; 10874} 10875