X86InstrInfo.cpp revision 280031 
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/LiveVariables.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineDominators.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/StackMaps.h"
28#include "llvm/IR/DerivedTypes.h"
29#include "llvm/IR/Function.h"
30#include "llvm/IR/LLVMContext.h"
31#include "llvm/MC/MCAsmInfo.h"
32#include "llvm/MC/MCExpr.h"
33#include "llvm/MC/MCInst.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/Target/TargetOptions.h"
39#include <limits>
40
41using namespace llvm;
42
43#define DEBUG_TYPE "x86-instr-info"
44
45#define GET_INSTRINFO_CTOR_DTOR
46#include "X86GenInstrInfo.inc"
47
48static cl::opt<bool>
49NoFusing("disable-spill-fusing",
50         cl::desc("Disable fusing of spill code into instructions"));
51static cl::opt<bool>
52PrintFailedFusing("print-failed-fuse-candidates",
53                  cl::desc("Print instructions that the allocator wants to"
54                           " fuse, but the X86 backend currently can't"),
55                  cl::Hidden);
56static cl::opt<bool>
57ReMatPICStubLoad("remat-pic-stub-load",
58                 cl::desc("Re-materialize load from stub in PIC mode"),
59                 cl::init(false), cl::Hidden);
60
61enum {
62  // Select which memory operand is being unfolded.
63  // (stored in bits 0 - 3)
64  TB_INDEX_0    = 0,
65  TB_INDEX_1    = 1,
66  TB_INDEX_2    = 2,
67  TB_INDEX_3    = 3,
68  TB_INDEX_4    = 4,
69  TB_INDEX_MASK = 0xf,
70
71  // Do not insert the reverse map (MemOp -> RegOp) into the table.
72  // This may be needed because there is a many -> one mapping.
73  TB_NO_REVERSE   = 1 << 4,
74
75  // Do not insert the forward map (RegOp -> MemOp) into the table.
76  // This is needed for Native Client, which prohibits branch
77  // instructions from using a memory operand.
78  TB_NO_FORWARD   = 1 << 5,
79
80  TB_FOLDED_LOAD  = 1 << 6,
81  TB_FOLDED_STORE = 1 << 7,
82
83  // Minimum alignment required for load/store.
84  // Used for RegOp->MemOp conversion.
85  // (stored in bits 8 - 15)
86  TB_ALIGN_SHIFT = 8,
87  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90  TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92};
93
94struct X86OpTblEntry {
95  uint16_t RegOp;
96  uint16_t MemOp;
97  uint16_t Flags;
98};
99
100// Pin the vtable to this file.
101void X86InstrInfo::anchor() {}
102
103X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104    : X86GenInstrInfo(
105          (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106          (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107      Subtarget(STI), RI(STI) {
108
109  static const X86OpTblEntry OpTbl2Addr[] = {
110    { X86::ADC32ri,     X86::ADC32mi,    0 },
111    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
112    { X86::ADC32rr,     X86::ADC32mr,    0 },
113    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
114    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
115    { X86::ADC64rr,     X86::ADC64mr,    0 },
116    { X86::ADD16ri,     X86::ADD16mi,    0 },
117    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
118    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
119    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
120    { X86::ADD16rr,     X86::ADD16mr,    0 },
121    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
122    { X86::ADD32ri,     X86::ADD32mi,    0 },
123    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
124    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
125    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
126    { X86::ADD32rr,     X86::ADD32mr,    0 },
127    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
128    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
129    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
130    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
131    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
132    { X86::ADD64rr,     X86::ADD64mr,    0 },
133    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
134    { X86::ADD8ri,      X86::ADD8mi,     0 },
135    { X86::ADD8rr,      X86::ADD8mr,     0 },
136    { X86::AND16ri,     X86::AND16mi,    0 },
137    { X86::AND16ri8,    X86::AND16mi8,   0 },
138    { X86::AND16rr,     X86::AND16mr,    0 },
139    { X86::AND32ri,     X86::AND32mi,    0 },
140    { X86::AND32ri8,    X86::AND32mi8,   0 },
141    { X86::AND32rr,     X86::AND32mr,    0 },
142    { X86::AND64ri32,   X86::AND64mi32,  0 },
143    { X86::AND64ri8,    X86::AND64mi8,   0 },
144    { X86::AND64rr,     X86::AND64mr,    0 },
145    { X86::AND8ri,      X86::AND8mi,     0 },
146    { X86::AND8rr,      X86::AND8mr,     0 },
147    { X86::DEC16r,      X86::DEC16m,     0 },
148    { X86::DEC32r,      X86::DEC32m,     0 },
149    { X86::DEC64r,      X86::DEC64m,     0 },
150    { X86::DEC8r,       X86::DEC8m,      0 },
151    { X86::INC16r,      X86::INC16m,     0 },
152    { X86::INC32r,      X86::INC32m,     0 },
153    { X86::INC64r,      X86::INC64m,     0 },
154    { X86::INC8r,       X86::INC8m,      0 },
155    { X86::NEG16r,      X86::NEG16m,     0 },
156    { X86::NEG32r,      X86::NEG32m,     0 },
157    { X86::NEG64r,      X86::NEG64m,     0 },
158    { X86::NEG8r,       X86::NEG8m,      0 },
159    { X86::NOT16r,      X86::NOT16m,     0 },
160    { X86::NOT32r,      X86::NOT32m,     0 },
161    { X86::NOT64r,      X86::NOT64m,     0 },
162    { X86::NOT8r,       X86::NOT8m,      0 },
163    { X86::OR16ri,      X86::OR16mi,     0 },
164    { X86::OR16ri8,     X86::OR16mi8,    0 },
165    { X86::OR16rr,      X86::OR16mr,     0 },
166    { X86::OR32ri,      X86::OR32mi,     0 },
167    { X86::OR32ri8,     X86::OR32mi8,    0 },
168    { X86::OR32rr,      X86::OR32mr,     0 },
169    { X86::OR64ri32,    X86::OR64mi32,   0 },
170    { X86::OR64ri8,     X86::OR64mi8,    0 },
171    { X86::OR64rr,      X86::OR64mr,     0 },
172    { X86::OR8ri,       X86::OR8mi,      0 },
173    { X86::OR8rr,       X86::OR8mr,      0 },
174    { X86::ROL16r1,     X86::ROL16m1,    0 },
175    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
176    { X86::ROL16ri,     X86::ROL16mi,    0 },
177    { X86::ROL32r1,     X86::ROL32m1,    0 },
178    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
179    { X86::ROL32ri,     X86::ROL32mi,    0 },
180    { X86::ROL64r1,     X86::ROL64m1,    0 },
181    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
182    { X86::ROL64ri,     X86::ROL64mi,    0 },
183    { X86::ROL8r1,      X86::ROL8m1,     0 },
184    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
185    { X86::ROL8ri,      X86::ROL8mi,     0 },
186    { X86::ROR16r1,     X86::ROR16m1,    0 },
187    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
188    { X86::ROR16ri,     X86::ROR16mi,    0 },
189    { X86::ROR32r1,     X86::ROR32m1,    0 },
190    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
191    { X86::ROR32ri,     X86::ROR32mi,    0 },
192    { X86::ROR64r1,     X86::ROR64m1,    0 },
193    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
194    { X86::ROR64ri,     X86::ROR64mi,    0 },
195    { X86::ROR8r1,      X86::ROR8m1,     0 },
196    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
197    { X86::ROR8ri,      X86::ROR8mi,     0 },
198    { X86::SAR16r1,     X86::SAR16m1,    0 },
199    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
200    { X86::SAR16ri,     X86::SAR16mi,    0 },
201    { X86::SAR32r1,     X86::SAR32m1,    0 },
202    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
203    { X86::SAR32ri,     X86::SAR32mi,    0 },
204    { X86::SAR64r1,     X86::SAR64m1,    0 },
205    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
206    { X86::SAR64ri,     X86::SAR64mi,    0 },
207    { X86::SAR8r1,      X86::SAR8m1,     0 },
208    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
209    { X86::SAR8ri,      X86::SAR8mi,     0 },
210    { X86::SBB32ri,     X86::SBB32mi,    0 },
211    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
212    { X86::SBB32rr,     X86::SBB32mr,    0 },
213    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
214    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
215    { X86::SBB64rr,     X86::SBB64mr,    0 },
216    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
217    { X86::SHL16ri,     X86::SHL16mi,    0 },
218    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
219    { X86::SHL32ri,     X86::SHL32mi,    0 },
220    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
221    { X86::SHL64ri,     X86::SHL64mi,    0 },
222    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
223    { X86::SHL8ri,      X86::SHL8mi,     0 },
224    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
225    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
226    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
227    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
228    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
229    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
230    { X86::SHR16r1,     X86::SHR16m1,    0 },
231    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
232    { X86::SHR16ri,     X86::SHR16mi,    0 },
233    { X86::SHR32r1,     X86::SHR32m1,    0 },
234    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
235    { X86::SHR32ri,     X86::SHR32mi,    0 },
236    { X86::SHR64r1,     X86::SHR64m1,    0 },
237    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
238    { X86::SHR64ri,     X86::SHR64mi,    0 },
239    { X86::SHR8r1,      X86::SHR8m1,     0 },
240    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
241    { X86::SHR8ri,      X86::SHR8mi,     0 },
242    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
243    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
244    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
245    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
246    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
247    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
248    { X86::SUB16ri,     X86::SUB16mi,    0 },
249    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
250    { X86::SUB16rr,     X86::SUB16mr,    0 },
251    { X86::SUB32ri,     X86::SUB32mi,    0 },
252    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
253    { X86::SUB32rr,     X86::SUB32mr,    0 },
254    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
255    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
256    { X86::SUB64rr,     X86::SUB64mr,    0 },
257    { X86::SUB8ri,      X86::SUB8mi,     0 },
258    { X86::SUB8rr,      X86::SUB8mr,     0 },
259    { X86::XOR16ri,     X86::XOR16mi,    0 },
260    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
261    { X86::XOR16rr,     X86::XOR16mr,    0 },
262    { X86::XOR32ri,     X86::XOR32mi,    0 },
263    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
264    { X86::XOR32rr,     X86::XOR32mr,    0 },
265    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
266    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
267    { X86::XOR64rr,     X86::XOR64mr,    0 },
268    { X86::XOR8ri,      X86::XOR8mi,     0 },
269    { X86::XOR8rr,      X86::XOR8mr,     0 }
270  };
271
272  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
273    unsigned RegOp = OpTbl2Addr[i].RegOp;
274    unsigned MemOp = OpTbl2Addr[i].MemOp;
275    unsigned Flags = OpTbl2Addr[i].Flags;
276    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                  RegOp, MemOp,
278                  // Index 0, folded load and store, no alignment requirement.
279                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280  }
281
282  static const X86OpTblEntry OpTbl0[] = {
283    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
337    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
338    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
339    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
340    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
341    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
342    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
343    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
344    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
345    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
346    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
347    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
348    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
349    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
350    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
351    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
352    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
353    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
354    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
355    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
356    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
357    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
358    // AVX 128-bit versions of foldable instructions
359    { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
360    { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
361    { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
362    { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
363    { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364    { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
365    { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
366    { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
367    { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
368    { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
369    { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
370    // AVX 256-bit foldable instructions
371    { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
372    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
373    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
374    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
375    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
376    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
377    // AVX-512 foldable instructions
378    { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
379    { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
380    { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
381    { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
382    { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
383    { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
384    { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
385    { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
386    { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
387    { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
388    { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
389    // AVX-512 foldable instructions (256-bit versions)
390    { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
391    { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
392    { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
393    { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
394    { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
395    { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
396    { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
397    { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
398    { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
399    { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
400    // AVX-512 foldable instructions (128-bit versions)
401    { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
402    { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
403    { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
404    { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
405    { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
406    { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
407    { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
408    { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
409    { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
410    { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE }
411  };
412
413  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
414    unsigned RegOp      = OpTbl0[i].RegOp;
415    unsigned MemOp      = OpTbl0[i].MemOp;
416    unsigned Flags      = OpTbl0[i].Flags;
417    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
418                  RegOp, MemOp, TB_INDEX_0 | Flags);
419  }
420
421  static const X86OpTblEntry OpTbl1[] = {
422    { X86::CMP16rr,         X86::CMP16rm,             0 },
423    { X86::CMP32rr,         X86::CMP32rm,             0 },
424    { X86::CMP64rr,         X86::CMP64rm,             0 },
425    { X86::CMP8rr,          X86::CMP8rm,              0 },
426    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
427    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
428    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
429    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
430    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
431    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
432    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
433    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
434    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
435    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
436    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
437    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
438    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
439    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
440    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
441    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
442    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
443    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
444    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
445    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
446    { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
447    { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
448    { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
449    { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
450    { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
451    { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
452    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
453    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
454    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
455    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
456    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
457    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
458    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
459    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
460    { X86::MOV16rr,         X86::MOV16rm,             0 },
461    { X86::MOV32rr,         X86::MOV32rm,             0 },
462    { X86::MOV64rr,         X86::MOV64rm,             0 },
463    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
464    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
465    { X86::MOV8rr,          X86::MOV8rm,              0 },
466    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
467    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
468    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
469    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
470    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
471    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
472    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
473    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
474    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
475    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
476    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
477    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
478    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
479    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
480    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
481    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
482    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
483    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
484    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
485    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
486    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
487    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
488    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
489    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
490    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
491    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
492    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
493    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
494    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
495    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
496    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
497    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
498    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
499    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
500    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
501    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
502    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
503    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
504    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
505    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
506    { X86::TEST16rr,        X86::TEST16rm,            0 },
507    { X86::TEST32rr,        X86::TEST32rm,            0 },
508    { X86::TEST64rr,        X86::TEST64rm,            0 },
509    { X86::TEST8rr,         X86::TEST8rm,             0 },
510    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
511    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
512    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
513    // AVX 128-bit versions of foldable instructions
514    { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
515    { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
516    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
517    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
518    { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
519    { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
520    { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
521    { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
522    { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
523    { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
524    { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
525    { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
526    { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
527    { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
528    { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
529    { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
530    { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
531    { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
532    { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
533    { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
534    { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
535    { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
536    { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
537    { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
538    { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
539    { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
540    { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
541    { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
542    { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
543    { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
544    { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
545    { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
546    { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
547    { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
548    { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
549    { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
550    { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
551    { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
552    { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
553    { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
554    { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
555    { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
556    { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
557    { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
558    { X86::VRCPPSr,         X86::VRCPPSm,             0 },
559    { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
560    { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
561    { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
562    { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
563    { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
564    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
565    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
566    { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
567
568    // AVX 256-bit foldable instructions
569    { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
570    { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
571    { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
572    { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
573    { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
574    { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
575    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
576    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
577    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
578    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
579    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
580    { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
581    { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
582    { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
583    { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
584    { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
585    { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
586    { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
587    { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
588    { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
589
590    // AVX2 foldable instructions
591    { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
592    { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
593    { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
594    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
595    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
596    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
597
598    // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
599    { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
600    { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
601    { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
602    { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
603    { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
604    { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
605    { X86::BLCI32rr,        X86::BLCI32rm,            0 },
606    { X86::BLCI64rr,        X86::BLCI64rm,            0 },
607    { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
608    { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
609    { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
610    { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
611    { X86::BLCS32rr,        X86::BLCS32rm,            0 },
612    { X86::BLCS64rr,        X86::BLCS64rm,            0 },
613    { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
614    { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
615    { X86::BLSI32rr,        X86::BLSI32rm,            0 },
616    { X86::BLSI64rr,        X86::BLSI64rm,            0 },
617    { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
618    { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
619    { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
620    { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
621    { X86::BLSR32rr,        X86::BLSR32rm,            0 },
622    { X86::BLSR64rr,        X86::BLSR64rm,            0 },
623    { X86::BZHI32rr,        X86::BZHI32rm,            0 },
624    { X86::BZHI64rr,        X86::BZHI64rm,            0 },
625    { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
626    { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
627    { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
628    { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
629    { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
630    { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
631    { X86::RORX32ri,        X86::RORX32mi,            0 },
632    { X86::RORX64ri,        X86::RORX64mi,            0 },
633    { X86::SARX32rr,        X86::SARX32rm,            0 },
634    { X86::SARX64rr,        X86::SARX64rm,            0 },
635    { X86::SHRX32rr,        X86::SHRX32rm,            0 },
636    { X86::SHRX64rr,        X86::SHRX64rm,            0 },
637    { X86::SHLX32rr,        X86::SHLX32rm,            0 },
638    { X86::SHLX64rr,        X86::SHLX64rm,            0 },
639    { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
640    { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
641    { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
642    { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
643    { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
644    { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
645    { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
646
647    // AVX-512 foldable instructions
648    { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
649    { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
650    { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
651    { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
652    { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
653    { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
654    { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
655    { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
656    { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
657    { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
658    { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
659    { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
660    { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
661    { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
662    { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
663    { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
664    // AVX-512 foldable instructions (256-bit versions)
665    { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
666    { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
667    { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
668    { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
669    { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
670    { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
671    { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
672    { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
673    { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
674    { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
675    { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
676    { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
677    // AVX-512 foldable instructions (256-bit versions)
678    { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
679    { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
680    { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
681    { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
682    { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
683    { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
684    { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
685    { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
686    { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
687    { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
688    { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
689
690    // AES foldable instructions
691    { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
692    { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
693    { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
694    { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
695  };
696
697  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
698    unsigned RegOp = OpTbl1[i].RegOp;
699    unsigned MemOp = OpTbl1[i].MemOp;
700    unsigned Flags = OpTbl1[i].Flags;
701    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
702                  RegOp, MemOp,
703                  // Index 1, folded load
704                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
705  }
706
707  static const X86OpTblEntry OpTbl2[] = {
708    { X86::ADC32rr,         X86::ADC32rm,       0 },
709    { X86::ADC64rr,         X86::ADC64rm,       0 },
710    { X86::ADD16rr,         X86::ADD16rm,       0 },
711    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
712    { X86::ADD32rr,         X86::ADD32rm,       0 },
713    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
714    { X86::ADD64rr,         X86::ADD64rm,       0 },
715    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
716    { X86::ADD8rr,          X86::ADD8rm,        0 },
717    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
718    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
719    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
720    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
721    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
722    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
723    { X86::AND16rr,         X86::AND16rm,       0 },
724    { X86::AND32rr,         X86::AND32rm,       0 },
725    { X86::AND64rr,         X86::AND64rm,       0 },
726    { X86::AND8rr,          X86::AND8rm,        0 },
727    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
728    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
729    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
730    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
731    { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
732    { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
733    { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
734    { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
735    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
736    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
737    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
738    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
739    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
740    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
741    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
742    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
743    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
744    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
745    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
746    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
747    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
748    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
749    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
750    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
751    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
752    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
753    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
754    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
755    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
756    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
757    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
758    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
759    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
760    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
761    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
762    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
763    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
764    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
765    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
766    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
767    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
768    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
769    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
770    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
771    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
772    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
773    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
774    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
775    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
776    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
777    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
778    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
779    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
780    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
781    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
782    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
783    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
784    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
785    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
786    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
787    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
788    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
789    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
790    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
791    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
792    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
793    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
794    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
795    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
796    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
797    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
798    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
799    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
800    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
801    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
802    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
803    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
804    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
805    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
806    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
807    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
808    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
809    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
810    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
811    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
812    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
813    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
814    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
815    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
816    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
817    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
818    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
819    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
820    { X86::MINSDrr,         X86::MINSDrm,       0 },
821    { X86::MINSSrr,         X86::MINSSrm,       0 },
822    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
823    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
824    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
825    { X86::MULSDrr,         X86::MULSDrm,       0 },
826    { X86::MULSSrr,         X86::MULSSrm,       0 },
827    { X86::OR16rr,          X86::OR16rm,        0 },
828    { X86::OR32rr,          X86::OR32rm,        0 },
829    { X86::OR64rr,          X86::OR64rm,        0 },
830    { X86::OR8rr,           X86::OR8rm,         0 },
831    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
832    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
833    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
834    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
835    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
836    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
837    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
838    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
839    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
840    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
841    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
842    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
843    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
844    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
845    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
846    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
847    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
848    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
849    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
850    { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
851    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
852    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
853    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
854    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
855    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
856    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
857    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
858    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
859    { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
860    { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
861    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
862    { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
863    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
864    { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
865    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
866    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
867    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
868    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
869    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
870    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
871    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
872    { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
873    { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
874    { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
875    { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
876    { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
877    { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
878    { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
879    { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
880    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
881    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
882    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
883    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
884    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
885    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
886    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
887    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
888    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
889    { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
890    { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
891    { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
892    { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
893    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
894    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
895    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
896    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
897    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
898    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
899    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
900    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
901    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
902    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
903    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
904    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
905    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
906    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
907    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
908    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
909    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
910    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
911    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
912    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
913    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
914    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
915    { X86::SBB32rr,         X86::SBB32rm,       0 },
916    { X86::SBB64rr,         X86::SBB64rm,       0 },
917    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
918    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
919    { X86::SUB16rr,         X86::SUB16rm,       0 },
920    { X86::SUB32rr,         X86::SUB32rm,       0 },
921    { X86::SUB64rr,         X86::SUB64rm,       0 },
922    { X86::SUB8rr,          X86::SUB8rm,        0 },
923    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
924    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
925    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
926    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
927    // FIXME: TEST*rr -> swapped operand of TEST*mr.
928    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
929    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
930    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
931    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
932    { X86::XOR16rr,         X86::XOR16rm,       0 },
933    { X86::XOR32rr,         X86::XOR32rm,       0 },
934    { X86::XOR64rr,         X86::XOR64rm,       0 },
935    { X86::XOR8rr,          X86::XOR8rm,        0 },
936    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
937    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
938    // AVX 128-bit versions of foldable instructions
939    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
940    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
941    { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
942    { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
943    { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
944    { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
945    { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
946    { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
947    { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
948    { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
949    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
950    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
951    { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
952    { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
953    { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
954    { X86::VADDPDrr,          X86::VADDPDrm,           0 },
955    { X86::VADDPSrr,          X86::VADDPSrm,           0 },
956    { X86::VADDSDrr,          X86::VADDSDrm,           0 },
957    { X86::VADDSSrr,          X86::VADDSSrm,           0 },
958    { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
959    { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
960    { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
961    { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
962    { X86::VANDPDrr,          X86::VANDPDrm,           0 },
963    { X86::VANDPSrr,          X86::VANDPSrm,           0 },
964    { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
965    { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
966    { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
967    { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
968    { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
969    { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
970    { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
971    { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
972    { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
973    { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
974    { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
975    { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
976    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
977    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
978    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
979    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
980    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
981    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
982    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
983    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
984    { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
985    { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
986    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
987    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
988    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
989    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
990    { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
991    { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
992    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
993    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
994    { X86::VMINPDrr,          X86::VMINPDrm,           0 },
995    { X86::VMINPSrr,          X86::VMINPSrm,           0 },
996    { X86::VMINSDrr,          X86::VMINSDrm,           0 },
997    { X86::VMINSSrr,          X86::VMINSSrm,           0 },
998    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
999    { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1000    { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1001    { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1002    { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1003    { X86::VORPDrr,           X86::VORPDrm,            0 },
1004    { X86::VORPSrr,           X86::VORPSrm,            0 },
1005    { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1006    { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1007    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1008    { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1009    { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1010    { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1011    { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1012    { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1013    { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1014    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1015    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1016    { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1017    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1018    { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1019    { X86::VPANDrr,           X86::VPANDrm,            0 },
1020    { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1021    { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1022    { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1023    { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1024    { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1025    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1026    { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1027    { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1028    { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1029    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1030    { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1031    { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1032    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1033    { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1034    { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1035    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1036    { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1037    { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1038    { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1039    { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1040    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1041    { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1042    { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1043    { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1044    { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1045    { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1046    { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1047    { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1048    { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1049    { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1050    { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1051    { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1052    { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1053    { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1054    { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1055    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1056    { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1057    { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1058    { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1059    { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1060    { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1061    { X86::VPORrr,            X86::VPORrm,             0 },
1062    { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1063    { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1064    { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1065    { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1066    { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1067    { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1068    { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1069    { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1070    { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1071    { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1072    { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1073    { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1074    { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1075    { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1076    { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1077    { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1078    { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1079    { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1080    { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1081    { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1082    { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1083    { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1084    { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1085    { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1086    { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1087    { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1088    { X86::VPXORrr,           X86::VPXORrm,            0 },
1089    { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1090    { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1091    { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1092    { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1093    { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1094    { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1095    { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1096    { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1097    { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1098    { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1099    { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1100    { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1101    // AVX 256-bit foldable instructions
1102    { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1103    { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1104    { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1105    { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1106    { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1107    { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1108    { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1109    { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1110    { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1111    { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1112    { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1113    { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1114    { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1115    { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1116    { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1117    { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1118    { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1119    { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1120    { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1121    { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1122    { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1123    { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1124    { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1125    { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1126    { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1127    { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1128    { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1129    { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1130    { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1131    { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1132    { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1133    { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1134    { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1135    { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1136    { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1137    { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1138    { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1139    { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1140    { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1141    { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1142    { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1143    { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1144    // AVX2 foldable instructions
1145    { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1146    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1147    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1148    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1149    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1150    { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1151    { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1152    { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1153    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1154    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1155    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1156    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1157    { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1158    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1159    { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1160    { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1161    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1162    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1163    { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1164    { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1165    { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1166    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1167    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1168    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1169    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1170    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1171    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1172    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1173    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1174    { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1175    { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1176    { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1177    { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1178    { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1179    { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1180    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1181    { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1182    { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1183    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1184    { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1185    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1186    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1187    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1188    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1189    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1190    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1191    { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1192    { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1193    { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1194    { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1195    { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1196    { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1197    { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1198    { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1199    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1200    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1201    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1202    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1203    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1204    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1205    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1206    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1207    { X86::VPORYrr,           X86::VPORYrm,            0 },
1208    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1209    { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1210    { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1211    { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1212    { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1213    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1214    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1215    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1216    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1217    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1218    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1219    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1220    { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1221    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1222    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1223    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1224    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1225    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1226    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1227    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1228    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1229    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1230    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1231    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1232    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1233    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1234    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1235    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1236    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1237    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1238    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1239    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1240    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1241    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1242    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1243    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1244    { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1245    // FIXME: add AVX 256-bit foldable instructions
1246
1247    // FMA4 foldable patterns
1248    { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1249    { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1250    { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1251    { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1252    { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1253    { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1254    { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1255    { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1256    { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1257    { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1258    { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1259    { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1260    { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1261    { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1262    { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1263    { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1264    { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1265    { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1266    { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1267    { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1268    { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1269    { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1270    { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1271    { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1272    { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1273    { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1274    { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1275    { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1276    { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1277    { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1278    { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1279    { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1280
1281    // BMI/BMI2 foldable instructions
1282    { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1283    { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1284    { X86::MULX32rr,          X86::MULX32rm,            0 },
1285    { X86::MULX64rr,          X86::MULX64rm,            0 },
1286    { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1287    { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1288    { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1289    { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1290
1291    // AVX-512 foldable instructions
1292    { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1293    { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1294    { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1295    { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1296    { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1297    { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1298    { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1299    { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1300    { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1301    { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1302    { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1303    { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1304    { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1305    { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1306    { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1307    { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1308    { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1309    { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1310    { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1311    { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1312    { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1313    { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1314    { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1315    { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1316    { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1317    { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1318    { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1319    { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1320    { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1321    { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1322    { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1323    { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1324    { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1325    { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1326    { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1327    { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1328    { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1329    { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1330    { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1331
1332    // AVX-512{F,VL} foldable instructions
1333    { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1334    { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1335    { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1336
1337    // AVX-512{F,VL} foldable instructions
1338    { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1339    { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1340    { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1341    { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1342
1343    // AES foldable instructions
1344    { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1345    { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1346    { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1347    { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1348    { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1349    { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1350    { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1351    { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1352
1353    // SHA foldable instructions
1354    { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1355    { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1356    { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1357    { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1358    { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1359    { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1360    { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1361  };
1362
1363  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1364    unsigned RegOp = OpTbl2[i].RegOp;
1365    unsigned MemOp = OpTbl2[i].MemOp;
1366    unsigned Flags = OpTbl2[i].Flags;
1367    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1368                  RegOp, MemOp,
1369                  // Index 2, folded load
1370                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1371  }
1372
1373  static const X86OpTblEntry OpTbl3[] = {
1374    // FMA foldable instructions
1375    { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1376    { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1377    { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1378    { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1379    { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1380    { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1381
1382    { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1383    { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1384    { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1385    { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1386    { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1387    { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1388    { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1389    { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1390    { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1391    { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1392    { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1393    { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1394
1395    { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1396    { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1397    { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1398    { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1399    { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1400    { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1401
1402    { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1403    { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1404    { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1405    { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1406    { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1407    { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1408    { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1409    { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1410    { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1411    { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1412    { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1413    { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1414
1415    { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1416    { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1417    { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1418    { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1419    { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1420    { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1421
1422    { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1423    { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1424    { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1425    { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1426    { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1427    { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1428    { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1429    { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1430    { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1431    { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1432    { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1433    { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1434
1435    { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1436    { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1437    { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1438    { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1439    { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1440    { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1441
1442    { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1443    { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1444    { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1445    { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1446    { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1447    { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1448    { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1449    { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1450    { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1451    { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1452    { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1453    { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1454
1455    { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1456    { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1457    { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1458    { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1459    { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1460    { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1461    { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1462    { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1463    { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1464    { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1465    { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1466    { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1467
1468    { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1469    { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1470    { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1471    { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1472    { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1473    { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1474    { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1475    { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1476    { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1477    { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1478    { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1479    { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1480
1481    // FMA4 foldable patterns
1482    { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1483    { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1484    { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1485    { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1486    { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1487    { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1488    { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1489    { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1490    { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1491    { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1492    { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1493    { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1494    { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1495    { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1496    { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1497    { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1498    { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1499    { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1500    { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1501    { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1502    { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1503    { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1504    { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1505    { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1506    { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1507    { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1508    { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1509    { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1510    { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1511    { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1512    { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1513    { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1514    // AVX-512 VPERMI instructions with 3 source operands.
1515    { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1516    { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1517    { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1518    { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1519    { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1520    { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1521    { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1522    { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1523    { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1524    { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1525    { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1526    { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1527    { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1528     // AVX-512 arithmetic instructions
1529    { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1530    { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1531    { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1532    { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1533    { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1534    { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1535    { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1536    { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1537    { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1538    { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1539    { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1540    { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1541    // AVX-512{F,VL} arithmetic instructions 256-bit
1542    { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1543    { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1544    { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1545    { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1546    { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1547    { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1548    { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1549    { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1550    { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1551    { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1552    { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1553    { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1554    // AVX-512{F,VL} arithmetic instructions 128-bit
1555    { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1556    { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1557    { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1558    { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1559    { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1560    { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1561    { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1562    { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1563    { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1564    { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1565    { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1566    { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1567  };
1568
1569  for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1570    unsigned RegOp = OpTbl3[i].RegOp;
1571    unsigned MemOp = OpTbl3[i].MemOp;
1572    unsigned Flags = OpTbl3[i].Flags;
1573    AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1574                  RegOp, MemOp,
1575                  // Index 3, folded load
1576                  Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1577  }
1578
1579  static const X86OpTblEntry OpTbl4[] = {
1580     // AVX-512 foldable instructions
1581    { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1582    { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1583    { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1584    { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1585    { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1586    { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1587    { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1588    { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1589    { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1590    { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1591    { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1592    { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1593    // AVX-512{F,VL} foldable instructions 256-bit
1594    { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1595    { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1596    { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1597    { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1598    { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1599    { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1600    { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1601    { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1602    { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1603    { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
1604    { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
1605    { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
1606    // AVX-512{F,VL} foldable instructions 128-bit
1607    { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
1608    { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
1609    { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
1610    { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
1611    { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
1612    { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
1613    { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
1614    { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
1615    { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
1616    { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
1617    { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
1618    { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
1619  };
1620
1621  for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) {
1622    unsigned RegOp = OpTbl4[i].RegOp;
1623    unsigned MemOp = OpTbl4[i].MemOp;
1624    unsigned Flags = OpTbl4[i].Flags;
1625    AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1626                  RegOp, MemOp,
1627                  // Index 4, folded load
1628                  Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1629  }
1630}
1631
1632void
1633X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1634                            MemOp2RegOpTableType &M2RTable,
1635                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
1636    if ((Flags & TB_NO_FORWARD) == 0) {
1637      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1638      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1639    }
1640    if ((Flags & TB_NO_REVERSE) == 0) {
1641      assert(!M2RTable.count(MemOp) &&
1642           "Duplicated entries in unfolding maps?");
1643      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1644    }
1645}
1646
1647bool
1648X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1649                                    unsigned &SrcReg, unsigned &DstReg,
1650                                    unsigned &SubIdx) const {
1651  switch (MI.getOpcode()) {
1652  default: break;
1653  case X86::MOVSX16rr8:
1654  case X86::MOVZX16rr8:
1655  case X86::MOVSX32rr8:
1656  case X86::MOVZX32rr8:
1657  case X86::MOVSX64rr8:
1658    if (!Subtarget.is64Bit())
1659      // It's not always legal to reference the low 8-bit of the larger
1660      // register in 32-bit mode.
1661      return false;
1662  case X86::MOVSX32rr16:
1663  case X86::MOVZX32rr16:
1664  case X86::MOVSX64rr16:
1665  case X86::MOVSX64rr32: {
1666    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1667      // Be conservative.
1668      return false;
1669    SrcReg = MI.getOperand(1).getReg();
1670    DstReg = MI.getOperand(0).getReg();
1671    switch (MI.getOpcode()) {
1672    default: llvm_unreachable("Unreachable!");
1673    case X86::MOVSX16rr8:
1674    case X86::MOVZX16rr8:
1675    case X86::MOVSX32rr8:
1676    case X86::MOVZX32rr8:
1677    case X86::MOVSX64rr8:
1678      SubIdx = X86::sub_8bit;
1679      break;
1680    case X86::MOVSX32rr16:
1681    case X86::MOVZX32rr16:
1682    case X86::MOVSX64rr16:
1683      SubIdx = X86::sub_16bit;
1684      break;
1685    case X86::MOVSX64rr32:
1686      SubIdx = X86::sub_32bit;
1687      break;
1688    }
1689    return true;
1690  }
1691  }
1692  return false;
1693}
1694
1695int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
1696  const MachineFunction *MF = MI->getParent()->getParent();
1697  const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1698
1699  if (MI->getOpcode() == getCallFrameSetupOpcode() ||
1700      MI->getOpcode() == getCallFrameDestroyOpcode()) {
1701    unsigned StackAlign = TFI->getStackAlignment();
1702    int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
1703                 StackAlign;
1704
1705    SPAdj -= MI->getOperand(1).getImm();
1706
1707    if (MI->getOpcode() == getCallFrameSetupOpcode())
1708      return SPAdj;
1709    else
1710      return -SPAdj;
1711  }
1712
1713  // To know whether a call adjusts the stack, we need information
1714  // that is bound to the following ADJCALLSTACKUP pseudo.
1715  // Look for the next ADJCALLSTACKUP that follows the call.
1716  if (MI->isCall()) {
1717    const MachineBasicBlock* MBB = MI->getParent();
1718    auto I = ++MachineBasicBlock::const_iterator(MI);
1719    for (auto E = MBB->end(); I != E; ++I) {
1720      if (I->getOpcode() == getCallFrameDestroyOpcode() ||
1721          I->isCall())
1722        break;
1723    }
1724
1725    // If we could not find a frame destroy opcode, then it has already
1726    // been simplified, so we don't care.
1727    if (I->getOpcode() != getCallFrameDestroyOpcode())
1728      return 0;
1729
1730    return -(I->getOperand(1).getImm());
1731  }
1732
1733  // Currently handle only PUSHes we can reasonably expect to see
1734  // in call sequences
1735  switch (MI->getOpcode()) {
1736  default:
1737    return 0;
1738  case X86::PUSH32i8:
1739  case X86::PUSH32r:
1740  case X86::PUSH32rmm:
1741  case X86::PUSH32rmr:
1742  case X86::PUSHi32:
1743    return 4;
1744  }
1745}
1746
1747/// isFrameOperand - Return true and the FrameIndex if the specified
1748/// operand and follow operands form a reference to the stack frame.
1749bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1750                                  int &FrameIndex) const {
1751  if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1752      MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1753      MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1754      MI->getOperand(Op+X86::AddrDisp).isImm() &&
1755      MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1756      MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1757      MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1758    FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1759    return true;
1760  }
1761  return false;
1762}
1763
1764static bool isFrameLoadOpcode(int Opcode) {
1765  switch (Opcode) {
1766  default:
1767    return false;
1768  case X86::MOV8rm:
1769  case X86::MOV16rm:
1770  case X86::MOV32rm:
1771  case X86::MOV64rm:
1772  case X86::LD_Fp64m:
1773  case X86::MOVSSrm:
1774  case X86::MOVSDrm:
1775  case X86::MOVAPSrm:
1776  case X86::MOVAPDrm:
1777  case X86::MOVDQArm:
1778  case X86::VMOVSSrm:
1779  case X86::VMOVSDrm:
1780  case X86::VMOVAPSrm:
1781  case X86::VMOVAPDrm:
1782  case X86::VMOVDQArm:
1783  case X86::VMOVUPSYrm:
1784  case X86::VMOVAPSYrm:
1785  case X86::VMOVUPDYrm:
1786  case X86::VMOVAPDYrm:
1787  case X86::VMOVDQUYrm:
1788  case X86::VMOVDQAYrm:
1789  case X86::MMX_MOVD64rm:
1790  case X86::MMX_MOVQ64rm:
1791  case X86::VMOVAPSZrm:
1792  case X86::VMOVUPSZrm:
1793    return true;
1794  }
1795}
1796
1797static bool isFrameStoreOpcode(int Opcode) {
1798  switch (Opcode) {
1799  default: break;
1800  case X86::MOV8mr:
1801  case X86::MOV16mr:
1802  case X86::MOV32mr:
1803  case X86::MOV64mr:
1804  case X86::ST_FpP64m:
1805  case X86::MOVSSmr:
1806  case X86::MOVSDmr:
1807  case X86::MOVAPSmr:
1808  case X86::MOVAPDmr:
1809  case X86::MOVDQAmr:
1810  case X86::VMOVSSmr:
1811  case X86::VMOVSDmr:
1812  case X86::VMOVAPSmr:
1813  case X86::VMOVAPDmr:
1814  case X86::VMOVDQAmr:
1815  case X86::VMOVUPSYmr:
1816  case X86::VMOVAPSYmr:
1817  case X86::VMOVUPDYmr:
1818  case X86::VMOVAPDYmr:
1819  case X86::VMOVDQUYmr:
1820  case X86::VMOVDQAYmr:
1821  case X86::VMOVUPSZmr:
1822  case X86::VMOVAPSZmr:
1823  case X86::MMX_MOVD64mr:
1824  case X86::MMX_MOVQ64mr:
1825  case X86::MMX_MOVNTQmr:
1826    return true;
1827  }
1828  return false;
1829}
1830
1831unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1832                                           int &FrameIndex) const {
1833  if (isFrameLoadOpcode(MI->getOpcode()))
1834    if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1835      return MI->getOperand(0).getReg();
1836  return 0;
1837}
1838
1839unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1840                                                 int &FrameIndex) const {
1841  if (isFrameLoadOpcode(MI->getOpcode())) {
1842    unsigned Reg;
1843    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1844      return Reg;
1845    // Check for post-frame index elimination operations
1846    const MachineMemOperand *Dummy;
1847    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1848  }
1849  return 0;
1850}
1851
1852unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1853                                          int &FrameIndex) const {
1854  if (isFrameStoreOpcode(MI->getOpcode()))
1855    if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1856        isFrameOperand(MI, 0, FrameIndex))
1857      return MI->getOperand(X86::AddrNumOperands).getReg();
1858  return 0;
1859}
1860
1861unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1862                                                int &FrameIndex) const {
1863  if (isFrameStoreOpcode(MI->getOpcode())) {
1864    unsigned Reg;
1865    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1866      return Reg;
1867    // Check for post-frame index elimination operations
1868    const MachineMemOperand *Dummy;
1869    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1870  }
1871  return 0;
1872}
1873
1874/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1875/// X86::MOVPC32r.
1876static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1877  // Don't waste compile time scanning use-def chains of physregs.
1878  if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1879    return false;
1880  bool isPICBase = false;
1881  for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1882         E = MRI.def_instr_end(); I != E; ++I) {
1883    MachineInstr *DefMI = &*I;
1884    if (DefMI->getOpcode() != X86::MOVPC32r)
1885      return false;
1886    assert(!isPICBase && "More than one PIC base?");
1887    isPICBase = true;
1888  }
1889  return isPICBase;
1890}
1891
1892bool
1893X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1894                                                AliasAnalysis *AA) const {
1895  switch (MI->getOpcode()) {
1896  default: break;
1897  case X86::MOV8rm:
1898  case X86::MOV16rm:
1899  case X86::MOV32rm:
1900  case X86::MOV64rm:
1901  case X86::LD_Fp64m:
1902  case X86::MOVSSrm:
1903  case X86::MOVSDrm:
1904  case X86::MOVAPSrm:
1905  case X86::MOVUPSrm:
1906  case X86::MOVAPDrm:
1907  case X86::MOVDQArm:
1908  case X86::MOVDQUrm:
1909  case X86::VMOVSSrm:
1910  case X86::VMOVSDrm:
1911  case X86::VMOVAPSrm:
1912  case X86::VMOVUPSrm:
1913  case X86::VMOVAPDrm:
1914  case X86::VMOVDQArm:
1915  case X86::VMOVDQUrm:
1916  case X86::VMOVAPSYrm:
1917  case X86::VMOVUPSYrm:
1918  case X86::VMOVAPDYrm:
1919  case X86::VMOVDQAYrm:
1920  case X86::VMOVDQUYrm:
1921  case X86::MMX_MOVD64rm:
1922  case X86::MMX_MOVQ64rm:
1923  case X86::FsVMOVAPSrm:
1924  case X86::FsVMOVAPDrm:
1925  case X86::FsMOVAPSrm:
1926  case X86::FsMOVAPDrm: {
1927    // Loads from constant pools are trivially rematerializable.
1928    if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1929        MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1930        MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1931        MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1932        MI->isInvariantLoad(AA)) {
1933      unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1934      if (BaseReg == 0 || BaseReg == X86::RIP)
1935        return true;
1936      // Allow re-materialization of PIC load.
1937      if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1938        return false;
1939      const MachineFunction &MF = *MI->getParent()->getParent();
1940      const MachineRegisterInfo &MRI = MF.getRegInfo();
1941      return regIsPICBase(BaseReg, MRI);
1942    }
1943    return false;
1944  }
1945
1946  case X86::LEA32r:
1947  case X86::LEA64r: {
1948    if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1949        MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1950        MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1951        !MI->getOperand(1+X86::AddrDisp).isReg()) {
1952      // lea fi#, lea GV, etc. are all rematerializable.
1953      if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
1954        return true;
1955      unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1956      if (BaseReg == 0)
1957        return true;
1958      // Allow re-materialization of lea PICBase + x.
1959      const MachineFunction &MF = *MI->getParent()->getParent();
1960      const MachineRegisterInfo &MRI = MF.getRegInfo();
1961      return regIsPICBase(BaseReg, MRI);
1962    }
1963    return false;
1964  }
1965  }
1966
1967  // All other instructions marked M_REMATERIALIZABLE are always trivially
1968  // rematerializable.
1969  return true;
1970}
1971
1972bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1973                                         MachineBasicBlock::iterator I) const {
1974  MachineBasicBlock::iterator E = MBB.end();
1975
1976  // For compile time consideration, if we are not able to determine the
1977  // safety after visiting 4 instructions in each direction, we will assume
1978  // it's not safe.
1979  MachineBasicBlock::iterator Iter = I;
1980  for (unsigned i = 0; Iter != E && i < 4; ++i) {
1981    bool SeenDef = false;
1982    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1983      MachineOperand &MO = Iter->getOperand(j);
1984      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1985        SeenDef = true;
1986      if (!MO.isReg())
1987        continue;
1988      if (MO.getReg() == X86::EFLAGS) {
1989        if (MO.isUse())
1990          return false;
1991        SeenDef = true;
1992      }
1993    }
1994
1995    if (SeenDef)
1996      // This instruction defines EFLAGS, no need to look any further.
1997      return true;
1998    ++Iter;
1999    // Skip over DBG_VALUE.
2000    while (Iter != E && Iter->isDebugValue())
2001      ++Iter;
2002  }
2003
2004  // It is safe to clobber EFLAGS at the end of a block of no successor has it
2005  // live in.
2006  if (Iter == E) {
2007    for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2008           SE = MBB.succ_end(); SI != SE; ++SI)
2009      if ((*SI)->isLiveIn(X86::EFLAGS))
2010        return false;
2011    return true;
2012  }
2013
2014  MachineBasicBlock::iterator B = MBB.begin();
2015  Iter = I;
2016  for (unsigned i = 0; i < 4; ++i) {
2017    // If we make it to the beginning of the block, it's safe to clobber
2018    // EFLAGS iff EFLAGS is not live-in.
2019    if (Iter == B)
2020      return !MBB.isLiveIn(X86::EFLAGS);
2021
2022    --Iter;
2023    // Skip over DBG_VALUE.
2024    while (Iter != B && Iter->isDebugValue())
2025      --Iter;
2026
2027    bool SawKill = false;
2028    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2029      MachineOperand &MO = Iter->getOperand(j);
2030      // A register mask may clobber EFLAGS, but we should still look for a
2031      // live EFLAGS def.
2032      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2033        SawKill = true;
2034      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2035        if (MO.isDef()) return MO.isDead();
2036        if (MO.isKill()) SawKill = true;
2037      }
2038    }
2039
2040    if (SawKill)
2041      // This instruction kills EFLAGS and doesn't redefine it, so
2042      // there's no need to look further.
2043      return true;
2044  }
2045
2046  // Conservative answer.
2047  return false;
2048}
2049
2050void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2051                                 MachineBasicBlock::iterator I,
2052                                 unsigned DestReg, unsigned SubIdx,
2053                                 const MachineInstr *Orig,
2054                                 const TargetRegisterInfo &TRI) const {
2055  // MOV32r0 is implemented with a xor which clobbers condition code.
2056  // Re-materialize it as movri instructions to avoid side effects.
2057  unsigned Opc = Orig->getOpcode();
2058  if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2059    DebugLoc DL = Orig->getDebugLoc();
2060    BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2061      .addImm(0);
2062  } else {
2063    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2064    MBB.insert(I, MI);
2065  }
2066
2067  MachineInstr *NewMI = std::prev(I);
2068  NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2069}
2070
2071/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
2072/// is not marked dead.
2073static bool hasLiveCondCodeDef(MachineInstr *MI) {
2074  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2075    MachineOperand &MO = MI->getOperand(i);
2076    if (MO.isReg() && MO.isDef() &&
2077        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2078      return true;
2079    }
2080  }
2081  return false;
2082}
2083
2084/// getTruncatedShiftCount - check whether the shift count for a machine operand
2085/// is non-zero.
2086inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2087                                              unsigned ShiftAmtOperandIdx) {
2088  // The shift count is six bits with the REX.W prefix and five bits without.
2089  unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2090  unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2091  return Imm & ShiftCountMask;
2092}
2093
2094/// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
2095/// can be represented by a LEA instruction.
2096inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2097  // Left shift instructions can be transformed into load-effective-address
2098  // instructions if we can encode them appropriately.
2099  // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2100  // The SIB.scale field is two bits wide which means that we can encode any
2101  // shift amount less than 4.
2102  return ShAmt < 4 && ShAmt > 0;
2103}
2104
2105bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2106                                  unsigned Opc, bool AllowSP,
2107                                  unsigned &NewSrc, bool &isKill, bool &isUndef,
2108                                  MachineOperand &ImplicitOp) const {
2109  MachineFunction &MF = *MI->getParent()->getParent();
2110  const TargetRegisterClass *RC;
2111  if (AllowSP) {
2112    RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2113  } else {
2114    RC = Opc != X86::LEA32r ?
2115      &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2116  }
2117  unsigned SrcReg = Src.getReg();
2118
2119  // For both LEA64 and LEA32 the register already has essentially the right
2120  // type (32-bit or 64-bit) we may just need to forbid SP.
2121  if (Opc != X86::LEA64_32r) {
2122    NewSrc = SrcReg;
2123    isKill = Src.isKill();
2124    isUndef = Src.isUndef();
2125
2126    if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2127        !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2128      return false;
2129
2130    return true;
2131  }
2132
2133  // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2134  // another we need to add 64-bit registers to the final MI.
2135  if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2136    ImplicitOp = Src;
2137    ImplicitOp.setImplicit();
2138
2139    NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2140    MachineBasicBlock::LivenessQueryResult LQR =
2141      MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2142
2143    switch (LQR) {
2144    case MachineBasicBlock::LQR_Unknown:
2145      // We can't give sane liveness flags to the instruction, abandon LEA
2146      // formation.
2147      return false;
2148    case MachineBasicBlock::LQR_Live:
2149      isKill = MI->killsRegister(SrcReg);
2150      isUndef = false;
2151      break;
2152    default:
2153      // The physreg itself is dead, so we have to use it as an <undef>.
2154      isKill = false;
2155      isUndef = true;
2156      break;
2157    }
2158  } else {
2159    // Virtual register of the wrong class, we have to create a temporary 64-bit
2160    // vreg to feed into the LEA.
2161    NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2162    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2163            get(TargetOpcode::COPY))
2164      .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2165        .addOperand(Src);
2166
2167    // Which is obviously going to be dead after we're done with it.
2168    isKill = true;
2169    isUndef = false;
2170  }
2171
2172  // We've set all the parameters without issue.
2173  return true;
2174}
2175
2176/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
2177/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2178/// to a 32-bit superregister and then truncating back down to a 16-bit
2179/// subregister.
2180MachineInstr *
2181X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2182                                           MachineFunction::iterator &MFI,
2183                                           MachineBasicBlock::iterator &MBBI,
2184                                           LiveVariables *LV) const {
2185  MachineInstr *MI = MBBI;
2186  unsigned Dest = MI->getOperand(0).getReg();
2187  unsigned Src = MI->getOperand(1).getReg();
2188  bool isDead = MI->getOperand(0).isDead();
2189  bool isKill = MI->getOperand(1).isKill();
2190
2191  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2192  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2193  unsigned Opc, leaInReg;
2194  if (Subtarget.is64Bit()) {
2195    Opc = X86::LEA64_32r;
2196    leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2197  } else {
2198    Opc = X86::LEA32r;
2199    leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2200  }
2201
2202  // Build and insert into an implicit UNDEF value. This is OK because
2203  // well be shifting and then extracting the lower 16-bits.
2204  // This has the potential to cause partial register stall. e.g.
2205  //   movw    (%rbp,%rcx,2), %dx
2206  //   leal    -65(%rdx), %esi
2207  // But testing has shown this *does* help performance in 64-bit mode (at
2208  // least on modern x86 machines).
2209  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2210  MachineInstr *InsMI =
2211    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2212    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2213    .addReg(Src, getKillRegState(isKill));
2214
2215  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2216                                    get(Opc), leaOutReg);
2217  switch (MIOpc) {
2218  default: llvm_unreachable("Unreachable!");
2219  case X86::SHL16ri: {
2220    unsigned ShAmt = MI->getOperand(2).getImm();
2221    MIB.addReg(0).addImm(1 << ShAmt)
2222       .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2223    break;
2224  }
2225  case X86::INC16r:
2226    addRegOffset(MIB, leaInReg, true, 1);
2227    break;
2228  case X86::DEC16r:
2229    addRegOffset(MIB, leaInReg, true, -1);
2230    break;
2231  case X86::ADD16ri:
2232  case X86::ADD16ri8:
2233  case X86::ADD16ri_DB:
2234  case X86::ADD16ri8_DB:
2235    addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2236    break;
2237  case X86::ADD16rr:
2238  case X86::ADD16rr_DB: {
2239    unsigned Src2 = MI->getOperand(2).getReg();
2240    bool isKill2 = MI->getOperand(2).isKill();
2241    unsigned leaInReg2 = 0;
2242    MachineInstr *InsMI2 = nullptr;
2243    if (Src == Src2) {
2244      // ADD16rr %reg1028<kill>, %reg1028
2245      // just a single insert_subreg.
2246      addRegReg(MIB, leaInReg, true, leaInReg, false);
2247    } else {
2248      if (Subtarget.is64Bit())
2249        leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2250      else
2251        leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2252      // Build and insert into an implicit UNDEF value. This is OK because
2253      // well be shifting and then extracting the lower 16-bits.
2254      BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2255      InsMI2 =
2256        BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2257        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2258        .addReg(Src2, getKillRegState(isKill2));
2259      addRegReg(MIB, leaInReg, true, leaInReg2, true);
2260    }
2261    if (LV && isKill2 && InsMI2)
2262      LV->replaceKillInstruction(Src2, MI, InsMI2);
2263    break;
2264  }
2265  }
2266
2267  MachineInstr *NewMI = MIB;
2268  MachineInstr *ExtMI =
2269    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2270    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2271    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2272
2273  if (LV) {
2274    // Update live variables
2275    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2276    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2277    if (isKill)
2278      LV->replaceKillInstruction(Src, MI, InsMI);
2279    if (isDead)
2280      LV->replaceKillInstruction(Dest, MI, ExtMI);
2281  }
2282
2283  return ExtMI;
2284}
2285
2286/// convertToThreeAddress - This method must be implemented by targets that
2287/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2288/// may be able to convert a two-address instruction into a true
2289/// three-address instruction on demand.  This allows the X86 target (for
2290/// example) to convert ADD and SHL instructions into LEA instructions if they
2291/// would require register copies due to two-addressness.
2292///
2293/// This method returns a null pointer if the transformation cannot be
2294/// performed, otherwise it returns the new instruction.
2295///
2296MachineInstr *
2297X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2298                                    MachineBasicBlock::iterator &MBBI,
2299                                    LiveVariables *LV) const {
2300  MachineInstr *MI = MBBI;
2301
2302  // The following opcodes also sets the condition code register(s). Only
2303  // convert them to equivalent lea if the condition code register def's
2304  // are dead!
2305  if (hasLiveCondCodeDef(MI))
2306    return nullptr;
2307
2308  MachineFunction &MF = *MI->getParent()->getParent();
2309  // All instructions input are two-addr instructions.  Get the known operands.
2310  const MachineOperand &Dest = MI->getOperand(0);
2311  const MachineOperand &Src = MI->getOperand(1);
2312
2313  MachineInstr *NewMI = nullptr;
2314  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2315  // we have better subtarget support, enable the 16-bit LEA generation here.
2316  // 16-bit LEA is also slow on Core2.
2317  bool DisableLEA16 = true;
2318  bool is64Bit = Subtarget.is64Bit();
2319
2320  unsigned MIOpc = MI->getOpcode();
2321  switch (MIOpc) {
2322  default: return nullptr;
2323  case X86::SHL64ri: {
2324    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2325    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2326    if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2327
2328    // LEA can't handle RSP.
2329    if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2330        !MF.getRegInfo().constrainRegClass(Src.getReg(),
2331                                           &X86::GR64_NOSPRegClass))
2332      return nullptr;
2333
2334    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2335      .addOperand(Dest)
2336      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2337    break;
2338  }
2339  case X86::SHL32ri: {
2340    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2341    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2342    if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2343
2344    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2345
2346    // LEA can't handle ESP.
2347    bool isKill, isUndef;
2348    unsigned SrcReg;
2349    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2350    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2351                        SrcReg, isKill, isUndef, ImplicitOp))
2352      return nullptr;
2353
2354    MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2355      .addOperand(Dest)
2356      .addReg(0).addImm(1 << ShAmt)
2357      .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2358      .addImm(0).addReg(0);
2359    if (ImplicitOp.getReg() != 0)
2360      MIB.addOperand(ImplicitOp);
2361    NewMI = MIB;
2362
2363    break;
2364  }
2365  case X86::SHL16ri: {
2366    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2367    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2368    if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2369
2370    if (DisableLEA16)
2371      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2372    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2373      .addOperand(Dest)
2374      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2375    break;
2376  }
2377  case X86::INC64r:
2378  case X86::INC32r: {
2379    assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2380    unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2381      : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2382    bool isKill, isUndef;
2383    unsigned SrcReg;
2384    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2385    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2386                        SrcReg, isKill, isUndef, ImplicitOp))
2387      return nullptr;
2388
2389    MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2390        .addOperand(Dest)
2391        .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2392    if (ImplicitOp.getReg() != 0)
2393      MIB.addOperand(ImplicitOp);
2394
2395    NewMI = addOffset(MIB, 1);
2396    break;
2397  }
2398  case X86::INC16r:
2399    if (DisableLEA16)
2400      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2401                     : nullptr;
2402    assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2403    NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2404                      .addOperand(Dest).addOperand(Src), 1);
2405    break;
2406  case X86::DEC64r:
2407  case X86::DEC32r: {
2408    assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2409    unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2410      : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2411
2412    bool isKill, isUndef;
2413    unsigned SrcReg;
2414    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2415    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2416                        SrcReg, isKill, isUndef, ImplicitOp))
2417      return nullptr;
2418
2419    MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2420        .addOperand(Dest)
2421        .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2422    if (ImplicitOp.getReg() != 0)
2423      MIB.addOperand(ImplicitOp);
2424
2425    NewMI = addOffset(MIB, -1);
2426
2427    break;
2428  }
2429  case X86::DEC16r:
2430    if (DisableLEA16)
2431      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2432                     : nullptr;
2433    assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2434    NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2435                      .addOperand(Dest).addOperand(Src), -1);
2436    break;
2437  case X86::ADD64rr:
2438  case X86::ADD64rr_DB:
2439  case X86::ADD32rr:
2440  case X86::ADD32rr_DB: {
2441    assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2442    unsigned Opc;
2443    if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2444      Opc = X86::LEA64r;
2445    else
2446      Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2447
2448    bool isKill, isUndef;
2449    unsigned SrcReg;
2450    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2451    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2452                        SrcReg, isKill, isUndef, ImplicitOp))
2453      return nullptr;
2454
2455    const MachineOperand &Src2 = MI->getOperand(2);
2456    bool isKill2, isUndef2;
2457    unsigned SrcReg2;
2458    MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2459    if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2460                        SrcReg2, isKill2, isUndef2, ImplicitOp2))
2461      return nullptr;
2462
2463    MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2464      .addOperand(Dest);
2465    if (ImplicitOp.getReg() != 0)
2466      MIB.addOperand(ImplicitOp);
2467    if (ImplicitOp2.getReg() != 0)
2468      MIB.addOperand(ImplicitOp2);
2469
2470    NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2471
2472    // Preserve undefness of the operands.
2473    NewMI->getOperand(1).setIsUndef(isUndef);
2474    NewMI->getOperand(3).setIsUndef(isUndef2);
2475
2476    if (LV && Src2.isKill())
2477      LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2478    break;
2479  }
2480  case X86::ADD16rr:
2481  case X86::ADD16rr_DB: {
2482    if (DisableLEA16)
2483      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2484                     : nullptr;
2485    assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2486    unsigned Src2 = MI->getOperand(2).getReg();
2487    bool isKill2 = MI->getOperand(2).isKill();
2488    NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2489                      .addOperand(Dest),
2490                      Src.getReg(), Src.isKill(), Src2, isKill2);
2491
2492    // Preserve undefness of the operands.
2493    bool isUndef = MI->getOperand(1).isUndef();
2494    bool isUndef2 = MI->getOperand(2).isUndef();
2495    NewMI->getOperand(1).setIsUndef(isUndef);
2496    NewMI->getOperand(3).setIsUndef(isUndef2);
2497
2498    if (LV && isKill2)
2499      LV->replaceKillInstruction(Src2, MI, NewMI);
2500    break;
2501  }
2502  case X86::ADD64ri32:
2503  case X86::ADD64ri8:
2504  case X86::ADD64ri32_DB:
2505  case X86::ADD64ri8_DB:
2506    assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2507    NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2508                      .addOperand(Dest).addOperand(Src),
2509                      MI->getOperand(2).getImm());
2510    break;
2511  case X86::ADD32ri:
2512  case X86::ADD32ri8:
2513  case X86::ADD32ri_DB:
2514  case X86::ADD32ri8_DB: {
2515    assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2516    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2517
2518    bool isKill, isUndef;
2519    unsigned SrcReg;
2520    MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2521    if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2522                        SrcReg, isKill, isUndef, ImplicitOp))
2523      return nullptr;
2524
2525    MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2526        .addOperand(Dest)
2527        .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2528    if (ImplicitOp.getReg() != 0)
2529      MIB.addOperand(ImplicitOp);
2530
2531    NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2532    break;
2533  }
2534  case X86::ADD16ri:
2535  case X86::ADD16ri8:
2536  case X86::ADD16ri_DB:
2537  case X86::ADD16ri8_DB:
2538    if (DisableLEA16)
2539      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2540                     : nullptr;
2541    assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2542    NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2543                      .addOperand(Dest).addOperand(Src),
2544                      MI->getOperand(2).getImm());
2545    break;
2546  }
2547
2548  if (!NewMI) return nullptr;
2549
2550  if (LV) {  // Update live variables
2551    if (Src.isKill())
2552      LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2553    if (Dest.isDead())
2554      LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2555  }
2556
2557  MFI->insert(MBBI, NewMI);          // Insert the new inst
2558  return NewMI;
2559}
2560
2561/// commuteInstruction - We have a few instructions that must be hacked on to
2562/// commute them.
2563///
2564MachineInstr *
2565X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2566  switch (MI->getOpcode()) {
2567  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2568  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2569  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2570  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2571  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2572  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2573    unsigned Opc;
2574    unsigned Size;
2575    switch (MI->getOpcode()) {
2576    default: llvm_unreachable("Unreachable!");
2577    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2578    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2579    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2580    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2581    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2582    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2583    }
2584    unsigned Amt = MI->getOperand(3).getImm();
2585    if (NewMI) {
2586      MachineFunction &MF = *MI->getParent()->getParent();
2587      MI = MF.CloneMachineInstr(MI);
2588      NewMI = false;
2589    }
2590    MI->setDesc(get(Opc));
2591    MI->getOperand(3).setImm(Size-Amt);
2592    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2593  }
2594  case X86::BLENDPDrri:
2595  case X86::BLENDPSrri:
2596  case X86::PBLENDWrri:
2597  case X86::VBLENDPDrri:
2598  case X86::VBLENDPSrri:
2599  case X86::VBLENDPDYrri:
2600  case X86::VBLENDPSYrri:
2601  case X86::VPBLENDDrri:
2602  case X86::VPBLENDWrri:
2603  case X86::VPBLENDDYrri:
2604  case X86::VPBLENDWYrri:{
2605    unsigned Mask;
2606    switch (MI->getOpcode()) {
2607    default: llvm_unreachable("Unreachable!");
2608    case X86::BLENDPDrri:    Mask = 0x03; break;
2609    case X86::BLENDPSrri:    Mask = 0x0F; break;
2610    case X86::PBLENDWrri:    Mask = 0xFF; break;
2611    case X86::VBLENDPDrri:   Mask = 0x03; break;
2612    case X86::VBLENDPSrri:   Mask = 0x0F; break;
2613    case X86::VBLENDPDYrri:  Mask = 0x0F; break;
2614    case X86::VBLENDPSYrri:  Mask = 0xFF; break;
2615    case X86::VPBLENDDrri:   Mask = 0x0F; break;
2616    case X86::VPBLENDWrri:   Mask = 0xFF; break;
2617    case X86::VPBLENDDYrri:  Mask = 0xFF; break;
2618    case X86::VPBLENDWYrri:  Mask = 0xFF; break;
2619    }
2620    // Only the least significant bits of Imm are used.
2621    unsigned Imm = MI->getOperand(3).getImm() & Mask;
2622    if (NewMI) {
2623      MachineFunction &MF = *MI->getParent()->getParent();
2624      MI = MF.CloneMachineInstr(MI);
2625      NewMI = false;
2626    }
2627    MI->getOperand(3).setImm(Mask ^ Imm);
2628    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2629  }
2630  case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2631  case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2632  case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2633  case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2634  case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2635  case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2636  case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2637  case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2638  case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2639  case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2640  case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2641  case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2642  case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2643  case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2644  case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2645  case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2646    unsigned Opc;
2647    switch (MI->getOpcode()) {
2648    default: llvm_unreachable("Unreachable!");
2649    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2650    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2651    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2652    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2653    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2654    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2655    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2656    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2657    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2658    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2659    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2660    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2661    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2662    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2663    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2664    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2665    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2666    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2667    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2668    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2669    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2670    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2671    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2672    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2673    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2674    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2675    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2676    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2677    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2678    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2679    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2680    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2681    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2682    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2683    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2684    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2685    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2686    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2687    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2688    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2689    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2690    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2691    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2692    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2693    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2694    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2695    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2696    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2697    }
2698    if (NewMI) {
2699      MachineFunction &MF = *MI->getParent()->getParent();
2700      MI = MF.CloneMachineInstr(MI);
2701      NewMI = false;
2702    }
2703    MI->setDesc(get(Opc));
2704    // Fallthrough intended.
2705  }
2706  default:
2707    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2708  }
2709}
2710
2711bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2712                                         unsigned &SrcOpIdx2) const {
2713  switch (MI->getOpcode()) {
2714    case X86::BLENDPDrri:
2715    case X86::BLENDPSrri:
2716    case X86::PBLENDWrri:
2717    case X86::VBLENDPDrri:
2718    case X86::VBLENDPSrri:
2719    case X86::VBLENDPDYrri:
2720    case X86::VBLENDPSYrri:
2721    case X86::VPBLENDDrri:
2722    case X86::VPBLENDDYrri:
2723    case X86::VPBLENDWrri:
2724    case X86::VPBLENDWYrri:
2725      SrcOpIdx1 = 1;
2726      SrcOpIdx2 = 2;
2727      return true;
2728    case X86::VFMADDPDr231r:
2729    case X86::VFMADDPSr231r:
2730    case X86::VFMADDSDr231r:
2731    case X86::VFMADDSSr231r:
2732    case X86::VFMSUBPDr231r:
2733    case X86::VFMSUBPSr231r:
2734    case X86::VFMSUBSDr231r:
2735    case X86::VFMSUBSSr231r:
2736    case X86::VFNMADDPDr231r:
2737    case X86::VFNMADDPSr231r:
2738    case X86::VFNMADDSDr231r:
2739    case X86::VFNMADDSSr231r:
2740    case X86::VFNMSUBPDr231r:
2741    case X86::VFNMSUBPSr231r:
2742    case X86::VFNMSUBSDr231r:
2743    case X86::VFNMSUBSSr231r:
2744    case X86::VFMADDPDr231rY:
2745    case X86::VFMADDPSr231rY:
2746    case X86::VFMSUBPDr231rY:
2747    case X86::VFMSUBPSr231rY:
2748    case X86::VFNMADDPDr231rY:
2749    case X86::VFNMADDPSr231rY:
2750    case X86::VFNMSUBPDr231rY:
2751    case X86::VFNMSUBPSr231rY:
2752      SrcOpIdx1 = 2;
2753      SrcOpIdx2 = 3;
2754      return true;
2755    default:
2756      return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2757  }
2758}
2759
2760static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2761  switch (BrOpc) {
2762  default: return X86::COND_INVALID;
2763  case X86::JE_1:  return X86::COND_E;
2764  case X86::JNE_1: return X86::COND_NE;
2765  case X86::JL_1:  return X86::COND_L;
2766  case X86::JLE_1: return X86::COND_LE;
2767  case X86::JG_1:  return X86::COND_G;
2768  case X86::JGE_1: return X86::COND_GE;
2769  case X86::JB_1:  return X86::COND_B;
2770  case X86::JBE_1: return X86::COND_BE;
2771  case X86::JA_1:  return X86::COND_A;
2772  case X86::JAE_1: return X86::COND_AE;
2773  case X86::JS_1:  return X86::COND_S;
2774  case X86::JNS_1: return X86::COND_NS;
2775  case X86::JP_1:  return X86::COND_P;
2776  case X86::JNP_1: return X86::COND_NP;
2777  case X86::JO_1:  return X86::COND_O;
2778  case X86::JNO_1: return X86::COND_NO;
2779  }
2780}
2781
2782/// getCondFromSETOpc - return condition code of a SET opcode.
2783static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2784  switch (Opc) {
2785  default: return X86::COND_INVALID;
2786  case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2787  case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2788  case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2789  case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2790  case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2791  case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2792  case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2793  case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2794  case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2795  case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2796  case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2797  case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2798  case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2799  case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2800  case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2801  case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2802  }
2803}
2804
2805/// getCondFromCmovOpc - return condition code of a CMov opcode.
2806X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2807  switch (Opc) {
2808  default: return X86::COND_INVALID;
2809  case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2810  case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2811    return X86::COND_A;
2812  case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2813  case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2814    return X86::COND_AE;
2815  case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2816  case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2817    return X86::COND_B;
2818  case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2819  case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2820    return X86::COND_BE;
2821  case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2822  case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2823    return X86::COND_E;
2824  case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2825  case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2826    return X86::COND_G;
2827  case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2828  case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2829    return X86::COND_GE;
2830  case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2831  case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2832    return X86::COND_L;
2833  case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2834  case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2835    return X86::COND_LE;
2836  case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2837  case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2838    return X86::COND_NE;
2839  case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2840  case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2841    return X86::COND_NO;
2842  case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2843  case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2844    return X86::COND_NP;
2845  case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2846  case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2847    return X86::COND_NS;
2848  case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2849  case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2850    return X86::COND_O;
2851  case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2852  case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2853    return X86::COND_P;
2854  case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2855  case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2856    return X86::COND_S;
2857  }
2858}
2859
2860unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2861  switch (CC) {
2862  default: llvm_unreachable("Illegal condition code!");
2863  case X86::COND_E:  return X86::JE_1;
2864  case X86::COND_NE: return X86::JNE_1;
2865  case X86::COND_L:  return X86::JL_1;
2866  case X86::COND_LE: return X86::JLE_1;
2867  case X86::COND_G:  return X86::JG_1;
2868  case X86::COND_GE: return X86::JGE_1;
2869  case X86::COND_B:  return X86::JB_1;
2870  case X86::COND_BE: return X86::JBE_1;
2871  case X86::COND_A:  return X86::JA_1;
2872  case X86::COND_AE: return X86::JAE_1;
2873  case X86::COND_S:  return X86::JS_1;
2874  case X86::COND_NS: return X86::JNS_1;
2875  case X86::COND_P:  return X86::JP_1;
2876  case X86::COND_NP: return X86::JNP_1;
2877  case X86::COND_O:  return X86::JO_1;
2878  case X86::COND_NO: return X86::JNO_1;
2879  }
2880}
2881
2882/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2883/// e.g. turning COND_E to COND_NE.
2884X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2885  switch (CC) {
2886  default: llvm_unreachable("Illegal condition code!");
2887  case X86::COND_E:  return X86::COND_NE;
2888  case X86::COND_NE: return X86::COND_E;
2889  case X86::COND_L:  return X86::COND_GE;
2890  case X86::COND_LE: return X86::COND_G;
2891  case X86::COND_G:  return X86::COND_LE;
2892  case X86::COND_GE: return X86::COND_L;
2893  case X86::COND_B:  return X86::COND_AE;
2894  case X86::COND_BE: return X86::COND_A;
2895  case X86::COND_A:  return X86::COND_BE;
2896  case X86::COND_AE: return X86::COND_B;
2897  case X86::COND_S:  return X86::COND_NS;
2898  case X86::COND_NS: return X86::COND_S;
2899  case X86::COND_P:  return X86::COND_NP;
2900  case X86::COND_NP: return X86::COND_P;
2901  case X86::COND_O:  return X86::COND_NO;
2902  case X86::COND_NO: return X86::COND_O;
2903  }
2904}
2905
2906/// getSwappedCondition - assume the flags are set by MI(a,b), return
2907/// the condition code if we modify the instructions such that flags are
2908/// set by MI(b,a).
2909static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2910  switch (CC) {
2911  default: return X86::COND_INVALID;
2912  case X86::COND_E:  return X86::COND_E;
2913  case X86::COND_NE: return X86::COND_NE;
2914  case X86::COND_L:  return X86::COND_G;
2915  case X86::COND_LE: return X86::COND_GE;
2916  case X86::COND_G:  return X86::COND_L;
2917  case X86::COND_GE: return X86::COND_LE;
2918  case X86::COND_B:  return X86::COND_A;
2919  case X86::COND_BE: return X86::COND_AE;
2920  case X86::COND_A:  return X86::COND_B;
2921  case X86::COND_AE: return X86::COND_BE;
2922  }
2923}
2924
2925/// getSETFromCond - Return a set opcode for the given condition and
2926/// whether it has memory operand.
2927unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2928  static const uint16_t Opc[16][2] = {
2929    { X86::SETAr,  X86::SETAm  },
2930    { X86::SETAEr, X86::SETAEm },
2931    { X86::SETBr,  X86::SETBm  },
2932    { X86::SETBEr, X86::SETBEm },
2933    { X86::SETEr,  X86::SETEm  },
2934    { X86::SETGr,  X86::SETGm  },
2935    { X86::SETGEr, X86::SETGEm },
2936    { X86::SETLr,  X86::SETLm  },
2937    { X86::SETLEr, X86::SETLEm },
2938    { X86::SETNEr, X86::SETNEm },
2939    { X86::SETNOr, X86::SETNOm },
2940    { X86::SETNPr, X86::SETNPm },
2941    { X86::SETNSr, X86::SETNSm },
2942    { X86::SETOr,  X86::SETOm  },
2943    { X86::SETPr,  X86::SETPm  },
2944    { X86::SETSr,  X86::SETSm  }
2945  };
2946
2947  assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2948  return Opc[CC][HasMemoryOperand ? 1 : 0];
2949}
2950
2951/// getCMovFromCond - Return a cmov opcode for the given condition,
2952/// register size in bytes, and operand type.
2953unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2954                              bool HasMemoryOperand) {
2955  static const uint16_t Opc[32][3] = {
2956    { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2957    { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2958    { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2959    { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2960    { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2961    { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2962    { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2963    { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2964    { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2965    { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2966    { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2967    { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2968    { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2969    { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2970    { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2971    { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2972    { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2973    { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2974    { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2975    { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2976    { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2977    { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2978    { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2979    { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2980    { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2981    { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2982    { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2983    { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2984    { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2985    { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2986    { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2987    { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2988  };
2989
2990  assert(CC < 16 && "Can only handle standard cond codes");
2991  unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2992  switch(RegBytes) {
2993  default: llvm_unreachable("Illegal register size!");
2994  case 2: return Opc[Idx][0];
2995  case 4: return Opc[Idx][1];
2996  case 8: return Opc[Idx][2];
2997  }
2998}
2999
3000bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3001  if (!MI->isTerminator()) return false;
3002
3003  // Conditional branch is a special case.
3004  if (MI->isBranch() && !MI->isBarrier())
3005    return true;
3006  if (!MI->isPredicable())
3007    return true;
3008  return !isPredicated(MI);
3009}
3010
3011bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3012                                 MachineBasicBlock *&TBB,
3013                                 MachineBasicBlock *&FBB,
3014                                 SmallVectorImpl<MachineOperand> &Cond,
3015                                 bool AllowModify) const {
3016  // Start from the bottom of the block and work up, examining the
3017  // terminator instructions.
3018  MachineBasicBlock::iterator I = MBB.end();
3019  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3020  while (I != MBB.begin()) {
3021    --I;
3022    if (I->isDebugValue())
3023      continue;
3024
3025    // Working from the bottom, when we see a non-terminator instruction, we're
3026    // done.
3027    if (!isUnpredicatedTerminator(I))
3028      break;
3029
3030    // A terminator that isn't a branch can't easily be handled by this
3031    // analysis.
3032    if (!I->isBranch())
3033      return true;
3034
3035    // Handle unconditional branches.
3036    if (I->getOpcode() == X86::JMP_1) {
3037      UnCondBrIter = I;
3038
3039      if (!AllowModify) {
3040        TBB = I->getOperand(0).getMBB();
3041        continue;
3042      }
3043
3044      // If the block has any instructions after a JMP, delete them.
3045      while (std::next(I) != MBB.end())
3046        std::next(I)->eraseFromParent();
3047
3048      Cond.clear();
3049      FBB = nullptr;
3050
3051      // Delete the JMP if it's equivalent to a fall-through.
3052      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3053        TBB = nullptr;
3054        I->eraseFromParent();
3055        I = MBB.end();
3056        UnCondBrIter = MBB.end();
3057        continue;
3058      }
3059
3060      // TBB is used to indicate the unconditional destination.
3061      TBB = I->getOperand(0).getMBB();
3062      continue;
3063    }
3064
3065    // Handle conditional branches.
3066    X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3067    if (BranchCode == X86::COND_INVALID)
3068      return true;  // Can't handle indirect branch.
3069
3070    // Working from the bottom, handle the first conditional branch.
3071    if (Cond.empty()) {
3072      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3073      if (AllowModify && UnCondBrIter != MBB.end() &&
3074          MBB.isLayoutSuccessor(TargetBB)) {
3075        // If we can modify the code and it ends in something like:
3076        //
3077        //     jCC L1
3078        //     jmp L2
3079        //   L1:
3080        //     ...
3081        //   L2:
3082        //
3083        // Then we can change this to:
3084        //
3085        //     jnCC L2
3086        //   L1:
3087        //     ...
3088        //   L2:
3089        //
3090        // Which is a bit more efficient.
3091        // We conditionally jump to the fall-through block.
3092        BranchCode = GetOppositeBranchCondition(BranchCode);
3093        unsigned JNCC = GetCondBranchFromCond(BranchCode);
3094        MachineBasicBlock::iterator OldInst = I;
3095
3096        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3097          .addMBB(UnCondBrIter->getOperand(0).getMBB());
3098        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3099          .addMBB(TargetBB);
3100
3101        OldInst->eraseFromParent();
3102        UnCondBrIter->eraseFromParent();
3103
3104        // Restart the analysis.
3105        UnCondBrIter = MBB.end();
3106        I = MBB.end();
3107        continue;
3108      }
3109
3110      FBB = TBB;
3111      TBB = I->getOperand(0).getMBB();
3112      Cond.push_back(MachineOperand::CreateImm(BranchCode));
3113      continue;
3114    }
3115
3116    // Handle subsequent conditional branches. Only handle the case where all
3117    // conditional branches branch to the same destination and their condition
3118    // opcodes fit one of the special multi-branch idioms.
3119    assert(Cond.size() == 1);
3120    assert(TBB);
3121
3122    // Only handle the case where all conditional branches branch to the same
3123    // destination.
3124    if (TBB != I->getOperand(0).getMBB())
3125      return true;
3126
3127    // If the conditions are the same, we can leave them alone.
3128    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3129    if (OldBranchCode == BranchCode)
3130      continue;
3131
3132    // If they differ, see if they fit one of the known patterns. Theoretically,
3133    // we could handle more patterns here, but we shouldn't expect to see them
3134    // if instruction selection has done a reasonable job.
3135    if ((OldBranchCode == X86::COND_NP &&
3136         BranchCode == X86::COND_E) ||
3137        (OldBranchCode == X86::COND_E &&
3138         BranchCode == X86::COND_NP))
3139      BranchCode = X86::COND_NP_OR_E;
3140    else if ((OldBranchCode == X86::COND_P &&
3141              BranchCode == X86::COND_NE) ||
3142             (OldBranchCode == X86::COND_NE &&
3143              BranchCode == X86::COND_P))
3144      BranchCode = X86::COND_NE_OR_P;
3145    else
3146      return true;
3147
3148    // Update the MachineOperand.
3149    Cond[0].setImm(BranchCode);
3150  }
3151
3152  return false;
3153}
3154
3155unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3156  MachineBasicBlock::iterator I = MBB.end();
3157  unsigned Count = 0;
3158
3159  while (I != MBB.begin()) {
3160    --I;
3161    if (I->isDebugValue())
3162      continue;
3163    if (I->getOpcode() != X86::JMP_1 &&
3164        getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3165      break;
3166    // Remove the branch.
3167    I->eraseFromParent();
3168    I = MBB.end();
3169    ++Count;
3170  }
3171
3172  return Count;
3173}
3174
3175unsigned
3176X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3177                           MachineBasicBlock *FBB,
3178                           const SmallVectorImpl<MachineOperand> &Cond,
3179                           DebugLoc DL) const {
3180  // Shouldn't be a fall through.
3181  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3182  assert((Cond.size() == 1 || Cond.size() == 0) &&
3183         "X86 branch conditions have one component!");
3184
3185  if (Cond.empty()) {
3186    // Unconditional branch?
3187    assert(!FBB && "Unconditional branch with multiple successors!");
3188    BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3189    return 1;
3190  }
3191
3192  // Conditional branch.
3193  unsigned Count = 0;
3194  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3195  switch (CC) {
3196  case X86::COND_NP_OR_E:
3197    // Synthesize NP_OR_E with two branches.
3198    BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
3199    ++Count;
3200    BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
3201    ++Count;
3202    break;
3203  case X86::COND_NE_OR_P:
3204    // Synthesize NE_OR_P with two branches.
3205    BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
3206    ++Count;
3207    BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
3208    ++Count;
3209    break;
3210  default: {
3211    unsigned Opc = GetCondBranchFromCond(CC);
3212    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3213    ++Count;
3214  }
3215  }
3216  if (FBB) {
3217    // Two-way Conditional branch. Insert the second branch.
3218    BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3219    ++Count;
3220  }
3221  return Count;
3222}
3223
3224bool X86InstrInfo::
3225canInsertSelect(const MachineBasicBlock &MBB,
3226                const SmallVectorImpl<MachineOperand> &Cond,
3227                unsigned TrueReg, unsigned FalseReg,
3228                int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3229  // Not all subtargets have cmov instructions.
3230  if (!Subtarget.hasCMov())
3231    return false;
3232  if (Cond.size() != 1)
3233    return false;
3234  // We cannot do the composite conditions, at least not in SSA form.
3235  if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3236    return false;
3237
3238  // Check register classes.
3239  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3240  const TargetRegisterClass *RC =
3241    RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3242  if (!RC)
3243    return false;
3244
3245  // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3246  if (X86::GR16RegClass.hasSubClassEq(RC) ||
3247      X86::GR32RegClass.hasSubClassEq(RC) ||
3248      X86::GR64RegClass.hasSubClassEq(RC)) {
3249    // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3250    // Bridge. Probably Ivy Bridge as well.
3251    CondCycles = 2;
3252    TrueCycles = 2;
3253    FalseCycles = 2;
3254    return true;
3255  }
3256
3257  // Can't do vectors.
3258  return false;
3259}
3260
3261void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3262                                MachineBasicBlock::iterator I, DebugLoc DL,
3263                                unsigned DstReg,
3264                                const SmallVectorImpl<MachineOperand> &Cond,
3265                                unsigned TrueReg, unsigned FalseReg) const {
3266   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3267   assert(Cond.size() == 1 && "Invalid Cond array");
3268   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3269                                  MRI.getRegClass(DstReg)->getSize(),
3270                                  false/*HasMemoryOperand*/);
3271   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3272}
3273
3274/// isHReg - Test if the given register is a physical h register.
3275static bool isHReg(unsigned Reg) {
3276  return X86::GR8_ABCD_HRegClass.contains(Reg);
3277}
3278
3279// Try and copy between VR128/VR64 and GR64 registers.
3280static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3281                                        const X86Subtarget &Subtarget) {
3282
3283  // SrcReg(VR128) -> DestReg(GR64)
3284  // SrcReg(VR64)  -> DestReg(GR64)
3285  // SrcReg(GR64)  -> DestReg(VR128)
3286  // SrcReg(GR64)  -> DestReg(VR64)
3287
3288  bool HasAVX = Subtarget.hasAVX();
3289  bool HasAVX512 = Subtarget.hasAVX512();
3290  if (X86::GR64RegClass.contains(DestReg)) {
3291    if (X86::VR128XRegClass.contains(SrcReg))
3292      // Copy from a VR128 register to a GR64 register.
3293      return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3294                                               X86::MOVPQIto64rr);
3295    if (X86::VR64RegClass.contains(SrcReg))
3296      // Copy from a VR64 register to a GR64 register.
3297      return X86::MOVSDto64rr;
3298  } else if (X86::GR64RegClass.contains(SrcReg)) {
3299    // Copy from a GR64 register to a VR128 register.
3300    if (X86::VR128XRegClass.contains(DestReg))
3301      return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3302                                               X86::MOV64toPQIrr);
3303    // Copy from a GR64 register to a VR64 register.
3304    if (X86::VR64RegClass.contains(DestReg))
3305      return X86::MOV64toSDrr;
3306  }
3307
3308  // SrcReg(FR32) -> DestReg(GR32)
3309  // SrcReg(GR32) -> DestReg(FR32)
3310
3311  if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3312    // Copy from a FR32 register to a GR32 register.
3313    return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3314
3315  if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3316    // Copy from a GR32 register to a FR32 register.
3317    return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3318  return 0;
3319}
3320
3321inline static bool MaskRegClassContains(unsigned Reg) {
3322  return X86::VK8RegClass.contains(Reg) ||
3323         X86::VK16RegClass.contains(Reg) ||
3324         X86::VK32RegClass.contains(Reg) ||
3325         X86::VK64RegClass.contains(Reg) ||
3326         X86::VK1RegClass.contains(Reg);
3327}
3328static
3329unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3330  if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3331      X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3332      X86::VR512RegClass.contains(DestReg, SrcReg)) {
3333     DestReg = get512BitSuperRegister(DestReg);
3334     SrcReg = get512BitSuperRegister(SrcReg);
3335     return X86::VMOVAPSZrr;
3336  }
3337  if (MaskRegClassContains(DestReg) &&
3338      MaskRegClassContains(SrcReg))
3339    return X86::KMOVWkk;
3340  if (MaskRegClassContains(DestReg) &&
3341      (X86::GR32RegClass.contains(SrcReg) ||
3342       X86::GR16RegClass.contains(SrcReg) ||
3343       X86::GR8RegClass.contains(SrcReg))) {
3344    SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3345    return X86::KMOVWkr;
3346  }
3347  if ((X86::GR32RegClass.contains(DestReg) ||
3348       X86::GR16RegClass.contains(DestReg) ||
3349       X86::GR8RegClass.contains(DestReg)) &&
3350       MaskRegClassContains(SrcReg)) {
3351    DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3352    return X86::KMOVWrk;
3353  }
3354  return 0;
3355}
3356
3357void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3358                               MachineBasicBlock::iterator MI, DebugLoc DL,
3359                               unsigned DestReg, unsigned SrcReg,
3360                               bool KillSrc) const {
3361  // First deal with the normal symmetric copies.
3362  bool HasAVX = Subtarget.hasAVX();
3363  bool HasAVX512 = Subtarget.hasAVX512();
3364  unsigned Opc = 0;
3365  if (X86::GR64RegClass.contains(DestReg, SrcReg))
3366    Opc = X86::MOV64rr;
3367  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3368    Opc = X86::MOV32rr;
3369  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3370    Opc = X86::MOV16rr;
3371  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3372    // Copying to or from a physical H register on x86-64 requires a NOREX
3373    // move.  Otherwise use a normal move.
3374    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3375        Subtarget.is64Bit()) {
3376      Opc = X86::MOV8rr_NOREX;
3377      // Both operands must be encodable without an REX prefix.
3378      assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3379             "8-bit H register can not be copied outside GR8_NOREX");
3380    } else
3381      Opc = X86::MOV8rr;
3382  }
3383  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3384    Opc = X86::MMX_MOVQ64rr;
3385  else if (HasAVX512)
3386    Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3387  else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3388    Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3389  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3390    Opc = X86::VMOVAPSYrr;
3391  if (!Opc)
3392    Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3393
3394  if (Opc) {
3395    BuildMI(MBB, MI, DL, get(Opc), DestReg)
3396      .addReg(SrcReg, getKillRegState(KillSrc));
3397    return;
3398  }
3399
3400  // Moving EFLAGS to / from another register requires a push and a pop.
3401  // Notice that we have to adjust the stack if we don't want to clobber the
3402  // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3403  if (SrcReg == X86::EFLAGS) {
3404    if (X86::GR64RegClass.contains(DestReg)) {
3405      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3406      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3407      return;
3408    }
3409    if (X86::GR32RegClass.contains(DestReg)) {
3410      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3411      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3412      return;
3413    }
3414  }
3415  if (DestReg == X86::EFLAGS) {
3416    if (X86::GR64RegClass.contains(SrcReg)) {
3417      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3418        .addReg(SrcReg, getKillRegState(KillSrc));
3419      BuildMI(MBB, MI, DL, get(X86::POPF64));
3420      return;
3421    }
3422    if (X86::GR32RegClass.contains(SrcReg)) {
3423      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3424        .addReg(SrcReg, getKillRegState(KillSrc));
3425      BuildMI(MBB, MI, DL, get(X86::POPF32));
3426      return;
3427    }
3428  }
3429
3430  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3431               << " to " << RI.getName(DestReg) << '\n');
3432  llvm_unreachable("Cannot emit physreg copy instruction");
3433}
3434
3435static unsigned getLoadStoreRegOpcode(unsigned Reg,
3436                                      const TargetRegisterClass *RC,
3437                                      bool isStackAligned,
3438                                      const X86Subtarget &STI,
3439                                      bool load) {
3440  if (STI.hasAVX512()) {
3441    if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3442      X86::VK16RegClass.hasSubClassEq(RC))
3443      return load ? X86::KMOVWkm : X86::KMOVWmk;
3444    if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3445      return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3446    if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3447      return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3448    if (X86::VR512RegClass.hasSubClassEq(RC))
3449      return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3450  }
3451
3452  bool HasAVX = STI.hasAVX();
3453  switch (RC->getSize()) {
3454  default:
3455    llvm_unreachable("Unknown spill size");
3456  case 1:
3457    assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3458    if (STI.is64Bit())
3459      // Copying to or from a physical H register on x86-64 requires a NOREX
3460      // move.  Otherwise use a normal move.
3461      if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3462        return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3463    return load ? X86::MOV8rm : X86::MOV8mr;
3464  case 2:
3465    assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3466    return load ? X86::MOV16rm : X86::MOV16mr;
3467  case 4:
3468    if (X86::GR32RegClass.hasSubClassEq(RC))
3469      return load ? X86::MOV32rm : X86::MOV32mr;
3470    if (X86::FR32RegClass.hasSubClassEq(RC))
3471      return load ?
3472        (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3473        (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3474    if (X86::RFP32RegClass.hasSubClassEq(RC))
3475      return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3476    llvm_unreachable("Unknown 4-byte regclass");
3477  case 8:
3478    if (X86::GR64RegClass.hasSubClassEq(RC))
3479      return load ? X86::MOV64rm : X86::MOV64mr;
3480    if (X86::FR64RegClass.hasSubClassEq(RC))
3481      return load ?
3482        (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3483        (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3484    if (X86::VR64RegClass.hasSubClassEq(RC))
3485      return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3486    if (X86::RFP64RegClass.hasSubClassEq(RC))
3487      return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3488    llvm_unreachable("Unknown 8-byte regclass");
3489  case 10:
3490    assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3491    return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3492  case 16: {
3493    assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3494            X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3495    // If stack is realigned we can use aligned stores.
3496    if (isStackAligned)
3497      return load ?
3498        (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3499        (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3500    else
3501      return load ?
3502        (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3503        (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3504  }
3505  case 32:
3506    assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3507            X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3508    // If stack is realigned we can use aligned stores.
3509    if (isStackAligned)
3510      return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3511    else
3512      return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3513  case 64:
3514    assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3515    if (isStackAligned)
3516      return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3517    else
3518      return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3519  }
3520}
3521
3522static unsigned getStoreRegOpcode(unsigned SrcReg,
3523                                  const TargetRegisterClass *RC,
3524                                  bool isStackAligned,
3525                                  const X86Subtarget &STI) {
3526  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3527}
3528
3529
3530static unsigned getLoadRegOpcode(unsigned DestReg,
3531                                 const TargetRegisterClass *RC,
3532                                 bool isStackAligned,
3533                                 const X86Subtarget &STI) {
3534  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3535}
3536
3537void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3538                                       MachineBasicBlock::iterator MI,
3539                                       unsigned SrcReg, bool isKill, int FrameIdx,
3540                                       const TargetRegisterClass *RC,
3541                                       const TargetRegisterInfo *TRI) const {
3542  const MachineFunction &MF = *MBB.getParent();
3543  assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3544         "Stack slot too small for store");
3545  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3546  bool isAligned = (MF.getTarget()
3547                        .getSubtargetImpl()
3548                        ->getFrameLowering()
3549                        ->getStackAlignment() >= Alignment) ||
3550                   RI.canRealignStack(MF);
3551  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3552  DebugLoc DL = MBB.findDebugLoc(MI);
3553  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3554    .addReg(SrcReg, getKillRegState(isKill));
3555}
3556
3557void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3558                                  bool isKill,
3559                                  SmallVectorImpl<MachineOperand> &Addr,
3560                                  const TargetRegisterClass *RC,
3561                                  MachineInstr::mmo_iterator MMOBegin,
3562                                  MachineInstr::mmo_iterator MMOEnd,
3563                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3564  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3565  bool isAligned = MMOBegin != MMOEnd &&
3566                   (*MMOBegin)->getAlignment() >= Alignment;
3567  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3568  DebugLoc DL;
3569  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3570  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3571    MIB.addOperand(Addr[i]);
3572  MIB.addReg(SrcReg, getKillRegState(isKill));
3573  (*MIB).setMemRefs(MMOBegin, MMOEnd);
3574  NewMIs.push_back(MIB);
3575}
3576
3577
3578void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3579                                        MachineBasicBlock::iterator MI,
3580                                        unsigned DestReg, int FrameIdx,
3581                                        const TargetRegisterClass *RC,
3582                                        const TargetRegisterInfo *TRI) const {
3583  const MachineFunction &MF = *MBB.getParent();
3584  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3585  bool isAligned = (MF.getTarget()
3586                        .getSubtargetImpl()
3587                        ->getFrameLowering()
3588                        ->getStackAlignment() >= Alignment) ||
3589                   RI.canRealignStack(MF);
3590  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3591  DebugLoc DL = MBB.findDebugLoc(MI);
3592  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3593}
3594
3595void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3596                                 SmallVectorImpl<MachineOperand> &Addr,
3597                                 const TargetRegisterClass *RC,
3598                                 MachineInstr::mmo_iterator MMOBegin,
3599                                 MachineInstr::mmo_iterator MMOEnd,
3600                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3601  unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3602  bool isAligned = MMOBegin != MMOEnd &&
3603                   (*MMOBegin)->getAlignment() >= Alignment;
3604  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3605  DebugLoc DL;
3606  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3607  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3608    MIB.addOperand(Addr[i]);
3609  (*MIB).setMemRefs(MMOBegin, MMOEnd);
3610  NewMIs.push_back(MIB);
3611}
3612
3613bool X86InstrInfo::
3614analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3615               int &CmpMask, int &CmpValue) const {
3616  switch (MI->getOpcode()) {
3617  default: break;
3618  case X86::CMP64ri32:
3619  case X86::CMP64ri8:
3620  case X86::CMP32ri:
3621  case X86::CMP32ri8:
3622  case X86::CMP16ri:
3623  case X86::CMP16ri8:
3624  case X86::CMP8ri:
3625    SrcReg = MI->getOperand(0).getReg();
3626    SrcReg2 = 0;
3627    CmpMask = ~0;
3628    CmpValue = MI->getOperand(1).getImm();
3629    return true;
3630  // A SUB can be used to perform comparison.
3631  case X86::SUB64rm:
3632  case X86::SUB32rm:
3633  case X86::SUB16rm:
3634  case X86::SUB8rm:
3635    SrcReg = MI->getOperand(1).getReg();
3636    SrcReg2 = 0;
3637    CmpMask = ~0;
3638    CmpValue = 0;
3639    return true;
3640  case X86::SUB64rr:
3641  case X86::SUB32rr:
3642  case X86::SUB16rr:
3643  case X86::SUB8rr:
3644    SrcReg = MI->getOperand(1).getReg();
3645    SrcReg2 = MI->getOperand(2).getReg();
3646    CmpMask = ~0;
3647    CmpValue = 0;
3648    return true;
3649  case X86::SUB64ri32:
3650  case X86::SUB64ri8:
3651  case X86::SUB32ri:
3652  case X86::SUB32ri8:
3653  case X86::SUB16ri:
3654  case X86::SUB16ri8:
3655  case X86::SUB8ri:
3656    SrcReg = MI->getOperand(1).getReg();
3657    SrcReg2 = 0;
3658    CmpMask = ~0;
3659    CmpValue = MI->getOperand(2).getImm();
3660    return true;
3661  case X86::CMP64rr:
3662  case X86::CMP32rr:
3663  case X86::CMP16rr:
3664  case X86::CMP8rr:
3665    SrcReg = MI->getOperand(0).getReg();
3666    SrcReg2 = MI->getOperand(1).getReg();
3667    CmpMask = ~0;
3668    CmpValue = 0;
3669    return true;
3670  case X86::TEST8rr:
3671  case X86::TEST16rr:
3672  case X86::TEST32rr:
3673  case X86::TEST64rr:
3674    SrcReg = MI->getOperand(0).getReg();
3675    if (MI->getOperand(1).getReg() != SrcReg) return false;
3676    // Compare against zero.
3677    SrcReg2 = 0;
3678    CmpMask = ~0;
3679    CmpValue = 0;
3680    return true;
3681  }
3682  return false;
3683}
3684
3685/// isRedundantFlagInstr - check whether the first instruction, whose only
3686/// purpose is to update flags, can be made redundant.
3687/// CMPrr can be made redundant by SUBrr if the operands are the same.
3688/// This function can be extended later on.
3689/// SrcReg, SrcRegs: register operands for FlagI.
3690/// ImmValue: immediate for FlagI if it takes an immediate.
3691inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3692                                        unsigned SrcReg2, int ImmValue,
3693                                        MachineInstr *OI) {
3694  if (((FlagI->getOpcode() == X86::CMP64rr &&
3695        OI->getOpcode() == X86::SUB64rr) ||
3696       (FlagI->getOpcode() == X86::CMP32rr &&
3697        OI->getOpcode() == X86::SUB32rr)||
3698       (FlagI->getOpcode() == X86::CMP16rr &&
3699        OI->getOpcode() == X86::SUB16rr)||
3700       (FlagI->getOpcode() == X86::CMP8rr &&
3701        OI->getOpcode() == X86::SUB8rr)) &&
3702      ((OI->getOperand(1).getReg() == SrcReg &&
3703        OI->getOperand(2).getReg() == SrcReg2) ||
3704       (OI->getOperand(1).getReg() == SrcReg2 &&
3705        OI->getOperand(2).getReg() == SrcReg)))
3706    return true;
3707
3708  if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3709        OI->getOpcode() == X86::SUB64ri32) ||
3710       (FlagI->getOpcode() == X86::CMP64ri8 &&
3711        OI->getOpcode() == X86::SUB64ri8) ||
3712       (FlagI->getOpcode() == X86::CMP32ri &&
3713        OI->getOpcode() == X86::SUB32ri) ||
3714       (FlagI->getOpcode() == X86::CMP32ri8 &&
3715        OI->getOpcode() == X86::SUB32ri8) ||
3716       (FlagI->getOpcode() == X86::CMP16ri &&
3717        OI->getOpcode() == X86::SUB16ri) ||
3718       (FlagI->getOpcode() == X86::CMP16ri8 &&
3719        OI->getOpcode() == X86::SUB16ri8) ||
3720       (FlagI->getOpcode() == X86::CMP8ri &&
3721        OI->getOpcode() == X86::SUB8ri)) &&
3722      OI->getOperand(1).getReg() == SrcReg &&
3723      OI->getOperand(2).getImm() == ImmValue)
3724    return true;
3725  return false;
3726}
3727
3728/// isDefConvertible - check whether the definition can be converted
3729/// to remove a comparison against zero.
3730inline static bool isDefConvertible(MachineInstr *MI) {
3731  switch (MI->getOpcode()) {
3732  default: return false;
3733
3734  // The shift instructions only modify ZF if their shift count is non-zero.
3735  // N.B.: The processor truncates the shift count depending on the encoding.
3736  case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3737  case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3738     return getTruncatedShiftCount(MI, 2) != 0;
3739
3740  // Some left shift instructions can be turned into LEA instructions but only
3741  // if their flags aren't used. Avoid transforming such instructions.
3742  case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3743    unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3744    if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3745    return ShAmt != 0;
3746  }
3747
3748  case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3749  case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3750     return getTruncatedShiftCount(MI, 3) != 0;
3751
3752  case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3753  case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3754  case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3755  case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3756  case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3757  case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3758  case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3759  case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3760  case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3761  case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3762  case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3763  case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3764  case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3765  case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3766  case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3767  case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3768  case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3769  case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3770  case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3771  case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3772  case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3773  case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3774  case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3775  case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3776  case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3777  case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3778  case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3779  case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3780  case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3781  case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3782  case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3783  case X86::ADC32ri:   case X86::ADC32ri8:
3784  case X86::ADC32rr:   case X86::ADC64ri32:
3785  case X86::ADC64ri8:  case X86::ADC64rr:
3786  case X86::SBB32ri:   case X86::SBB32ri8:
3787  case X86::SBB32rr:   case X86::SBB64ri32:
3788  case X86::SBB64ri8:  case X86::SBB64rr:
3789  case X86::ANDN32rr:  case X86::ANDN32rm:
3790  case X86::ANDN64rr:  case X86::ANDN64rm:
3791  case X86::BEXTR32rr: case X86::BEXTR64rr:
3792  case X86::BEXTR32rm: case X86::BEXTR64rm:
3793  case X86::BLSI32rr:  case X86::BLSI32rm:
3794  case X86::BLSI64rr:  case X86::BLSI64rm:
3795  case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3796  case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3797  case X86::BLSR32rr:  case X86::BLSR32rm:
3798  case X86::BLSR64rr:  case X86::BLSR64rm:
3799  case X86::BZHI32rr:  case X86::BZHI32rm:
3800  case X86::BZHI64rr:  case X86::BZHI64rm:
3801  case X86::LZCNT16rr: case X86::LZCNT16rm:
3802  case X86::LZCNT32rr: case X86::LZCNT32rm:
3803  case X86::LZCNT64rr: case X86::LZCNT64rm:
3804  case X86::POPCNT16rr:case X86::POPCNT16rm:
3805  case X86::POPCNT32rr:case X86::POPCNT32rm:
3806  case X86::POPCNT64rr:case X86::POPCNT64rm:
3807  case X86::TZCNT16rr: case X86::TZCNT16rm:
3808  case X86::TZCNT32rr: case X86::TZCNT32rm:
3809  case X86::TZCNT64rr: case X86::TZCNT64rm:
3810    return true;
3811  }
3812}
3813
3814/// isUseDefConvertible - check whether the use can be converted
3815/// to remove a comparison against zero.
3816static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3817  switch (MI->getOpcode()) {
3818  default: return X86::COND_INVALID;
3819  case X86::LZCNT16rr: case X86::LZCNT16rm:
3820  case X86::LZCNT32rr: case X86::LZCNT32rm:
3821  case X86::LZCNT64rr: case X86::LZCNT64rm:
3822    return X86::COND_B;
3823  case X86::POPCNT16rr:case X86::POPCNT16rm:
3824  case X86::POPCNT32rr:case X86::POPCNT32rm:
3825  case X86::POPCNT64rr:case X86::POPCNT64rm:
3826    return X86::COND_E;
3827  case X86::TZCNT16rr: case X86::TZCNT16rm:
3828  case X86::TZCNT32rr: case X86::TZCNT32rm:
3829  case X86::TZCNT64rr: case X86::TZCNT64rm:
3830    return X86::COND_B;
3831  }
3832}
3833
3834/// optimizeCompareInstr - Check if there exists an earlier instruction that
3835/// operates on the same source operands and sets flags in the same way as
3836/// Compare; remove Compare if possible.
3837bool X86InstrInfo::
3838optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3839                     int CmpMask, int CmpValue,
3840                     const MachineRegisterInfo *MRI) const {
3841  // Check whether we can replace SUB with CMP.
3842  unsigned NewOpcode = 0;
3843  switch (CmpInstr->getOpcode()) {
3844  default: break;
3845  case X86::SUB64ri32:
3846  case X86::SUB64ri8:
3847  case X86::SUB32ri:
3848  case X86::SUB32ri8:
3849  case X86::SUB16ri:
3850  case X86::SUB16ri8:
3851  case X86::SUB8ri:
3852  case X86::SUB64rm:
3853  case X86::SUB32rm:
3854  case X86::SUB16rm:
3855  case X86::SUB8rm:
3856  case X86::SUB64rr:
3857  case X86::SUB32rr:
3858  case X86::SUB16rr:
3859  case X86::SUB8rr: {
3860    if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3861      return false;
3862    // There is no use of the destination register, we can replace SUB with CMP.
3863    switch (CmpInstr->getOpcode()) {
3864    default: llvm_unreachable("Unreachable!");
3865    case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3866    case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3867    case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3868    case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3869    case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3870    case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3871    case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3872    case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3873    case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3874    case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3875    case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3876    case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3877    case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3878    case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3879    case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3880    }
3881    CmpInstr->setDesc(get(NewOpcode));
3882    CmpInstr->RemoveOperand(0);
3883    // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3884    if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3885        NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3886      return false;
3887  }
3888  }
3889
3890  // Get the unique definition of SrcReg.
3891  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3892  if (!MI) return false;
3893
3894  // CmpInstr is the first instruction of the BB.
3895  MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3896
3897  // If we are comparing against zero, check whether we can use MI to update
3898  // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3899  bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3900  if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
3901    return false;
3902
3903  // If we have a use of the source register between the def and our compare
3904  // instruction we can eliminate the compare iff the use sets EFLAGS in the
3905  // right way.
3906  bool ShouldUpdateCC = false;
3907  X86::CondCode NewCC = X86::COND_INVALID;
3908  if (IsCmpZero && !isDefConvertible(MI)) {
3909    // Scan forward from the use until we hit the use we're looking for or the
3910    // compare instruction.
3911    for (MachineBasicBlock::iterator J = MI;; ++J) {
3912      // Do we have a convertible instruction?
3913      NewCC = isUseDefConvertible(J);
3914      if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3915          J->getOperand(1).getReg() == SrcReg) {
3916        assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3917        ShouldUpdateCC = true; // Update CC later on.
3918        // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3919        // with the new def.
3920        MI = Def = J;
3921        break;
3922      }
3923
3924      if (J == I)
3925        return false;
3926    }
3927  }
3928
3929  // We are searching for an earlier instruction that can make CmpInstr
3930  // redundant and that instruction will be saved in Sub.
3931  MachineInstr *Sub = nullptr;
3932  const TargetRegisterInfo *TRI = &getRegisterInfo();
3933
3934  // We iterate backward, starting from the instruction before CmpInstr and
3935  // stop when reaching the definition of a source register or done with the BB.
3936  // RI points to the instruction before CmpInstr.
3937  // If the definition is in this basic block, RE points to the definition;
3938  // otherwise, RE is the rend of the basic block.
3939  MachineBasicBlock::reverse_iterator
3940      RI = MachineBasicBlock::reverse_iterator(I),
3941      RE = CmpInstr->getParent() == MI->getParent() ?
3942           MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3943           CmpInstr->getParent()->rend();
3944  MachineInstr *Movr0Inst = nullptr;
3945  for (; RI != RE; ++RI) {
3946    MachineInstr *Instr = &*RI;
3947    // Check whether CmpInstr can be made redundant by the current instruction.
3948    if (!IsCmpZero &&
3949        isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3950      Sub = Instr;
3951      break;
3952    }
3953
3954    if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3955        Instr->readsRegister(X86::EFLAGS, TRI)) {
3956      // This instruction modifies or uses EFLAGS.
3957
3958      // MOV32r0 etc. are implemented with xor which clobbers condition code.
3959      // They are safe to move up, if the definition to EFLAGS is dead and
3960      // earlier instructions do not read or write EFLAGS.
3961      if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3962          Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3963        Movr0Inst = Instr;
3964        continue;
3965      }
3966
3967      // We can't remove CmpInstr.
3968      return false;
3969    }
3970  }
3971
3972  // Return false if no candidates exist.
3973  if (!IsCmpZero && !Sub)
3974    return false;
3975
3976  bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3977                    Sub->getOperand(2).getReg() == SrcReg);
3978
3979  // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3980  // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3981  // If we are done with the basic block, we need to check whether EFLAGS is
3982  // live-out.
3983  bool IsSafe = false;
3984  SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3985  MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3986  for (++I; I != E; ++I) {
3987    const MachineInstr &Instr = *I;
3988    bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3989    bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3990    // We should check the usage if this instruction uses and updates EFLAGS.
3991    if (!UseEFLAGS && ModifyEFLAGS) {
3992      // It is safe to remove CmpInstr if EFLAGS is updated again.
3993      IsSafe = true;
3994      break;
3995    }
3996    if (!UseEFLAGS && !ModifyEFLAGS)
3997      continue;
3998
3999    // EFLAGS is used by this instruction.
4000    X86::CondCode OldCC = X86::COND_INVALID;
4001    bool OpcIsSET = false;
4002    if (IsCmpZero || IsSwapped) {
4003      // We decode the condition code from opcode.
4004      if (Instr.isBranch())
4005        OldCC = getCondFromBranchOpc(Instr.getOpcode());
4006      else {
4007        OldCC = getCondFromSETOpc(Instr.getOpcode());
4008        if (OldCC != X86::COND_INVALID)
4009          OpcIsSET = true;
4010        else
4011          OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
4012      }
4013      if (OldCC == X86::COND_INVALID) return false;
4014    }
4015    if (IsCmpZero) {
4016      switch (OldCC) {
4017      default: break;
4018      case X86::COND_A: case X86::COND_AE:
4019      case X86::COND_B: case X86::COND_BE:
4020      case X86::COND_G: case X86::COND_GE:
4021      case X86::COND_L: case X86::COND_LE:
4022      case X86::COND_O: case X86::COND_NO:
4023        // CF and OF are used, we can't perform this optimization.
4024        return false;
4025      }
4026
4027      // If we're updating the condition code check if we have to reverse the
4028      // condition.
4029      if (ShouldUpdateCC)
4030        switch (OldCC) {
4031        default:
4032          return false;
4033        case X86::COND_E:
4034          break;
4035        case X86::COND_NE:
4036          NewCC = GetOppositeBranchCondition(NewCC);
4037          break;
4038        }
4039    } else if (IsSwapped) {
4040      // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4041      // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4042      // We swap the condition code and synthesize the new opcode.
4043      NewCC = getSwappedCondition(OldCC);
4044      if (NewCC == X86::COND_INVALID) return false;
4045    }
4046
4047    if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4048      // Synthesize the new opcode.
4049      bool HasMemoryOperand = Instr.hasOneMemOperand();
4050      unsigned NewOpc;
4051      if (Instr.isBranch())
4052        NewOpc = GetCondBranchFromCond(NewCC);
4053      else if(OpcIsSET)
4054        NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4055      else {
4056        unsigned DstReg = Instr.getOperand(0).getReg();
4057        NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4058                                 HasMemoryOperand);
4059      }
4060
4061      // Push the MachineInstr to OpsToUpdate.
4062      // If it is safe to remove CmpInstr, the condition code of these
4063      // instructions will be modified.
4064      OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4065    }
4066    if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4067      // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4068      IsSafe = true;
4069      break;
4070    }
4071  }
4072
4073  // If EFLAGS is not killed nor re-defined, we should check whether it is
4074  // live-out. If it is live-out, do not optimize.
4075  if ((IsCmpZero || IsSwapped) && !IsSafe) {
4076    MachineBasicBlock *MBB = CmpInstr->getParent();
4077    for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4078             SE = MBB->succ_end(); SI != SE; ++SI)
4079      if ((*SI)->isLiveIn(X86::EFLAGS))
4080        return false;
4081  }
4082
4083  // The instruction to be updated is either Sub or MI.
4084  Sub = IsCmpZero ? MI : Sub;
4085  // Move Movr0Inst to the appropriate place before Sub.
4086  if (Movr0Inst) {
4087    // Look backwards until we find a def that doesn't use the current EFLAGS.
4088    Def = Sub;
4089    MachineBasicBlock::reverse_iterator
4090      InsertI = MachineBasicBlock::reverse_iterator(++Def),
4091                InsertE = Sub->getParent()->rend();
4092    for (; InsertI != InsertE; ++InsertI) {
4093      MachineInstr *Instr = &*InsertI;
4094      if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4095          Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4096        Sub->getParent()->remove(Movr0Inst);
4097        Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4098                                   Movr0Inst);
4099        break;
4100      }
4101    }
4102    if (InsertI == InsertE)
4103      return false;
4104  }
4105
4106  // Make sure Sub instruction defines EFLAGS and mark the def live.
4107  unsigned i = 0, e = Sub->getNumOperands();
4108  for (; i != e; ++i) {
4109    MachineOperand &MO = Sub->getOperand(i);
4110    if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4111      MO.setIsDead(false);
4112      break;
4113    }
4114  }
4115  assert(i != e && "Unable to locate a def EFLAGS operand");
4116
4117  CmpInstr->eraseFromParent();
4118
4119  // Modify the condition code of instructions in OpsToUpdate.
4120  for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4121    OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4122  return true;
4123}
4124
4125/// optimizeLoadInstr - Try to remove the load by folding it to a register
4126/// operand at the use. We fold the load instructions if load defines a virtual
4127/// register, the virtual register is used once in the same BB, and the
4128/// instructions in-between do not load or store, and have no side effects.
4129MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4130                                              const MachineRegisterInfo *MRI,
4131                                              unsigned &FoldAsLoadDefReg,
4132                                              MachineInstr *&DefMI) const {
4133  if (FoldAsLoadDefReg == 0)
4134    return nullptr;
4135  // To be conservative, if there exists another load, clear the load candidate.
4136  if (MI->mayLoad()) {
4137    FoldAsLoadDefReg = 0;
4138    return nullptr;
4139  }
4140
4141  // Check whether we can move DefMI here.
4142  DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4143  assert(DefMI);
4144  bool SawStore = false;
4145  if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4146    return nullptr;
4147
4148  // Collect information about virtual register operands of MI.
4149  unsigned SrcOperandId = 0;
4150  bool FoundSrcOperand = false;
4151  for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4152    MachineOperand &MO = MI->getOperand(i);
4153    if (!MO.isReg())
4154      continue;
4155    unsigned Reg = MO.getReg();
4156    if (Reg != FoldAsLoadDefReg)
4157      continue;
4158    // Do not fold if we have a subreg use or a def or multiple uses.
4159    if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4160      return nullptr;
4161
4162    SrcOperandId = i;
4163    FoundSrcOperand = true;
4164  }
4165  if (!FoundSrcOperand)
4166    return nullptr;
4167
4168  // Check whether we can fold the def into SrcOperandId.
4169  SmallVector<unsigned, 8> Ops;
4170  Ops.push_back(SrcOperandId);
4171  MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4172  if (FoldMI) {
4173    FoldAsLoadDefReg = 0;
4174    return FoldMI;
4175  }
4176
4177  return nullptr;
4178}
4179
4180/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4181/// instruction with two undef reads of the register being defined.  This is
4182/// used for mapping:
4183///   %xmm4 = V_SET0
4184/// to:
4185///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4186///
4187static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4188                             const MCInstrDesc &Desc) {
4189  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4190  unsigned Reg = MIB->getOperand(0).getReg();
4191  MIB->setDesc(Desc);
4192
4193  // MachineInstr::addOperand() will insert explicit operands before any
4194  // implicit operands.
4195  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4196  // But we don't trust that.
4197  assert(MIB->getOperand(1).getReg() == Reg &&
4198         MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4199  return true;
4200}
4201
4202// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4203// code sequence is needed for other targets.
4204static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4205                                 const TargetInstrInfo &TII) {
4206  MachineBasicBlock &MBB = *MIB->getParent();
4207  DebugLoc DL = MIB->getDebugLoc();
4208  unsigned Reg = MIB->getOperand(0).getReg();
4209  const GlobalValue *GV =
4210      cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4211  unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4212  MachineMemOperand *MMO = MBB.getParent()->
4213      getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
4214  MachineBasicBlock::iterator I = MIB.getInstr();
4215
4216  BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4217      .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4218      .addMemOperand(MMO);
4219  MIB->setDebugLoc(DL);
4220  MIB->setDesc(TII.get(X86::MOV64rm));
4221  MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4222}
4223
4224bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4225  bool HasAVX = Subtarget.hasAVX();
4226  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4227  switch (MI->getOpcode()) {
4228  case X86::MOV32r0:
4229    return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4230  case X86::SETB_C8r:
4231    return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4232  case X86::SETB_C16r:
4233    return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4234  case X86::SETB_C32r:
4235    return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4236  case X86::SETB_C64r:
4237    return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4238  case X86::V_SET0:
4239  case X86::FsFLD0SS:
4240  case X86::FsFLD0SD:
4241    return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4242  case X86::AVX_SET0:
4243    assert(HasAVX && "AVX not supported");
4244    return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4245  case X86::AVX512_512_SET0:
4246    return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4247  case X86::V_SETALLONES:
4248    return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4249  case X86::AVX2_SETALLONES:
4250    return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4251  case X86::TEST8ri_NOREX:
4252    MI->setDesc(get(X86::TEST8ri));
4253    return true;
4254  case X86::KSET0B:
4255  case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4256  case X86::KSET1B:
4257  case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4258  case TargetOpcode::LOAD_STACK_GUARD:
4259    expandLoadStackGuard(MIB, *this);
4260    return true;
4261  }
4262  return false;
4263}
4264
4265static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4266                                     const SmallVectorImpl<MachineOperand> &MOs,
4267                                     MachineInstr *MI,
4268                                     const TargetInstrInfo &TII) {
4269  // Create the base instruction with the memory operand as the first part.
4270  // Omit the implicit operands, something BuildMI can't do.
4271  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4272                                              MI->getDebugLoc(), true);
4273  MachineInstrBuilder MIB(MF, NewMI);
4274  unsigned NumAddrOps = MOs.size();
4275  for (unsigned i = 0; i != NumAddrOps; ++i)
4276    MIB.addOperand(MOs[i]);
4277  if (NumAddrOps < 4)  // FrameIndex only
4278    addOffset(MIB, 0);
4279
4280  // Loop over the rest of the ri operands, converting them over.
4281  unsigned NumOps = MI->getDesc().getNumOperands()-2;
4282  for (unsigned i = 0; i != NumOps; ++i) {
4283    MachineOperand &MO = MI->getOperand(i+2);
4284    MIB.addOperand(MO);
4285  }
4286  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4287    MachineOperand &MO = MI->getOperand(i);
4288    MIB.addOperand(MO);
4289  }
4290  return MIB;
4291}
4292
4293static MachineInstr *FuseInst(MachineFunction &MF,
4294                              unsigned Opcode, unsigned OpNo,
4295                              const SmallVectorImpl<MachineOperand> &MOs,
4296                              MachineInstr *MI, const TargetInstrInfo &TII) {
4297  // Omit the implicit operands, something BuildMI can't do.
4298  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4299                                              MI->getDebugLoc(), true);
4300  MachineInstrBuilder MIB(MF, NewMI);
4301
4302  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4303    MachineOperand &MO = MI->getOperand(i);
4304    if (i == OpNo) {
4305      assert(MO.isReg() && "Expected to fold into reg operand!");
4306      unsigned NumAddrOps = MOs.size();
4307      for (unsigned i = 0; i != NumAddrOps; ++i)
4308        MIB.addOperand(MOs[i]);
4309      if (NumAddrOps < 4)  // FrameIndex only
4310        addOffset(MIB, 0);
4311    } else {
4312      MIB.addOperand(MO);
4313    }
4314  }
4315  return MIB;
4316}
4317
4318static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4319                                const SmallVectorImpl<MachineOperand> &MOs,
4320                                MachineInstr *MI) {
4321  MachineFunction &MF = *MI->getParent()->getParent();
4322  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4323
4324  unsigned NumAddrOps = MOs.size();
4325  for (unsigned i = 0; i != NumAddrOps; ++i)
4326    MIB.addOperand(MOs[i]);
4327  if (NumAddrOps < 4)  // FrameIndex only
4328    addOffset(MIB, 0);
4329  return MIB.addImm(0);
4330}
4331
4332MachineInstr*
4333X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4334                                    MachineInstr *MI, unsigned i,
4335                                    const SmallVectorImpl<MachineOperand> &MOs,
4336                                    unsigned Size, unsigned Align,
4337                                    bool AllowCommute) const {
4338  const DenseMap<unsigned,
4339                 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4340  bool isCallRegIndirect = Subtarget.callRegIndirect();
4341  bool isTwoAddrFold = false;
4342
4343  // Atom favors register form of call. So, we do not fold loads into calls
4344  // when X86Subtarget is Atom.
4345  if (isCallRegIndirect &&
4346    (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4347    return nullptr;
4348  }
4349
4350  unsigned NumOps = MI->getDesc().getNumOperands();
4351  bool isTwoAddr = NumOps > 1 &&
4352    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4353
4354  // FIXME: AsmPrinter doesn't know how to handle
4355  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4356  if (MI->getOpcode() == X86::ADD32ri &&
4357      MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4358    return nullptr;
4359
4360  MachineInstr *NewMI = nullptr;
4361  // Folding a memory location into the two-address part of a two-address
4362  // instruction is different than folding it other places.  It requires
4363  // replacing the *two* registers with the memory location.
4364  if (isTwoAddr && NumOps >= 2 && i < 2 &&
4365      MI->getOperand(0).isReg() &&
4366      MI->getOperand(1).isReg() &&
4367      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4368    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4369    isTwoAddrFold = true;
4370  } else if (i == 0) { // If operand 0
4371    if (MI->getOpcode() == X86::MOV32r0) {
4372      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4373      if (NewMI)
4374        return NewMI;
4375    }
4376
4377    OpcodeTablePtr = &RegOp2MemOpTable0;
4378  } else if (i == 1) {
4379    OpcodeTablePtr = &RegOp2MemOpTable1;
4380  } else if (i == 2) {
4381    OpcodeTablePtr = &RegOp2MemOpTable2;
4382  } else if (i == 3) {
4383    OpcodeTablePtr = &RegOp2MemOpTable3;
4384  } else if (i == 4) {
4385    OpcodeTablePtr = &RegOp2MemOpTable4;
4386  }
4387
4388  // If table selected...
4389  if (OpcodeTablePtr) {
4390    // Find the Opcode to fuse
4391    DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4392      OpcodeTablePtr->find(MI->getOpcode());
4393    if (I != OpcodeTablePtr->end()) {
4394      unsigned Opcode = I->second.first;
4395      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4396      if (Align < MinAlign)
4397        return nullptr;
4398      bool NarrowToMOV32rm = false;
4399      if (Size) {
4400        unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4401        if (Size < RCSize) {
4402          // Check if it's safe to fold the load. If the size of the object is
4403          // narrower than the load width, then it's not.
4404          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4405            return nullptr;
4406          // If this is a 64-bit load, but the spill slot is 32, then we can do
4407          // a 32-bit load which is implicitly zero-extended. This likely is
4408          // due to live interval analysis remat'ing a load from stack slot.
4409          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4410            return nullptr;
4411          Opcode = X86::MOV32rm;
4412          NarrowToMOV32rm = true;
4413        }
4414      }
4415
4416      if (isTwoAddrFold)
4417        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4418      else
4419        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4420
4421      if (NarrowToMOV32rm) {
4422        // If this is the special case where we use a MOV32rm to load a 32-bit
4423        // value and zero-extend the top bits. Change the destination register
4424        // to a 32-bit one.
4425        unsigned DstReg = NewMI->getOperand(0).getReg();
4426        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4427          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4428        else
4429          NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4430      }
4431      return NewMI;
4432    }
4433  }
4434
4435  // If the instruction and target operand are commutable, commute the
4436  // instruction and try again.
4437  if (AllowCommute) {
4438    unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2;
4439    if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4440      bool HasDef = MI->getDesc().getNumDefs();
4441      unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4442      unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4443      unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4444      bool Tied0 =
4445          0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4446      bool Tied1 =
4447          0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4448
4449      // If either of the commutable operands are tied to the destination
4450      // then we can not commute + fold.
4451      if ((HasDef && Reg0 == Reg1 && Tied0) ||
4452          (HasDef && Reg0 == Reg2 && Tied1))
4453        return nullptr;
4454
4455      if ((CommuteOpIdx1 == OriginalOpIdx) ||
4456          (CommuteOpIdx2 == OriginalOpIdx)) {
4457        MachineInstr *CommutedMI = commuteInstruction(MI, false);
4458        if (!CommutedMI) {
4459          // Unable to commute.
4460          return nullptr;
4461        }
4462        if (CommutedMI != MI) {
4463          // New instruction. We can't fold from this.
4464          CommutedMI->eraseFromParent();
4465          return nullptr;
4466        }
4467
4468        // Attempt to fold with the commuted version of the instruction.
4469        unsigned CommuteOp =
4470            (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4471        NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4472                                      /*AllowCommute=*/false);
4473        if (NewMI)
4474          return NewMI;
4475
4476        // Folding failed again - undo the commute before returning.
4477        MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4478        if (!UncommutedMI) {
4479          // Unable to commute.
4480          return nullptr;
4481        }
4482        if (UncommutedMI != MI) {
4483          // New instruction. It doesn't need to be kept.
4484          UncommutedMI->eraseFromParent();
4485          return nullptr;
4486        }
4487
4488        // Return here to prevent duplicate fuse failure report.
4489        return nullptr;
4490      }
4491    }
4492  }
4493
4494  // No fusion
4495  if (PrintFailedFusing && !MI->isCopy())
4496    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4497  return nullptr;
4498}
4499
4500/// hasPartialRegUpdate - Return true for all instructions that only update
4501/// the first 32 or 64-bits of the destination register and leave the rest
4502/// unmodified. This can be used to avoid folding loads if the instructions
4503/// only update part of the destination register, and the non-updated part is
4504/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4505/// instructions breaks the partial register dependency and it can improve
4506/// performance. e.g.:
4507///
4508///   movss (%rdi), %xmm0
4509///   cvtss2sd %xmm0, %xmm0
4510///
4511/// Instead of
4512///   cvtss2sd (%rdi), %xmm0
4513///
4514/// FIXME: This should be turned into a TSFlags.
4515///
4516static bool hasPartialRegUpdate(unsigned Opcode) {
4517  switch (Opcode) {
4518  case X86::CVTSI2SSrr:
4519  case X86::CVTSI2SSrm:
4520  case X86::CVTSI2SS64rr:
4521  case X86::CVTSI2SS64rm:
4522  case X86::CVTSI2SDrr:
4523  case X86::CVTSI2SDrm:
4524  case X86::CVTSI2SD64rr:
4525  case X86::CVTSI2SD64rm:
4526  case X86::CVTSD2SSrr:
4527  case X86::CVTSD2SSrm:
4528  case X86::Int_CVTSD2SSrr:
4529  case X86::Int_CVTSD2SSrm:
4530  case X86::CVTSS2SDrr:
4531  case X86::CVTSS2SDrm:
4532  case X86::Int_CVTSS2SDrr:
4533  case X86::Int_CVTSS2SDrm:
4534  case X86::RCPSSr:
4535  case X86::RCPSSm:
4536  case X86::RCPSSr_Int:
4537  case X86::RCPSSm_Int:
4538  case X86::ROUNDSDr:
4539  case X86::ROUNDSDm:
4540  case X86::ROUNDSDr_Int:
4541  case X86::ROUNDSSr:
4542  case X86::ROUNDSSm:
4543  case X86::ROUNDSSr_Int:
4544  case X86::RSQRTSSr:
4545  case X86::RSQRTSSm:
4546  case X86::RSQRTSSr_Int:
4547  case X86::RSQRTSSm_Int:
4548  case X86::SQRTSSr:
4549  case X86::SQRTSSm:
4550  case X86::SQRTSSr_Int:
4551  case X86::SQRTSSm_Int:
4552  case X86::SQRTSDr:
4553  case X86::SQRTSDm:
4554  case X86::SQRTSDr_Int:
4555  case X86::SQRTSDm_Int:
4556    return true;
4557  }
4558
4559  return false;
4560}
4561
4562/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4563/// instructions we would like before a partial register update.
4564unsigned X86InstrInfo::
4565getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4566                             const TargetRegisterInfo *TRI) const {
4567  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4568    return 0;
4569
4570  // If MI is marked as reading Reg, the partial register update is wanted.
4571  const MachineOperand &MO = MI->getOperand(0);
4572  unsigned Reg = MO.getReg();
4573  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4574    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4575      return 0;
4576  } else {
4577    if (MI->readsRegister(Reg, TRI))
4578      return 0;
4579  }
4580
4581  // If any of the preceding 16 instructions are reading Reg, insert a
4582  // dependency breaking instruction.  The magic number is based on a few
4583  // Nehalem experiments.
4584  return 16;
4585}
4586
4587// Return true for any instruction the copies the high bits of the first source
4588// operand into the unused high bits of the destination operand.
4589static bool hasUndefRegUpdate(unsigned Opcode) {
4590  switch (Opcode) {
4591  case X86::VCVTSI2SSrr:
4592  case X86::VCVTSI2SSrm:
4593  case X86::Int_VCVTSI2SSrr:
4594  case X86::Int_VCVTSI2SSrm:
4595  case X86::VCVTSI2SS64rr:
4596  case X86::VCVTSI2SS64rm:
4597  case X86::Int_VCVTSI2SS64rr:
4598  case X86::Int_VCVTSI2SS64rm:
4599  case X86::VCVTSI2SDrr:
4600  case X86::VCVTSI2SDrm:
4601  case X86::Int_VCVTSI2SDrr:
4602  case X86::Int_VCVTSI2SDrm:
4603  case X86::VCVTSI2SD64rr:
4604  case X86::VCVTSI2SD64rm:
4605  case X86::Int_VCVTSI2SD64rr:
4606  case X86::Int_VCVTSI2SD64rm:
4607  case X86::VCVTSD2SSrr:
4608  case X86::VCVTSD2SSrm:
4609  case X86::Int_VCVTSD2SSrr:
4610  case X86::Int_VCVTSD2SSrm:
4611  case X86::VCVTSS2SDrr:
4612  case X86::VCVTSS2SDrm:
4613  case X86::Int_VCVTSS2SDrr:
4614  case X86::Int_VCVTSS2SDrm:
4615  case X86::VRCPSSr:
4616  case X86::VRCPSSm:
4617  case X86::VRCPSSm_Int:
4618  case X86::VROUNDSDr:
4619  case X86::VROUNDSDm:
4620  case X86::VROUNDSDr_Int:
4621  case X86::VROUNDSSr:
4622  case X86::VROUNDSSm:
4623  case X86::VROUNDSSr_Int:
4624  case X86::VRSQRTSSr:
4625  case X86::VRSQRTSSm:
4626  case X86::VRSQRTSSm_Int:
4627  case X86::VSQRTSSr:
4628  case X86::VSQRTSSm:
4629  case X86::VSQRTSSm_Int:
4630  case X86::VSQRTSDr:
4631  case X86::VSQRTSDm:
4632  case X86::VSQRTSDm_Int:
4633    // AVX-512
4634  case X86::VCVTSD2SSZrr:
4635  case X86::VCVTSD2SSZrm:
4636  case X86::VCVTSS2SDZrr:
4637  case X86::VCVTSS2SDZrm:
4638    return true;
4639  }
4640
4641  return false;
4642}
4643
4644/// Inform the ExeDepsFix pass how many idle instructions we would like before
4645/// certain undef register reads.
4646///
4647/// This catches the VCVTSI2SD family of instructions:
4648///
4649/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4650///
4651/// We should to be careful *not* to catch VXOR idioms which are presumably
4652/// handled specially in the pipeline:
4653///
4654/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4655///
4656/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4657/// high bits that are passed-through are not live.
4658unsigned X86InstrInfo::
4659getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4660                     const TargetRegisterInfo *TRI) const {
4661  if (!hasUndefRegUpdate(MI->getOpcode()))
4662    return 0;
4663
4664  // Set the OpNum parameter to the first source operand.
4665  OpNum = 1;
4666
4667  const MachineOperand &MO = MI->getOperand(OpNum);
4668  if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4669    // Use the same magic number as getPartialRegUpdateClearance.
4670    return 16;
4671  }
4672  return 0;
4673}
4674
4675void X86InstrInfo::
4676breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4677                          const TargetRegisterInfo *TRI) const {
4678  unsigned Reg = MI->getOperand(OpNum).getReg();
4679  // If MI kills this register, the false dependence is already broken.
4680  if (MI->killsRegister(Reg, TRI))
4681    return;
4682  if (X86::VR128RegClass.contains(Reg)) {
4683    // These instructions are all floating point domain, so xorps is the best
4684    // choice.
4685    bool HasAVX = Subtarget.hasAVX();
4686    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4687    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4688      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4689  } else if (X86::VR256RegClass.contains(Reg)) {
4690    // Use vxorps to clear the full ymm register.
4691    // It wants to read and write the xmm sub-register.
4692    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4693    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4694      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4695      .addReg(Reg, RegState::ImplicitDefine);
4696  } else
4697    return;
4698  MI->addRegisterKilled(Reg, TRI, true);
4699}
4700
4701MachineInstr*
4702X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4703                                    const SmallVectorImpl<unsigned> &Ops,
4704                                    int FrameIndex) const {
4705  // Check switch flag
4706  if (NoFusing) return nullptr;
4707
4708  // Unless optimizing for size, don't fold to avoid partial
4709  // register update stalls
4710  if (!MF.getFunction()->getAttributes().
4711        hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4712      hasPartialRegUpdate(MI->getOpcode()))
4713    return nullptr;
4714
4715  const MachineFrameInfo *MFI = MF.getFrameInfo();
4716  unsigned Size = MFI->getObjectSize(FrameIndex);
4717  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4718  // If the function stack isn't realigned we don't want to fold instructions
4719  // that need increased alignment.
4720  if (!RI.needsStackRealignment(MF))
4721    Alignment = std::min(Alignment, MF.getTarget()
4722                                        .getSubtargetImpl()
4723                                        ->getFrameLowering()
4724                                        ->getStackAlignment());
4725  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4726    unsigned NewOpc = 0;
4727    unsigned RCSize = 0;
4728    switch (MI->getOpcode()) {
4729    default: return nullptr;
4730    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4731    case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4732    case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4733    case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4734    }
4735    // Check if it's safe to fold the load. If the size of the object is
4736    // narrower than the load width, then it's not.
4737    if (Size < RCSize)
4738      return nullptr;
4739    // Change to CMPXXri r, 0 first.
4740    MI->setDesc(get(NewOpc));
4741    MI->getOperand(1).ChangeToImmediate(0);
4742  } else if (Ops.size() != 1)
4743    return nullptr;
4744
4745  SmallVector<MachineOperand,4> MOs;
4746  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4747  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4748                               Size, Alignment, /*AllowCommute=*/true);
4749}
4750
4751static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
4752                                  const MachineFunction &MF) {
4753  unsigned Opc = LoadMI.getOpcode();
4754  unsigned RegSize =
4755      MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
4756
4757  if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
4758    // These instructions only load 32 bits, we can't fold them if the
4759    // destination register is wider than 32 bits (4 bytes).
4760    return true;
4761
4762  if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
4763    // These instructions only load 64 bits, we can't fold them if the
4764    // destination register is wider than 64 bits (8 bytes).
4765    return true;
4766
4767  return false;
4768}
4769
4770MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4771                                                  MachineInstr *MI,
4772                                           const SmallVectorImpl<unsigned> &Ops,
4773                                                  MachineInstr *LoadMI) const {
4774  // If loading from a FrameIndex, fold directly from the FrameIndex.
4775  unsigned NumOps = LoadMI->getDesc().getNumOperands();
4776  int FrameIndex;
4777  if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4778    if (isPartialRegisterLoad(*LoadMI, MF))
4779      return nullptr;
4780    return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4781  }
4782
4783  // Check switch flag
4784  if (NoFusing) return nullptr;
4785
4786  // Unless optimizing for size, don't fold to avoid partial
4787  // register update stalls
4788  if (!MF.getFunction()->getAttributes().
4789        hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4790      hasPartialRegUpdate(MI->getOpcode()))
4791    return nullptr;
4792
4793  // Determine the alignment of the load.
4794  unsigned Alignment = 0;
4795  if (LoadMI->hasOneMemOperand())
4796    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4797  else
4798    switch (LoadMI->getOpcode()) {
4799    case X86::AVX2_SETALLONES:
4800    case X86::AVX_SET0:
4801      Alignment = 32;
4802      break;
4803    case X86::V_SET0:
4804    case X86::V_SETALLONES:
4805      Alignment = 16;
4806      break;
4807    case X86::FsFLD0SD:
4808      Alignment = 8;
4809      break;
4810    case X86::FsFLD0SS:
4811      Alignment = 4;
4812      break;
4813    default:
4814      return nullptr;
4815    }
4816  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4817    unsigned NewOpc = 0;
4818    switch (MI->getOpcode()) {
4819    default: return nullptr;
4820    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4821    case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4822    case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4823    case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4824    }
4825    // Change to CMPXXri r, 0 first.
4826    MI->setDesc(get(NewOpc));
4827    MI->getOperand(1).ChangeToImmediate(0);
4828  } else if (Ops.size() != 1)
4829    return nullptr;
4830
4831  // Make sure the subregisters match.
4832  // Otherwise we risk changing the size of the load.
4833  if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4834    return nullptr;
4835
4836  SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4837  switch (LoadMI->getOpcode()) {
4838  case X86::V_SET0:
4839  case X86::V_SETALLONES:
4840  case X86::AVX2_SETALLONES:
4841  case X86::AVX_SET0:
4842  case X86::FsFLD0SD:
4843  case X86::FsFLD0SS: {
4844    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4845    // Create a constant-pool entry and operands to load from it.
4846
4847    // Medium and large mode can't fold loads this way.
4848    if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4849        MF.getTarget().getCodeModel() != CodeModel::Kernel)
4850      return nullptr;
4851
4852    // x86-32 PIC requires a PIC base register for constant pools.
4853    unsigned PICBase = 0;
4854    if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4855      if (Subtarget.is64Bit())
4856        PICBase = X86::RIP;
4857      else
4858        // FIXME: PICBase = getGlobalBaseReg(&MF);
4859        // This doesn't work for several reasons.
4860        // 1. GlobalBaseReg may have been spilled.
4861        // 2. It may not be live at MI.
4862        return nullptr;
4863    }
4864
4865    // Create a constant-pool entry.
4866    MachineConstantPool &MCP = *MF.getConstantPool();
4867    Type *Ty;
4868    unsigned Opc = LoadMI->getOpcode();
4869    if (Opc == X86::FsFLD0SS)
4870      Ty = Type::getFloatTy(MF.getFunction()->getContext());
4871    else if (Opc == X86::FsFLD0SD)
4872      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4873    else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4874      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4875    else
4876      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4877
4878    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4879    const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4880                                    Constant::getNullValue(Ty);
4881    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4882
4883    // Create operands to load from the constant pool entry.
4884    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4885    MOs.push_back(MachineOperand::CreateImm(1));
4886    MOs.push_back(MachineOperand::CreateReg(0, false));
4887    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4888    MOs.push_back(MachineOperand::CreateReg(0, false));
4889    break;
4890  }
4891  default: {
4892    if (isPartialRegisterLoad(*LoadMI, MF))
4893      return nullptr;
4894
4895    // Folding a normal load. Just copy the load's address operands.
4896    for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4897      MOs.push_back(LoadMI->getOperand(i));
4898    break;
4899  }
4900  }
4901  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4902                               /*Size=*/0, Alignment, /*AllowCommute=*/true);
4903}
4904
4905
4906bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4907                                  const SmallVectorImpl<unsigned> &Ops) const {
4908  // Check switch flag
4909  if (NoFusing) return 0;
4910
4911  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4912    switch (MI->getOpcode()) {
4913    default: return false;
4914    case X86::TEST8rr:
4915    case X86::TEST16rr:
4916    case X86::TEST32rr:
4917    case X86::TEST64rr:
4918      return true;
4919    case X86::ADD32ri:
4920      // FIXME: AsmPrinter doesn't know how to handle
4921      // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4922      if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4923        return false;
4924      break;
4925    }
4926  }
4927
4928  if (Ops.size() != 1)
4929    return false;
4930
4931  unsigned OpNum = Ops[0];
4932  unsigned Opc = MI->getOpcode();
4933  unsigned NumOps = MI->getDesc().getNumOperands();
4934  bool isTwoAddr = NumOps > 1 &&
4935    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4936
4937  // Folding a memory location into the two-address part of a two-address
4938  // instruction is different than folding it other places.  It requires
4939  // replacing the *two* registers with the memory location.
4940  const DenseMap<unsigned,
4941                 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4942  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4943    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4944  } else if (OpNum == 0) { // If operand 0
4945    if (Opc == X86::MOV32r0)
4946      return true;
4947
4948    OpcodeTablePtr = &RegOp2MemOpTable0;
4949  } else if (OpNum == 1) {
4950    OpcodeTablePtr = &RegOp2MemOpTable1;
4951  } else if (OpNum == 2) {
4952    OpcodeTablePtr = &RegOp2MemOpTable2;
4953  } else if (OpNum == 3) {
4954    OpcodeTablePtr = &RegOp2MemOpTable3;
4955  }
4956
4957  if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4958    return true;
4959  return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4960}
4961
4962bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4963                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4964                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
4965  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4966    MemOp2RegOpTable.find(MI->getOpcode());
4967  if (I == MemOp2RegOpTable.end())
4968    return false;
4969  unsigned Opc = I->second.first;
4970  unsigned Index = I->second.second & TB_INDEX_MASK;
4971  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4972  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4973  if (UnfoldLoad && !FoldedLoad)
4974    return false;
4975  UnfoldLoad &= FoldedLoad;
4976  if (UnfoldStore && !FoldedStore)
4977    return false;
4978  UnfoldStore &= FoldedStore;
4979
4980  const MCInstrDesc &MCID = get(Opc);
4981  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4982  if (!MI->hasOneMemOperand() &&
4983      RC == &X86::VR128RegClass &&
4984      !Subtarget.isUnalignedMemAccessFast())
4985    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4986    // conservatively assume the address is unaligned. That's bad for
4987    // performance.
4988    return false;
4989  SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4990  SmallVector<MachineOperand,2> BeforeOps;
4991  SmallVector<MachineOperand,2> AfterOps;
4992  SmallVector<MachineOperand,4> ImpOps;
4993  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4994    MachineOperand &Op = MI->getOperand(i);
4995    if (i >= Index && i < Index + X86::AddrNumOperands)
4996      AddrOps.push_back(Op);
4997    else if (Op.isReg() && Op.isImplicit())
4998      ImpOps.push_back(Op);
4999    else if (i < Index)
5000      BeforeOps.push_back(Op);
5001    else if (i > Index)
5002      AfterOps.push_back(Op);
5003  }
5004
5005  // Emit the load instruction.
5006  if (UnfoldLoad) {
5007    std::pair<MachineInstr::mmo_iterator,
5008              MachineInstr::mmo_iterator> MMOs =
5009      MF.extractLoadMemRefs(MI->memoperands_begin(),
5010                            MI->memoperands_end());
5011    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5012    if (UnfoldStore) {
5013      // Address operands cannot be marked isKill.
5014      for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5015        MachineOperand &MO = NewMIs[0]->getOperand(i);
5016        if (MO.isReg())
5017          MO.setIsKill(false);
5018      }
5019    }
5020  }
5021
5022  // Emit the data processing instruction.
5023  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
5024  MachineInstrBuilder MIB(MF, DataMI);
5025
5026  if (FoldedStore)
5027    MIB.addReg(Reg, RegState::Define);
5028  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
5029    MIB.addOperand(BeforeOps[i]);
5030  if (FoldedLoad)
5031    MIB.addReg(Reg);
5032  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
5033    MIB.addOperand(AfterOps[i]);
5034  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5035    MachineOperand &MO = ImpOps[i];
5036    MIB.addReg(MO.getReg(),
5037               getDefRegState(MO.isDef()) |
5038               RegState::Implicit |
5039               getKillRegState(MO.isKill()) |
5040               getDeadRegState(MO.isDead()) |
5041               getUndefRegState(MO.isUndef()));
5042  }
5043  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5044  switch (DataMI->getOpcode()) {
5045  default: break;
5046  case X86::CMP64ri32:
5047  case X86::CMP64ri8:
5048  case X86::CMP32ri:
5049  case X86::CMP32ri8:
5050  case X86::CMP16ri:
5051  case X86::CMP16ri8:
5052  case X86::CMP8ri: {
5053    MachineOperand &MO0 = DataMI->getOperand(0);
5054    MachineOperand &MO1 = DataMI->getOperand(1);
5055    if (MO1.getImm() == 0) {
5056      unsigned NewOpc;
5057      switch (DataMI->getOpcode()) {
5058      default: llvm_unreachable("Unreachable!");
5059      case X86::CMP64ri8:
5060      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5061      case X86::CMP32ri8:
5062      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
5063      case X86::CMP16ri8:
5064      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
5065      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
5066      }
5067      DataMI->setDesc(get(NewOpc));
5068      MO1.ChangeToRegister(MO0.getReg(), false);
5069    }
5070  }
5071  }
5072  NewMIs.push_back(DataMI);
5073
5074  // Emit the store instruction.
5075  if (UnfoldStore) {
5076    const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5077    std::pair<MachineInstr::mmo_iterator,
5078              MachineInstr::mmo_iterator> MMOs =
5079      MF.extractStoreMemRefs(MI->memoperands_begin(),
5080                             MI->memoperands_end());
5081    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5082  }
5083
5084  return true;
5085}
5086
5087bool
5088X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5089                                  SmallVectorImpl<SDNode*> &NewNodes) const {
5090  if (!N->isMachineOpcode())
5091    return false;
5092
5093  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5094    MemOp2RegOpTable.find(N->getMachineOpcode());
5095  if (I == MemOp2RegOpTable.end())
5096    return false;
5097  unsigned Opc = I->second.first;
5098  unsigned Index = I->second.second & TB_INDEX_MASK;
5099  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5100  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5101  const MCInstrDesc &MCID = get(Opc);
5102  MachineFunction &MF = DAG.getMachineFunction();
5103  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5104  unsigned NumDefs = MCID.NumDefs;
5105  std::vector<SDValue> AddrOps;
5106  std::vector<SDValue> BeforeOps;
5107  std::vector<SDValue> AfterOps;
5108  SDLoc dl(N);
5109  unsigned NumOps = N->getNumOperands();
5110  for (unsigned i = 0; i != NumOps-1; ++i) {
5111    SDValue Op = N->getOperand(i);
5112    if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5113      AddrOps.push_back(Op);
5114    else if (i < Index-NumDefs)
5115      BeforeOps.push_back(Op);
5116    else if (i > Index-NumDefs)
5117      AfterOps.push_back(Op);
5118  }
5119  SDValue Chain = N->getOperand(NumOps-1);
5120  AddrOps.push_back(Chain);
5121
5122  // Emit the load instruction.
5123  SDNode *Load = nullptr;
5124  if (FoldedLoad) {
5125    EVT VT = *RC->vt_begin();
5126    std::pair<MachineInstr::mmo_iterator,
5127              MachineInstr::mmo_iterator> MMOs =
5128      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5129                            cast<MachineSDNode>(N)->memoperands_end());
5130    if (!(*MMOs.first) &&
5131        RC == &X86::VR128RegClass &&
5132        !Subtarget.isUnalignedMemAccessFast())
5133      // Do not introduce a slow unaligned load.
5134      return false;
5135    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5136    bool isAligned = (*MMOs.first) &&
5137                     (*MMOs.first)->getAlignment() >= Alignment;
5138    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5139                              VT, MVT::Other, AddrOps);
5140    NewNodes.push_back(Load);
5141
5142    // Preserve memory reference information.
5143    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5144  }
5145
5146  // Emit the data processing instruction.
5147  std::vector<EVT> VTs;
5148  const TargetRegisterClass *DstRC = nullptr;
5149  if (MCID.getNumDefs() > 0) {
5150    DstRC = getRegClass(MCID, 0, &RI, MF);
5151    VTs.push_back(*DstRC->vt_begin());
5152  }
5153  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5154    EVT VT = N->getValueType(i);
5155    if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5156      VTs.push_back(VT);
5157  }
5158  if (Load)
5159    BeforeOps.push_back(SDValue(Load, 0));
5160  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
5161  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5162  NewNodes.push_back(NewNode);
5163
5164  // Emit the store instruction.
5165  if (FoldedStore) {
5166    AddrOps.pop_back();
5167    AddrOps.push_back(SDValue(NewNode, 0));
5168    AddrOps.push_back(Chain);
5169    std::pair<MachineInstr::mmo_iterator,
5170              MachineInstr::mmo_iterator> MMOs =
5171      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5172                             cast<MachineSDNode>(N)->memoperands_end());
5173    if (!(*MMOs.first) &&
5174        RC == &X86::VR128RegClass &&
5175        !Subtarget.isUnalignedMemAccessFast())
5176      // Do not introduce a slow unaligned store.
5177      return false;
5178    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5179    bool isAligned = (*MMOs.first) &&
5180                     (*MMOs.first)->getAlignment() >= Alignment;
5181    SDNode *Store =
5182        DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5183                           dl, MVT::Other, AddrOps);
5184    NewNodes.push_back(Store);
5185
5186    // Preserve memory reference information.
5187    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5188  }
5189
5190  return true;
5191}
5192
5193unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5194                                      bool UnfoldLoad, bool UnfoldStore,
5195                                      unsigned *LoadRegIndex) const {
5196  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5197    MemOp2RegOpTable.find(Opc);
5198  if (I == MemOp2RegOpTable.end())
5199    return 0;
5200  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5201  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5202  if (UnfoldLoad && !FoldedLoad)
5203    return 0;
5204  if (UnfoldStore && !FoldedStore)
5205    return 0;
5206  if (LoadRegIndex)
5207    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5208  return I->second.first;
5209}
5210
5211bool
5212X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5213                                     int64_t &Offset1, int64_t &Offset2) const {
5214  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5215    return false;
5216  unsigned Opc1 = Load1->getMachineOpcode();
5217  unsigned Opc2 = Load2->getMachineOpcode();
5218  switch (Opc1) {
5219  default: return false;
5220  case X86::MOV8rm:
5221  case X86::MOV16rm:
5222  case X86::MOV32rm:
5223  case X86::MOV64rm:
5224  case X86::LD_Fp32m:
5225  case X86::LD_Fp64m:
5226  case X86::LD_Fp80m:
5227  case X86::MOVSSrm:
5228  case X86::MOVSDrm:
5229  case X86::MMX_MOVD64rm:
5230  case X86::MMX_MOVQ64rm:
5231  case X86::FsMOVAPSrm:
5232  case X86::FsMOVAPDrm:
5233  case X86::MOVAPSrm:
5234  case X86::MOVUPSrm:
5235  case X86::MOVAPDrm:
5236  case X86::MOVDQArm:
5237  case X86::MOVDQUrm:
5238  // AVX load instructions
5239  case X86::VMOVSSrm:
5240  case X86::VMOVSDrm:
5241  case X86::FsVMOVAPSrm:
5242  case X86::FsVMOVAPDrm:
5243  case X86::VMOVAPSrm:
5244  case X86::VMOVUPSrm:
5245  case X86::VMOVAPDrm:
5246  case X86::VMOVDQArm:
5247  case X86::VMOVDQUrm:
5248  case X86::VMOVAPSYrm:
5249  case X86::VMOVUPSYrm:
5250  case X86::VMOVAPDYrm:
5251  case X86::VMOVDQAYrm:
5252  case X86::VMOVDQUYrm:
5253    break;
5254  }
5255  switch (Opc2) {
5256  default: return false;
5257  case X86::MOV8rm:
5258  case X86::MOV16rm:
5259  case X86::MOV32rm:
5260  case X86::MOV64rm:
5261  case X86::LD_Fp32m:
5262  case X86::LD_Fp64m:
5263  case X86::LD_Fp80m:
5264  case X86::MOVSSrm:
5265  case X86::MOVSDrm:
5266  case X86::MMX_MOVD64rm:
5267  case X86::MMX_MOVQ64rm:
5268  case X86::FsMOVAPSrm:
5269  case X86::FsMOVAPDrm:
5270  case X86::MOVAPSrm:
5271  case X86::MOVUPSrm:
5272  case X86::MOVAPDrm:
5273  case X86::MOVDQArm:
5274  case X86::MOVDQUrm:
5275  // AVX load instructions
5276  case X86::VMOVSSrm:
5277  case X86::VMOVSDrm:
5278  case X86::FsVMOVAPSrm:
5279  case X86::FsVMOVAPDrm:
5280  case X86::VMOVAPSrm:
5281  case X86::VMOVUPSrm:
5282  case X86::VMOVAPDrm:
5283  case X86::VMOVDQArm:
5284  case X86::VMOVDQUrm:
5285  case X86::VMOVAPSYrm:
5286  case X86::VMOVUPSYrm:
5287  case X86::VMOVAPDYrm:
5288  case X86::VMOVDQAYrm:
5289  case X86::VMOVDQUYrm:
5290    break;
5291  }
5292
5293  // Check if chain operands and base addresses match.
5294  if (Load1->getOperand(0) != Load2->getOperand(0) ||
5295      Load1->getOperand(5) != Load2->getOperand(5))
5296    return false;
5297  // Segment operands should match as well.
5298  if (Load1->getOperand(4) != Load2->getOperand(4))
5299    return false;
5300  // Scale should be 1, Index should be Reg0.
5301  if (Load1->getOperand(1) == Load2->getOperand(1) &&
5302      Load1->getOperand(2) == Load2->getOperand(2)) {
5303    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5304      return false;
5305
5306    // Now let's examine the displacements.
5307    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5308        isa<ConstantSDNode>(Load2->getOperand(3))) {
5309      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5310      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5311      return true;
5312    }
5313  }
5314  return false;
5315}
5316
5317bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5318                                           int64_t Offset1, int64_t Offset2,
5319                                           unsigned NumLoads) const {
5320  assert(Offset2 > Offset1);
5321  if ((Offset2 - Offset1) / 8 > 64)
5322    return false;
5323
5324  unsigned Opc1 = Load1->getMachineOpcode();
5325  unsigned Opc2 = Load2->getMachineOpcode();
5326  if (Opc1 != Opc2)
5327    return false;  // FIXME: overly conservative?
5328
5329  switch (Opc1) {
5330  default: break;
5331  case X86::LD_Fp32m:
5332  case X86::LD_Fp64m:
5333  case X86::LD_Fp80m:
5334  case X86::MMX_MOVD64rm:
5335  case X86::MMX_MOVQ64rm:
5336    return false;
5337  }
5338
5339  EVT VT = Load1->getValueType(0);
5340  switch (VT.getSimpleVT().SimpleTy) {
5341  default:
5342    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5343    // have 16 of them to play with.
5344    if (Subtarget.is64Bit()) {
5345      if (NumLoads >= 3)
5346        return false;
5347    } else if (NumLoads) {
5348      return false;
5349    }
5350    break;
5351  case MVT::i8:
5352  case MVT::i16:
5353  case MVT::i32:
5354  case MVT::i64:
5355  case MVT::f32:
5356  case MVT::f64:
5357    if (NumLoads)
5358      return false;
5359    break;
5360  }
5361
5362  return true;
5363}
5364
5365bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5366                                          MachineInstr *Second) const {
5367  // Check if this processor supports macro-fusion. Since this is a minor
5368  // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5369  // proxy for SandyBridge+.
5370  if (!Subtarget.hasAVX())
5371    return false;
5372
5373  enum {
5374    FuseTest,
5375    FuseCmp,
5376    FuseInc
5377  } FuseKind;
5378
5379  switch(Second->getOpcode()) {
5380  default:
5381    return false;
5382  case X86::JE_1:
5383  case X86::JNE_1:
5384  case X86::JL_1:
5385  case X86::JLE_1:
5386  case X86::JG_1:
5387  case X86::JGE_1:
5388    FuseKind = FuseInc;
5389    break;
5390  case X86::JB_1:
5391  case X86::JBE_1:
5392  case X86::JA_1:
5393  case X86::JAE_1:
5394    FuseKind = FuseCmp;
5395    break;
5396  case X86::JS_1:
5397  case X86::JNS_1:
5398  case X86::JP_1:
5399  case X86::JNP_1:
5400  case X86::JO_1:
5401  case X86::JNO_1:
5402    FuseKind = FuseTest;
5403    break;
5404  }
5405  switch (First->getOpcode()) {
5406  default:
5407    return false;
5408  case X86::TEST8rr:
5409  case X86::TEST16rr:
5410  case X86::TEST32rr:
5411  case X86::TEST64rr:
5412  case X86::TEST8ri:
5413  case X86::TEST16ri:
5414  case X86::TEST32ri:
5415  case X86::TEST32i32:
5416  case X86::TEST64i32:
5417  case X86::TEST64ri32:
5418  case X86::TEST8rm:
5419  case X86::TEST16rm:
5420  case X86::TEST32rm:
5421  case X86::TEST64rm:
5422  case X86::TEST8ri_NOREX:
5423  case X86::AND16i16:
5424  case X86::AND16ri:
5425  case X86::AND16ri8:
5426  case X86::AND16rm:
5427  case X86::AND16rr:
5428  case X86::AND32i32:
5429  case X86::AND32ri:
5430  case X86::AND32ri8:
5431  case X86::AND32rm:
5432  case X86::AND32rr:
5433  case X86::AND64i32:
5434  case X86::AND64ri32:
5435  case X86::AND64ri8:
5436  case X86::AND64rm:
5437  case X86::AND64rr:
5438  case X86::AND8i8:
5439  case X86::AND8ri:
5440  case X86::AND8rm:
5441  case X86::AND8rr:
5442    return true;
5443  case X86::CMP16i16:
5444  case X86::CMP16ri:
5445  case X86::CMP16ri8:
5446  case X86::CMP16rm:
5447  case X86::CMP16rr:
5448  case X86::CMP32i32:
5449  case X86::CMP32ri:
5450  case X86::CMP32ri8:
5451  case X86::CMP32rm:
5452  case X86::CMP32rr:
5453  case X86::CMP64i32:
5454  case X86::CMP64ri32:
5455  case X86::CMP64ri8:
5456  case X86::CMP64rm:
5457  case X86::CMP64rr:
5458  case X86::CMP8i8:
5459  case X86::CMP8ri:
5460  case X86::CMP8rm:
5461  case X86::CMP8rr:
5462  case X86::ADD16i16:
5463  case X86::ADD16ri:
5464  case X86::ADD16ri8:
5465  case X86::ADD16ri8_DB:
5466  case X86::ADD16ri_DB:
5467  case X86::ADD16rm:
5468  case X86::ADD16rr:
5469  case X86::ADD16rr_DB:
5470  case X86::ADD32i32:
5471  case X86::ADD32ri:
5472  case X86::ADD32ri8:
5473  case X86::ADD32ri8_DB:
5474  case X86::ADD32ri_DB:
5475  case X86::ADD32rm:
5476  case X86::ADD32rr:
5477  case X86::ADD32rr_DB:
5478  case X86::ADD64i32:
5479  case X86::ADD64ri32:
5480  case X86::ADD64ri32_DB:
5481  case X86::ADD64ri8:
5482  case X86::ADD64ri8_DB:
5483  case X86::ADD64rm:
5484  case X86::ADD64rr:
5485  case X86::ADD64rr_DB:
5486  case X86::ADD8i8:
5487  case X86::ADD8mi:
5488  case X86::ADD8mr:
5489  case X86::ADD8ri:
5490  case X86::ADD8rm:
5491  case X86::ADD8rr:
5492  case X86::SUB16i16:
5493  case X86::SUB16ri:
5494  case X86::SUB16ri8:
5495  case X86::SUB16rm:
5496  case X86::SUB16rr:
5497  case X86::SUB32i32:
5498  case X86::SUB32ri:
5499  case X86::SUB32ri8:
5500  case X86::SUB32rm:
5501  case X86::SUB32rr:
5502  case X86::SUB64i32:
5503  case X86::SUB64ri32:
5504  case X86::SUB64ri8:
5505  case X86::SUB64rm:
5506  case X86::SUB64rr:
5507  case X86::SUB8i8:
5508  case X86::SUB8ri:
5509  case X86::SUB8rm:
5510  case X86::SUB8rr:
5511    return FuseKind == FuseCmp || FuseKind == FuseInc;
5512  case X86::INC16r:
5513  case X86::INC32r:
5514  case X86::INC64r:
5515  case X86::INC8r:
5516  case X86::DEC16r:
5517  case X86::DEC32r:
5518  case X86::DEC64r:
5519  case X86::DEC8r:
5520    return FuseKind == FuseInc;
5521  }
5522}
5523
5524bool X86InstrInfo::
5525ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5526  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5527  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5528  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5529    return true;
5530  Cond[0].setImm(GetOppositeBranchCondition(CC));
5531  return false;
5532}
5533
5534bool X86InstrInfo::
5535isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5536  // FIXME: Return false for x87 stack register classes for now. We can't
5537  // allow any loads of these registers before FpGet_ST0_80.
5538  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5539           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5540}
5541
5542/// getGlobalBaseReg - Return a virtual register initialized with the
5543/// the global base register value. Output instructions required to
5544/// initialize the register in the function entry block, if necessary.
5545///
5546/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5547///
5548unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5549  assert(!Subtarget.is64Bit() &&
5550         "X86-64 PIC uses RIP relative addressing");
5551
5552  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5553  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5554  if (GlobalBaseReg != 0)
5555    return GlobalBaseReg;
5556
5557  // Create the register. The code to initialize it is inserted
5558  // later, by the CGBR pass (below).
5559  MachineRegisterInfo &RegInfo = MF->getRegInfo();
5560  GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5561  X86FI->setGlobalBaseReg(GlobalBaseReg);
5562  return GlobalBaseReg;
5563}
5564
5565// These are the replaceable SSE instructions. Some of these have Int variants
5566// that we don't include here. We don't want to replace instructions selected
5567// by intrinsics.
5568static const uint16_t ReplaceableInstrs[][3] = {
5569  //PackedSingle     PackedDouble    PackedInt
5570  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5571  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5572  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5573  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5574  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5575  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5576  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5577  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5578  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5579  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5580  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5581  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5582  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5583  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5584  // AVX 128-bit support
5585  { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5586  { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5587  { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5588  { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5589  { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5590  { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5591  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5592  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5593  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5594  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5595  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5596  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5597  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5598  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5599  // AVX 256-bit support
5600  { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5601  { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5602  { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5603  { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5604  { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5605  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5606};
5607
5608static const uint16_t ReplaceableInstrsAVX2[][3] = {
5609  //PackedSingle       PackedDouble       PackedInt
5610  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5611  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5612  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5613  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5614  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5615  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5616  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5617  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5618  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5619  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5620  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5621  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5622  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5623  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
5624  { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5625  { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5626  { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5627  { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5628  { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5629  { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5630};
5631
5632// FIXME: Some shuffle and unpack instructions have equivalents in different
5633// domains, but they require a bit more work than just switching opcodes.
5634
5635static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5636  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5637    if (ReplaceableInstrs[i][domain-1] == opcode)
5638      return ReplaceableInstrs[i];
5639  return nullptr;
5640}
5641
5642static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5643  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5644    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5645      return ReplaceableInstrsAVX2[i];
5646  return nullptr;
5647}
5648
5649std::pair<uint16_t, uint16_t>
5650X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5651  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5652  bool hasAVX2 = Subtarget.hasAVX2();
5653  uint16_t validDomains = 0;
5654  if (domain && lookup(MI->getOpcode(), domain))
5655    validDomains = 0xe;
5656  else if (domain && lookupAVX2(MI->getOpcode(), domain))
5657    validDomains = hasAVX2 ? 0xe : 0x6;
5658  return std::make_pair(domain, validDomains);
5659}
5660
5661void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5662  assert(Domain>0 && Domain<4 && "Invalid execution domain");
5663  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5664  assert(dom && "Not an SSE instruction");
5665  const uint16_t *table = lookup(MI->getOpcode(), dom);
5666  if (!table) { // try the other table
5667    assert((Subtarget.hasAVX2() || Domain < 3) &&
5668           "256-bit vector operations only available in AVX2");
5669    table = lookupAVX2(MI->getOpcode(), dom);
5670  }
5671  assert(table && "Cannot change domain");
5672  MI->setDesc(get(table[Domain-1]));
5673}
5674
5675/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5676void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5677  NopInst.setOpcode(X86::NOOP);
5678}
5679
5680// This code must remain in sync with getJumpInstrTableEntryBound in this class!
5681// In particular, getJumpInstrTableEntryBound must always return an upper bound
5682// on the encoding lengths of the instructions generated by
5683// getUnconditionalBranch and getTrap.
5684void X86InstrInfo::getUnconditionalBranch(
5685    MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
5686  Branch.setOpcode(X86::JMP_1);
5687  Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5688}
5689
5690// This code must remain in sync with getJumpInstrTableEntryBound in this class!
5691// In particular, getJumpInstrTableEntryBound must always return an upper bound
5692// on the encoding lengths of the instructions generated by
5693// getUnconditionalBranch and getTrap.
5694void X86InstrInfo::getTrap(MCInst &MI) const {
5695  MI.setOpcode(X86::TRAP);
5696}
5697
5698// See getTrap and getUnconditionalBranch for conditions on the value returned
5699// by this function.
5700unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
5701  // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
5702  // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
5703  return 5;
5704}
5705
5706bool X86InstrInfo::isHighLatencyDef(int opc) const {
5707  switch (opc) {
5708  default: return false;
5709  case X86::DIVSDrm:
5710  case X86::DIVSDrm_Int:
5711  case X86::DIVSDrr:
5712  case X86::DIVSDrr_Int:
5713  case X86::DIVSSrm:
5714  case X86::DIVSSrm_Int:
5715  case X86::DIVSSrr:
5716  case X86::DIVSSrr_Int:
5717  case X86::SQRTPDm:
5718  case X86::SQRTPDr:
5719  case X86::SQRTPSm:
5720  case X86::SQRTPSr:
5721  case X86::SQRTSDm:
5722  case X86::SQRTSDm_Int:
5723  case X86::SQRTSDr:
5724  case X86::SQRTSDr_Int:
5725  case X86::SQRTSSm:
5726  case X86::SQRTSSm_Int:
5727  case X86::SQRTSSr:
5728  case X86::SQRTSSr_Int:
5729  // AVX instructions with high latency
5730  case X86::VDIVSDrm:
5731  case X86::VDIVSDrm_Int:
5732  case X86::VDIVSDrr:
5733  case X86::VDIVSDrr_Int:
5734  case X86::VDIVSSrm:
5735  case X86::VDIVSSrm_Int:
5736  case X86::VDIVSSrr:
5737  case X86::VDIVSSrr_Int:
5738  case X86::VSQRTPDm:
5739  case X86::VSQRTPDr:
5740  case X86::VSQRTPSm:
5741  case X86::VSQRTPSr:
5742  case X86::VSQRTSDm:
5743  case X86::VSQRTSDm_Int:
5744  case X86::VSQRTSDr:
5745  case X86::VSQRTSSm:
5746  case X86::VSQRTSSm_Int:
5747  case X86::VSQRTSSr:
5748  case X86::VSQRTPDZm:
5749  case X86::VSQRTPDZr:
5750  case X86::VSQRTPSZm:
5751  case X86::VSQRTPSZr:
5752  case X86::VSQRTSDZm:
5753  case X86::VSQRTSDZm_Int:
5754  case X86::VSQRTSDZr:
5755  case X86::VSQRTSSZm_Int:
5756  case X86::VSQRTSSZr:
5757  case X86::VSQRTSSZm:
5758  case X86::VDIVSDZrm:
5759  case X86::VDIVSDZrr:
5760  case X86::VDIVSSZrm:
5761  case X86::VDIVSSZrr:
5762
5763  case X86::VGATHERQPSZrm:
5764  case X86::VGATHERQPDZrm:
5765  case X86::VGATHERDPDZrm:
5766  case X86::VGATHERDPSZrm:
5767  case X86::VPGATHERQDZrm:
5768  case X86::VPGATHERQQZrm:
5769  case X86::VPGATHERDDZrm:
5770  case X86::VPGATHERDQZrm:
5771  case X86::VSCATTERQPDZmr:
5772  case X86::VSCATTERQPSZmr:
5773  case X86::VSCATTERDPDZmr:
5774  case X86::VSCATTERDPSZmr:
5775  case X86::VPSCATTERQDZmr:
5776  case X86::VPSCATTERQQZmr:
5777  case X86::VPSCATTERDDZmr:
5778  case X86::VPSCATTERDQZmr:
5779    return true;
5780  }
5781}
5782
5783bool X86InstrInfo::
5784hasHighOperandLatency(const InstrItineraryData *ItinData,
5785                      const MachineRegisterInfo *MRI,
5786                      const MachineInstr *DefMI, unsigned DefIdx,
5787                      const MachineInstr *UseMI, unsigned UseIdx) const {
5788  return isHighLatencyDef(DefMI->getOpcode());
5789}
5790
5791namespace {
5792  /// CGBR - Create Global Base Reg pass. This initializes the PIC
5793  /// global base register for x86-32.
5794  struct CGBR : public MachineFunctionPass {
5795    static char ID;
5796    CGBR() : MachineFunctionPass(ID) {}
5797
5798    bool runOnMachineFunction(MachineFunction &MF) override {
5799      const X86TargetMachine *TM =
5800        static_cast<const X86TargetMachine *>(&MF.getTarget());
5801
5802      // Don't do anything if this is 64-bit as 64-bit PIC
5803      // uses RIP relative addressing.
5804      if (TM->getSubtarget<X86Subtarget>().is64Bit())
5805        return false;
5806
5807      // Only emit a global base reg in PIC mode.
5808      if (TM->getRelocationModel() != Reloc::PIC_)
5809        return false;
5810
5811      X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5812      unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5813
5814      // If we didn't need a GlobalBaseReg, don't insert code.
5815      if (GlobalBaseReg == 0)
5816        return false;
5817
5818      // Insert the set of GlobalBaseReg into the first MBB of the function
5819      MachineBasicBlock &FirstMBB = MF.front();
5820      MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5821      DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5822      MachineRegisterInfo &RegInfo = MF.getRegInfo();
5823      const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5824
5825      unsigned PC;
5826      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5827        PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5828      else
5829        PC = GlobalBaseReg;
5830
5831      // Operand of MovePCtoStack is completely ignored by asm printer. It's
5832      // only used in JIT code emission as displacement to pc.
5833      BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5834
5835      // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5836      // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5837      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5838        // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5839        BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5840          .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5841                                        X86II::MO_GOT_ABSOLUTE_ADDRESS);
5842      }
5843
5844      return true;
5845    }
5846
5847    const char *getPassName() const override {
5848      return "X86 PIC Global Base Reg Initialization";
5849    }
5850
5851    void getAnalysisUsage(AnalysisUsage &AU) const override {
5852      AU.setPreservesCFG();
5853      MachineFunctionPass::getAnalysisUsage(AU);
5854    }
5855  };
5856}
5857
5858char CGBR::ID = 0;
5859FunctionPass*
5860llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
5861
5862namespace {
5863  struct LDTLSCleanup : public MachineFunctionPass {
5864    static char ID;
5865    LDTLSCleanup() : MachineFunctionPass(ID) {}
5866
5867    bool runOnMachineFunction(MachineFunction &MF) override {
5868      X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5869      if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5870        // No point folding accesses if there isn't at least two.
5871        return false;
5872      }
5873
5874      MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5875      return VisitNode(DT->getRootNode(), 0);
5876    }
5877
5878    // Visit the dominator subtree rooted at Node in pre-order.
5879    // If TLSBaseAddrReg is non-null, then use that to replace any
5880    // TLS_base_addr instructions. Otherwise, create the register
5881    // when the first such instruction is seen, and then use it
5882    // as we encounter more instructions.
5883    bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5884      MachineBasicBlock *BB = Node->getBlock();
5885      bool Changed = false;
5886
5887      // Traverse the current block.
5888      for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5889           ++I) {
5890        switch (I->getOpcode()) {
5891          case X86::TLS_base_addr32:
5892          case X86::TLS_base_addr64:
5893            if (TLSBaseAddrReg)
5894              I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5895            else
5896              I = SetRegister(I, &TLSBaseAddrReg);
5897            Changed = true;
5898            break;
5899          default:
5900            break;
5901        }
5902      }
5903
5904      // Visit the children of this block in the dominator tree.
5905      for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5906           I != E; ++I) {
5907        Changed |= VisitNode(*I, TLSBaseAddrReg);
5908      }
5909
5910      return Changed;
5911    }
5912
5913    // Replace the TLS_base_addr instruction I with a copy from
5914    // TLSBaseAddrReg, returning the new instruction.
5915    MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5916                                         unsigned TLSBaseAddrReg) {
5917      MachineFunction *MF = I->getParent()->getParent();
5918      const X86TargetMachine *TM =
5919          static_cast<const X86TargetMachine *>(&MF->getTarget());
5920      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5921      const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5922
5923      // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5924      MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5925                                   TII->get(TargetOpcode::COPY),
5926                                   is64Bit ? X86::RAX : X86::EAX)
5927                                   .addReg(TLSBaseAddrReg);
5928
5929      // Erase the TLS_base_addr instruction.
5930      I->eraseFromParent();
5931
5932      return Copy;
5933    }
5934
5935    // Create a virtal register in *TLSBaseAddrReg, and populate it by
5936    // inserting a copy instruction after I. Returns the new instruction.
5937    MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5938      MachineFunction *MF = I->getParent()->getParent();
5939      const X86TargetMachine *TM =
5940          static_cast<const X86TargetMachine *>(&MF->getTarget());
5941      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5942      const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5943
5944      // Create a virtual register for the TLS base address.
5945      MachineRegisterInfo &RegInfo = MF->getRegInfo();
5946      *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5947                                                      ? &X86::GR64RegClass
5948                                                      : &X86::GR32RegClass);
5949
5950      // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5951      MachineInstr *Next = I->getNextNode();
5952      MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5953                                   TII->get(TargetOpcode::COPY),
5954                                   *TLSBaseAddrReg)
5955                                   .addReg(is64Bit ? X86::RAX : X86::EAX);
5956
5957      return Copy;
5958    }
5959
5960    const char *getPassName() const override {
5961      return "Local Dynamic TLS Access Clean-up";
5962    }
5963
5964    void getAnalysisUsage(AnalysisUsage &AU) const override {
5965      AU.setPreservesCFG();
5966      AU.addRequired<MachineDominatorTree>();
5967      MachineFunctionPass::getAnalysisUsage(AU);
5968    }
5969  };
5970}
5971
5972char LDTLSCleanup::ID = 0;
5973FunctionPass*
5974llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5975