X86InstrInfo.cpp revision 256090
1234353Sdim//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the X86 implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "X86InstrInfo.h" 15193323Sed#include "X86.h" 16193323Sed#include "X86InstrBuilder.h" 17193323Sed#include "X86MachineFunctionInfo.h" 18193323Sed#include "X86Subtarget.h" 19193323Sed#include "X86TargetMachine.h" 20193323Sed#include "llvm/ADT/STLExtras.h" 21249423Sdim#include "llvm/CodeGen/LiveVariables.h" 22193323Sed#include "llvm/CodeGen/MachineConstantPool.h" 23239462Sdim#include "llvm/CodeGen/MachineDominators.h" 24193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 25193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 26193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 27249423Sdim#include "llvm/IR/DerivedTypes.h" 28249423Sdim#include "llvm/IR/LLVMContext.h" 29234353Sdim#include "llvm/MC/MCAsmInfo.h" 30207618Srdivacky#include "llvm/MC/MCInst.h" 31193323Sed#include "llvm/Support/CommandLine.h" 32202375Srdivacky#include "llvm/Support/Debug.h" 33198090Srdivacky#include "llvm/Support/ErrorHandling.h" 34198090Srdivacky#include "llvm/Support/raw_ostream.h" 35193323Sed#include "llvm/Target/TargetOptions.h" 36199481Srdivacky#include <limits> 37199481Srdivacky 38224145Sdim#define GET_INSTRINFO_CTOR 39224145Sdim#include "X86GenInstrInfo.inc" 40224145Sdim 41193323Sedusing namespace llvm; 42193323Sed 43198090Srdivackystatic cl::opt<bool> 44198090SrdivackyNoFusing("disable-spill-fusing", 45198090Srdivacky cl::desc("Disable fusing of spill code into instructions")); 46198090Srdivackystatic cl::opt<bool> 47198090SrdivackyPrintFailedFusing("print-failed-fuse-candidates", 48198090Srdivacky cl::desc("Print instructions that the allocator wants to" 49198090Srdivacky " fuse, but the X86 backend currently can't"), 50198090Srdivacky cl::Hidden); 51198090Srdivackystatic cl::opt<bool> 52198090SrdivackyReMatPICStubLoad("remat-pic-stub-load", 53198090Srdivacky cl::desc("Re-materialize load from stub in PIC mode"), 54198090Srdivacky cl::init(false), cl::Hidden); 55193323Sed 56226633Sdimenum { 57226633Sdim // Select which memory operand is being unfolded. 58239462Sdim // (stored in bits 0 - 3) 59226633Sdim TB_INDEX_0 = 0, 60226633Sdim TB_INDEX_1 = 1, 61226633Sdim TB_INDEX_2 = 2, 62239462Sdim TB_INDEX_3 = 3, 63239462Sdim TB_INDEX_MASK = 0xf, 64226633Sdim 65239462Sdim // Do not insert the reverse map (MemOp -> RegOp) into the table. 66239462Sdim // This may be needed because there is a many -> one mapping. 67239462Sdim TB_NO_REVERSE = 1 << 4, 68239462Sdim 69239462Sdim // Do not insert the forward map (RegOp -> MemOp) into the table. 70239462Sdim // This is needed for Native Client, which prohibits branch 71239462Sdim // instructions from using a memory operand. 72239462Sdim TB_NO_FORWARD = 1 << 5, 73239462Sdim 74239462Sdim TB_FOLDED_LOAD = 1 << 6, 75239462Sdim TB_FOLDED_STORE = 1 << 7, 76239462Sdim 77226633Sdim // Minimum alignment required for load/store. 78226633Sdim // Used for RegOp->MemOp conversion. 79226633Sdim // (stored in bits 8 - 15) 80226633Sdim TB_ALIGN_SHIFT = 8, 81226633Sdim TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 82226633Sdim TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 83226633Sdim TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 84239462Sdim TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 85226633Sdim}; 86226633Sdim 87234353Sdimstruct X86OpTblEntry { 88234353Sdim uint16_t RegOp; 89234353Sdim uint16_t MemOp; 90239462Sdim uint16_t Flags; 91234353Sdim}; 92234353Sdim 93193323SedX86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 94224145Sdim : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 95224145Sdim ? X86::ADJCALLSTACKDOWN64 96224145Sdim : X86::ADJCALLSTACKDOWN32), 97224145Sdim (tm.getSubtarget<X86Subtarget>().is64Bit() 98224145Sdim ? X86::ADJCALLSTACKUP64 99224145Sdim : X86::ADJCALLSTACKUP32)), 100193323Sed TM(tm), RI(tm, *this) { 101218893Sdim 102234353Sdim static const X86OpTblEntry OpTbl2Addr[] = { 103226633Sdim { X86::ADC32ri, X86::ADC32mi, 0 }, 104226633Sdim { X86::ADC32ri8, X86::ADC32mi8, 0 }, 105226633Sdim { X86::ADC32rr, X86::ADC32mr, 0 }, 106226633Sdim { X86::ADC64ri32, X86::ADC64mi32, 0 }, 107226633Sdim { X86::ADC64ri8, X86::ADC64mi8, 0 }, 108226633Sdim { X86::ADC64rr, X86::ADC64mr, 0 }, 109226633Sdim { X86::ADD16ri, X86::ADD16mi, 0 }, 110226633Sdim { X86::ADD16ri8, X86::ADD16mi8, 0 }, 111226633Sdim { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 112226633Sdim { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 113226633Sdim { X86::ADD16rr, X86::ADD16mr, 0 }, 114226633Sdim { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 115226633Sdim { X86::ADD32ri, X86::ADD32mi, 0 }, 116226633Sdim { X86::ADD32ri8, X86::ADD32mi8, 0 }, 117226633Sdim { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 118226633Sdim { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 119226633Sdim { X86::ADD32rr, X86::ADD32mr, 0 }, 120226633Sdim { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 121226633Sdim { X86::ADD64ri32, X86::ADD64mi32, 0 }, 122226633Sdim { X86::ADD64ri8, X86::ADD64mi8, 0 }, 123226633Sdim { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 124226633Sdim { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 125226633Sdim { X86::ADD64rr, X86::ADD64mr, 0 }, 126226633Sdim { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 127226633Sdim { X86::ADD8ri, X86::ADD8mi, 0 }, 128226633Sdim { X86::ADD8rr, X86::ADD8mr, 0 }, 129226633Sdim { X86::AND16ri, X86::AND16mi, 0 }, 130226633Sdim { X86::AND16ri8, X86::AND16mi8, 0 }, 131226633Sdim { X86::AND16rr, X86::AND16mr, 0 }, 132226633Sdim { X86::AND32ri, X86::AND32mi, 0 }, 133226633Sdim { X86::AND32ri8, X86::AND32mi8, 0 }, 134226633Sdim { X86::AND32rr, X86::AND32mr, 0 }, 135226633Sdim { X86::AND64ri32, X86::AND64mi32, 0 }, 136226633Sdim { X86::AND64ri8, X86::AND64mi8, 0 }, 137226633Sdim { X86::AND64rr, X86::AND64mr, 0 }, 138226633Sdim { X86::AND8ri, X86::AND8mi, 0 }, 139226633Sdim { X86::AND8rr, X86::AND8mr, 0 }, 140226633Sdim { X86::DEC16r, X86::DEC16m, 0 }, 141226633Sdim { X86::DEC32r, X86::DEC32m, 0 }, 142226633Sdim { X86::DEC64_16r, X86::DEC64_16m, 0 }, 143226633Sdim { X86::DEC64_32r, X86::DEC64_32m, 0 }, 144226633Sdim { X86::DEC64r, X86::DEC64m, 0 }, 145226633Sdim { X86::DEC8r, X86::DEC8m, 0 }, 146226633Sdim { X86::INC16r, X86::INC16m, 0 }, 147226633Sdim { X86::INC32r, X86::INC32m, 0 }, 148226633Sdim { X86::INC64_16r, X86::INC64_16m, 0 }, 149226633Sdim { X86::INC64_32r, X86::INC64_32m, 0 }, 150226633Sdim { X86::INC64r, X86::INC64m, 0 }, 151226633Sdim { X86::INC8r, X86::INC8m, 0 }, 152226633Sdim { X86::NEG16r, X86::NEG16m, 0 }, 153226633Sdim { X86::NEG32r, X86::NEG32m, 0 }, 154226633Sdim { X86::NEG64r, X86::NEG64m, 0 }, 155226633Sdim { X86::NEG8r, X86::NEG8m, 0 }, 156226633Sdim { X86::NOT16r, X86::NOT16m, 0 }, 157226633Sdim { X86::NOT32r, X86::NOT32m, 0 }, 158226633Sdim { X86::NOT64r, X86::NOT64m, 0 }, 159226633Sdim { X86::NOT8r, X86::NOT8m, 0 }, 160226633Sdim { X86::OR16ri, X86::OR16mi, 0 }, 161226633Sdim { X86::OR16ri8, X86::OR16mi8, 0 }, 162226633Sdim { X86::OR16rr, X86::OR16mr, 0 }, 163226633Sdim { X86::OR32ri, X86::OR32mi, 0 }, 164226633Sdim { X86::OR32ri8, X86::OR32mi8, 0 }, 165226633Sdim { X86::OR32rr, X86::OR32mr, 0 }, 166226633Sdim { X86::OR64ri32, X86::OR64mi32, 0 }, 167226633Sdim { X86::OR64ri8, X86::OR64mi8, 0 }, 168226633Sdim { X86::OR64rr, X86::OR64mr, 0 }, 169226633Sdim { X86::OR8ri, X86::OR8mi, 0 }, 170226633Sdim { X86::OR8rr, X86::OR8mr, 0 }, 171226633Sdim { X86::ROL16r1, X86::ROL16m1, 0 }, 172226633Sdim { X86::ROL16rCL, X86::ROL16mCL, 0 }, 173226633Sdim { X86::ROL16ri, X86::ROL16mi, 0 }, 174226633Sdim { X86::ROL32r1, X86::ROL32m1, 0 }, 175226633Sdim { X86::ROL32rCL, X86::ROL32mCL, 0 }, 176226633Sdim { X86::ROL32ri, X86::ROL32mi, 0 }, 177226633Sdim { X86::ROL64r1, X86::ROL64m1, 0 }, 178226633Sdim { X86::ROL64rCL, X86::ROL64mCL, 0 }, 179226633Sdim { X86::ROL64ri, X86::ROL64mi, 0 }, 180226633Sdim { X86::ROL8r1, X86::ROL8m1, 0 }, 181226633Sdim { X86::ROL8rCL, X86::ROL8mCL, 0 }, 182226633Sdim { X86::ROL8ri, X86::ROL8mi, 0 }, 183226633Sdim { X86::ROR16r1, X86::ROR16m1, 0 }, 184226633Sdim { X86::ROR16rCL, X86::ROR16mCL, 0 }, 185226633Sdim { X86::ROR16ri, X86::ROR16mi, 0 }, 186226633Sdim { X86::ROR32r1, X86::ROR32m1, 0 }, 187226633Sdim { X86::ROR32rCL, X86::ROR32mCL, 0 }, 188226633Sdim { X86::ROR32ri, X86::ROR32mi, 0 }, 189226633Sdim { X86::ROR64r1, X86::ROR64m1, 0 }, 190226633Sdim { X86::ROR64rCL, X86::ROR64mCL, 0 }, 191226633Sdim { X86::ROR64ri, X86::ROR64mi, 0 }, 192226633Sdim { X86::ROR8r1, X86::ROR8m1, 0 }, 193226633Sdim { X86::ROR8rCL, X86::ROR8mCL, 0 }, 194226633Sdim { X86::ROR8ri, X86::ROR8mi, 0 }, 195226633Sdim { X86::SAR16r1, X86::SAR16m1, 0 }, 196226633Sdim { X86::SAR16rCL, X86::SAR16mCL, 0 }, 197226633Sdim { X86::SAR16ri, X86::SAR16mi, 0 }, 198226633Sdim { X86::SAR32r1, X86::SAR32m1, 0 }, 199226633Sdim { X86::SAR32rCL, X86::SAR32mCL, 0 }, 200226633Sdim { X86::SAR32ri, X86::SAR32mi, 0 }, 201226633Sdim { X86::SAR64r1, X86::SAR64m1, 0 }, 202226633Sdim { X86::SAR64rCL, X86::SAR64mCL, 0 }, 203226633Sdim { X86::SAR64ri, X86::SAR64mi, 0 }, 204226633Sdim { X86::SAR8r1, X86::SAR8m1, 0 }, 205226633Sdim { X86::SAR8rCL, X86::SAR8mCL, 0 }, 206226633Sdim { X86::SAR8ri, X86::SAR8mi, 0 }, 207226633Sdim { X86::SBB32ri, X86::SBB32mi, 0 }, 208226633Sdim { X86::SBB32ri8, X86::SBB32mi8, 0 }, 209226633Sdim { X86::SBB32rr, X86::SBB32mr, 0 }, 210226633Sdim { X86::SBB64ri32, X86::SBB64mi32, 0 }, 211226633Sdim { X86::SBB64ri8, X86::SBB64mi8, 0 }, 212226633Sdim { X86::SBB64rr, X86::SBB64mr, 0 }, 213226633Sdim { X86::SHL16rCL, X86::SHL16mCL, 0 }, 214226633Sdim { X86::SHL16ri, X86::SHL16mi, 0 }, 215226633Sdim { X86::SHL32rCL, X86::SHL32mCL, 0 }, 216226633Sdim { X86::SHL32ri, X86::SHL32mi, 0 }, 217226633Sdim { X86::SHL64rCL, X86::SHL64mCL, 0 }, 218226633Sdim { X86::SHL64ri, X86::SHL64mi, 0 }, 219226633Sdim { X86::SHL8rCL, X86::SHL8mCL, 0 }, 220226633Sdim { X86::SHL8ri, X86::SHL8mi, 0 }, 221226633Sdim { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 222226633Sdim { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 223226633Sdim { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 224226633Sdim { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 225226633Sdim { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 226226633Sdim { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 227226633Sdim { X86::SHR16r1, X86::SHR16m1, 0 }, 228226633Sdim { X86::SHR16rCL, X86::SHR16mCL, 0 }, 229226633Sdim { X86::SHR16ri, X86::SHR16mi, 0 }, 230226633Sdim { X86::SHR32r1, X86::SHR32m1, 0 }, 231226633Sdim { X86::SHR32rCL, X86::SHR32mCL, 0 }, 232226633Sdim { X86::SHR32ri, X86::SHR32mi, 0 }, 233226633Sdim { X86::SHR64r1, X86::SHR64m1, 0 }, 234226633Sdim { X86::SHR64rCL, X86::SHR64mCL, 0 }, 235226633Sdim { X86::SHR64ri, X86::SHR64mi, 0 }, 236226633Sdim { X86::SHR8r1, X86::SHR8m1, 0 }, 237226633Sdim { X86::SHR8rCL, X86::SHR8mCL, 0 }, 238226633Sdim { X86::SHR8ri, X86::SHR8mi, 0 }, 239226633Sdim { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 240226633Sdim { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 241226633Sdim { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 242226633Sdim { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 243226633Sdim { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 244226633Sdim { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 245226633Sdim { X86::SUB16ri, X86::SUB16mi, 0 }, 246226633Sdim { X86::SUB16ri8, X86::SUB16mi8, 0 }, 247226633Sdim { X86::SUB16rr, X86::SUB16mr, 0 }, 248226633Sdim { X86::SUB32ri, X86::SUB32mi, 0 }, 249226633Sdim { X86::SUB32ri8, X86::SUB32mi8, 0 }, 250226633Sdim { X86::SUB32rr, X86::SUB32mr, 0 }, 251226633Sdim { X86::SUB64ri32, X86::SUB64mi32, 0 }, 252226633Sdim { X86::SUB64ri8, X86::SUB64mi8, 0 }, 253226633Sdim { X86::SUB64rr, X86::SUB64mr, 0 }, 254226633Sdim { X86::SUB8ri, X86::SUB8mi, 0 }, 255226633Sdim { X86::SUB8rr, X86::SUB8mr, 0 }, 256226633Sdim { X86::XOR16ri, X86::XOR16mi, 0 }, 257226633Sdim { X86::XOR16ri8, X86::XOR16mi8, 0 }, 258226633Sdim { X86::XOR16rr, X86::XOR16mr, 0 }, 259226633Sdim { X86::XOR32ri, X86::XOR32mi, 0 }, 260226633Sdim { X86::XOR32ri8, X86::XOR32mi8, 0 }, 261226633Sdim { X86::XOR32rr, X86::XOR32mr, 0 }, 262226633Sdim { X86::XOR64ri32, X86::XOR64mi32, 0 }, 263226633Sdim { X86::XOR64ri8, X86::XOR64mi8, 0 }, 264226633Sdim { X86::XOR64rr, X86::XOR64mr, 0 }, 265226633Sdim { X86::XOR8ri, X86::XOR8mi, 0 }, 266226633Sdim { X86::XOR8rr, X86::XOR8mr, 0 } 267193323Sed }; 268193323Sed 269193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 270234353Sdim unsigned RegOp = OpTbl2Addr[i].RegOp; 271234353Sdim unsigned MemOp = OpTbl2Addr[i].MemOp; 272234353Sdim unsigned Flags = OpTbl2Addr[i].Flags; 273226633Sdim AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 274226633Sdim RegOp, MemOp, 275226633Sdim // Index 0, folded load and store, no alignment requirement. 276226633Sdim Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 277193323Sed } 278193323Sed 279234353Sdim static const X86OpTblEntry OpTbl0[] = { 280226633Sdim { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 281226633Sdim { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 282226633Sdim { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 283226633Sdim { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 284226633Sdim { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 285226633Sdim { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 286226633Sdim { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 287226633Sdim { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 288226633Sdim { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 289226633Sdim { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 290226633Sdim { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 291226633Sdim { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 292226633Sdim { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 293226633Sdim { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 294226633Sdim { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 295226633Sdim { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 296226633Sdim { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 297226633Sdim { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 298226633Sdim { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 299226633Sdim { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 300249423Sdim { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 301226633Sdim { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 302226633Sdim { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 303226633Sdim { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304226633Sdim { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305226633Sdim { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306226633Sdim { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307226633Sdim { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308226633Sdim { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309226633Sdim { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310226633Sdim { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311226633Sdim { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312226633Sdim { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313226633Sdim { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314226633Sdim { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315226633Sdim { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316226633Sdim { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317226633Sdim { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318226633Sdim { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319226633Sdim { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320226633Sdim { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321226633Sdim { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322226633Sdim { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323226633Sdim { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324226633Sdim { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325226633Sdim { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326226633Sdim { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327226633Sdim { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328226633Sdim { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329226633Sdim { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330226633Sdim { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331226633Sdim { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332226633Sdim { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333226633Sdim { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334226633Sdim { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335226633Sdim { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 336226633Sdim { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 337226633Sdim { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 338226633Sdim { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 339226633Sdim { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 340226633Sdim { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 341226633Sdim { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 342226633Sdim { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 343226633Sdim { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 344226633Sdim { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 345226633Sdim { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 346226633Sdim { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 347226633Sdim { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 348226633Sdim { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 349226633Sdim { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 350226633Sdim { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 351226633Sdim { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 352226633Sdim { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 353226633Sdim { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 354226633Sdim { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 355226633Sdim { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 356226633Sdim { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 357226633Sdim // AVX 128-bit versions of foldable instructions 358249423Sdim { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 359226633Sdim { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 360226633Sdim { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 361234353Sdim { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362226633Sdim { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363226633Sdim { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364226633Sdim { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365226633Sdim { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 366226633Sdim { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 367226633Sdim { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 368226633Sdim { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 369226633Sdim { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 370226633Sdim { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 371226633Sdim // AVX 256-bit foldable instructions 372234353Sdim { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 373226633Sdim { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374226633Sdim { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375226633Sdim { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376226633Sdim { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 377226633Sdim { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE } 378193323Sed }; 379193323Sed 380193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 381234353Sdim unsigned RegOp = OpTbl0[i].RegOp; 382234353Sdim unsigned MemOp = OpTbl0[i].MemOp; 383234353Sdim unsigned Flags = OpTbl0[i].Flags; 384226633Sdim AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 385226633Sdim RegOp, MemOp, TB_INDEX_0 | Flags); 386193323Sed } 387193323Sed 388234353Sdim static const X86OpTblEntry OpTbl1[] = { 389226633Sdim { X86::CMP16rr, X86::CMP16rm, 0 }, 390226633Sdim { X86::CMP32rr, X86::CMP32rm, 0 }, 391226633Sdim { X86::CMP64rr, X86::CMP64rm, 0 }, 392226633Sdim { X86::CMP8rr, X86::CMP8rm, 0 }, 393226633Sdim { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 394226633Sdim { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 395226633Sdim { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 396226633Sdim { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 397226633Sdim { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 398226633Sdim { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 399226633Sdim { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 400226633Sdim { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 401226633Sdim { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 402226633Sdim { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 403226633Sdim { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE }, 404226633Sdim { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE }, 405226633Sdim { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 406226633Sdim { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 407226633Sdim { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 408226633Sdim { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 409226633Sdim { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 410226633Sdim { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 411226633Sdim { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 412226633Sdim { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 413226633Sdim { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 414226633Sdim { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 415239462Sdim { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 416239462Sdim { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 417226633Sdim { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 418226633Sdim { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 419226633Sdim { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 420226633Sdim { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 421226633Sdim { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 422226633Sdim { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 423226633Sdim { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 424226633Sdim { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 425226633Sdim { X86::MOV16rr, X86::MOV16rm, 0 }, 426226633Sdim { X86::MOV32rr, X86::MOV32rm, 0 }, 427226633Sdim { X86::MOV64rr, X86::MOV64rm, 0 }, 428226633Sdim { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 429226633Sdim { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 430226633Sdim { X86::MOV8rr, X86::MOV8rm, 0 }, 431226633Sdim { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 432226633Sdim { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 433226633Sdim { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 434226633Sdim { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 435226633Sdim { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 436226633Sdim { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 437226633Sdim { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 438226633Sdim { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 439226633Sdim { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 440226633Sdim { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 441226633Sdim { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 442226633Sdim { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 443226633Sdim { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 444226633Sdim { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 445226633Sdim { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 446226633Sdim { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 447226633Sdim { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 448226633Sdim { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449226633Sdim { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450226633Sdim { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451226633Sdim { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452226633Sdim { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453226633Sdim { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454226633Sdim { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 455226633Sdim { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 456226633Sdim { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 457234353Sdim { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 458234353Sdim { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 459234353Sdim { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 460226633Sdim { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 461226633Sdim { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 462226633Sdim { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 463226633Sdim { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 464226633Sdim { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 465226633Sdim { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 466226633Sdim { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 467226633Sdim { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 468226633Sdim { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 469226633Sdim { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 470226633Sdim { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 471226633Sdim { X86::SQRTSDr, X86::SQRTSDm, 0 }, 472226633Sdim { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 473226633Sdim { X86::SQRTSSr, X86::SQRTSSm, 0 }, 474226633Sdim { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 475226633Sdim { X86::TEST16rr, X86::TEST16rm, 0 }, 476226633Sdim { X86::TEST32rr, X86::TEST32rm, 0 }, 477226633Sdim { X86::TEST64rr, X86::TEST64rm, 0 }, 478226633Sdim { X86::TEST8rr, X86::TEST8rm, 0 }, 479193323Sed // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 480226633Sdim { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 481226633Sdim { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 482226633Sdim // AVX 128-bit versions of foldable instructions 483226633Sdim { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 484226633Sdim { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 485226633Sdim { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 486226633Sdim { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 487239462Sdim { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 488239462Sdim { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 489239462Sdim { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 490239462Sdim { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 491239462Sdim { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 492239462Sdim { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 493239462Sdim { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 494239462Sdim { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 495239462Sdim { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 496239462Sdim { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 497239462Sdim { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 498239462Sdim { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 499226633Sdim { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE }, 500226633Sdim { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE }, 501226633Sdim { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 502226633Sdim { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 503226633Sdim { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 504226633Sdim { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 505226633Sdim { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 506226633Sdim { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 507226633Sdim { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 508226633Sdim { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 509226633Sdim { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 510226633Sdim { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 511249423Sdim { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 512226633Sdim { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 513226633Sdim { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 }, 514226633Sdim { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 515226633Sdim { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 516249423Sdim { X86::VPABSBrr128, X86::VPABSBrm128, 0 }, 517249423Sdim { X86::VPABSDrr128, X86::VPABSDrm128, 0 }, 518249423Sdim { X86::VPABSWrr128, X86::VPABSWrm128, 0 }, 519249423Sdim { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 520249423Sdim { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 521249423Sdim { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 522249423Sdim { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 523249423Sdim { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 524249423Sdim { X86::VRCPPSr, X86::VRCPPSm, 0 }, 525249423Sdim { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 }, 526249423Sdim { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 527249423Sdim { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 }, 528249423Sdim { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 529249423Sdim { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 530226633Sdim { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 531226633Sdim { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 532239462Sdim { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 533239462Sdim 534226633Sdim // AVX 256-bit foldable instructions 535226633Sdim { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 536226633Sdim { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 537234353Sdim { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 538226633Sdim { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 539234353Sdim { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 540249423Sdim { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 541249423Sdim { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 542239462Sdim 543234353Sdim // AVX2 foldable instructions 544249423Sdim { X86::VPABSBrr256, X86::VPABSBrm256, 0 }, 545249423Sdim { X86::VPABSDrr256, X86::VPABSDrm256, 0 }, 546249423Sdim { X86::VPABSWrr256, X86::VPABSWrm256, 0 }, 547249423Sdim { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 548249423Sdim { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 549249423Sdim { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 550249423Sdim { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 551249423Sdim { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 }, 552249423Sdim { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 553249423Sdim { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 554249423Sdim { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 555239462Sdim { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 556239462Sdim { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 557243830Sdim 558249423Sdim // BMI/BMI2/LZCNT/POPCNT foldable instructions 559249423Sdim { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 560249423Sdim { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 561249423Sdim { X86::BLSI32rr, X86::BLSI32rm, 0 }, 562249423Sdim { X86::BLSI64rr, X86::BLSI64rm, 0 }, 563249423Sdim { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 564249423Sdim { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 565249423Sdim { X86::BLSR32rr, X86::BLSR32rm, 0 }, 566249423Sdim { X86::BLSR64rr, X86::BLSR64rm, 0 }, 567249423Sdim { X86::BZHI32rr, X86::BZHI32rm, 0 }, 568249423Sdim { X86::BZHI64rr, X86::BZHI64rm, 0 }, 569249423Sdim { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 570249423Sdim { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 571249423Sdim { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 572249423Sdim { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 573249423Sdim { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 574249423Sdim { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 575243830Sdim { X86::RORX32ri, X86::RORX32mi, 0 }, 576243830Sdim { X86::RORX64ri, X86::RORX64mi, 0 }, 577243830Sdim { X86::SARX32rr, X86::SARX32rm, 0 }, 578243830Sdim { X86::SARX64rr, X86::SARX64rm, 0 }, 579243830Sdim { X86::SHRX32rr, X86::SHRX32rm, 0 }, 580243830Sdim { X86::SHRX64rr, X86::SHRX64rm, 0 }, 581243830Sdim { X86::SHLX32rr, X86::SHLX32rm, 0 }, 582243830Sdim { X86::SHLX64rr, X86::SHLX64rm, 0 }, 583249423Sdim { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 584249423Sdim { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 585249423Sdim { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 586193323Sed }; 587193323Sed 588193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 589234353Sdim unsigned RegOp = OpTbl1[i].RegOp; 590234353Sdim unsigned MemOp = OpTbl1[i].MemOp; 591234353Sdim unsigned Flags = OpTbl1[i].Flags; 592226633Sdim AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 593226633Sdim RegOp, MemOp, 594226633Sdim // Index 1, folded load 595226633Sdim Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 596193323Sed } 597193323Sed 598234353Sdim static const X86OpTblEntry OpTbl2[] = { 599226633Sdim { X86::ADC32rr, X86::ADC32rm, 0 }, 600226633Sdim { X86::ADC64rr, X86::ADC64rm, 0 }, 601226633Sdim { X86::ADD16rr, X86::ADD16rm, 0 }, 602226633Sdim { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 603226633Sdim { X86::ADD32rr, X86::ADD32rm, 0 }, 604226633Sdim { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 605226633Sdim { X86::ADD64rr, X86::ADD64rm, 0 }, 606226633Sdim { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 607226633Sdim { X86::ADD8rr, X86::ADD8rm, 0 }, 608226633Sdim { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 609226633Sdim { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 610226633Sdim { X86::ADDSDrr, X86::ADDSDrm, 0 }, 611226633Sdim { X86::ADDSSrr, X86::ADDSSrm, 0 }, 612226633Sdim { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 613226633Sdim { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 614226633Sdim { X86::AND16rr, X86::AND16rm, 0 }, 615226633Sdim { X86::AND32rr, X86::AND32rm, 0 }, 616226633Sdim { X86::AND64rr, X86::AND64rm, 0 }, 617226633Sdim { X86::AND8rr, X86::AND8rm, 0 }, 618226633Sdim { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 619226633Sdim { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 620226633Sdim { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 621226633Sdim { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 622234353Sdim { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 623234353Sdim { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 624234353Sdim { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 625234353Sdim { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 626226633Sdim { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 627226633Sdim { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 628226633Sdim { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 629226633Sdim { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 630226633Sdim { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 631226633Sdim { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 632226633Sdim { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 633226633Sdim { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 634226633Sdim { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 635226633Sdim { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 636226633Sdim { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 637226633Sdim { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 638226633Sdim { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 639226633Sdim { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 640226633Sdim { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 641226633Sdim { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 642226633Sdim { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 643226633Sdim { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 644226633Sdim { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 645226633Sdim { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 646226633Sdim { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 647226633Sdim { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 648226633Sdim { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 649226633Sdim { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 650226633Sdim { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 651226633Sdim { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 652226633Sdim { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 653226633Sdim { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 654226633Sdim { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 655226633Sdim { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 656226633Sdim { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 657226633Sdim { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 658226633Sdim { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 659226633Sdim { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 660226633Sdim { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 661226633Sdim { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 662226633Sdim { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 663226633Sdim { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 664226633Sdim { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 665226633Sdim { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 666226633Sdim { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 667226633Sdim { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 668226633Sdim { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 669226633Sdim { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 670226633Sdim { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 671226633Sdim { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 672226633Sdim { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 673226633Sdim { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 674226633Sdim { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 675226633Sdim { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 676226633Sdim { X86::CMPSDrr, X86::CMPSDrm, 0 }, 677226633Sdim { X86::CMPSSrr, X86::CMPSSrm, 0 }, 678226633Sdim { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 679226633Sdim { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 680226633Sdim { X86::DIVSDrr, X86::DIVSDrm, 0 }, 681226633Sdim { X86::DIVSSrr, X86::DIVSSrm, 0 }, 682226633Sdim { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 683226633Sdim { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 684226633Sdim { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 685226633Sdim { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 686226633Sdim { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 687226633Sdim { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 688226633Sdim { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 689226633Sdim { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 690226633Sdim { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 691226633Sdim { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 692226633Sdim { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 693226633Sdim { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 694226633Sdim { X86::IMUL16rr, X86::IMUL16rm, 0 }, 695226633Sdim { X86::IMUL32rr, X86::IMUL32rm, 0 }, 696226633Sdim { X86::IMUL64rr, X86::IMUL64rm, 0 }, 697226633Sdim { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 698226633Sdim { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 699239462Sdim { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 700239462Sdim { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 701239462Sdim { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 702239462Sdim { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 703239462Sdim { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 704239462Sdim { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 705226633Sdim { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 706226633Sdim { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 707226633Sdim { X86::MAXSDrr, X86::MAXSDrm, 0 }, 708226633Sdim { X86::MAXSSrr, X86::MAXSSrm, 0 }, 709226633Sdim { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 710226633Sdim { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 711226633Sdim { X86::MINSDrr, X86::MINSDrm, 0 }, 712226633Sdim { X86::MINSSrr, X86::MINSSrm, 0 }, 713234353Sdim { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 714226633Sdim { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 715226633Sdim { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 716226633Sdim { X86::MULSDrr, X86::MULSDrm, 0 }, 717226633Sdim { X86::MULSSrr, X86::MULSSrm, 0 }, 718226633Sdim { X86::OR16rr, X86::OR16rm, 0 }, 719226633Sdim { X86::OR32rr, X86::OR32rm, 0 }, 720226633Sdim { X86::OR64rr, X86::OR64rm, 0 }, 721226633Sdim { X86::OR8rr, X86::OR8rm, 0 }, 722226633Sdim { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 723226633Sdim { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 724226633Sdim { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 725226633Sdim { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 726234353Sdim { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 727226633Sdim { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 728226633Sdim { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 729226633Sdim { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 730226633Sdim { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 731226633Sdim { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 732226633Sdim { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 733234353Sdim { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 734234353Sdim { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 735226633Sdim { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 736234353Sdim { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 737226633Sdim { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 738226633Sdim { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 739226633Sdim { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 740226633Sdim { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 741234353Sdim { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 742226633Sdim { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 743226633Sdim { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 744234353Sdim { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 745226633Sdim { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 746226633Sdim { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 747226633Sdim { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 748234353Sdim { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 749226633Sdim { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 750234353Sdim { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 751234353Sdim { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 752234353Sdim { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 753234353Sdim { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 754234353Sdim { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 755234353Sdim { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 756226633Sdim { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 757234353Sdim { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 758226633Sdim { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 759226633Sdim { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 760226633Sdim { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 761226633Sdim { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 762226633Sdim { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 763249423Sdim { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 764249423Sdim { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 765249423Sdim { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 766249423Sdim { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 767249423Sdim { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 768249423Sdim { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 769249423Sdim { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 770249423Sdim { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 771226633Sdim { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 772234353Sdim { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 773226633Sdim { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 774226633Sdim { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 775226633Sdim { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 776226633Sdim { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 777226633Sdim { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 778226633Sdim { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 779226633Sdim { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 780234353Sdim { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 781234353Sdim { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 782234353Sdim { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 783234353Sdim { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 784226633Sdim { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 785226633Sdim { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 786226633Sdim { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 787226633Sdim { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 788226633Sdim { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 789226633Sdim { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 790226633Sdim { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 791226633Sdim { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 792226633Sdim { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 793226633Sdim { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 794226633Sdim { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 795226633Sdim { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 796226633Sdim { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 797226633Sdim { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 798226633Sdim { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 799226633Sdim { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 800226633Sdim { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 801226633Sdim { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 802226633Sdim { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 803226633Sdim { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 804226633Sdim { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 805226633Sdim { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 806226633Sdim { X86::SBB32rr, X86::SBB32rm, 0 }, 807226633Sdim { X86::SBB64rr, X86::SBB64rm, 0 }, 808226633Sdim { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 809226633Sdim { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 810226633Sdim { X86::SUB16rr, X86::SUB16rm, 0 }, 811226633Sdim { X86::SUB32rr, X86::SUB32rm, 0 }, 812226633Sdim { X86::SUB64rr, X86::SUB64rm, 0 }, 813226633Sdim { X86::SUB8rr, X86::SUB8rm, 0 }, 814226633Sdim { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 815226633Sdim { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 816226633Sdim { X86::SUBSDrr, X86::SUBSDrm, 0 }, 817226633Sdim { X86::SUBSSrr, X86::SUBSSrm, 0 }, 818193323Sed // FIXME: TEST*rr -> swapped operand of TEST*mr. 819226633Sdim { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 820226633Sdim { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 821226633Sdim { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 822226633Sdim { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 823226633Sdim { X86::XOR16rr, X86::XOR16rm, 0 }, 824226633Sdim { X86::XOR32rr, X86::XOR32rm, 0 }, 825226633Sdim { X86::XOR64rr, X86::XOR64rm, 0 }, 826226633Sdim { X86::XOR8rr, X86::XOR8rm, 0 }, 827226633Sdim { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 828226633Sdim { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 829226633Sdim // AVX 128-bit versions of foldable instructions 830226633Sdim { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 831226633Sdim { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 832226633Sdim { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 833226633Sdim { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 834226633Sdim { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 835226633Sdim { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 836226633Sdim { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 837226633Sdim { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 838226633Sdim { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 839226633Sdim { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 840226633Sdim { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 841226633Sdim { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 842249423Sdim { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, 843249423Sdim { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 844226633Sdim { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 845226633Sdim { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 846226633Sdim { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 847249423Sdim { X86::VADDPDrr, X86::VADDPDrm, 0 }, 848249423Sdim { X86::VADDPSrr, X86::VADDPSrm, 0 }, 849226633Sdim { X86::VADDSDrr, X86::VADDSDrm, 0 }, 850226633Sdim { X86::VADDSSrr, X86::VADDSSrm, 0 }, 851249423Sdim { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 852249423Sdim { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 853249423Sdim { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 854249423Sdim { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 855249423Sdim { X86::VANDPDrr, X86::VANDPDrm, 0 }, 856249423Sdim { X86::VANDPSrr, X86::VANDPSrm, 0 }, 857249423Sdim { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 858249423Sdim { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 859249423Sdim { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 860249423Sdim { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 861249423Sdim { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 862249423Sdim { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 863226633Sdim { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 864226633Sdim { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 865249423Sdim { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 866249423Sdim { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 867226633Sdim { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 868226633Sdim { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 869226633Sdim { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 870226633Sdim { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 871226633Sdim { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 872226633Sdim { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 873226633Sdim { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 874226633Sdim { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 875226633Sdim { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 876226633Sdim { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 877249423Sdim { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 878249423Sdim { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 879249423Sdim { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 880249423Sdim { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 881226633Sdim { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 882226633Sdim { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 883249423Sdim { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 884249423Sdim { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 885226633Sdim { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 886226633Sdim { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 887249423Sdim { X86::VMINPDrr, X86::VMINPDrm, 0 }, 888249423Sdim { X86::VMINPSrr, X86::VMINPSrm, 0 }, 889226633Sdim { X86::VMINSDrr, X86::VMINSDrm, 0 }, 890226633Sdim { X86::VMINSSrr, X86::VMINSSrm, 0 }, 891249423Sdim { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 892249423Sdim { X86::VMULPDrr, X86::VMULPDrm, 0 }, 893249423Sdim { X86::VMULPSrr, X86::VMULPSrm, 0 }, 894226633Sdim { X86::VMULSDrr, X86::VMULSDrm, 0 }, 895226633Sdim { X86::VMULSSrr, X86::VMULSSrm, 0 }, 896249423Sdim { X86::VORPDrr, X86::VORPDrm, 0 }, 897249423Sdim { X86::VORPSrr, X86::VORPSrm, 0 }, 898249423Sdim { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 899249423Sdim { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 900249423Sdim { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 901249423Sdim { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 902249423Sdim { X86::VPADDBrr, X86::VPADDBrm, 0 }, 903249423Sdim { X86::VPADDDrr, X86::VPADDDrm, 0 }, 904249423Sdim { X86::VPADDQrr, X86::VPADDQrm, 0 }, 905249423Sdim { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 906249423Sdim { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 907249423Sdim { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 908249423Sdim { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 909249423Sdim { X86::VPADDWrr, X86::VPADDWrm, 0 }, 910249423Sdim { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 }, 911249423Sdim { X86::VPANDNrr, X86::VPANDNrm, 0 }, 912249423Sdim { X86::VPANDrr, X86::VPANDrm, 0 }, 913249423Sdim { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 914249423Sdim { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 915249423Sdim { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 916249423Sdim { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 917249423Sdim { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 918249423Sdim { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 919249423Sdim { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 920249423Sdim { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 921249423Sdim { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 922249423Sdim { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 923249423Sdim { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 924249423Sdim { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 925249423Sdim { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 926249423Sdim { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 927249423Sdim { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 928249423Sdim { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 929249423Sdim { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 930249423Sdim { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 931249423Sdim { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 932249423Sdim { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 933249423Sdim { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 }, 934249423Sdim { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 935249423Sdim { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 936249423Sdim { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 937249423Sdim { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 938249423Sdim { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 939249423Sdim { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 940249423Sdim { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 941249423Sdim { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 942249423Sdim { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 943249423Sdim { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 944249423Sdim { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 945249423Sdim { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 946249423Sdim { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 947249423Sdim { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 948249423Sdim { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 }, 949249423Sdim { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 950249423Sdim { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 951249423Sdim { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 952249423Sdim { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 953249423Sdim { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 954249423Sdim { X86::VPORrr, X86::VPORrm, 0 }, 955249423Sdim { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 956249423Sdim { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 957249423Sdim { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 }, 958249423Sdim { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 }, 959249423Sdim { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 }, 960249423Sdim { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 961249423Sdim { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 962249423Sdim { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 963249423Sdim { X86::VPSRADrr, X86::VPSRADrm, 0 }, 964249423Sdim { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 965249423Sdim { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 966249423Sdim { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 967249423Sdim { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 968249423Sdim { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 969249423Sdim { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 970249423Sdim { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 971249423Sdim { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 972249423Sdim { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 973249423Sdim { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 974249423Sdim { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 975249423Sdim { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 976249423Sdim { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 977249423Sdim { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 978249423Sdim { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 979249423Sdim { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 980249423Sdim { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 981249423Sdim { X86::VPXORrr, X86::VPXORrm, 0 }, 982249423Sdim { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 983249423Sdim { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 984249423Sdim { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 985249423Sdim { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 986226633Sdim { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 987226633Sdim { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 988249423Sdim { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 989249423Sdim { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 990249423Sdim { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 991249423Sdim { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 992249423Sdim { X86::VXORPDrr, X86::VXORPDrm, 0 }, 993249423Sdim { X86::VXORPSrr, X86::VXORPSrm, 0 }, 994234353Sdim // AVX 256-bit foldable instructions 995249423Sdim { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 996249423Sdim { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 997249423Sdim { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 998249423Sdim { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 999249423Sdim { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 1000249423Sdim { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 1001249423Sdim { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 1002249423Sdim { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1003249423Sdim { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1004249423Sdim { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1005249423Sdim { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1006249423Sdim { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1007249423Sdim { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1008249423Sdim { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1009249423Sdim { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1010249423Sdim { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1011249423Sdim { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1012249423Sdim { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1013249423Sdim { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1014249423Sdim { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1015249423Sdim { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1016249423Sdim { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1017249423Sdim { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1018249423Sdim { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1019249423Sdim { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1020249423Sdim { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1021249423Sdim { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1022249423Sdim { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1023249423Sdim { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1024249423Sdim { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1025249423Sdim { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1026249423Sdim { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1027249423Sdim { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1028249423Sdim { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1029249423Sdim { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1030249423Sdim { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1031249423Sdim { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1032249423Sdim { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1033249423Sdim { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1034249423Sdim { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1035249423Sdim { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1036249423Sdim { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1037234353Sdim // AVX2 foldable instructions 1038249423Sdim { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1039249423Sdim { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1040249423Sdim { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1041249423Sdim { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1042249423Sdim { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1043249423Sdim { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1044249423Sdim { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1045249423Sdim { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1046249423Sdim { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1047249423Sdim { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1048249423Sdim { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1049249423Sdim { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1050249423Sdim { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1051249423Sdim { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 }, 1052249423Sdim { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1053249423Sdim { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1054249423Sdim { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1055249423Sdim { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1056249423Sdim { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1057249423Sdim { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1058249423Sdim { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1059249423Sdim { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1060249423Sdim { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1061249423Sdim { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1062249423Sdim { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1063249423Sdim { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1064249423Sdim { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1065249423Sdim { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1066249423Sdim { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1067249423Sdim { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1068249423Sdim { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1069249423Sdim { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 1070249423Sdim { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1071249423Sdim { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 1072249423Sdim { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1073249423Sdim { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1074249423Sdim { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1075249423Sdim { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1076249423Sdim { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1077249423Sdim { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1078249423Sdim { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 }, 1079249423Sdim { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1080249423Sdim { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1081249423Sdim { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1082249423Sdim { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1083249423Sdim { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1084249423Sdim { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1085249423Sdim { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1086249423Sdim { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1087249423Sdim { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1088249423Sdim { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1089249423Sdim { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1090249423Sdim { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1091249423Sdim { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1092249423Sdim { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1093249423Sdim { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1094249423Sdim { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 }, 1095249423Sdim { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1096249423Sdim { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1097249423Sdim { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1098249423Sdim { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1099249423Sdim { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1100249423Sdim { X86::VPORYrr, X86::VPORYrm, 0 }, 1101249423Sdim { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1102249423Sdim { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1103249423Sdim { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 }, 1104249423Sdim { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 }, 1105249423Sdim { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 }, 1106249423Sdim { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1107249423Sdim { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1108249423Sdim { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1109249423Sdim { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1110249423Sdim { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1111249423Sdim { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1112249423Sdim { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1113249423Sdim { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1114249423Sdim { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1115249423Sdim { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1116249423Sdim { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1117249423Sdim { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1118249423Sdim { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1119249423Sdim { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1120249423Sdim { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1121249423Sdim { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1122249423Sdim { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1123249423Sdim { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1124249423Sdim { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1125249423Sdim { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1126249423Sdim { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1127249423Sdim { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1128249423Sdim { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1129249423Sdim { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1130249423Sdim { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1131249423Sdim { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1132249423Sdim { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1133249423Sdim { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1134249423Sdim { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1135249423Sdim { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1136249423Sdim { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1137249423Sdim { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1138226633Sdim // FIXME: add AVX 256-bit foldable instructions 1139243830Sdim 1140243830Sdim // FMA4 foldable patterns 1141243830Sdim { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 }, 1142243830Sdim { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 }, 1143243830Sdim { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1144243830Sdim { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1145243830Sdim { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1146243830Sdim { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1147243830Sdim { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 }, 1148243830Sdim { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 }, 1149243830Sdim { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1150243830Sdim { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1151243830Sdim { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1152243830Sdim { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1153243830Sdim { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 }, 1154243830Sdim { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 }, 1155243830Sdim { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1156243830Sdim { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1157243830Sdim { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1158243830Sdim { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1159243830Sdim { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 }, 1160243830Sdim { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 }, 1161243830Sdim { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1162243830Sdim { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1163243830Sdim { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1164243830Sdim { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1165243830Sdim { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1166243830Sdim { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1167243830Sdim { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1168243830Sdim { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1169243830Sdim { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1170243830Sdim { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1171243830Sdim { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1172243830Sdim { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1173243830Sdim 1174243830Sdim // BMI/BMI2 foldable instructions 1175249423Sdim { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1176249423Sdim { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1177243830Sdim { X86::MULX32rr, X86::MULX32rm, 0 }, 1178243830Sdim { X86::MULX64rr, X86::MULX64rm, 0 }, 1179249423Sdim { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1180249423Sdim { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1181249423Sdim { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1182249423Sdim { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1183193323Sed }; 1184193323Sed 1185193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1186234353Sdim unsigned RegOp = OpTbl2[i].RegOp; 1187234353Sdim unsigned MemOp = OpTbl2[i].MemOp; 1188234353Sdim unsigned Flags = OpTbl2[i].Flags; 1189226633Sdim AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1190226633Sdim RegOp, MemOp, 1191226633Sdim // Index 2, folded load 1192226633Sdim Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1193226633Sdim } 1194239462Sdim 1195239462Sdim static const X86OpTblEntry OpTbl3[] = { 1196239462Sdim // FMA foldable instructions 1197239462Sdim { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 }, 1198239462Sdim { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 }, 1199239462Sdim { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 }, 1200239462Sdim { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 }, 1201239462Sdim { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 }, 1202239462Sdim { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 }, 1203239462Sdim { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 }, 1204239462Sdim { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 }, 1205239462Sdim 1206239462Sdim { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 }, 1207239462Sdim { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 }, 1208239462Sdim { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 }, 1209239462Sdim { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 }, 1210239462Sdim { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 }, 1211239462Sdim { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 }, 1212239462Sdim { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 }, 1213239462Sdim { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 }, 1214239462Sdim { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 }, 1215239462Sdim { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 }, 1216239462Sdim { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 }, 1217239462Sdim { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 }, 1218239462Sdim 1219239462Sdim { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 }, 1220239462Sdim { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 }, 1221239462Sdim { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 }, 1222239462Sdim { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 }, 1223239462Sdim { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 }, 1224239462Sdim { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 }, 1225239462Sdim { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 }, 1226239462Sdim { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 }, 1227239462Sdim 1228239462Sdim { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 }, 1229239462Sdim { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 }, 1230239462Sdim { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 }, 1231239462Sdim { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 }, 1232239462Sdim { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 }, 1233239462Sdim { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 }, 1234239462Sdim { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 }, 1235239462Sdim { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 }, 1236239462Sdim { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 }, 1237239462Sdim { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 }, 1238239462Sdim { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 }, 1239239462Sdim { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 }, 1240239462Sdim 1241239462Sdim { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 }, 1242239462Sdim { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 }, 1243239462Sdim { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 }, 1244239462Sdim { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 }, 1245239462Sdim { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 }, 1246239462Sdim { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 }, 1247239462Sdim { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 }, 1248239462Sdim { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 }, 1249239462Sdim 1250239462Sdim { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 }, 1251239462Sdim { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 }, 1252239462Sdim { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 }, 1253239462Sdim { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 }, 1254239462Sdim { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 }, 1255239462Sdim { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 }, 1256239462Sdim { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 }, 1257239462Sdim { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 }, 1258239462Sdim { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 }, 1259239462Sdim { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 }, 1260239462Sdim { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 }, 1261239462Sdim { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 }, 1262239462Sdim 1263239462Sdim { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 }, 1264239462Sdim { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 }, 1265239462Sdim { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 }, 1266239462Sdim { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 }, 1267239462Sdim { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 }, 1268239462Sdim { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 }, 1269239462Sdim { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 }, 1270239462Sdim { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 }, 1271239462Sdim 1272239462Sdim { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 }, 1273239462Sdim { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 }, 1274239462Sdim { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 }, 1275239462Sdim { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 }, 1276239462Sdim { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 }, 1277239462Sdim { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 }, 1278239462Sdim { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 }, 1279239462Sdim { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 }, 1280239462Sdim { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 }, 1281239462Sdim { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 }, 1282239462Sdim { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 }, 1283239462Sdim { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 }, 1284239462Sdim 1285239462Sdim { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 }, 1286239462Sdim { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 }, 1287239462Sdim { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 }, 1288239462Sdim { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 }, 1289239462Sdim { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 }, 1290239462Sdim { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 }, 1291239462Sdim { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 }, 1292239462Sdim { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 }, 1293239462Sdim { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 }, 1294239462Sdim { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 }, 1295239462Sdim { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 }, 1296239462Sdim { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 }, 1297239462Sdim 1298239462Sdim { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 }, 1299239462Sdim { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 }, 1300239462Sdim { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 }, 1301239462Sdim { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 }, 1302239462Sdim { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 }, 1303239462Sdim { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 }, 1304239462Sdim { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 }, 1305239462Sdim { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 }, 1306239462Sdim { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 }, 1307239462Sdim { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 }, 1308239462Sdim { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 }, 1309239462Sdim { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 }, 1310243830Sdim 1311243830Sdim // FMA4 foldable patterns 1312243830Sdim { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 }, 1313243830Sdim { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 }, 1314243830Sdim { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1315243830Sdim { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1316243830Sdim { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1317243830Sdim { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1318243830Sdim { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 }, 1319243830Sdim { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 }, 1320243830Sdim { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1321243830Sdim { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1322243830Sdim { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1323243830Sdim { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1324243830Sdim { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 }, 1325243830Sdim { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 }, 1326243830Sdim { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1327243830Sdim { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1328243830Sdim { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1329243830Sdim { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1330243830Sdim { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 }, 1331243830Sdim { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 }, 1332243830Sdim { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1333243830Sdim { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1334243830Sdim { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1335243830Sdim { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1336243830Sdim { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1337243830Sdim { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1338243830Sdim { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1339243830Sdim { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1340243830Sdim { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1341243830Sdim { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1342243830Sdim { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1343243830Sdim { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1344239462Sdim }; 1345239462Sdim 1346239462Sdim for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1347239462Sdim unsigned RegOp = OpTbl3[i].RegOp; 1348239462Sdim unsigned MemOp = OpTbl3[i].MemOp; 1349239462Sdim unsigned Flags = OpTbl3[i].Flags; 1350239462Sdim AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1351239462Sdim RegOp, MemOp, 1352239462Sdim // Index 3, folded load 1353239462Sdim Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1354239462Sdim } 1355239462Sdim 1356226633Sdim} 1357218893Sdim 1358226633Sdimvoid 1359226633SdimX86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1360226633Sdim MemOp2RegOpTableType &M2RTable, 1361226633Sdim unsigned RegOp, unsigned MemOp, unsigned Flags) { 1362226633Sdim if ((Flags & TB_NO_FORWARD) == 0) { 1363226633Sdim assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1364226633Sdim R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1365226633Sdim } 1366226633Sdim if ((Flags & TB_NO_REVERSE) == 0) { 1367226633Sdim assert(!M2RTable.count(MemOp) && 1368218893Sdim "Duplicated entries in unfolding maps?"); 1369226633Sdim M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1370226633Sdim } 1371193323Sed} 1372193323Sed 1373202375Srdivackybool 1374202375SrdivackyX86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1375202375Srdivacky unsigned &SrcReg, unsigned &DstReg, 1376202375Srdivacky unsigned &SubIdx) const { 1377202375Srdivacky switch (MI.getOpcode()) { 1378202375Srdivacky default: break; 1379202375Srdivacky case X86::MOVSX16rr8: 1380202375Srdivacky case X86::MOVZX16rr8: 1381202375Srdivacky case X86::MOVSX32rr8: 1382202375Srdivacky case X86::MOVZX32rr8: 1383202375Srdivacky case X86::MOVSX64rr8: 1384202375Srdivacky case X86::MOVZX64rr8: 1385202375Srdivacky if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1386202375Srdivacky // It's not always legal to reference the low 8-bit of the larger 1387202375Srdivacky // register in 32-bit mode. 1388202375Srdivacky return false; 1389202375Srdivacky case X86::MOVSX32rr16: 1390202375Srdivacky case X86::MOVZX32rr16: 1391202375Srdivacky case X86::MOVSX64rr16: 1392202375Srdivacky case X86::MOVZX64rr16: 1393202375Srdivacky case X86::MOVSX64rr32: 1394202375Srdivacky case X86::MOVZX64rr32: { 1395202375Srdivacky if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1396202375Srdivacky // Be conservative. 1397202375Srdivacky return false; 1398202375Srdivacky SrcReg = MI.getOperand(1).getReg(); 1399202375Srdivacky DstReg = MI.getOperand(0).getReg(); 1400202375Srdivacky switch (MI.getOpcode()) { 1401243830Sdim default: llvm_unreachable("Unreachable!"); 1402202375Srdivacky case X86::MOVSX16rr8: 1403202375Srdivacky case X86::MOVZX16rr8: 1404202375Srdivacky case X86::MOVSX32rr8: 1405202375Srdivacky case X86::MOVZX32rr8: 1406202375Srdivacky case X86::MOVSX64rr8: 1407202375Srdivacky case X86::MOVZX64rr8: 1408208599Srdivacky SubIdx = X86::sub_8bit; 1409202375Srdivacky break; 1410202375Srdivacky case X86::MOVSX32rr16: 1411202375Srdivacky case X86::MOVZX32rr16: 1412202375Srdivacky case X86::MOVSX64rr16: 1413202375Srdivacky case X86::MOVZX64rr16: 1414208599Srdivacky SubIdx = X86::sub_16bit; 1415202375Srdivacky break; 1416202375Srdivacky case X86::MOVSX64rr32: 1417202375Srdivacky case X86::MOVZX64rr32: 1418208599Srdivacky SubIdx = X86::sub_32bit; 1419202375Srdivacky break; 1420202375Srdivacky } 1421202375Srdivacky return true; 1422202375Srdivacky } 1423202375Srdivacky } 1424202375Srdivacky return false; 1425202375Srdivacky} 1426202375Srdivacky 1427199481Srdivacky/// isFrameOperand - Return true and the FrameIndex if the specified 1428199481Srdivacky/// operand and follow operands form a reference to the stack frame. 1429199481Srdivackybool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1430199481Srdivacky int &FrameIndex) const { 1431199481Srdivacky if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 1432199481Srdivacky MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 1433199481Srdivacky MI->getOperand(Op+1).getImm() == 1 && 1434199481Srdivacky MI->getOperand(Op+2).getReg() == 0 && 1435199481Srdivacky MI->getOperand(Op+3).getImm() == 0) { 1436199481Srdivacky FrameIndex = MI->getOperand(Op).getIndex(); 1437199481Srdivacky return true; 1438199481Srdivacky } 1439199481Srdivacky return false; 1440199481Srdivacky} 1441199481Srdivacky 1442199481Srdivackystatic bool isFrameLoadOpcode(int Opcode) { 1443199481Srdivacky switch (Opcode) { 1444234353Sdim default: 1445234353Sdim return false; 1446193323Sed case X86::MOV8rm: 1447193323Sed case X86::MOV16rm: 1448193323Sed case X86::MOV32rm: 1449193323Sed case X86::MOV64rm: 1450193323Sed case X86::LD_Fp64m: 1451193323Sed case X86::MOVSSrm: 1452193323Sed case X86::MOVSDrm: 1453193323Sed case X86::MOVAPSrm: 1454193323Sed case X86::MOVAPDrm: 1455193323Sed case X86::MOVDQArm: 1456226633Sdim case X86::VMOVSSrm: 1457226633Sdim case X86::VMOVSDrm: 1458226633Sdim case X86::VMOVAPSrm: 1459226633Sdim case X86::VMOVAPDrm: 1460226633Sdim case X86::VMOVDQArm: 1461224145Sdim case X86::VMOVAPSYrm: 1462224145Sdim case X86::VMOVAPDYrm: 1463224145Sdim case X86::VMOVDQAYrm: 1464193323Sed case X86::MMX_MOVD64rm: 1465193323Sed case X86::MMX_MOVQ64rm: 1466199481Srdivacky return true; 1467193323Sed } 1468193323Sed} 1469193323Sed 1470199481Srdivackystatic bool isFrameStoreOpcode(int Opcode) { 1471199481Srdivacky switch (Opcode) { 1472193323Sed default: break; 1473193323Sed case X86::MOV8mr: 1474193323Sed case X86::MOV16mr: 1475193323Sed case X86::MOV32mr: 1476193323Sed case X86::MOV64mr: 1477193323Sed case X86::ST_FpP64m: 1478193323Sed case X86::MOVSSmr: 1479193323Sed case X86::MOVSDmr: 1480193323Sed case X86::MOVAPSmr: 1481193323Sed case X86::MOVAPDmr: 1482193323Sed case X86::MOVDQAmr: 1483226633Sdim case X86::VMOVSSmr: 1484226633Sdim case X86::VMOVSDmr: 1485226633Sdim case X86::VMOVAPSmr: 1486226633Sdim case X86::VMOVAPDmr: 1487226633Sdim case X86::VMOVDQAmr: 1488224145Sdim case X86::VMOVAPSYmr: 1489224145Sdim case X86::VMOVAPDYmr: 1490224145Sdim case X86::VMOVDQAYmr: 1491193323Sed case X86::MMX_MOVD64mr: 1492193323Sed case X86::MMX_MOVQ64mr: 1493193323Sed case X86::MMX_MOVNTQmr: 1494199481Srdivacky return true; 1495199481Srdivacky } 1496199481Srdivacky return false; 1497199481Srdivacky} 1498199481Srdivacky 1499218893Sdimunsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1500199481Srdivacky int &FrameIndex) const { 1501199481Srdivacky if (isFrameLoadOpcode(MI->getOpcode())) 1502212904Sdim if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1503199481Srdivacky return MI->getOperand(0).getReg(); 1504199481Srdivacky return 0; 1505199481Srdivacky} 1506199481Srdivacky 1507218893Sdimunsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1508199481Srdivacky int &FrameIndex) const { 1509199481Srdivacky if (isFrameLoadOpcode(MI->getOpcode())) { 1510199481Srdivacky unsigned Reg; 1511199481Srdivacky if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1512199481Srdivacky return Reg; 1513199481Srdivacky // Check for post-frame index elimination operations 1514200581Srdivacky const MachineMemOperand *Dummy; 1515200581Srdivacky return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1516199481Srdivacky } 1517199481Srdivacky return 0; 1518199481Srdivacky} 1519199481Srdivacky 1520199481Srdivackyunsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1521199481Srdivacky int &FrameIndex) const { 1522199481Srdivacky if (isFrameStoreOpcode(MI->getOpcode())) 1523212904Sdim if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1524212904Sdim isFrameOperand(MI, 0, FrameIndex)) 1525210299Sed return MI->getOperand(X86::AddrNumOperands).getReg(); 1526199481Srdivacky return 0; 1527199481Srdivacky} 1528199481Srdivacky 1529199481Srdivackyunsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1530199481Srdivacky int &FrameIndex) const { 1531199481Srdivacky if (isFrameStoreOpcode(MI->getOpcode())) { 1532199481Srdivacky unsigned Reg; 1533199481Srdivacky if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1534199481Srdivacky return Reg; 1535199481Srdivacky // Check for post-frame index elimination operations 1536200581Srdivacky const MachineMemOperand *Dummy; 1537200581Srdivacky return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1538193323Sed } 1539193323Sed return 0; 1540193323Sed} 1541193323Sed 1542193323Sed/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1543193323Sed/// X86::MOVPC32r. 1544193323Sedstatic bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1545239462Sdim // Don't waste compile time scanning use-def chains of physregs. 1546239462Sdim if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1547239462Sdim return false; 1548193323Sed bool isPICBase = false; 1549193323Sed for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1550193323Sed E = MRI.def_end(); I != E; ++I) { 1551193323Sed MachineInstr *DefMI = I.getOperand().getParent(); 1552193323Sed if (DefMI->getOpcode() != X86::MOVPC32r) 1553193323Sed return false; 1554193323Sed assert(!isPICBase && "More than one PIC base?"); 1555193323Sed isPICBase = true; 1556193323Sed } 1557193323Sed return isPICBase; 1558193323Sed} 1559193323Sed 1560193323Sedbool 1561198090SrdivackyX86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1562198090Srdivacky AliasAnalysis *AA) const { 1563193323Sed switch (MI->getOpcode()) { 1564193323Sed default: break; 1565243830Sdim case X86::MOV8rm: 1566243830Sdim case X86::MOV16rm: 1567243830Sdim case X86::MOV32rm: 1568243830Sdim case X86::MOV64rm: 1569243830Sdim case X86::LD_Fp64m: 1570243830Sdim case X86::MOVSSrm: 1571243830Sdim case X86::MOVSDrm: 1572243830Sdim case X86::MOVAPSrm: 1573243830Sdim case X86::MOVUPSrm: 1574243830Sdim case X86::MOVAPDrm: 1575243830Sdim case X86::MOVDQArm: 1576249423Sdim case X86::MOVDQUrm: 1577243830Sdim case X86::VMOVSSrm: 1578243830Sdim case X86::VMOVSDrm: 1579243830Sdim case X86::VMOVAPSrm: 1580243830Sdim case X86::VMOVUPSrm: 1581243830Sdim case X86::VMOVAPDrm: 1582243830Sdim case X86::VMOVDQArm: 1583249423Sdim case X86::VMOVDQUrm: 1584243830Sdim case X86::VMOVAPSYrm: 1585243830Sdim case X86::VMOVUPSYrm: 1586243830Sdim case X86::VMOVAPDYrm: 1587243830Sdim case X86::VMOVDQAYrm: 1588249423Sdim case X86::VMOVDQUYrm: 1589243830Sdim case X86::MMX_MOVD64rm: 1590243830Sdim case X86::MMX_MOVQ64rm: 1591243830Sdim case X86::FsVMOVAPSrm: 1592243830Sdim case X86::FsVMOVAPDrm: 1593243830Sdim case X86::FsMOVAPSrm: 1594243830Sdim case X86::FsMOVAPDrm: { 1595243830Sdim // Loads from constant pools are trivially rematerializable. 1596243830Sdim if (MI->getOperand(1).isReg() && 1597243830Sdim MI->getOperand(2).isImm() && 1598243830Sdim MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1599243830Sdim MI->isInvariantLoad(AA)) { 1600243830Sdim unsigned BaseReg = MI->getOperand(1).getReg(); 1601243830Sdim if (BaseReg == 0 || BaseReg == X86::RIP) 1602243830Sdim return true; 1603243830Sdim // Allow re-materialization of PIC load. 1604243830Sdim if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 1605243830Sdim return false; 1606243830Sdim const MachineFunction &MF = *MI->getParent()->getParent(); 1607243830Sdim const MachineRegisterInfo &MRI = MF.getRegInfo(); 1608243830Sdim return regIsPICBase(BaseReg, MRI); 1609193323Sed } 1610243830Sdim return false; 1611243830Sdim } 1612218893Sdim 1613243830Sdim case X86::LEA32r: 1614243830Sdim case X86::LEA64r: { 1615243830Sdim if (MI->getOperand(2).isImm() && 1616243830Sdim MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1617243830Sdim !MI->getOperand(4).isReg()) { 1618243830Sdim // lea fi#, lea GV, etc. are all rematerializable. 1619243830Sdim if (!MI->getOperand(1).isReg()) 1620243830Sdim return true; 1621243830Sdim unsigned BaseReg = MI->getOperand(1).getReg(); 1622243830Sdim if (BaseReg == 0) 1623243830Sdim return true; 1624243830Sdim // Allow re-materialization of lea PICBase + x. 1625243830Sdim const MachineFunction &MF = *MI->getParent()->getParent(); 1626243830Sdim const MachineRegisterInfo &MRI = MF.getRegInfo(); 1627243830Sdim return regIsPICBase(BaseReg, MRI); 1628243830Sdim } 1629243830Sdim return false; 1630193323Sed } 1631243830Sdim } 1632193323Sed 1633193323Sed // All other instructions marked M_REMATERIALIZABLE are always trivially 1634193323Sed // rematerializable. 1635193323Sed return true; 1636193323Sed} 1637193323Sed 1638193323Sed/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 1639193323Sed/// would clobber the EFLAGS condition register. Note the result may be 1640193323Sed/// conservative. If it cannot definitely determine the safety after visiting 1641198090Srdivacky/// a few instructions in each direction it assumes it's not safe. 1642193323Sedstatic bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1643193323Sed MachineBasicBlock::iterator I) { 1644206083Srdivacky MachineBasicBlock::iterator E = MBB.end(); 1645206083Srdivacky 1646193323Sed // For compile time consideration, if we are not able to determine the 1647198090Srdivacky // safety after visiting 4 instructions in each direction, we will assume 1648198090Srdivacky // it's not safe. 1649198090Srdivacky MachineBasicBlock::iterator Iter = I; 1650226633Sdim for (unsigned i = 0; Iter != E && i < 4; ++i) { 1651193323Sed bool SeenDef = false; 1652198090Srdivacky for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1653198090Srdivacky MachineOperand &MO = Iter->getOperand(j); 1654234353Sdim if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1655234353Sdim SeenDef = true; 1656193323Sed if (!MO.isReg()) 1657193323Sed continue; 1658193323Sed if (MO.getReg() == X86::EFLAGS) { 1659193323Sed if (MO.isUse()) 1660193323Sed return false; 1661193323Sed SeenDef = true; 1662193323Sed } 1663193323Sed } 1664193323Sed 1665193323Sed if (SeenDef) 1666193323Sed // This instruction defines EFLAGS, no need to look any further. 1667193323Sed return true; 1668198090Srdivacky ++Iter; 1669206083Srdivacky // Skip over DBG_VALUE. 1670206083Srdivacky while (Iter != E && Iter->isDebugValue()) 1671206083Srdivacky ++Iter; 1672226633Sdim } 1673193323Sed 1674226633Sdim // It is safe to clobber EFLAGS at the end of a block of no successor has it 1675226633Sdim // live in. 1676226633Sdim if (Iter == E) { 1677226633Sdim for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1678226633Sdim SE = MBB.succ_end(); SI != SE; ++SI) 1679226633Sdim if ((*SI)->isLiveIn(X86::EFLAGS)) 1680226633Sdim return false; 1681226633Sdim return true; 1682193323Sed } 1683193323Sed 1684206083Srdivacky MachineBasicBlock::iterator B = MBB.begin(); 1685198090Srdivacky Iter = I; 1686198090Srdivacky for (unsigned i = 0; i < 4; ++i) { 1687198090Srdivacky // If we make it to the beginning of the block, it's safe to clobber 1688198090Srdivacky // EFLAGS iff EFLAGS is not live-in. 1689206083Srdivacky if (Iter == B) 1690198090Srdivacky return !MBB.isLiveIn(X86::EFLAGS); 1691198090Srdivacky 1692198090Srdivacky --Iter; 1693206083Srdivacky // Skip over DBG_VALUE. 1694206083Srdivacky while (Iter != B && Iter->isDebugValue()) 1695206083Srdivacky --Iter; 1696206083Srdivacky 1697198090Srdivacky bool SawKill = false; 1698198090Srdivacky for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1699198090Srdivacky MachineOperand &MO = Iter->getOperand(j); 1700234353Sdim // A register mask may clobber EFLAGS, but we should still look for a 1701234353Sdim // live EFLAGS def. 1702234353Sdim if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1703234353Sdim SawKill = true; 1704198090Srdivacky if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1705198090Srdivacky if (MO.isDef()) return MO.isDead(); 1706198090Srdivacky if (MO.isKill()) SawKill = true; 1707198090Srdivacky } 1708198090Srdivacky } 1709198090Srdivacky 1710198090Srdivacky if (SawKill) 1711198090Srdivacky // This instruction kills EFLAGS and doesn't redefine it, so 1712198090Srdivacky // there's no need to look further. 1713198090Srdivacky return true; 1714198090Srdivacky } 1715198090Srdivacky 1716193323Sed // Conservative answer. 1717193323Sed return false; 1718193323Sed} 1719193323Sed 1720193323Sedvoid X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1721193323Sed MachineBasicBlock::iterator I, 1722198090Srdivacky unsigned DestReg, unsigned SubIdx, 1723199481Srdivacky const MachineInstr *Orig, 1724210299Sed const TargetRegisterInfo &TRI) const { 1725208599Srdivacky DebugLoc DL = Orig->getDebugLoc(); 1726193323Sed 1727193323Sed // MOV32r0 etc. are implemented with xor which clobbers condition code. 1728193323Sed // Re-materialize them as movri instructions to avoid side effects. 1729198090Srdivacky bool Clone = true; 1730198090Srdivacky unsigned Opc = Orig->getOpcode(); 1731198090Srdivacky switch (Opc) { 1732193323Sed default: break; 1733193323Sed case X86::MOV8r0: 1734202375Srdivacky case X86::MOV16r0: 1735202375Srdivacky case X86::MOV32r0: 1736202375Srdivacky case X86::MOV64r0: { 1737193323Sed if (!isSafeToClobberEFLAGS(MBB, I)) { 1738198090Srdivacky switch (Opc) { 1739243830Sdim default: llvm_unreachable("Unreachable!"); 1740193323Sed case X86::MOV8r0: Opc = X86::MOV8ri; break; 1741202375Srdivacky case X86::MOV16r0: Opc = X86::MOV16ri; break; 1742193323Sed case X86::MOV32r0: Opc = X86::MOV32ri; break; 1743204642Srdivacky case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1744193323Sed } 1745198090Srdivacky Clone = false; 1746193323Sed } 1747193323Sed break; 1748193323Sed } 1749193323Sed } 1750193323Sed 1751198090Srdivacky if (Clone) { 1752193323Sed MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1753193323Sed MBB.insert(I, MI); 1754198090Srdivacky } else { 1755210299Sed BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1756193323Sed } 1757193323Sed 1758198090Srdivacky MachineInstr *NewMI = prior(I); 1759210299Sed NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1760193323Sed} 1761193323Sed 1762193323Sed/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1763193323Sed/// is not marked dead. 1764193323Sedstatic bool hasLiveCondCodeDef(MachineInstr *MI) { 1765193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1766193323Sed MachineOperand &MO = MI->getOperand(i); 1767193323Sed if (MO.isReg() && MO.isDef() && 1768193323Sed MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1769193323Sed return true; 1770193323Sed } 1771193323Sed } 1772193323Sed return false; 1773193323Sed} 1774193323Sed 1775200581Srdivacky/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1776200581Srdivacky/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1777200581Srdivacky/// to a 32-bit superregister and then truncating back down to a 16-bit 1778200581Srdivacky/// subregister. 1779200581SrdivackyMachineInstr * 1780200581SrdivackyX86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1781200581Srdivacky MachineFunction::iterator &MFI, 1782200581Srdivacky MachineBasicBlock::iterator &MBBI, 1783200581Srdivacky LiveVariables *LV) const { 1784200581Srdivacky MachineInstr *MI = MBBI; 1785200581Srdivacky unsigned Dest = MI->getOperand(0).getReg(); 1786200581Srdivacky unsigned Src = MI->getOperand(1).getReg(); 1787200581Srdivacky bool isDead = MI->getOperand(0).isDead(); 1788200581Srdivacky bool isKill = MI->getOperand(1).isKill(); 1789200581Srdivacky 1790200581Srdivacky unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1791200581Srdivacky ? X86::LEA64_32r : X86::LEA32r; 1792200581Srdivacky MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1793218893Sdim unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1794200581Srdivacky unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1795218893Sdim 1796200581Srdivacky // Build and insert into an implicit UNDEF value. This is OK because 1797218893Sdim // well be shifting and then extracting the lower 16-bits. 1798200581Srdivacky // This has the potential to cause partial register stall. e.g. 1799200581Srdivacky // movw (%rbp,%rcx,2), %dx 1800200581Srdivacky // leal -65(%rdx), %esi 1801200581Srdivacky // But testing has shown this *does* help performance in 64-bit mode (at 1802200581Srdivacky // least on modern x86 machines). 1803200581Srdivacky BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1804200581Srdivacky MachineInstr *InsMI = 1805210299Sed BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1806210299Sed .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1807210299Sed .addReg(Src, getKillRegState(isKill)); 1808200581Srdivacky 1809200581Srdivacky MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1810200581Srdivacky get(Opc), leaOutReg); 1811200581Srdivacky switch (MIOpc) { 1812243830Sdim default: llvm_unreachable("Unreachable!"); 1813200581Srdivacky case X86::SHL16ri: { 1814200581Srdivacky unsigned ShAmt = MI->getOperand(2).getImm(); 1815200581Srdivacky MIB.addReg(0).addImm(1 << ShAmt) 1816210299Sed .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1817200581Srdivacky break; 1818200581Srdivacky } 1819200581Srdivacky case X86::INC16r: 1820200581Srdivacky case X86::INC64_16r: 1821210299Sed addRegOffset(MIB, leaInReg, true, 1); 1822200581Srdivacky break; 1823200581Srdivacky case X86::DEC16r: 1824200581Srdivacky case X86::DEC64_16r: 1825210299Sed addRegOffset(MIB, leaInReg, true, -1); 1826200581Srdivacky break; 1827200581Srdivacky case X86::ADD16ri: 1828200581Srdivacky case X86::ADD16ri8: 1829218893Sdim case X86::ADD16ri_DB: 1830218893Sdim case X86::ADD16ri8_DB: 1831218893Sdim addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1832200581Srdivacky break; 1833218893Sdim case X86::ADD16rr: 1834218893Sdim case X86::ADD16rr_DB: { 1835200581Srdivacky unsigned Src2 = MI->getOperand(2).getReg(); 1836200581Srdivacky bool isKill2 = MI->getOperand(2).isKill(); 1837200581Srdivacky unsigned leaInReg2 = 0; 1838200581Srdivacky MachineInstr *InsMI2 = 0; 1839200581Srdivacky if (Src == Src2) { 1840200581Srdivacky // ADD16rr %reg1028<kill>, %reg1028 1841200581Srdivacky // just a single insert_subreg. 1842200581Srdivacky addRegReg(MIB, leaInReg, true, leaInReg, false); 1843200581Srdivacky } else { 1844218893Sdim leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1845200581Srdivacky // Build and insert into an implicit UNDEF value. This is OK because 1846218893Sdim // well be shifting and then extracting the lower 16-bits. 1847234353Sdim BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1848200581Srdivacky InsMI2 = 1849234353Sdim BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1850210299Sed .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1851210299Sed .addReg(Src2, getKillRegState(isKill2)); 1852200581Srdivacky addRegReg(MIB, leaInReg, true, leaInReg2, true); 1853200581Srdivacky } 1854200581Srdivacky if (LV && isKill2 && InsMI2) 1855200581Srdivacky LV->replaceKillInstruction(Src2, MI, InsMI2); 1856200581Srdivacky break; 1857200581Srdivacky } 1858200581Srdivacky } 1859200581Srdivacky 1860200581Srdivacky MachineInstr *NewMI = MIB; 1861200581Srdivacky MachineInstr *ExtMI = 1862210299Sed BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1863200581Srdivacky .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1864210299Sed .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1865200581Srdivacky 1866200581Srdivacky if (LV) { 1867200581Srdivacky // Update live variables 1868200581Srdivacky LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1869200581Srdivacky LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1870200581Srdivacky if (isKill) 1871200581Srdivacky LV->replaceKillInstruction(Src, MI, InsMI); 1872200581Srdivacky if (isDead) 1873200581Srdivacky LV->replaceKillInstruction(Dest, MI, ExtMI); 1874200581Srdivacky } 1875200581Srdivacky 1876200581Srdivacky return ExtMI; 1877200581Srdivacky} 1878200581Srdivacky 1879193323Sed/// convertToThreeAddress - This method must be implemented by targets that 1880193323Sed/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1881193323Sed/// may be able to convert a two-address instruction into a true 1882193323Sed/// three-address instruction on demand. This allows the X86 target (for 1883193323Sed/// example) to convert ADD and SHL instructions into LEA instructions if they 1884193323Sed/// would require register copies due to two-addressness. 1885193323Sed/// 1886193323Sed/// This method returns a null pointer if the transformation cannot be 1887193323Sed/// performed, otherwise it returns the new instruction. 1888193323Sed/// 1889193323SedMachineInstr * 1890193323SedX86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1891193323Sed MachineBasicBlock::iterator &MBBI, 1892193323Sed LiveVariables *LV) const { 1893193323Sed MachineInstr *MI = MBBI; 1894193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 1895193323Sed // All instructions input are two-addr instructions. Get the known operands. 1896243830Sdim const MachineOperand &Dest = MI->getOperand(0); 1897243830Sdim const MachineOperand &Src = MI->getOperand(1); 1898193323Sed 1899193323Sed MachineInstr *NewMI = NULL; 1900193323Sed // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1901193323Sed // we have better subtarget support, enable the 16-bit LEA generation here. 1902200581Srdivacky // 16-bit LEA is also slow on Core2. 1903193323Sed bool DisableLEA16 = true; 1904200581Srdivacky bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1905193323Sed 1906193323Sed unsigned MIOpc = MI->getOpcode(); 1907193323Sed switch (MIOpc) { 1908193323Sed case X86::SHUFPSrri: { 1909193323Sed assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1910193323Sed if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1911218893Sdim 1912193323Sed unsigned B = MI->getOperand(1).getReg(); 1913193323Sed unsigned C = MI->getOperand(2).getReg(); 1914193323Sed if (B != C) return 0; 1915193323Sed unsigned M = MI->getOperand(3).getImm(); 1916193323Sed NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1917243830Sdim .addOperand(Dest).addOperand(Src).addImm(M); 1918193323Sed break; 1919193323Sed } 1920234353Sdim case X86::SHUFPDrri: { 1921234353Sdim assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 1922234353Sdim if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1923234353Sdim 1924234353Sdim unsigned B = MI->getOperand(1).getReg(); 1925234353Sdim unsigned C = MI->getOperand(2).getReg(); 1926234353Sdim if (B != C) return 0; 1927234353Sdim unsigned M = MI->getOperand(3).getImm(); 1928234353Sdim 1929234353Sdim // Convert to PSHUFD mask. 1930234353Sdim M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 1931234353Sdim 1932234353Sdim NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1933243830Sdim .addOperand(Dest).addOperand(Src).addImm(M); 1934234353Sdim break; 1935234353Sdim } 1936193323Sed case X86::SHL64ri: { 1937193323Sed assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1938193323Sed // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1939193323Sed // the flags produced by a shift yet, so this is safe. 1940193323Sed unsigned ShAmt = MI->getOperand(2).getImm(); 1941193323Sed if (ShAmt == 0 || ShAmt >= 4) return 0; 1942193323Sed 1943218893Sdim // LEA can't handle RSP. 1944243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1945243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), 1946243830Sdim &X86::GR64_NOSPRegClass)) 1947218893Sdim return 0; 1948218893Sdim 1949193323Sed NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1950243830Sdim .addOperand(Dest) 1951243830Sdim .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1952193323Sed break; 1953193323Sed } 1954193323Sed case X86::SHL32ri: { 1955193323Sed assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1956193323Sed // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1957193323Sed // the flags produced by a shift yet, so this is safe. 1958193323Sed unsigned ShAmt = MI->getOperand(2).getImm(); 1959193323Sed if (ShAmt == 0 || ShAmt >= 4) return 0; 1960193323Sed 1961218893Sdim // LEA can't handle ESP. 1962243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1963243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), 1964243830Sdim &X86::GR32_NOSPRegClass)) 1965218893Sdim return 0; 1966218893Sdim 1967200581Srdivacky unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1968193323Sed NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1969243830Sdim .addOperand(Dest) 1970243830Sdim .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1971193323Sed break; 1972193323Sed } 1973193323Sed case X86::SHL16ri: { 1974193323Sed assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1975193323Sed // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1976193323Sed // the flags produced by a shift yet, so this is safe. 1977193323Sed unsigned ShAmt = MI->getOperand(2).getImm(); 1978193323Sed if (ShAmt == 0 || ShAmt >= 4) return 0; 1979193323Sed 1980200581Srdivacky if (DisableLEA16) 1981200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1982200581Srdivacky NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1983243830Sdim .addOperand(Dest) 1984243830Sdim .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1985193323Sed break; 1986193323Sed } 1987193323Sed default: { 1988193323Sed // The following opcodes also sets the condition code register(s). Only 1989193323Sed // convert them to equivalent lea if the condition code register def's 1990193323Sed // are dead! 1991193323Sed if (hasLiveCondCodeDef(MI)) 1992193323Sed return 0; 1993193323Sed 1994193323Sed switch (MIOpc) { 1995193323Sed default: return 0; 1996193323Sed case X86::INC64r: 1997193323Sed case X86::INC32r: 1998193323Sed case X86::INC64_32r: { 1999193323Sed assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2000193323Sed unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 2001193323Sed : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2002239462Sdim const TargetRegisterClass *RC = MIOpc == X86::INC64r ? 2003239462Sdim (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 2004239462Sdim (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 2005218893Sdim 2006218893Sdim // LEA can't handle RSP. 2007243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2008243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 2009218893Sdim return 0; 2010218893Sdim 2011243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2012243830Sdim .addOperand(Dest).addOperand(Src), 1); 2013193323Sed break; 2014193323Sed } 2015193323Sed case X86::INC16r: 2016193323Sed case X86::INC64_16r: 2017200581Srdivacky if (DisableLEA16) 2018200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2019193323Sed assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2020243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2021243830Sdim .addOperand(Dest).addOperand(Src), 1); 2022193323Sed break; 2023193323Sed case X86::DEC64r: 2024193323Sed case X86::DEC32r: 2025193323Sed case X86::DEC64_32r: { 2026193323Sed assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2027193323Sed unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2028193323Sed : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2029239462Sdim const TargetRegisterClass *RC = MIOpc == X86::DEC64r ? 2030239462Sdim (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 2031239462Sdim (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 2032218893Sdim // LEA can't handle RSP. 2033243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2034243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 2035218893Sdim return 0; 2036218893Sdim 2037243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2038243830Sdim .addOperand(Dest).addOperand(Src), -1); 2039193323Sed break; 2040193323Sed } 2041193323Sed case X86::DEC16r: 2042193323Sed case X86::DEC64_16r: 2043200581Srdivacky if (DisableLEA16) 2044200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2045193323Sed assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2046243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2047243830Sdim .addOperand(Dest).addOperand(Src), -1); 2048193323Sed break; 2049193323Sed case X86::ADD64rr: 2050218893Sdim case X86::ADD64rr_DB: 2051218893Sdim case X86::ADD32rr: 2052218893Sdim case X86::ADD32rr_DB: { 2053193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2054218893Sdim unsigned Opc; 2055234353Sdim const TargetRegisterClass *RC; 2056218893Sdim if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) { 2057218893Sdim Opc = X86::LEA64r; 2058239462Sdim RC = &X86::GR64_NOSPRegClass; 2059218893Sdim } else { 2060218893Sdim Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2061239462Sdim RC = &X86::GR32_NOSPRegClass; 2062218893Sdim } 2063218893Sdim 2064218893Sdim 2065193323Sed unsigned Src2 = MI->getOperand(2).getReg(); 2066193323Sed bool isKill2 = MI->getOperand(2).isKill(); 2067218893Sdim 2068218893Sdim // LEA can't handle RSP. 2069218893Sdim if (TargetRegisterInfo::isVirtualRegister(Src2) && 2070218893Sdim !MF.getRegInfo().constrainRegClass(Src2, RC)) 2071218893Sdim return 0; 2072218893Sdim 2073193323Sed NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2074243830Sdim .addOperand(Dest), 2075243830Sdim Src.getReg(), Src.isKill(), Src2, isKill2); 2076239462Sdim 2077239462Sdim // Preserve undefness of the operands. 2078239462Sdim bool isUndef = MI->getOperand(1).isUndef(); 2079239462Sdim bool isUndef2 = MI->getOperand(2).isUndef(); 2080239462Sdim NewMI->getOperand(1).setIsUndef(isUndef); 2081239462Sdim NewMI->getOperand(3).setIsUndef(isUndef2); 2082239462Sdim 2083193323Sed if (LV && isKill2) 2084193323Sed LV->replaceKillInstruction(Src2, MI, NewMI); 2085193323Sed break; 2086193323Sed } 2087218893Sdim case X86::ADD16rr: 2088218893Sdim case X86::ADD16rr_DB: { 2089200581Srdivacky if (DisableLEA16) 2090200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2091193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2092193323Sed unsigned Src2 = MI->getOperand(2).getReg(); 2093193323Sed bool isKill2 = MI->getOperand(2).isKill(); 2094193323Sed NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2095243830Sdim .addOperand(Dest), 2096243830Sdim Src.getReg(), Src.isKill(), Src2, isKill2); 2097243830Sdim 2098243830Sdim // Preserve undefness of the operands. 2099243830Sdim bool isUndef = MI->getOperand(1).isUndef(); 2100243830Sdim bool isUndef2 = MI->getOperand(2).isUndef(); 2101243830Sdim NewMI->getOperand(1).setIsUndef(isUndef); 2102243830Sdim NewMI->getOperand(3).setIsUndef(isUndef2); 2103243830Sdim 2104193323Sed if (LV && isKill2) 2105193323Sed LV->replaceKillInstruction(Src2, MI, NewMI); 2106193323Sed break; 2107193323Sed } 2108193323Sed case X86::ADD64ri32: 2109193323Sed case X86::ADD64ri8: 2110218893Sdim case X86::ADD64ri32_DB: 2111218893Sdim case X86::ADD64ri8_DB: 2112193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2113243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2114243830Sdim .addOperand(Dest).addOperand(Src), 2115243830Sdim MI->getOperand(2).getImm()); 2116193323Sed break; 2117193323Sed case X86::ADD32ri: 2118218893Sdim case X86::ADD32ri8: 2119218893Sdim case X86::ADD32ri_DB: 2120218893Sdim case X86::ADD32ri8_DB: { 2121193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2122200581Srdivacky unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2123243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2124243830Sdim .addOperand(Dest).addOperand(Src), 2125243830Sdim MI->getOperand(2).getImm()); 2126193323Sed break; 2127200581Srdivacky } 2128193323Sed case X86::ADD16ri: 2129193323Sed case X86::ADD16ri8: 2130218893Sdim case X86::ADD16ri_DB: 2131218893Sdim case X86::ADD16ri8_DB: 2132200581Srdivacky if (DisableLEA16) 2133200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2134193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2135243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2136243830Sdim .addOperand(Dest).addOperand(Src), 2137243830Sdim MI->getOperand(2).getImm()); 2138193323Sed break; 2139193323Sed } 2140193323Sed } 2141193323Sed } 2142193323Sed 2143193323Sed if (!NewMI) return 0; 2144193323Sed 2145193323Sed if (LV) { // Update live variables 2146243830Sdim if (Src.isKill()) 2147243830Sdim LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2148243830Sdim if (Dest.isDead()) 2149243830Sdim LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2150193323Sed } 2151193323Sed 2152218893Sdim MFI->insert(MBBI, NewMI); // Insert the new inst 2153193323Sed return NewMI; 2154193323Sed} 2155193323Sed 2156193323Sed/// commuteInstruction - We have a few instructions that must be hacked on to 2157193323Sed/// commute them. 2158193323Sed/// 2159193323SedMachineInstr * 2160193323SedX86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2161193323Sed switch (MI->getOpcode()) { 2162193323Sed case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2163193323Sed case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2164193323Sed case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2165193323Sed case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2166193323Sed case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2167193323Sed case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2168193323Sed unsigned Opc; 2169193323Sed unsigned Size; 2170193323Sed switch (MI->getOpcode()) { 2171198090Srdivacky default: llvm_unreachable("Unreachable!"); 2172193323Sed case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2173193323Sed case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2174193323Sed case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2175193323Sed case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2176193323Sed case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2177193323Sed case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2178193323Sed } 2179193323Sed unsigned Amt = MI->getOperand(3).getImm(); 2180193323Sed if (NewMI) { 2181193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 2182193323Sed MI = MF.CloneMachineInstr(MI); 2183193323Sed NewMI = false; 2184193323Sed } 2185193323Sed MI->setDesc(get(Opc)); 2186193323Sed MI->getOperand(3).setImm(Size-Amt); 2187249423Sdim return TargetInstrInfo::commuteInstruction(MI, NewMI); 2188193323Sed } 2189243830Sdim case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2190243830Sdim case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2191243830Sdim case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2192243830Sdim case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2193243830Sdim case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2194243830Sdim case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2195243830Sdim case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2196243830Sdim case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2197243830Sdim case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2198243830Sdim case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2199243830Sdim case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2200243830Sdim case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2201243830Sdim case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2202243830Sdim case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2203243830Sdim case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2204243830Sdim case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2205243830Sdim unsigned Opc; 2206193323Sed switch (MI->getOpcode()) { 2207243830Sdim default: llvm_unreachable("Unreachable!"); 2208193323Sed case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2209193323Sed case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2210193323Sed case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2211193323Sed case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2212193323Sed case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2213193323Sed case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2214193323Sed case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2215193323Sed case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2216193323Sed case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2217193323Sed case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2218193323Sed case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2219193323Sed case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2220193323Sed case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2221193323Sed case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2222193323Sed case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2223193323Sed case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2224193323Sed case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2225193323Sed case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2226193323Sed case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2227193323Sed case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2228193323Sed case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2229193323Sed case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2230193323Sed case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2231193323Sed case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2232193323Sed case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2233193323Sed case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2234193323Sed case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2235193323Sed case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2236193323Sed case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2237193323Sed case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2238193323Sed case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2239193323Sed case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2240193323Sed case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2241193323Sed case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2242193323Sed case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2243193323Sed case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2244193323Sed case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2245193323Sed case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2246193323Sed case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2247193323Sed case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2248193323Sed case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2249193323Sed case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2250193323Sed case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2251193323Sed case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2252193323Sed case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2253193323Sed case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2254193323Sed case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2255193323Sed case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2256193323Sed } 2257193323Sed if (NewMI) { 2258193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 2259193323Sed MI = MF.CloneMachineInstr(MI); 2260193323Sed NewMI = false; 2261193323Sed } 2262193323Sed MI->setDesc(get(Opc)); 2263193323Sed // Fallthrough intended. 2264193323Sed } 2265193323Sed default: 2266249423Sdim return TargetInstrInfo::commuteInstruction(MI, NewMI); 2267193323Sed } 2268193323Sed} 2269193323Sed 2270239462Sdimstatic X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2271193323Sed switch (BrOpc) { 2272193323Sed default: return X86::COND_INVALID; 2273203954Srdivacky case X86::JE_4: return X86::COND_E; 2274203954Srdivacky case X86::JNE_4: return X86::COND_NE; 2275203954Srdivacky case X86::JL_4: return X86::COND_L; 2276203954Srdivacky case X86::JLE_4: return X86::COND_LE; 2277203954Srdivacky case X86::JG_4: return X86::COND_G; 2278203954Srdivacky case X86::JGE_4: return X86::COND_GE; 2279203954Srdivacky case X86::JB_4: return X86::COND_B; 2280203954Srdivacky case X86::JBE_4: return X86::COND_BE; 2281203954Srdivacky case X86::JA_4: return X86::COND_A; 2282203954Srdivacky case X86::JAE_4: return X86::COND_AE; 2283203954Srdivacky case X86::JS_4: return X86::COND_S; 2284203954Srdivacky case X86::JNS_4: return X86::COND_NS; 2285203954Srdivacky case X86::JP_4: return X86::COND_P; 2286203954Srdivacky case X86::JNP_4: return X86::COND_NP; 2287203954Srdivacky case X86::JO_4: return X86::COND_O; 2288203954Srdivacky case X86::JNO_4: return X86::COND_NO; 2289193323Sed } 2290193323Sed} 2291193323Sed 2292239462Sdim/// getCondFromSETOpc - return condition code of a SET opcode. 2293239462Sdimstatic X86::CondCode getCondFromSETOpc(unsigned Opc) { 2294239462Sdim switch (Opc) { 2295239462Sdim default: return X86::COND_INVALID; 2296239462Sdim case X86::SETAr: case X86::SETAm: return X86::COND_A; 2297239462Sdim case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2298239462Sdim case X86::SETBr: case X86::SETBm: return X86::COND_B; 2299239462Sdim case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2300239462Sdim case X86::SETEr: case X86::SETEm: return X86::COND_E; 2301239462Sdim case X86::SETGr: case X86::SETGm: return X86::COND_G; 2302239462Sdim case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2303239462Sdim case X86::SETLr: case X86::SETLm: return X86::COND_L; 2304239462Sdim case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2305239462Sdim case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2306239462Sdim case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2307239462Sdim case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2308239462Sdim case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2309239462Sdim case X86::SETOr: case X86::SETOm: return X86::COND_O; 2310239462Sdim case X86::SETPr: case X86::SETPm: return X86::COND_P; 2311239462Sdim case X86::SETSr: case X86::SETSm: return X86::COND_S; 2312239462Sdim } 2313239462Sdim} 2314239462Sdim 2315239462Sdim/// getCondFromCmovOpc - return condition code of a CMov opcode. 2316243830SdimX86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2317239462Sdim switch (Opc) { 2318239462Sdim default: return X86::COND_INVALID; 2319239462Sdim case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2320239462Sdim case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2321239462Sdim return X86::COND_A; 2322239462Sdim case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2323239462Sdim case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2324239462Sdim return X86::COND_AE; 2325239462Sdim case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2326239462Sdim case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2327239462Sdim return X86::COND_B; 2328239462Sdim case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2329239462Sdim case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2330239462Sdim return X86::COND_BE; 2331239462Sdim case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2332239462Sdim case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2333239462Sdim return X86::COND_E; 2334239462Sdim case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2335239462Sdim case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2336239462Sdim return X86::COND_G; 2337239462Sdim case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2338239462Sdim case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2339239462Sdim return X86::COND_GE; 2340239462Sdim case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2341239462Sdim case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2342239462Sdim return X86::COND_L; 2343239462Sdim case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2344239462Sdim case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2345239462Sdim return X86::COND_LE; 2346239462Sdim case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2347239462Sdim case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2348239462Sdim return X86::COND_NE; 2349239462Sdim case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2350239462Sdim case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2351239462Sdim return X86::COND_NO; 2352239462Sdim case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2353239462Sdim case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2354239462Sdim return X86::COND_NP; 2355239462Sdim case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2356239462Sdim case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2357239462Sdim return X86::COND_NS; 2358239462Sdim case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2359239462Sdim case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2360239462Sdim return X86::COND_O; 2361239462Sdim case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2362239462Sdim case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2363239462Sdim return X86::COND_P; 2364239462Sdim case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2365239462Sdim case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2366239462Sdim return X86::COND_S; 2367239462Sdim } 2368239462Sdim} 2369239462Sdim 2370193323Sedunsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2371193323Sed switch (CC) { 2372198090Srdivacky default: llvm_unreachable("Illegal condition code!"); 2373203954Srdivacky case X86::COND_E: return X86::JE_4; 2374203954Srdivacky case X86::COND_NE: return X86::JNE_4; 2375203954Srdivacky case X86::COND_L: return X86::JL_4; 2376203954Srdivacky case X86::COND_LE: return X86::JLE_4; 2377203954Srdivacky case X86::COND_G: return X86::JG_4; 2378203954Srdivacky case X86::COND_GE: return X86::JGE_4; 2379203954Srdivacky case X86::COND_B: return X86::JB_4; 2380203954Srdivacky case X86::COND_BE: return X86::JBE_4; 2381203954Srdivacky case X86::COND_A: return X86::JA_4; 2382203954Srdivacky case X86::COND_AE: return X86::JAE_4; 2383203954Srdivacky case X86::COND_S: return X86::JS_4; 2384203954Srdivacky case X86::COND_NS: return X86::JNS_4; 2385203954Srdivacky case X86::COND_P: return X86::JP_4; 2386203954Srdivacky case X86::COND_NP: return X86::JNP_4; 2387203954Srdivacky case X86::COND_O: return X86::JO_4; 2388203954Srdivacky case X86::COND_NO: return X86::JNO_4; 2389193323Sed } 2390193323Sed} 2391193323Sed 2392193323Sed/// GetOppositeBranchCondition - Return the inverse of the specified condition, 2393193323Sed/// e.g. turning COND_E to COND_NE. 2394193323SedX86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2395193323Sed switch (CC) { 2396198090Srdivacky default: llvm_unreachable("Illegal condition code!"); 2397193323Sed case X86::COND_E: return X86::COND_NE; 2398193323Sed case X86::COND_NE: return X86::COND_E; 2399193323Sed case X86::COND_L: return X86::COND_GE; 2400193323Sed case X86::COND_LE: return X86::COND_G; 2401193323Sed case X86::COND_G: return X86::COND_LE; 2402193323Sed case X86::COND_GE: return X86::COND_L; 2403193323Sed case X86::COND_B: return X86::COND_AE; 2404193323Sed case X86::COND_BE: return X86::COND_A; 2405193323Sed case X86::COND_A: return X86::COND_BE; 2406193323Sed case X86::COND_AE: return X86::COND_B; 2407193323Sed case X86::COND_S: return X86::COND_NS; 2408193323Sed case X86::COND_NS: return X86::COND_S; 2409193323Sed case X86::COND_P: return X86::COND_NP; 2410193323Sed case X86::COND_NP: return X86::COND_P; 2411193323Sed case X86::COND_O: return X86::COND_NO; 2412193323Sed case X86::COND_NO: return X86::COND_O; 2413193323Sed } 2414193323Sed} 2415193323Sed 2416239462Sdim/// getSwappedCondition - assume the flags are set by MI(a,b), return 2417239462Sdim/// the condition code if we modify the instructions such that flags are 2418239462Sdim/// set by MI(b,a). 2419239462Sdimstatic X86::CondCode getSwappedCondition(X86::CondCode CC) { 2420239462Sdim switch (CC) { 2421239462Sdim default: return X86::COND_INVALID; 2422239462Sdim case X86::COND_E: return X86::COND_E; 2423239462Sdim case X86::COND_NE: return X86::COND_NE; 2424239462Sdim case X86::COND_L: return X86::COND_G; 2425239462Sdim case X86::COND_LE: return X86::COND_GE; 2426239462Sdim case X86::COND_G: return X86::COND_L; 2427239462Sdim case X86::COND_GE: return X86::COND_LE; 2428239462Sdim case X86::COND_B: return X86::COND_A; 2429239462Sdim case X86::COND_BE: return X86::COND_AE; 2430239462Sdim case X86::COND_A: return X86::COND_B; 2431239462Sdim case X86::COND_AE: return X86::COND_BE; 2432239462Sdim } 2433239462Sdim} 2434239462Sdim 2435239462Sdim/// getSETFromCond - Return a set opcode for the given condition and 2436239462Sdim/// whether it has memory operand. 2437239462Sdimstatic unsigned getSETFromCond(X86::CondCode CC, 2438239462Sdim bool HasMemoryOperand) { 2439243830Sdim static const uint16_t Opc[16][2] = { 2440239462Sdim { X86::SETAr, X86::SETAm }, 2441239462Sdim { X86::SETAEr, X86::SETAEm }, 2442239462Sdim { X86::SETBr, X86::SETBm }, 2443239462Sdim { X86::SETBEr, X86::SETBEm }, 2444239462Sdim { X86::SETEr, X86::SETEm }, 2445239462Sdim { X86::SETGr, X86::SETGm }, 2446239462Sdim { X86::SETGEr, X86::SETGEm }, 2447239462Sdim { X86::SETLr, X86::SETLm }, 2448239462Sdim { X86::SETLEr, X86::SETLEm }, 2449239462Sdim { X86::SETNEr, X86::SETNEm }, 2450239462Sdim { X86::SETNOr, X86::SETNOm }, 2451239462Sdim { X86::SETNPr, X86::SETNPm }, 2452239462Sdim { X86::SETNSr, X86::SETNSm }, 2453239462Sdim { X86::SETOr, X86::SETOm }, 2454239462Sdim { X86::SETPr, X86::SETPm }, 2455239462Sdim { X86::SETSr, X86::SETSm } 2456239462Sdim }; 2457239462Sdim 2458239462Sdim assert(CC < 16 && "Can only handle standard cond codes"); 2459239462Sdim return Opc[CC][HasMemoryOperand ? 1 : 0]; 2460239462Sdim} 2461239462Sdim 2462239462Sdim/// getCMovFromCond - Return a cmov opcode for the given condition, 2463239462Sdim/// register size in bytes, and operand type. 2464239462Sdimstatic unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, 2465239462Sdim bool HasMemoryOperand) { 2466243830Sdim static const uint16_t Opc[32][3] = { 2467239462Sdim { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2468239462Sdim { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2469239462Sdim { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2470239462Sdim { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2471239462Sdim { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2472239462Sdim { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2473239462Sdim { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2474239462Sdim { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2475239462Sdim { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2476239462Sdim { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2477239462Sdim { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2478239462Sdim { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2479239462Sdim { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2480239462Sdim { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2481239462Sdim { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2482239462Sdim { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2483239462Sdim { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2484239462Sdim { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2485239462Sdim { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2486239462Sdim { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2487239462Sdim { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2488239462Sdim { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2489239462Sdim { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2490239462Sdim { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2491239462Sdim { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2492239462Sdim { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2493239462Sdim { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2494239462Sdim { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2495239462Sdim { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2496239462Sdim { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2497239462Sdim { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2498239462Sdim { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2499239462Sdim }; 2500239462Sdim 2501239462Sdim assert(CC < 16 && "Can only handle standard cond codes"); 2502239462Sdim unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2503239462Sdim switch(RegBytes) { 2504239462Sdim default: llvm_unreachable("Illegal register size!"); 2505239462Sdim case 2: return Opc[Idx][0]; 2506239462Sdim case 4: return Opc[Idx][1]; 2507239462Sdim case 8: return Opc[Idx][2]; 2508239462Sdim } 2509239462Sdim} 2510239462Sdim 2511193323Sedbool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2512234353Sdim if (!MI->isTerminator()) return false; 2513218893Sdim 2514193323Sed // Conditional branch is a special case. 2515234353Sdim if (MI->isBranch() && !MI->isBarrier()) 2516193323Sed return true; 2517234353Sdim if (!MI->isPredicable()) 2518193323Sed return true; 2519193323Sed return !isPredicated(MI); 2520193323Sed} 2521193323Sed 2522218893Sdimbool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2523193323Sed MachineBasicBlock *&TBB, 2524193323Sed MachineBasicBlock *&FBB, 2525193323Sed SmallVectorImpl<MachineOperand> &Cond, 2526193323Sed bool AllowModify) const { 2527193323Sed // Start from the bottom of the block and work up, examining the 2528193323Sed // terminator instructions. 2529193323Sed MachineBasicBlock::iterator I = MBB.end(); 2530207618Srdivacky MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2531193323Sed while (I != MBB.begin()) { 2532193323Sed --I; 2533206083Srdivacky if (I->isDebugValue()) 2534206083Srdivacky continue; 2535200581Srdivacky 2536200581Srdivacky // Working from the bottom, when we see a non-terminator instruction, we're 2537200581Srdivacky // done. 2538212904Sdim if (!isUnpredicatedTerminator(I)) 2539193323Sed break; 2540200581Srdivacky 2541200581Srdivacky // A terminator that isn't a branch can't easily be handled by this 2542200581Srdivacky // analysis. 2543234353Sdim if (!I->isBranch()) 2544193323Sed return true; 2545200581Srdivacky 2546193323Sed // Handle unconditional branches. 2547203954Srdivacky if (I->getOpcode() == X86::JMP_4) { 2548207618Srdivacky UnCondBrIter = I; 2549207618Srdivacky 2550193323Sed if (!AllowModify) { 2551193323Sed TBB = I->getOperand(0).getMBB(); 2552193323Sed continue; 2553193323Sed } 2554193323Sed 2555193323Sed // If the block has any instructions after a JMP, delete them. 2556200581Srdivacky while (llvm::next(I) != MBB.end()) 2557200581Srdivacky llvm::next(I)->eraseFromParent(); 2558200581Srdivacky 2559193323Sed Cond.clear(); 2560193323Sed FBB = 0; 2561200581Srdivacky 2562193323Sed // Delete the JMP if it's equivalent to a fall-through. 2563193323Sed if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2564193323Sed TBB = 0; 2565193323Sed I->eraseFromParent(); 2566193323Sed I = MBB.end(); 2567207618Srdivacky UnCondBrIter = MBB.end(); 2568193323Sed continue; 2569193323Sed } 2570200581Srdivacky 2571207618Srdivacky // TBB is used to indicate the unconditional destination. 2572193323Sed TBB = I->getOperand(0).getMBB(); 2573193323Sed continue; 2574193323Sed } 2575200581Srdivacky 2576193323Sed // Handle conditional branches. 2577239462Sdim X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2578193323Sed if (BranchCode == X86::COND_INVALID) 2579193323Sed return true; // Can't handle indirect branch. 2580200581Srdivacky 2581193323Sed // Working from the bottom, handle the first conditional branch. 2582193323Sed if (Cond.empty()) { 2583207618Srdivacky MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2584207618Srdivacky if (AllowModify && UnCondBrIter != MBB.end() && 2585207618Srdivacky MBB.isLayoutSuccessor(TargetBB)) { 2586207618Srdivacky // If we can modify the code and it ends in something like: 2587207618Srdivacky // 2588207618Srdivacky // jCC L1 2589207618Srdivacky // jmp L2 2590207618Srdivacky // L1: 2591207618Srdivacky // ... 2592207618Srdivacky // L2: 2593207618Srdivacky // 2594207618Srdivacky // Then we can change this to: 2595207618Srdivacky // 2596207618Srdivacky // jnCC L2 2597207618Srdivacky // L1: 2598207618Srdivacky // ... 2599207618Srdivacky // L2: 2600207618Srdivacky // 2601207618Srdivacky // Which is a bit more efficient. 2602207618Srdivacky // We conditionally jump to the fall-through block. 2603207618Srdivacky BranchCode = GetOppositeBranchCondition(BranchCode); 2604207618Srdivacky unsigned JNCC = GetCondBranchFromCond(BranchCode); 2605207618Srdivacky MachineBasicBlock::iterator OldInst = I; 2606207618Srdivacky 2607207618Srdivacky BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2608207618Srdivacky .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2609207618Srdivacky BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2610207618Srdivacky .addMBB(TargetBB); 2611207618Srdivacky 2612207618Srdivacky OldInst->eraseFromParent(); 2613207618Srdivacky UnCondBrIter->eraseFromParent(); 2614207618Srdivacky 2615207618Srdivacky // Restart the analysis. 2616207618Srdivacky UnCondBrIter = MBB.end(); 2617207618Srdivacky I = MBB.end(); 2618207618Srdivacky continue; 2619207618Srdivacky } 2620207618Srdivacky 2621193323Sed FBB = TBB; 2622193323Sed TBB = I->getOperand(0).getMBB(); 2623193323Sed Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2624193323Sed continue; 2625193323Sed } 2626200581Srdivacky 2627200581Srdivacky // Handle subsequent conditional branches. Only handle the case where all 2628200581Srdivacky // conditional branches branch to the same destination and their condition 2629200581Srdivacky // opcodes fit one of the special multi-branch idioms. 2630193323Sed assert(Cond.size() == 1); 2631193323Sed assert(TBB); 2632200581Srdivacky 2633200581Srdivacky // Only handle the case where all conditional branches branch to the same 2634200581Srdivacky // destination. 2635193323Sed if (TBB != I->getOperand(0).getMBB()) 2636193323Sed return true; 2637200581Srdivacky 2638200581Srdivacky // If the conditions are the same, we can leave them alone. 2639193323Sed X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2640193323Sed if (OldBranchCode == BranchCode) 2641193323Sed continue; 2642200581Srdivacky 2643200581Srdivacky // If they differ, see if they fit one of the known patterns. Theoretically, 2644200581Srdivacky // we could handle more patterns here, but we shouldn't expect to see them 2645200581Srdivacky // if instruction selection has done a reasonable job. 2646193323Sed if ((OldBranchCode == X86::COND_NP && 2647193323Sed BranchCode == X86::COND_E) || 2648193323Sed (OldBranchCode == X86::COND_E && 2649193323Sed BranchCode == X86::COND_NP)) 2650193323Sed BranchCode = X86::COND_NP_OR_E; 2651193323Sed else if ((OldBranchCode == X86::COND_P && 2652193323Sed BranchCode == X86::COND_NE) || 2653193323Sed (OldBranchCode == X86::COND_NE && 2654193323Sed BranchCode == X86::COND_P)) 2655193323Sed BranchCode = X86::COND_NE_OR_P; 2656193323Sed else 2657193323Sed return true; 2658200581Srdivacky 2659193323Sed // Update the MachineOperand. 2660193323Sed Cond[0].setImm(BranchCode); 2661193323Sed } 2662193323Sed 2663193323Sed return false; 2664193323Sed} 2665193323Sed 2666193323Sedunsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2667193323Sed MachineBasicBlock::iterator I = MBB.end(); 2668193323Sed unsigned Count = 0; 2669193323Sed 2670193323Sed while (I != MBB.begin()) { 2671193323Sed --I; 2672206083Srdivacky if (I->isDebugValue()) 2673206083Srdivacky continue; 2674203954Srdivacky if (I->getOpcode() != X86::JMP_4 && 2675239462Sdim getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2676193323Sed break; 2677193323Sed // Remove the branch. 2678193323Sed I->eraseFromParent(); 2679193323Sed I = MBB.end(); 2680193323Sed ++Count; 2681193323Sed } 2682218893Sdim 2683193323Sed return Count; 2684193323Sed} 2685193323Sed 2686193323Sedunsigned 2687193323SedX86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2688193323Sed MachineBasicBlock *FBB, 2689210299Sed const SmallVectorImpl<MachineOperand> &Cond, 2690210299Sed DebugLoc DL) const { 2691193323Sed // Shouldn't be a fall through. 2692193323Sed assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2693193323Sed assert((Cond.size() == 1 || Cond.size() == 0) && 2694193323Sed "X86 branch conditions have one component!"); 2695193323Sed 2696193323Sed if (Cond.empty()) { 2697193323Sed // Unconditional branch? 2698193323Sed assert(!FBB && "Unconditional branch with multiple successors!"); 2699210299Sed BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2700193323Sed return 1; 2701193323Sed } 2702193323Sed 2703193323Sed // Conditional branch. 2704193323Sed unsigned Count = 0; 2705193323Sed X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2706193323Sed switch (CC) { 2707193323Sed case X86::COND_NP_OR_E: 2708193323Sed // Synthesize NP_OR_E with two branches. 2709210299Sed BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2710193323Sed ++Count; 2711210299Sed BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2712193323Sed ++Count; 2713193323Sed break; 2714193323Sed case X86::COND_NE_OR_P: 2715193323Sed // Synthesize NE_OR_P with two branches. 2716210299Sed BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2717193323Sed ++Count; 2718210299Sed BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2719193323Sed ++Count; 2720193323Sed break; 2721193323Sed default: { 2722193323Sed unsigned Opc = GetCondBranchFromCond(CC); 2723210299Sed BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2724193323Sed ++Count; 2725193323Sed } 2726193323Sed } 2727193323Sed if (FBB) { 2728193323Sed // Two-way Conditional branch. Insert the second branch. 2729210299Sed BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2730193323Sed ++Count; 2731193323Sed } 2732193323Sed return Count; 2733193323Sed} 2734193323Sed 2735239462Sdimbool X86InstrInfo:: 2736239462SdimcanInsertSelect(const MachineBasicBlock &MBB, 2737239462Sdim const SmallVectorImpl<MachineOperand> &Cond, 2738239462Sdim unsigned TrueReg, unsigned FalseReg, 2739239462Sdim int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2740239462Sdim // Not all subtargets have cmov instructions. 2741239462Sdim if (!TM.getSubtarget<X86Subtarget>().hasCMov()) 2742239462Sdim return false; 2743239462Sdim if (Cond.size() != 1) 2744239462Sdim return false; 2745239462Sdim // We cannot do the composite conditions, at least not in SSA form. 2746239462Sdim if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2747239462Sdim return false; 2748239462Sdim 2749239462Sdim // Check register classes. 2750239462Sdim const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2751239462Sdim const TargetRegisterClass *RC = 2752239462Sdim RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2753239462Sdim if (!RC) 2754239462Sdim return false; 2755239462Sdim 2756239462Sdim // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2757239462Sdim if (X86::GR16RegClass.hasSubClassEq(RC) || 2758239462Sdim X86::GR32RegClass.hasSubClassEq(RC) || 2759239462Sdim X86::GR64RegClass.hasSubClassEq(RC)) { 2760239462Sdim // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2761239462Sdim // Bridge. Probably Ivy Bridge as well. 2762239462Sdim CondCycles = 2; 2763239462Sdim TrueCycles = 2; 2764239462Sdim FalseCycles = 2; 2765239462Sdim return true; 2766239462Sdim } 2767239462Sdim 2768239462Sdim // Can't do vectors. 2769239462Sdim return false; 2770239462Sdim} 2771239462Sdim 2772239462Sdimvoid X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 2773239462Sdim MachineBasicBlock::iterator I, DebugLoc DL, 2774239462Sdim unsigned DstReg, 2775239462Sdim const SmallVectorImpl<MachineOperand> &Cond, 2776239462Sdim unsigned TrueReg, unsigned FalseReg) const { 2777239462Sdim MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2778239462Sdim assert(Cond.size() == 1 && "Invalid Cond array"); 2779239462Sdim unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 2780239462Sdim MRI.getRegClass(DstReg)->getSize(), 2781239462Sdim false/*HasMemoryOperand*/); 2782239462Sdim BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 2783239462Sdim} 2784239462Sdim 2785193323Sed/// isHReg - Test if the given register is a physical h register. 2786193323Sedstatic bool isHReg(unsigned Reg) { 2787193323Sed return X86::GR8_ABCD_HRegClass.contains(Reg); 2788193323Sed} 2789193323Sed 2790212904Sdim// Try and copy between VR128/VR64 and GR64 registers. 2791226633Sdimstatic unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 2792226633Sdim bool HasAVX) { 2793212904Sdim // SrcReg(VR128) -> DestReg(GR64) 2794212904Sdim // SrcReg(VR64) -> DestReg(GR64) 2795212904Sdim // SrcReg(GR64) -> DestReg(VR128) 2796212904Sdim // SrcReg(GR64) -> DestReg(VR64) 2797212904Sdim 2798212904Sdim if (X86::GR64RegClass.contains(DestReg)) { 2799243830Sdim if (X86::VR128RegClass.contains(SrcReg)) 2800212904Sdim // Copy from a VR128 register to a GR64 register. 2801226633Sdim return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr; 2802243830Sdim if (X86::VR64RegClass.contains(SrcReg)) 2803212904Sdim // Copy from a VR64 register to a GR64 register. 2804212904Sdim return X86::MOVSDto64rr; 2805212904Sdim } else if (X86::GR64RegClass.contains(SrcReg)) { 2806212904Sdim // Copy from a GR64 register to a VR128 register. 2807212904Sdim if (X86::VR128RegClass.contains(DestReg)) 2808226633Sdim return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr; 2809212904Sdim // Copy from a GR64 register to a VR64 register. 2810243830Sdim if (X86::VR64RegClass.contains(DestReg)) 2811212904Sdim return X86::MOV64toSDrr; 2812212904Sdim } 2813212904Sdim 2814226633Sdim // SrcReg(FR32) -> DestReg(GR32) 2815226633Sdim // SrcReg(GR32) -> DestReg(FR32) 2816226633Sdim 2817226633Sdim if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg)) 2818243830Sdim // Copy from a FR32 register to a GR32 register. 2819243830Sdim return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr; 2820226633Sdim 2821226633Sdim if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 2822243830Sdim // Copy from a GR32 register to a FR32 register. 2823243830Sdim return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr; 2824226633Sdim 2825212904Sdim return 0; 2826212904Sdim} 2827212904Sdim 2828210299Sedvoid X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 2829210299Sed MachineBasicBlock::iterator MI, DebugLoc DL, 2830210299Sed unsigned DestReg, unsigned SrcReg, 2831210299Sed bool KillSrc) const { 2832210299Sed // First deal with the normal symmetric copies. 2833226633Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2834243830Sdim unsigned Opc; 2835210299Sed if (X86::GR64RegClass.contains(DestReg, SrcReg)) 2836210299Sed Opc = X86::MOV64rr; 2837210299Sed else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 2838210299Sed Opc = X86::MOV32rr; 2839210299Sed else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 2840210299Sed Opc = X86::MOV16rr; 2841210299Sed else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 2842210299Sed // Copying to or from a physical H register on x86-64 requires a NOREX 2843210299Sed // move. Otherwise use a normal move. 2844210299Sed if ((isHReg(DestReg) || isHReg(SrcReg)) && 2845226633Sdim TM.getSubtarget<X86Subtarget>().is64Bit()) { 2846210299Sed Opc = X86::MOV8rr_NOREX; 2847226633Sdim // Both operands must be encodable without an REX prefix. 2848226633Sdim assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 2849226633Sdim "8-bit H register can not be copied outside GR8_NOREX"); 2850226633Sdim } else 2851210299Sed Opc = X86::MOV8rr; 2852210299Sed } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 2853226633Sdim Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 2854224145Sdim else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 2855224145Sdim Opc = X86::VMOVAPSYrr; 2856210299Sed else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 2857210299Sed Opc = X86::MMX_MOVQ64rr; 2858212904Sdim else 2859226633Sdim Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX); 2860193323Sed 2861210299Sed if (Opc) { 2862210299Sed BuildMI(MBB, MI, DL, get(Opc), DestReg) 2863210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 2864210299Sed return; 2865193323Sed } 2866198090Srdivacky 2867193323Sed // Moving EFLAGS to / from another register requires a push and a pop. 2868249423Sdim // Notice that we have to adjust the stack if we don't want to clobber the 2869249423Sdim // first frame index. See X86FrameLowering.cpp - colobbersTheStack. 2870210299Sed if (SrcReg == X86::EFLAGS) { 2871210299Sed if (X86::GR64RegClass.contains(DestReg)) { 2872208599Srdivacky BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 2873193323Sed BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 2874210299Sed return; 2875243830Sdim } 2876243830Sdim if (X86::GR32RegClass.contains(DestReg)) { 2877208599Srdivacky BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 2878193323Sed BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 2879210299Sed return; 2880193323Sed } 2881210299Sed } 2882210299Sed if (DestReg == X86::EFLAGS) { 2883210299Sed if (X86::GR64RegClass.contains(SrcReg)) { 2884210299Sed BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 2885210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 2886208599Srdivacky BuildMI(MBB, MI, DL, get(X86::POPF64)); 2887210299Sed return; 2888243830Sdim } 2889243830Sdim if (X86::GR32RegClass.contains(SrcReg)) { 2890210299Sed BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2891210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 2892208599Srdivacky BuildMI(MBB, MI, DL, get(X86::POPF32)); 2893210299Sed return; 2894193323Sed } 2895193323Sed } 2896193323Sed 2897210299Sed DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2898210299Sed << " to " << RI.getName(DestReg) << '\n'); 2899210299Sed llvm_unreachable("Cannot emit physreg copy instruction"); 2900193323Sed} 2901193323Sed 2902210299Sedstatic unsigned getLoadStoreRegOpcode(unsigned Reg, 2903210299Sed const TargetRegisterClass *RC, 2904210299Sed bool isStackAligned, 2905210299Sed const TargetMachine &TM, 2906210299Sed bool load) { 2907226633Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2908223017Sdim switch (RC->getSize()) { 2909210299Sed default: 2910223017Sdim llvm_unreachable("Unknown spill size"); 2911223017Sdim case 1: 2912223017Sdim assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 2913223017Sdim if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2914223017Sdim // Copying to or from a physical H register on x86-64 requires a NOREX 2915223017Sdim // move. Otherwise use a normal move. 2916223017Sdim if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 2917223017Sdim return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2918223017Sdim return load ? X86::MOV8rm : X86::MOV8mr; 2919223017Sdim case 2: 2920223017Sdim assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 2921210299Sed return load ? X86::MOV16rm : X86::MOV16mr; 2922223017Sdim case 4: 2923223017Sdim if (X86::GR32RegClass.hasSubClassEq(RC)) 2924223017Sdim return load ? X86::MOV32rm : X86::MOV32mr; 2925223017Sdim if (X86::FR32RegClass.hasSubClassEq(RC)) 2926226633Sdim return load ? 2927226633Sdim (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 2928226633Sdim (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 2929223017Sdim if (X86::RFP32RegClass.hasSubClassEq(RC)) 2930223017Sdim return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2931223017Sdim llvm_unreachable("Unknown 4-byte regclass"); 2932223017Sdim case 8: 2933223017Sdim if (X86::GR64RegClass.hasSubClassEq(RC)) 2934223017Sdim return load ? X86::MOV64rm : X86::MOV64mr; 2935223017Sdim if (X86::FR64RegClass.hasSubClassEq(RC)) 2936226633Sdim return load ? 2937226633Sdim (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 2938226633Sdim (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 2939223017Sdim if (X86::VR64RegClass.hasSubClassEq(RC)) 2940223017Sdim return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2941223017Sdim if (X86::RFP64RegClass.hasSubClassEq(RC)) 2942223017Sdim return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2943223017Sdim llvm_unreachable("Unknown 8-byte regclass"); 2944223017Sdim case 10: 2945223017Sdim assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 2946210299Sed return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2947226633Sdim case 16: { 2948223017Sdim assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); 2949193323Sed // If stack is realigned we can use aligned stores. 2950210299Sed if (isStackAligned) 2951226633Sdim return load ? 2952226633Sdim (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 2953226633Sdim (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 2954210299Sed else 2955226633Sdim return load ? 2956226633Sdim (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 2957226633Sdim (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 2958226633Sdim } 2959224145Sdim case 32: 2960224145Sdim assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 2961224145Sdim // If stack is realigned we can use aligned stores. 2962224145Sdim if (isStackAligned) 2963224145Sdim return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 2964224145Sdim else 2965224145Sdim return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 2966193323Sed } 2967210299Sed} 2968193323Sed 2969210299Sedstatic unsigned getStoreRegOpcode(unsigned SrcReg, 2970210299Sed const TargetRegisterClass *RC, 2971210299Sed bool isStackAligned, 2972210299Sed TargetMachine &TM) { 2973210299Sed return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2974193323Sed} 2975193323Sed 2976210299Sed 2977210299Sedstatic unsigned getLoadRegOpcode(unsigned DestReg, 2978210299Sed const TargetRegisterClass *RC, 2979210299Sed bool isStackAligned, 2980210299Sed const TargetMachine &TM) { 2981210299Sed return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2982210299Sed} 2983210299Sed 2984193323Sedvoid X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2985193323Sed MachineBasicBlock::iterator MI, 2986193323Sed unsigned SrcReg, bool isKill, int FrameIdx, 2987208599Srdivacky const TargetRegisterClass *RC, 2988208599Srdivacky const TargetRegisterInfo *TRI) const { 2989193323Sed const MachineFunction &MF = *MBB.getParent(); 2990212904Sdim assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2991212904Sdim "Stack slot too small for store"); 2992226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2993226633Sdim bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2994224145Sdim RI.canRealignStack(MF); 2995193323Sed unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2996203954Srdivacky DebugLoc DL = MBB.findDebugLoc(MI); 2997193323Sed addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2998193323Sed .addReg(SrcReg, getKillRegState(isKill)); 2999193323Sed} 3000193323Sed 3001193323Sedvoid X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 3002193323Sed bool isKill, 3003193323Sed SmallVectorImpl<MachineOperand> &Addr, 3004193323Sed const TargetRegisterClass *RC, 3005198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 3006198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 3007193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const { 3008226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3009226633Sdim bool isAligned = MMOBegin != MMOEnd && 3010226633Sdim (*MMOBegin)->getAlignment() >= Alignment; 3011193323Sed unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 3012206124Srdivacky DebugLoc DL; 3013193323Sed MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 3014193323Sed for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3015193323Sed MIB.addOperand(Addr[i]); 3016193323Sed MIB.addReg(SrcReg, getKillRegState(isKill)); 3017198090Srdivacky (*MIB).setMemRefs(MMOBegin, MMOEnd); 3018193323Sed NewMIs.push_back(MIB); 3019193323Sed} 3020193323Sed 3021193323Sed 3022193323Sedvoid X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 3023193323Sed MachineBasicBlock::iterator MI, 3024193323Sed unsigned DestReg, int FrameIdx, 3025208599Srdivacky const TargetRegisterClass *RC, 3026208599Srdivacky const TargetRegisterInfo *TRI) const { 3027193323Sed const MachineFunction &MF = *MBB.getParent(); 3028226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3029226633Sdim bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 3030224145Sdim RI.canRealignStack(MF); 3031193323Sed unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3032203954Srdivacky DebugLoc DL = MBB.findDebugLoc(MI); 3033193323Sed addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 3034193323Sed} 3035193323Sed 3036193323Sedvoid X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3037193323Sed SmallVectorImpl<MachineOperand> &Addr, 3038193323Sed const TargetRegisterClass *RC, 3039198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 3040198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 3041193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const { 3042226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3043226633Sdim bool isAligned = MMOBegin != MMOEnd && 3044226633Sdim (*MMOBegin)->getAlignment() >= Alignment; 3045193323Sed unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3046206124Srdivacky DebugLoc DL; 3047193323Sed MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3048193323Sed for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3049193323Sed MIB.addOperand(Addr[i]); 3050198090Srdivacky (*MIB).setMemRefs(MMOBegin, MMOEnd); 3051193323Sed NewMIs.push_back(MIB); 3052193323Sed} 3053193323Sed 3054239462Sdimbool X86InstrInfo:: 3055239462SdimanalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3056239462Sdim int &CmpMask, int &CmpValue) const { 3057239462Sdim switch (MI->getOpcode()) { 3058239462Sdim default: break; 3059239462Sdim case X86::CMP64ri32: 3060239462Sdim case X86::CMP64ri8: 3061239462Sdim case X86::CMP32ri: 3062239462Sdim case X86::CMP32ri8: 3063239462Sdim case X86::CMP16ri: 3064239462Sdim case X86::CMP16ri8: 3065239462Sdim case X86::CMP8ri: 3066239462Sdim SrcReg = MI->getOperand(0).getReg(); 3067239462Sdim SrcReg2 = 0; 3068239462Sdim CmpMask = ~0; 3069239462Sdim CmpValue = MI->getOperand(1).getImm(); 3070239462Sdim return true; 3071239462Sdim // A SUB can be used to perform comparison. 3072239462Sdim case X86::SUB64rm: 3073239462Sdim case X86::SUB32rm: 3074239462Sdim case X86::SUB16rm: 3075239462Sdim case X86::SUB8rm: 3076239462Sdim SrcReg = MI->getOperand(1).getReg(); 3077239462Sdim SrcReg2 = 0; 3078239462Sdim CmpMask = ~0; 3079239462Sdim CmpValue = 0; 3080239462Sdim return true; 3081239462Sdim case X86::SUB64rr: 3082239462Sdim case X86::SUB32rr: 3083239462Sdim case X86::SUB16rr: 3084239462Sdim case X86::SUB8rr: 3085239462Sdim SrcReg = MI->getOperand(1).getReg(); 3086239462Sdim SrcReg2 = MI->getOperand(2).getReg(); 3087239462Sdim CmpMask = ~0; 3088239462Sdim CmpValue = 0; 3089239462Sdim return true; 3090239462Sdim case X86::SUB64ri32: 3091239462Sdim case X86::SUB64ri8: 3092239462Sdim case X86::SUB32ri: 3093239462Sdim case X86::SUB32ri8: 3094239462Sdim case X86::SUB16ri: 3095239462Sdim case X86::SUB16ri8: 3096239462Sdim case X86::SUB8ri: 3097239462Sdim SrcReg = MI->getOperand(1).getReg(); 3098239462Sdim SrcReg2 = 0; 3099239462Sdim CmpMask = ~0; 3100239462Sdim CmpValue = MI->getOperand(2).getImm(); 3101239462Sdim return true; 3102239462Sdim case X86::CMP64rr: 3103239462Sdim case X86::CMP32rr: 3104239462Sdim case X86::CMP16rr: 3105239462Sdim case X86::CMP8rr: 3106239462Sdim SrcReg = MI->getOperand(0).getReg(); 3107239462Sdim SrcReg2 = MI->getOperand(1).getReg(); 3108239462Sdim CmpMask = ~0; 3109239462Sdim CmpValue = 0; 3110239462Sdim return true; 3111239462Sdim case X86::TEST8rr: 3112239462Sdim case X86::TEST16rr: 3113239462Sdim case X86::TEST32rr: 3114239462Sdim case X86::TEST64rr: 3115239462Sdim SrcReg = MI->getOperand(0).getReg(); 3116239462Sdim if (MI->getOperand(1).getReg() != SrcReg) return false; 3117239462Sdim // Compare against zero. 3118239462Sdim SrcReg2 = 0; 3119239462Sdim CmpMask = ~0; 3120239462Sdim CmpValue = 0; 3121239462Sdim return true; 3122239462Sdim } 3123239462Sdim return false; 3124239462Sdim} 3125239462Sdim 3126239462Sdim/// isRedundantFlagInstr - check whether the first instruction, whose only 3127239462Sdim/// purpose is to update flags, can be made redundant. 3128239462Sdim/// CMPrr can be made redundant by SUBrr if the operands are the same. 3129239462Sdim/// This function can be extended later on. 3130239462Sdim/// SrcReg, SrcRegs: register operands for FlagI. 3131239462Sdim/// ImmValue: immediate for FlagI if it takes an immediate. 3132239462Sdiminline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3133239462Sdim unsigned SrcReg2, int ImmValue, 3134239462Sdim MachineInstr *OI) { 3135239462Sdim if (((FlagI->getOpcode() == X86::CMP64rr && 3136239462Sdim OI->getOpcode() == X86::SUB64rr) || 3137239462Sdim (FlagI->getOpcode() == X86::CMP32rr && 3138239462Sdim OI->getOpcode() == X86::SUB32rr)|| 3139239462Sdim (FlagI->getOpcode() == X86::CMP16rr && 3140239462Sdim OI->getOpcode() == X86::SUB16rr)|| 3141239462Sdim (FlagI->getOpcode() == X86::CMP8rr && 3142239462Sdim OI->getOpcode() == X86::SUB8rr)) && 3143239462Sdim ((OI->getOperand(1).getReg() == SrcReg && 3144239462Sdim OI->getOperand(2).getReg() == SrcReg2) || 3145239462Sdim (OI->getOperand(1).getReg() == SrcReg2 && 3146239462Sdim OI->getOperand(2).getReg() == SrcReg))) 3147239462Sdim return true; 3148239462Sdim 3149239462Sdim if (((FlagI->getOpcode() == X86::CMP64ri32 && 3150239462Sdim OI->getOpcode() == X86::SUB64ri32) || 3151239462Sdim (FlagI->getOpcode() == X86::CMP64ri8 && 3152239462Sdim OI->getOpcode() == X86::SUB64ri8) || 3153239462Sdim (FlagI->getOpcode() == X86::CMP32ri && 3154239462Sdim OI->getOpcode() == X86::SUB32ri) || 3155239462Sdim (FlagI->getOpcode() == X86::CMP32ri8 && 3156239462Sdim OI->getOpcode() == X86::SUB32ri8) || 3157239462Sdim (FlagI->getOpcode() == X86::CMP16ri && 3158239462Sdim OI->getOpcode() == X86::SUB16ri) || 3159239462Sdim (FlagI->getOpcode() == X86::CMP16ri8 && 3160239462Sdim OI->getOpcode() == X86::SUB16ri8) || 3161239462Sdim (FlagI->getOpcode() == X86::CMP8ri && 3162239462Sdim OI->getOpcode() == X86::SUB8ri)) && 3163239462Sdim OI->getOperand(1).getReg() == SrcReg && 3164239462Sdim OI->getOperand(2).getImm() == ImmValue) 3165239462Sdim return true; 3166239462Sdim return false; 3167239462Sdim} 3168239462Sdim 3169239462Sdim/// isDefConvertible - check whether the definition can be converted 3170239462Sdim/// to remove a comparison against zero. 3171239462Sdiminline static bool isDefConvertible(MachineInstr *MI) { 3172239462Sdim switch (MI->getOpcode()) { 3173239462Sdim default: return false; 3174239462Sdim case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3175239462Sdim case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3176239462Sdim case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3177239462Sdim case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3178239462Sdim case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3179249423Sdim case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3180243830Sdim case X86::DEC64_32r: case X86::DEC64_16r: 3181239462Sdim case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3182239462Sdim case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3183239462Sdim case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3184239462Sdim case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3185239462Sdim case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3186249423Sdim case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3187243830Sdim case X86::INC64_32r: case X86::INC64_16r: 3188239462Sdim case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3189239462Sdim case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3190239462Sdim case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3191239462Sdim case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3192239462Sdim case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3193239462Sdim case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3194239462Sdim case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3195239462Sdim case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3196239462Sdim case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3197239462Sdim case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3198239462Sdim case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3199239462Sdim case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3200239462Sdim case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3201239462Sdim case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3202239462Sdim case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3203249423Sdim case X86::ANDN32rr: case X86::ANDN32rm: 3204249423Sdim case X86::ANDN64rr: case X86::ANDN64rm: 3205239462Sdim return true; 3206239462Sdim } 3207239462Sdim} 3208239462Sdim 3209239462Sdim/// optimizeCompareInstr - Check if there exists an earlier instruction that 3210239462Sdim/// operates on the same source operands and sets flags in the same way as 3211239462Sdim/// Compare; remove Compare if possible. 3212239462Sdimbool X86InstrInfo:: 3213239462SdimoptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3214239462Sdim int CmpMask, int CmpValue, 3215239462Sdim const MachineRegisterInfo *MRI) const { 3216239462Sdim // Check whether we can replace SUB with CMP. 3217239462Sdim unsigned NewOpcode = 0; 3218239462Sdim switch (CmpInstr->getOpcode()) { 3219239462Sdim default: break; 3220239462Sdim case X86::SUB64ri32: 3221239462Sdim case X86::SUB64ri8: 3222239462Sdim case X86::SUB32ri: 3223239462Sdim case X86::SUB32ri8: 3224239462Sdim case X86::SUB16ri: 3225239462Sdim case X86::SUB16ri8: 3226239462Sdim case X86::SUB8ri: 3227239462Sdim case X86::SUB64rm: 3228239462Sdim case X86::SUB32rm: 3229239462Sdim case X86::SUB16rm: 3230239462Sdim case X86::SUB8rm: 3231239462Sdim case X86::SUB64rr: 3232239462Sdim case X86::SUB32rr: 3233239462Sdim case X86::SUB16rr: 3234239462Sdim case X86::SUB8rr: { 3235239462Sdim if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3236239462Sdim return false; 3237239462Sdim // There is no use of the destination register, we can replace SUB with CMP. 3238239462Sdim switch (CmpInstr->getOpcode()) { 3239243830Sdim default: llvm_unreachable("Unreachable!"); 3240239462Sdim case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3241239462Sdim case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3242239462Sdim case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3243239462Sdim case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3244239462Sdim case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3245239462Sdim case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3246239462Sdim case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3247239462Sdim case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3248239462Sdim case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3249239462Sdim case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3250239462Sdim case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3251239462Sdim case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3252239462Sdim case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3253239462Sdim case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3254239462Sdim case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3255239462Sdim } 3256239462Sdim CmpInstr->setDesc(get(NewOpcode)); 3257239462Sdim CmpInstr->RemoveOperand(0); 3258239462Sdim // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3259239462Sdim if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3260239462Sdim NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3261239462Sdim return false; 3262239462Sdim } 3263239462Sdim } 3264239462Sdim 3265239462Sdim // Get the unique definition of SrcReg. 3266239462Sdim MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3267239462Sdim if (!MI) return false; 3268239462Sdim 3269239462Sdim // CmpInstr is the first instruction of the BB. 3270239462Sdim MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3271239462Sdim 3272239462Sdim // If we are comparing against zero, check whether we can use MI to update 3273239462Sdim // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3274239462Sdim bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3275239462Sdim if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() || 3276239462Sdim !isDefConvertible(MI))) 3277239462Sdim return false; 3278239462Sdim 3279239462Sdim // We are searching for an earlier instruction that can make CmpInstr 3280239462Sdim // redundant and that instruction will be saved in Sub. 3281239462Sdim MachineInstr *Sub = NULL; 3282239462Sdim const TargetRegisterInfo *TRI = &getRegisterInfo(); 3283239462Sdim 3284239462Sdim // We iterate backward, starting from the instruction before CmpInstr and 3285239462Sdim // stop when reaching the definition of a source register or done with the BB. 3286239462Sdim // RI points to the instruction before CmpInstr. 3287239462Sdim // If the definition is in this basic block, RE points to the definition; 3288239462Sdim // otherwise, RE is the rend of the basic block. 3289239462Sdim MachineBasicBlock::reverse_iterator 3290239462Sdim RI = MachineBasicBlock::reverse_iterator(I), 3291239462Sdim RE = CmpInstr->getParent() == MI->getParent() ? 3292239462Sdim MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3293239462Sdim CmpInstr->getParent()->rend(); 3294239462Sdim MachineInstr *Movr0Inst = 0; 3295239462Sdim for (; RI != RE; ++RI) { 3296239462Sdim MachineInstr *Instr = &*RI; 3297239462Sdim // Check whether CmpInstr can be made redundant by the current instruction. 3298239462Sdim if (!IsCmpZero && 3299239462Sdim isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3300239462Sdim Sub = Instr; 3301239462Sdim break; 3302239462Sdim } 3303239462Sdim 3304239462Sdim if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3305239462Sdim Instr->readsRegister(X86::EFLAGS, TRI)) { 3306239462Sdim // This instruction modifies or uses EFLAGS. 3307239462Sdim 3308239462Sdim // MOV32r0 etc. are implemented with xor which clobbers condition code. 3309239462Sdim // They are safe to move up, if the definition to EFLAGS is dead and 3310239462Sdim // earlier instructions do not read or write EFLAGS. 3311239462Sdim if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 || 3312239462Sdim Instr->getOpcode() == X86::MOV16r0 || 3313239462Sdim Instr->getOpcode() == X86::MOV32r0 || 3314239462Sdim Instr->getOpcode() == X86::MOV64r0) && 3315239462Sdim Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3316239462Sdim Movr0Inst = Instr; 3317239462Sdim continue; 3318239462Sdim } 3319239462Sdim 3320239462Sdim // We can't remove CmpInstr. 3321239462Sdim return false; 3322239462Sdim } 3323239462Sdim } 3324239462Sdim 3325239462Sdim // Return false if no candidates exist. 3326239462Sdim if (!IsCmpZero && !Sub) 3327239462Sdim return false; 3328239462Sdim 3329239462Sdim bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3330239462Sdim Sub->getOperand(2).getReg() == SrcReg); 3331239462Sdim 3332239462Sdim // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3333239462Sdim // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3334239462Sdim // If we are done with the basic block, we need to check whether EFLAGS is 3335239462Sdim // live-out. 3336239462Sdim bool IsSafe = false; 3337239462Sdim SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3338239462Sdim MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3339239462Sdim for (++I; I != E; ++I) { 3340239462Sdim const MachineInstr &Instr = *I; 3341239462Sdim bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3342239462Sdim bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3343239462Sdim // We should check the usage if this instruction uses and updates EFLAGS. 3344239462Sdim if (!UseEFLAGS && ModifyEFLAGS) { 3345239462Sdim // It is safe to remove CmpInstr if EFLAGS is updated again. 3346239462Sdim IsSafe = true; 3347239462Sdim break; 3348239462Sdim } 3349239462Sdim if (!UseEFLAGS && !ModifyEFLAGS) 3350239462Sdim continue; 3351239462Sdim 3352239462Sdim // EFLAGS is used by this instruction. 3353239462Sdim X86::CondCode OldCC; 3354239462Sdim bool OpcIsSET = false; 3355239462Sdim if (IsCmpZero || IsSwapped) { 3356239462Sdim // We decode the condition code from opcode. 3357239462Sdim if (Instr.isBranch()) 3358239462Sdim OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3359239462Sdim else { 3360239462Sdim OldCC = getCondFromSETOpc(Instr.getOpcode()); 3361239462Sdim if (OldCC != X86::COND_INVALID) 3362239462Sdim OpcIsSET = true; 3363239462Sdim else 3364243830Sdim OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3365239462Sdim } 3366239462Sdim if (OldCC == X86::COND_INVALID) return false; 3367239462Sdim } 3368239462Sdim if (IsCmpZero) { 3369239462Sdim switch (OldCC) { 3370239462Sdim default: break; 3371239462Sdim case X86::COND_A: case X86::COND_AE: 3372239462Sdim case X86::COND_B: case X86::COND_BE: 3373239462Sdim case X86::COND_G: case X86::COND_GE: 3374239462Sdim case X86::COND_L: case X86::COND_LE: 3375239462Sdim case X86::COND_O: case X86::COND_NO: 3376239462Sdim // CF and OF are used, we can't perform this optimization. 3377239462Sdim return false; 3378239462Sdim } 3379239462Sdim } else if (IsSwapped) { 3380239462Sdim // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3381239462Sdim // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3382239462Sdim // We swap the condition code and synthesize the new opcode. 3383239462Sdim X86::CondCode NewCC = getSwappedCondition(OldCC); 3384239462Sdim if (NewCC == X86::COND_INVALID) return false; 3385239462Sdim 3386239462Sdim // Synthesize the new opcode. 3387239462Sdim bool HasMemoryOperand = Instr.hasOneMemOperand(); 3388239462Sdim unsigned NewOpc; 3389239462Sdim if (Instr.isBranch()) 3390239462Sdim NewOpc = GetCondBranchFromCond(NewCC); 3391239462Sdim else if(OpcIsSET) 3392239462Sdim NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3393239462Sdim else { 3394239462Sdim unsigned DstReg = Instr.getOperand(0).getReg(); 3395239462Sdim NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3396239462Sdim HasMemoryOperand); 3397239462Sdim } 3398239462Sdim 3399239462Sdim // Push the MachineInstr to OpsToUpdate. 3400239462Sdim // If it is safe to remove CmpInstr, the condition code of these 3401239462Sdim // instructions will be modified. 3402239462Sdim OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3403239462Sdim } 3404239462Sdim if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3405239462Sdim // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3406239462Sdim IsSafe = true; 3407239462Sdim break; 3408239462Sdim } 3409239462Sdim } 3410239462Sdim 3411239462Sdim // If EFLAGS is not killed nor re-defined, we should check whether it is 3412239462Sdim // live-out. If it is live-out, do not optimize. 3413239462Sdim if ((IsCmpZero || IsSwapped) && !IsSafe) { 3414239462Sdim MachineBasicBlock *MBB = CmpInstr->getParent(); 3415239462Sdim for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3416239462Sdim SE = MBB->succ_end(); SI != SE; ++SI) 3417239462Sdim if ((*SI)->isLiveIn(X86::EFLAGS)) 3418239462Sdim return false; 3419239462Sdim } 3420239462Sdim 3421239462Sdim // The instruction to be updated is either Sub or MI. 3422239462Sdim Sub = IsCmpZero ? MI : Sub; 3423239462Sdim // Move Movr0Inst to the place right before Sub. 3424239462Sdim if (Movr0Inst) { 3425239462Sdim Sub->getParent()->remove(Movr0Inst); 3426239462Sdim Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst); 3427239462Sdim } 3428239462Sdim 3429243830Sdim // Make sure Sub instruction defines EFLAGS and mark the def live. 3430243830Sdim unsigned LastOperand = Sub->getNumOperands() - 1; 3431239462Sdim assert(Sub->getNumOperands() >= 2 && 3432243830Sdim Sub->getOperand(LastOperand).isReg() && 3433243830Sdim Sub->getOperand(LastOperand).getReg() == X86::EFLAGS && 3434239462Sdim "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND"); 3435243830Sdim Sub->getOperand(LastOperand).setIsDef(true); 3436243830Sdim Sub->getOperand(LastOperand).setIsDead(false); 3437239462Sdim CmpInstr->eraseFromParent(); 3438239462Sdim 3439239462Sdim // Modify the condition code of instructions in OpsToUpdate. 3440239462Sdim for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3441239462Sdim OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3442239462Sdim return true; 3443239462Sdim} 3444239462Sdim 3445239462Sdim/// optimizeLoadInstr - Try to remove the load by folding it to a register 3446239462Sdim/// operand at the use. We fold the load instructions if load defines a virtual 3447239462Sdim/// register, the virtual register is used once in the same BB, and the 3448239462Sdim/// instructions in-between do not load or store, and have no side effects. 3449239462SdimMachineInstr* X86InstrInfo:: 3450239462SdimoptimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3451239462Sdim unsigned &FoldAsLoadDefReg, 3452239462Sdim MachineInstr *&DefMI) const { 3453239462Sdim if (FoldAsLoadDefReg == 0) 3454239462Sdim return 0; 3455239462Sdim // To be conservative, if there exists another load, clear the load candidate. 3456239462Sdim if (MI->mayLoad()) { 3457239462Sdim FoldAsLoadDefReg = 0; 3458239462Sdim return 0; 3459239462Sdim } 3460239462Sdim 3461239462Sdim // Check whether we can move DefMI here. 3462239462Sdim DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3463239462Sdim assert(DefMI); 3464239462Sdim bool SawStore = false; 3465239462Sdim if (!DefMI->isSafeToMove(this, 0, SawStore)) 3466239462Sdim return 0; 3467239462Sdim 3468239462Sdim // We try to commute MI if possible. 3469239462Sdim unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3470239462Sdim for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3471239462Sdim // Collect information about virtual register operands of MI. 3472239462Sdim unsigned SrcOperandId = 0; 3473239462Sdim bool FoundSrcOperand = false; 3474239462Sdim for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3475239462Sdim MachineOperand &MO = MI->getOperand(i); 3476239462Sdim if (!MO.isReg()) 3477239462Sdim continue; 3478239462Sdim unsigned Reg = MO.getReg(); 3479239462Sdim if (Reg != FoldAsLoadDefReg) 3480239462Sdim continue; 3481239462Sdim // Do not fold if we have a subreg use or a def or multiple uses. 3482239462Sdim if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3483239462Sdim return 0; 3484239462Sdim 3485239462Sdim SrcOperandId = i; 3486239462Sdim FoundSrcOperand = true; 3487239462Sdim } 3488239462Sdim if (!FoundSrcOperand) return 0; 3489239462Sdim 3490239462Sdim // Check whether we can fold the def into SrcOperandId. 3491239462Sdim SmallVector<unsigned, 8> Ops; 3492239462Sdim Ops.push_back(SrcOperandId); 3493239462Sdim MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3494239462Sdim if (FoldMI) { 3495239462Sdim FoldAsLoadDefReg = 0; 3496239462Sdim return FoldMI; 3497239462Sdim } 3498239462Sdim 3499239462Sdim if (Idx == 1) { 3500239462Sdim // MI was changed but it didn't help, commute it back! 3501239462Sdim commuteInstruction(MI, false); 3502239462Sdim return 0; 3503239462Sdim } 3504239462Sdim 3505239462Sdim // Check whether we can commute MI and enable folding. 3506239462Sdim if (MI->isCommutable()) { 3507239462Sdim MachineInstr *NewMI = commuteInstruction(MI, false); 3508239462Sdim // Unable to commute. 3509239462Sdim if (!NewMI) return 0; 3510239462Sdim if (NewMI != MI) { 3511239462Sdim // New instruction. It doesn't need to be kept. 3512239462Sdim NewMI->eraseFromParent(); 3513239462Sdim return 0; 3514239462Sdim } 3515239462Sdim } 3516239462Sdim } 3517239462Sdim return 0; 3518239462Sdim} 3519239462Sdim 3520226633Sdim/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3521226633Sdim/// instruction with two undef reads of the register being defined. This is 3522226633Sdim/// used for mapping: 3523226633Sdim/// %xmm4 = V_SET0 3524226633Sdim/// to: 3525226633Sdim/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3526226633Sdim/// 3527249423Sdimstatic bool Expand2AddrUndef(MachineInstrBuilder &MIB, 3528249423Sdim const MCInstrDesc &Desc) { 3529226633Sdim assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3530249423Sdim unsigned Reg = MIB->getOperand(0).getReg(); 3531249423Sdim MIB->setDesc(Desc); 3532226633Sdim 3533226633Sdim // MachineInstr::addOperand() will insert explicit operands before any 3534226633Sdim // implicit operands. 3535249423Sdim MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3536226633Sdim // But we don't trust that. 3537249423Sdim assert(MIB->getOperand(1).getReg() == Reg && 3538249423Sdim MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 3539226633Sdim return true; 3540226633Sdim} 3541226633Sdim 3542226633Sdimbool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3543226633Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3544249423Sdim MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 3545226633Sdim switch (MI->getOpcode()) { 3546243830Sdim case X86::SETB_C8r: 3547249423Sdim return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 3548243830Sdim case X86::SETB_C16r: 3549249423Sdim return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 3550243830Sdim case X86::SETB_C32r: 3551249423Sdim return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 3552243830Sdim case X86::SETB_C64r: 3553249423Sdim return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 3554226633Sdim case X86::V_SET0: 3555234353Sdim case X86::FsFLD0SS: 3556234353Sdim case X86::FsFLD0SD: 3557249423Sdim return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3558243830Sdim case X86::AVX_SET0: 3559243830Sdim assert(HasAVX && "AVX not supported"); 3560249423Sdim return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); 3561243830Sdim case X86::V_SETALLONES: 3562249423Sdim return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 3563243830Sdim case X86::AVX2_SETALLONES: 3564249423Sdim return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 3565226633Sdim case X86::TEST8ri_NOREX: 3566226633Sdim MI->setDesc(get(X86::TEST8ri)); 3567226633Sdim return true; 3568226633Sdim } 3569226633Sdim return false; 3570226633Sdim} 3571226633Sdim 3572207618SrdivackyMachineInstr* 3573207618SrdivackyX86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 3574207618Srdivacky int FrameIx, uint64_t Offset, 3575207618Srdivacky const MDNode *MDPtr, 3576207618Srdivacky DebugLoc DL) const { 3577207618Srdivacky X86AddressMode AM; 3578207618Srdivacky AM.BaseType = X86AddressMode::FrameIndexBase; 3579207618Srdivacky AM.Base.FrameIndex = FrameIx; 3580207618Srdivacky MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 3581207618Srdivacky addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 3582207618Srdivacky return &*MIB; 3583207618Srdivacky} 3584207618Srdivacky 3585193323Sedstatic MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 3586193323Sed const SmallVectorImpl<MachineOperand> &MOs, 3587193323Sed MachineInstr *MI, 3588193323Sed const TargetInstrInfo &TII) { 3589193323Sed // Create the base instruction with the memory operand as the first part. 3590249423Sdim // Omit the implicit operands, something BuildMI can't do. 3591193323Sed MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3592193323Sed MI->getDebugLoc(), true); 3593249423Sdim MachineInstrBuilder MIB(MF, NewMI); 3594193323Sed unsigned NumAddrOps = MOs.size(); 3595193323Sed for (unsigned i = 0; i != NumAddrOps; ++i) 3596193323Sed MIB.addOperand(MOs[i]); 3597193323Sed if (NumAddrOps < 4) // FrameIndex only 3598193323Sed addOffset(MIB, 0); 3599218893Sdim 3600193323Sed // Loop over the rest of the ri operands, converting them over. 3601193323Sed unsigned NumOps = MI->getDesc().getNumOperands()-2; 3602193323Sed for (unsigned i = 0; i != NumOps; ++i) { 3603193323Sed MachineOperand &MO = MI->getOperand(i+2); 3604193323Sed MIB.addOperand(MO); 3605193323Sed } 3606193323Sed for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 3607193323Sed MachineOperand &MO = MI->getOperand(i); 3608193323Sed MIB.addOperand(MO); 3609193323Sed } 3610193323Sed return MIB; 3611193323Sed} 3612193323Sed 3613193323Sedstatic MachineInstr *FuseInst(MachineFunction &MF, 3614193323Sed unsigned Opcode, unsigned OpNo, 3615193323Sed const SmallVectorImpl<MachineOperand> &MOs, 3616193323Sed MachineInstr *MI, const TargetInstrInfo &TII) { 3617249423Sdim // Omit the implicit operands, something BuildMI can't do. 3618193323Sed MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3619193323Sed MI->getDebugLoc(), true); 3620249423Sdim MachineInstrBuilder MIB(MF, NewMI); 3621218893Sdim 3622193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3623193323Sed MachineOperand &MO = MI->getOperand(i); 3624193323Sed if (i == OpNo) { 3625193323Sed assert(MO.isReg() && "Expected to fold into reg operand!"); 3626193323Sed unsigned NumAddrOps = MOs.size(); 3627193323Sed for (unsigned i = 0; i != NumAddrOps; ++i) 3628193323Sed MIB.addOperand(MOs[i]); 3629193323Sed if (NumAddrOps < 4) // FrameIndex only 3630193323Sed addOffset(MIB, 0); 3631193323Sed } else { 3632193323Sed MIB.addOperand(MO); 3633193323Sed } 3634193323Sed } 3635193323Sed return MIB; 3636193323Sed} 3637193323Sed 3638193323Sedstatic MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 3639193323Sed const SmallVectorImpl<MachineOperand> &MOs, 3640193323Sed MachineInstr *MI) { 3641193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 3642193323Sed MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 3643193323Sed 3644193323Sed unsigned NumAddrOps = MOs.size(); 3645193323Sed for (unsigned i = 0; i != NumAddrOps; ++i) 3646193323Sed MIB.addOperand(MOs[i]); 3647193323Sed if (NumAddrOps < 4) // FrameIndex only 3648193323Sed addOffset(MIB, 0); 3649193323Sed return MIB.addImm(0); 3650193323Sed} 3651193323Sed 3652193323SedMachineInstr* 3653193323SedX86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3654193323Sed MachineInstr *MI, unsigned i, 3655198090Srdivacky const SmallVectorImpl<MachineOperand> &MOs, 3656198090Srdivacky unsigned Size, unsigned Align) const { 3657218893Sdim const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3658249423Sdim bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect(); 3659193323Sed bool isTwoAddrFold = false; 3660249423Sdim 3661249423Sdim // Atom favors register form of call. So, we do not fold loads into calls 3662249423Sdim // when X86Subtarget is Atom. 3663249423Sdim if (isCallRegIndirect && 3664249423Sdim (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) { 3665249423Sdim return NULL; 3666249423Sdim } 3667249423Sdim 3668193323Sed unsigned NumOps = MI->getDesc().getNumOperands(); 3669193323Sed bool isTwoAddr = NumOps > 1 && 3670224145Sdim MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3671193323Sed 3672221345Sdim // FIXME: AsmPrinter doesn't know how to handle 3673221345Sdim // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3674221345Sdim if (MI->getOpcode() == X86::ADD32ri && 3675221345Sdim MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3676221345Sdim return NULL; 3677221345Sdim 3678193323Sed MachineInstr *NewMI = NULL; 3679193323Sed // Folding a memory location into the two-address part of a two-address 3680193323Sed // instruction is different than folding it other places. It requires 3681193323Sed // replacing the *two* registers with the memory location. 3682193323Sed if (isTwoAddr && NumOps >= 2 && i < 2 && 3683193323Sed MI->getOperand(0).isReg() && 3684193323Sed MI->getOperand(1).isReg() && 3685218893Sdim MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 3686193323Sed OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3687193323Sed isTwoAddrFold = true; 3688193323Sed } else if (i == 0) { // If operand 0 3689243830Sdim unsigned Opc = 0; 3690243830Sdim switch (MI->getOpcode()) { 3691243830Sdim default: break; 3692243830Sdim case X86::MOV64r0: Opc = X86::MOV64mi32; break; 3693243830Sdim case X86::MOV32r0: Opc = X86::MOV32mi; break; 3694243830Sdim case X86::MOV16r0: Opc = X86::MOV16mi; break; 3695243830Sdim case X86::MOV8r0: Opc = X86::MOV8mi; break; 3696243830Sdim } 3697243830Sdim if (Opc) 3698243830Sdim NewMI = MakeM0Inst(*this, Opc, MOs, MI); 3699193323Sed if (NewMI) 3700193323Sed return NewMI; 3701218893Sdim 3702193323Sed OpcodeTablePtr = &RegOp2MemOpTable0; 3703193323Sed } else if (i == 1) { 3704193323Sed OpcodeTablePtr = &RegOp2MemOpTable1; 3705193323Sed } else if (i == 2) { 3706193323Sed OpcodeTablePtr = &RegOp2MemOpTable2; 3707239462Sdim } else if (i == 3) { 3708239462Sdim OpcodeTablePtr = &RegOp2MemOpTable3; 3709193323Sed } 3710218893Sdim 3711193323Sed // If table selected... 3712193323Sed if (OpcodeTablePtr) { 3713193323Sed // Find the Opcode to fuse 3714218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3715218893Sdim OpcodeTablePtr->find(MI->getOpcode()); 3716193323Sed if (I != OpcodeTablePtr->end()) { 3717198090Srdivacky unsigned Opcode = I->second.first; 3718226633Sdim unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 3719198090Srdivacky if (Align < MinAlign) 3720198090Srdivacky return NULL; 3721198090Srdivacky bool NarrowToMOV32rm = false; 3722198090Srdivacky if (Size) { 3723239462Sdim unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 3724198090Srdivacky if (Size < RCSize) { 3725198090Srdivacky // Check if it's safe to fold the load. If the size of the object is 3726198090Srdivacky // narrower than the load width, then it's not. 3727198090Srdivacky if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 3728198090Srdivacky return NULL; 3729198090Srdivacky // If this is a 64-bit load, but the spill slot is 32, then we can do 3730198090Srdivacky // a 32-bit load which is implicitly zero-extended. This likely is due 3731198090Srdivacky // to liveintervalanalysis remat'ing a load from stack slot. 3732198090Srdivacky if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 3733198090Srdivacky return NULL; 3734198090Srdivacky Opcode = X86::MOV32rm; 3735198090Srdivacky NarrowToMOV32rm = true; 3736198090Srdivacky } 3737198090Srdivacky } 3738198090Srdivacky 3739193323Sed if (isTwoAddrFold) 3740198090Srdivacky NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 3741193323Sed else 3742198090Srdivacky NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 3743198090Srdivacky 3744198090Srdivacky if (NarrowToMOV32rm) { 3745198090Srdivacky // If this is the special case where we use a MOV32rm to load a 32-bit 3746198090Srdivacky // value and zero-extend the top bits. Change the destination register 3747198090Srdivacky // to a 32-bit one. 3748198090Srdivacky unsigned DstReg = NewMI->getOperand(0).getReg(); 3749198090Srdivacky if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 3750198090Srdivacky NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 3751208599Srdivacky X86::sub_32bit)); 3752198090Srdivacky else 3753208599Srdivacky NewMI->getOperand(0).setSubReg(X86::sub_32bit); 3754198090Srdivacky } 3755193323Sed return NewMI; 3756193323Sed } 3757193323Sed } 3758218893Sdim 3759218893Sdim // No fusion 3760210299Sed if (PrintFailedFusing && !MI->isCopy()) 3761202375Srdivacky dbgs() << "We failed to fuse operand " << i << " in " << *MI; 3762193323Sed return NULL; 3763193323Sed} 3764193323Sed 3765226633Sdim/// hasPartialRegUpdate - Return true for all instructions that only update 3766226633Sdim/// the first 32 or 64-bits of the destination register and leave the rest 3767226633Sdim/// unmodified. This can be used to avoid folding loads if the instructions 3768226633Sdim/// only update part of the destination register, and the non-updated part is 3769226633Sdim/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 3770226633Sdim/// instructions breaks the partial register dependency and it can improve 3771226633Sdim/// performance. e.g.: 3772226633Sdim/// 3773226633Sdim/// movss (%rdi), %xmm0 3774226633Sdim/// cvtss2sd %xmm0, %xmm0 3775226633Sdim/// 3776226633Sdim/// Instead of 3777226633Sdim/// cvtss2sd (%rdi), %xmm0 3778226633Sdim/// 3779226633Sdim/// FIXME: This should be turned into a TSFlags. 3780226633Sdim/// 3781226633Sdimstatic bool hasPartialRegUpdate(unsigned Opcode) { 3782226633Sdim switch (Opcode) { 3783234353Sdim case X86::CVTSI2SSrr: 3784234353Sdim case X86::CVTSI2SS64rr: 3785234353Sdim case X86::CVTSI2SDrr: 3786234353Sdim case X86::CVTSI2SD64rr: 3787226633Sdim case X86::CVTSD2SSrr: 3788226633Sdim case X86::Int_CVTSD2SSrr: 3789226633Sdim case X86::CVTSS2SDrr: 3790226633Sdim case X86::Int_CVTSS2SDrr: 3791226633Sdim case X86::RCPSSr: 3792226633Sdim case X86::RCPSSr_Int: 3793226633Sdim case X86::ROUNDSDr: 3794234353Sdim case X86::ROUNDSDr_Int: 3795226633Sdim case X86::ROUNDSSr: 3796234353Sdim case X86::ROUNDSSr_Int: 3797226633Sdim case X86::RSQRTSSr: 3798226633Sdim case X86::RSQRTSSr_Int: 3799226633Sdim case X86::SQRTSSr: 3800226633Sdim case X86::SQRTSSr_Int: 3801226633Sdim // AVX encoded versions 3802226633Sdim case X86::VCVTSD2SSrr: 3803226633Sdim case X86::Int_VCVTSD2SSrr: 3804226633Sdim case X86::VCVTSS2SDrr: 3805226633Sdim case X86::Int_VCVTSS2SDrr: 3806226633Sdim case X86::VRCPSSr: 3807226633Sdim case X86::VROUNDSDr: 3808234353Sdim case X86::VROUNDSDr_Int: 3809226633Sdim case X86::VROUNDSSr: 3810234353Sdim case X86::VROUNDSSr_Int: 3811226633Sdim case X86::VRSQRTSSr: 3812226633Sdim case X86::VSQRTSSr: 3813226633Sdim return true; 3814226633Sdim } 3815193323Sed 3816226633Sdim return false; 3817226633Sdim} 3818226633Sdim 3819234353Sdim/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 3820234353Sdim/// instructions we would like before a partial register update. 3821234353Sdimunsigned X86InstrInfo:: 3822234353SdimgetPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3823234353Sdim const TargetRegisterInfo *TRI) const { 3824234353Sdim if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 3825234353Sdim return 0; 3826234353Sdim 3827234353Sdim // If MI is marked as reading Reg, the partial register update is wanted. 3828234353Sdim const MachineOperand &MO = MI->getOperand(0); 3829234353Sdim unsigned Reg = MO.getReg(); 3830234353Sdim if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3831234353Sdim if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 3832234353Sdim return 0; 3833234353Sdim } else { 3834234353Sdim if (MI->readsRegister(Reg, TRI)) 3835234353Sdim return 0; 3836234353Sdim } 3837234353Sdim 3838234353Sdim // If any of the preceding 16 instructions are reading Reg, insert a 3839234353Sdim // dependency breaking instruction. The magic number is based on a few 3840234353Sdim // Nehalem experiments. 3841234353Sdim return 16; 3842234353Sdim} 3843234353Sdim 3844234353Sdimvoid X86InstrInfo:: 3845234353SdimbreakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 3846234353Sdim const TargetRegisterInfo *TRI) const { 3847234353Sdim unsigned Reg = MI->getOperand(OpNum).getReg(); 3848234353Sdim if (X86::VR128RegClass.contains(Reg)) { 3849234353Sdim // These instructions are all floating point domain, so xorps is the best 3850234353Sdim // choice. 3851234353Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3852234353Sdim unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 3853234353Sdim BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 3854234353Sdim .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3855234353Sdim } else if (X86::VR256RegClass.contains(Reg)) { 3856234353Sdim // Use vxorps to clear the full ymm register. 3857234353Sdim // It wants to read and write the xmm sub-register. 3858234353Sdim unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 3859234353Sdim BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 3860234353Sdim .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 3861234353Sdim .addReg(Reg, RegState::ImplicitDefine); 3862234353Sdim } else 3863234353Sdim return; 3864234353Sdim MI->addRegisterKilled(Reg, TRI, true); 3865234353Sdim} 3866234353Sdim 3867193323SedMachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3868193323Sed MachineInstr *MI, 3869198090Srdivacky const SmallVectorImpl<unsigned> &Ops, 3870193323Sed int FrameIndex) const { 3871218893Sdim // Check switch flag 3872193323Sed if (NoFusing) return NULL; 3873193323Sed 3874226633Sdim // Unless optimizing for size, don't fold to avoid partial 3875226633Sdim // register update stalls 3876249423Sdim if (!MF.getFunction()->getAttributes(). 3877249423Sdim hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 3878226633Sdim hasPartialRegUpdate(MI->getOpcode())) 3879226633Sdim return 0; 3880201360Srdivacky 3881193323Sed const MachineFrameInfo *MFI = MF.getFrameInfo(); 3882198090Srdivacky unsigned Size = MFI->getObjectSize(FrameIndex); 3883193323Sed unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 3884256090Sdim // If the function stack isn't realigned we don't want to fold instructions 3885256090Sdim // that need increased alignment. 3886256090Sdim if (!RI.needsStackRealignment(MF)) 3887256090Sdim Alignment = std::min(Alignment, TM.getFrameLowering()->getStackAlignment()); 3888193323Sed if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3889193323Sed unsigned NewOpc = 0; 3890198090Srdivacky unsigned RCSize = 0; 3891193323Sed switch (MI->getOpcode()) { 3892193323Sed default: return NULL; 3893198090Srdivacky case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 3894208599Srdivacky case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 3895208599Srdivacky case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 3896208599Srdivacky case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 3897193323Sed } 3898198090Srdivacky // Check if it's safe to fold the load. If the size of the object is 3899198090Srdivacky // narrower than the load width, then it's not. 3900198090Srdivacky if (Size < RCSize) 3901198090Srdivacky return NULL; 3902193323Sed // Change to CMPXXri r, 0 first. 3903193323Sed MI->setDesc(get(NewOpc)); 3904193323Sed MI->getOperand(1).ChangeToImmediate(0); 3905193323Sed } else if (Ops.size() != 1) 3906193323Sed return NULL; 3907193323Sed 3908193323Sed SmallVector<MachineOperand,4> MOs; 3909193323Sed MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 3910198090Srdivacky return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 3911193323Sed} 3912193323Sed 3913193323SedMachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3914193323Sed MachineInstr *MI, 3915198090Srdivacky const SmallVectorImpl<unsigned> &Ops, 3916193323Sed MachineInstr *LoadMI) const { 3917218893Sdim // Check switch flag 3918193323Sed if (NoFusing) return NULL; 3919193323Sed 3920226633Sdim // Unless optimizing for size, don't fold to avoid partial 3921226633Sdim // register update stalls 3922249423Sdim if (!MF.getFunction()->getAttributes(). 3923249423Sdim hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 3924226633Sdim hasPartialRegUpdate(MI->getOpcode())) 3925226633Sdim return 0; 3926201360Srdivacky 3927193323Sed // Determine the alignment of the load. 3928193323Sed unsigned Alignment = 0; 3929193323Sed if (LoadMI->hasOneMemOperand()) 3930198090Srdivacky Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 3931198090Srdivacky else 3932198090Srdivacky switch (LoadMI->getOpcode()) { 3933234353Sdim case X86::AVX2_SETALLONES: 3934243830Sdim case X86::AVX_SET0: 3935212904Sdim Alignment = 32; 3936212904Sdim break; 3937226633Sdim case X86::V_SET0: 3938198090Srdivacky case X86::V_SETALLONES: 3939198090Srdivacky Alignment = 16; 3940198090Srdivacky break; 3941198090Srdivacky case X86::FsFLD0SD: 3942198090Srdivacky Alignment = 8; 3943198090Srdivacky break; 3944198090Srdivacky case X86::FsFLD0SS: 3945198090Srdivacky Alignment = 4; 3946198090Srdivacky break; 3947198090Srdivacky default: 3948223017Sdim return 0; 3949193323Sed } 3950193323Sed if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3951193323Sed unsigned NewOpc = 0; 3952193323Sed switch (MI->getOpcode()) { 3953193323Sed default: return NULL; 3954193323Sed case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 3955208599Srdivacky case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 3956208599Srdivacky case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 3957208599Srdivacky case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 3958193323Sed } 3959193323Sed // Change to CMPXXri r, 0 first. 3960193323Sed MI->setDesc(get(NewOpc)); 3961193323Sed MI->getOperand(1).ChangeToImmediate(0); 3962193323Sed } else if (Ops.size() != 1) 3963193323Sed return NULL; 3964193323Sed 3965212904Sdim // Make sure the subregisters match. 3966212904Sdim // Otherwise we risk changing the size of the load. 3967212904Sdim if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 3968212904Sdim return NULL; 3969212904Sdim 3970210299Sed SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 3971198090Srdivacky switch (LoadMI->getOpcode()) { 3972226633Sdim case X86::V_SET0: 3973198090Srdivacky case X86::V_SETALLONES: 3974234353Sdim case X86::AVX2_SETALLONES: 3975243830Sdim case X86::AVX_SET0: 3976198090Srdivacky case X86::FsFLD0SD: 3977234353Sdim case X86::FsFLD0SS: { 3978226633Sdim // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 3979193323Sed // Create a constant-pool entry and operands to load from it. 3980193323Sed 3981204961Srdivacky // Medium and large mode can't fold loads this way. 3982204961Srdivacky if (TM.getCodeModel() != CodeModel::Small && 3983204961Srdivacky TM.getCodeModel() != CodeModel::Kernel) 3984204961Srdivacky return NULL; 3985204961Srdivacky 3986193323Sed // x86-32 PIC requires a PIC base register for constant pools. 3987193323Sed unsigned PICBase = 0; 3988198090Srdivacky if (TM.getRelocationModel() == Reloc::PIC_) { 3989198090Srdivacky if (TM.getSubtarget<X86Subtarget>().is64Bit()) 3990198090Srdivacky PICBase = X86::RIP; 3991198090Srdivacky else 3992210299Sed // FIXME: PICBase = getGlobalBaseReg(&MF); 3993198090Srdivacky // This doesn't work for several reasons. 3994198090Srdivacky // 1. GlobalBaseReg may have been spilled. 3995198090Srdivacky // 2. It may not be live at MI. 3996198090Srdivacky return NULL; 3997198090Srdivacky } 3998193323Sed 3999198090Srdivacky // Create a constant-pool entry. 4000193323Sed MachineConstantPool &MCP = *MF.getConstantPool(); 4001226633Sdim Type *Ty; 4002212904Sdim unsigned Opc = LoadMI->getOpcode(); 4003234353Sdim if (Opc == X86::FsFLD0SS) 4004198090Srdivacky Ty = Type::getFloatTy(MF.getFunction()->getContext()); 4005234353Sdim else if (Opc == X86::FsFLD0SD) 4006198090Srdivacky Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 4007243830Sdim else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 4008234353Sdim Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 4009198090Srdivacky else 4010198090Srdivacky Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 4011226633Sdim 4012243830Sdim bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 4013226633Sdim const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 4014226633Sdim Constant::getNullValue(Ty); 4015198090Srdivacky unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 4016193323Sed 4017193323Sed // Create operands to load from the constant pool entry. 4018193323Sed MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 4019193323Sed MOs.push_back(MachineOperand::CreateImm(1)); 4020193323Sed MOs.push_back(MachineOperand::CreateReg(0, false)); 4021193323Sed MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 4022193323Sed MOs.push_back(MachineOperand::CreateReg(0, false)); 4023198090Srdivacky break; 4024198090Srdivacky } 4025198090Srdivacky default: { 4026249423Sdim if ((LoadMI->getOpcode() == X86::MOVSSrm || 4027249423Sdim LoadMI->getOpcode() == X86::VMOVSSrm) && 4028249423Sdim MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4029249423Sdim > 4) 4030249423Sdim // These instructions only load 32 bits, we can't fold them if the 4031249423Sdim // destination register is wider than 32 bits (4 bytes). 4032249423Sdim return NULL; 4033249423Sdim if ((LoadMI->getOpcode() == X86::MOVSDrm || 4034249423Sdim LoadMI->getOpcode() == X86::VMOVSDrm) && 4035249423Sdim MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4036249423Sdim > 8) 4037249423Sdim // These instructions only load 64 bits, we can't fold them if the 4038249423Sdim // destination register is wider than 64 bits (8 bytes). 4039249423Sdim return NULL; 4040249423Sdim 4041193323Sed // Folding a normal load. Just copy the load's address operands. 4042193323Sed unsigned NumOps = LoadMI->getDesc().getNumOperands(); 4043210299Sed for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 4044193323Sed MOs.push_back(LoadMI->getOperand(i)); 4045198090Srdivacky break; 4046193323Sed } 4047198090Srdivacky } 4048198090Srdivacky return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 4049193323Sed} 4050193323Sed 4051193323Sed 4052193323Sedbool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 4053193323Sed const SmallVectorImpl<unsigned> &Ops) const { 4054218893Sdim // Check switch flag 4055193323Sed if (NoFusing) return 0; 4056193323Sed 4057193323Sed if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4058193323Sed switch (MI->getOpcode()) { 4059193323Sed default: return false; 4060218893Sdim case X86::TEST8rr: 4061193323Sed case X86::TEST16rr: 4062193323Sed case X86::TEST32rr: 4063193323Sed case X86::TEST64rr: 4064193323Sed return true; 4065221345Sdim case X86::ADD32ri: 4066221345Sdim // FIXME: AsmPrinter doesn't know how to handle 4067221345Sdim // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4068221345Sdim if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4069221345Sdim return false; 4070221345Sdim break; 4071193323Sed } 4072193323Sed } 4073193323Sed 4074193323Sed if (Ops.size() != 1) 4075193323Sed return false; 4076193323Sed 4077193323Sed unsigned OpNum = Ops[0]; 4078193323Sed unsigned Opc = MI->getOpcode(); 4079193323Sed unsigned NumOps = MI->getDesc().getNumOperands(); 4080193323Sed bool isTwoAddr = NumOps > 1 && 4081224145Sdim MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4082193323Sed 4083193323Sed // Folding a memory location into the two-address part of a two-address 4084193323Sed // instruction is different than folding it other places. It requires 4085193323Sed // replacing the *two* registers with the memory location. 4086218893Sdim const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 4087218893Sdim if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4088193323Sed OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4089193323Sed } else if (OpNum == 0) { // If operand 0 4090193323Sed switch (Opc) { 4091198090Srdivacky case X86::MOV8r0: 4092202375Srdivacky case X86::MOV16r0: 4093193323Sed case X86::MOV32r0: 4094218893Sdim case X86::MOV64r0: return true; 4095193323Sed default: break; 4096193323Sed } 4097193323Sed OpcodeTablePtr = &RegOp2MemOpTable0; 4098193323Sed } else if (OpNum == 1) { 4099193323Sed OpcodeTablePtr = &RegOp2MemOpTable1; 4100193323Sed } else if (OpNum == 2) { 4101193323Sed OpcodeTablePtr = &RegOp2MemOpTable2; 4102243830Sdim } else if (OpNum == 3) { 4103243830Sdim OpcodeTablePtr = &RegOp2MemOpTable3; 4104193323Sed } 4105218893Sdim 4106218893Sdim if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4107218893Sdim return true; 4108249423Sdim return TargetInstrInfo::canFoldMemoryOperand(MI, Ops); 4109193323Sed} 4110193323Sed 4111193323Sedbool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4112193323Sed unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4113193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const { 4114218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4115218893Sdim MemOp2RegOpTable.find(MI->getOpcode()); 4116193323Sed if (I == MemOp2RegOpTable.end()) 4117193323Sed return false; 4118193323Sed unsigned Opc = I->second.first; 4119226633Sdim unsigned Index = I->second.second & TB_INDEX_MASK; 4120226633Sdim bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4121226633Sdim bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4122193323Sed if (UnfoldLoad && !FoldedLoad) 4123193323Sed return false; 4124193323Sed UnfoldLoad &= FoldedLoad; 4125193323Sed if (UnfoldStore && !FoldedStore) 4126193323Sed return false; 4127193323Sed UnfoldStore &= FoldedStore; 4128193323Sed 4129224145Sdim const MCInstrDesc &MCID = get(Opc); 4130239462Sdim const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4131210299Sed if (!MI->hasOneMemOperand() && 4132210299Sed RC == &X86::VR128RegClass && 4133210299Sed !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4134210299Sed // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4135210299Sed // conservatively assume the address is unaligned. That's bad for 4136210299Sed // performance. 4137210299Sed return false; 4138210299Sed SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4139193323Sed SmallVector<MachineOperand,2> BeforeOps; 4140193323Sed SmallVector<MachineOperand,2> AfterOps; 4141193323Sed SmallVector<MachineOperand,4> ImpOps; 4142193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4143193323Sed MachineOperand &Op = MI->getOperand(i); 4144210299Sed if (i >= Index && i < Index + X86::AddrNumOperands) 4145193323Sed AddrOps.push_back(Op); 4146193323Sed else if (Op.isReg() && Op.isImplicit()) 4147193323Sed ImpOps.push_back(Op); 4148193323Sed else if (i < Index) 4149193323Sed BeforeOps.push_back(Op); 4150193323Sed else if (i > Index) 4151193323Sed AfterOps.push_back(Op); 4152193323Sed } 4153193323Sed 4154193323Sed // Emit the load instruction. 4155193323Sed if (UnfoldLoad) { 4156198090Srdivacky std::pair<MachineInstr::mmo_iterator, 4157198090Srdivacky MachineInstr::mmo_iterator> MMOs = 4158198090Srdivacky MF.extractLoadMemRefs(MI->memoperands_begin(), 4159198090Srdivacky MI->memoperands_end()); 4160198090Srdivacky loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4161193323Sed if (UnfoldStore) { 4162193323Sed // Address operands cannot be marked isKill. 4163210299Sed for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4164193323Sed MachineOperand &MO = NewMIs[0]->getOperand(i); 4165193323Sed if (MO.isReg()) 4166193323Sed MO.setIsKill(false); 4167193323Sed } 4168193323Sed } 4169193323Sed } 4170193323Sed 4171193323Sed // Emit the data processing instruction. 4172224145Sdim MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4173249423Sdim MachineInstrBuilder MIB(MF, DataMI); 4174218893Sdim 4175193323Sed if (FoldedStore) 4176193323Sed MIB.addReg(Reg, RegState::Define); 4177193323Sed for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4178193323Sed MIB.addOperand(BeforeOps[i]); 4179193323Sed if (FoldedLoad) 4180193323Sed MIB.addReg(Reg); 4181193323Sed for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4182193323Sed MIB.addOperand(AfterOps[i]); 4183193323Sed for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4184193323Sed MachineOperand &MO = ImpOps[i]; 4185193323Sed MIB.addReg(MO.getReg(), 4186193323Sed getDefRegState(MO.isDef()) | 4187193323Sed RegState::Implicit | 4188193323Sed getKillRegState(MO.isKill()) | 4189195340Sed getDeadRegState(MO.isDead()) | 4190195340Sed getUndefRegState(MO.isUndef())); 4191193323Sed } 4192193323Sed // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4193193323Sed switch (DataMI->getOpcode()) { 4194193323Sed default: break; 4195193323Sed case X86::CMP64ri32: 4196208599Srdivacky case X86::CMP64ri8: 4197193323Sed case X86::CMP32ri: 4198208599Srdivacky case X86::CMP32ri8: 4199193323Sed case X86::CMP16ri: 4200208599Srdivacky case X86::CMP16ri8: 4201193323Sed case X86::CMP8ri: { 4202193323Sed MachineOperand &MO0 = DataMI->getOperand(0); 4203193323Sed MachineOperand &MO1 = DataMI->getOperand(1); 4204193323Sed if (MO1.getImm() == 0) { 4205243830Sdim unsigned NewOpc; 4206193323Sed switch (DataMI->getOpcode()) { 4207243830Sdim default: llvm_unreachable("Unreachable!"); 4208208599Srdivacky case X86::CMP64ri8: 4209193323Sed case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4210208599Srdivacky case X86::CMP32ri8: 4211193323Sed case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4212208599Srdivacky case X86::CMP16ri8: 4213193323Sed case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4214193323Sed case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4215193323Sed } 4216193323Sed DataMI->setDesc(get(NewOpc)); 4217193323Sed MO1.ChangeToRegister(MO0.getReg(), false); 4218193323Sed } 4219193323Sed } 4220193323Sed } 4221193323Sed NewMIs.push_back(DataMI); 4222193323Sed 4223193323Sed // Emit the store instruction. 4224193323Sed if (UnfoldStore) { 4225239462Sdim const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4226198090Srdivacky std::pair<MachineInstr::mmo_iterator, 4227198090Srdivacky MachineInstr::mmo_iterator> MMOs = 4228198090Srdivacky MF.extractStoreMemRefs(MI->memoperands_begin(), 4229198090Srdivacky MI->memoperands_end()); 4230198090Srdivacky storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4231193323Sed } 4232193323Sed 4233193323Sed return true; 4234193323Sed} 4235193323Sed 4236193323Sedbool 4237193323SedX86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4238193323Sed SmallVectorImpl<SDNode*> &NewNodes) const { 4239193323Sed if (!N->isMachineOpcode()) 4240193323Sed return false; 4241193323Sed 4242218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4243218893Sdim MemOp2RegOpTable.find(N->getMachineOpcode()); 4244193323Sed if (I == MemOp2RegOpTable.end()) 4245193323Sed return false; 4246193323Sed unsigned Opc = I->second.first; 4247226633Sdim unsigned Index = I->second.second & TB_INDEX_MASK; 4248226633Sdim bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4249226633Sdim bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4250224145Sdim const MCInstrDesc &MCID = get(Opc); 4251239462Sdim MachineFunction &MF = DAG.getMachineFunction(); 4252239462Sdim const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4253224145Sdim unsigned NumDefs = MCID.NumDefs; 4254193323Sed std::vector<SDValue> AddrOps; 4255193323Sed std::vector<SDValue> BeforeOps; 4256193323Sed std::vector<SDValue> AfterOps; 4257193323Sed DebugLoc dl = N->getDebugLoc(); 4258193323Sed unsigned NumOps = N->getNumOperands(); 4259193323Sed for (unsigned i = 0; i != NumOps-1; ++i) { 4260193323Sed SDValue Op = N->getOperand(i); 4261210299Sed if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4262193323Sed AddrOps.push_back(Op); 4263193323Sed else if (i < Index-NumDefs) 4264193323Sed BeforeOps.push_back(Op); 4265193323Sed else if (i > Index-NumDefs) 4266193323Sed AfterOps.push_back(Op); 4267193323Sed } 4268193323Sed SDValue Chain = N->getOperand(NumOps-1); 4269193323Sed AddrOps.push_back(Chain); 4270193323Sed 4271193323Sed // Emit the load instruction. 4272193323Sed SDNode *Load = 0; 4273193323Sed if (FoldedLoad) { 4274198090Srdivacky EVT VT = *RC->vt_begin(); 4275199481Srdivacky std::pair<MachineInstr::mmo_iterator, 4276199481Srdivacky MachineInstr::mmo_iterator> MMOs = 4277199481Srdivacky MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4278199481Srdivacky cast<MachineSDNode>(N)->memoperands_end()); 4279210299Sed if (!(*MMOs.first) && 4280210299Sed RC == &X86::VR128RegClass && 4281210299Sed !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4282210299Sed // Do not introduce a slow unaligned load. 4283210299Sed return false; 4284226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4285226633Sdim bool isAligned = (*MMOs.first) && 4286226633Sdim (*MMOs.first)->getAlignment() >= Alignment; 4287198090Srdivacky Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 4288251662Sdim VT, MVT::Other, AddrOps); 4289193323Sed NewNodes.push_back(Load); 4290198090Srdivacky 4291198090Srdivacky // Preserve memory reference information. 4292198090Srdivacky cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4293193323Sed } 4294193323Sed 4295193323Sed // Emit the data processing instruction. 4296198090Srdivacky std::vector<EVT> VTs; 4297193323Sed const TargetRegisterClass *DstRC = 0; 4298224145Sdim if (MCID.getNumDefs() > 0) { 4299239462Sdim DstRC = getRegClass(MCID, 0, &RI, MF); 4300193323Sed VTs.push_back(*DstRC->vt_begin()); 4301193323Sed } 4302193323Sed for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4303198090Srdivacky EVT VT = N->getValueType(i); 4304224145Sdim if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4305193323Sed VTs.push_back(VT); 4306193323Sed } 4307193323Sed if (Load) 4308193323Sed BeforeOps.push_back(SDValue(Load, 0)); 4309193323Sed std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4310251662Sdim SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 4311193323Sed NewNodes.push_back(NewNode); 4312193323Sed 4313193323Sed // Emit the store instruction. 4314193323Sed if (FoldedStore) { 4315193323Sed AddrOps.pop_back(); 4316193323Sed AddrOps.push_back(SDValue(NewNode, 0)); 4317193323Sed AddrOps.push_back(Chain); 4318199481Srdivacky std::pair<MachineInstr::mmo_iterator, 4319199481Srdivacky MachineInstr::mmo_iterator> MMOs = 4320199481Srdivacky MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4321199481Srdivacky cast<MachineSDNode>(N)->memoperands_end()); 4322210299Sed if (!(*MMOs.first) && 4323210299Sed RC == &X86::VR128RegClass && 4324210299Sed !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4325210299Sed // Do not introduce a slow unaligned store. 4326210299Sed return false; 4327226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4328226633Sdim bool isAligned = (*MMOs.first) && 4329226633Sdim (*MMOs.first)->getAlignment() >= Alignment; 4330198090Srdivacky SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 4331198090Srdivacky isAligned, TM), 4332251662Sdim dl, MVT::Other, AddrOps); 4333193323Sed NewNodes.push_back(Store); 4334198090Srdivacky 4335198090Srdivacky // Preserve memory reference information. 4336198090Srdivacky cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4337193323Sed } 4338193323Sed 4339193323Sed return true; 4340193323Sed} 4341193323Sed 4342193323Sedunsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4343198892Srdivacky bool UnfoldLoad, bool UnfoldStore, 4344198892Srdivacky unsigned *LoadRegIndex) const { 4345218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4346218893Sdim MemOp2RegOpTable.find(Opc); 4347193323Sed if (I == MemOp2RegOpTable.end()) 4348193323Sed return 0; 4349226633Sdim bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4350226633Sdim bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4351193323Sed if (UnfoldLoad && !FoldedLoad) 4352193323Sed return 0; 4353193323Sed if (UnfoldStore && !FoldedStore) 4354193323Sed return 0; 4355198892Srdivacky if (LoadRegIndex) 4356226633Sdim *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4357193323Sed return I->second.first; 4358193323Sed} 4359193323Sed 4360202878Srdivackybool 4361202878SrdivackyX86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4362202878Srdivacky int64_t &Offset1, int64_t &Offset2) const { 4363202878Srdivacky if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4364202878Srdivacky return false; 4365202878Srdivacky unsigned Opc1 = Load1->getMachineOpcode(); 4366202878Srdivacky unsigned Opc2 = Load2->getMachineOpcode(); 4367202878Srdivacky switch (Opc1) { 4368202878Srdivacky default: return false; 4369202878Srdivacky case X86::MOV8rm: 4370202878Srdivacky case X86::MOV16rm: 4371202878Srdivacky case X86::MOV32rm: 4372202878Srdivacky case X86::MOV64rm: 4373202878Srdivacky case X86::LD_Fp32m: 4374202878Srdivacky case X86::LD_Fp64m: 4375202878Srdivacky case X86::LD_Fp80m: 4376202878Srdivacky case X86::MOVSSrm: 4377202878Srdivacky case X86::MOVSDrm: 4378202878Srdivacky case X86::MMX_MOVD64rm: 4379202878Srdivacky case X86::MMX_MOVQ64rm: 4380202878Srdivacky case X86::FsMOVAPSrm: 4381202878Srdivacky case X86::FsMOVAPDrm: 4382202878Srdivacky case X86::MOVAPSrm: 4383202878Srdivacky case X86::MOVUPSrm: 4384202878Srdivacky case X86::MOVAPDrm: 4385202878Srdivacky case X86::MOVDQArm: 4386202878Srdivacky case X86::MOVDQUrm: 4387226633Sdim // AVX load instructions 4388226633Sdim case X86::VMOVSSrm: 4389226633Sdim case X86::VMOVSDrm: 4390226633Sdim case X86::FsVMOVAPSrm: 4391226633Sdim case X86::FsVMOVAPDrm: 4392226633Sdim case X86::VMOVAPSrm: 4393226633Sdim case X86::VMOVUPSrm: 4394226633Sdim case X86::VMOVAPDrm: 4395226633Sdim case X86::VMOVDQArm: 4396226633Sdim case X86::VMOVDQUrm: 4397224145Sdim case X86::VMOVAPSYrm: 4398224145Sdim case X86::VMOVUPSYrm: 4399224145Sdim case X86::VMOVAPDYrm: 4400224145Sdim case X86::VMOVDQAYrm: 4401224145Sdim case X86::VMOVDQUYrm: 4402202878Srdivacky break; 4403202878Srdivacky } 4404202878Srdivacky switch (Opc2) { 4405202878Srdivacky default: return false; 4406202878Srdivacky case X86::MOV8rm: 4407202878Srdivacky case X86::MOV16rm: 4408202878Srdivacky case X86::MOV32rm: 4409202878Srdivacky case X86::MOV64rm: 4410202878Srdivacky case X86::LD_Fp32m: 4411202878Srdivacky case X86::LD_Fp64m: 4412202878Srdivacky case X86::LD_Fp80m: 4413202878Srdivacky case X86::MOVSSrm: 4414202878Srdivacky case X86::MOVSDrm: 4415202878Srdivacky case X86::MMX_MOVD64rm: 4416202878Srdivacky case X86::MMX_MOVQ64rm: 4417202878Srdivacky case X86::FsMOVAPSrm: 4418202878Srdivacky case X86::FsMOVAPDrm: 4419202878Srdivacky case X86::MOVAPSrm: 4420202878Srdivacky case X86::MOVUPSrm: 4421202878Srdivacky case X86::MOVAPDrm: 4422202878Srdivacky case X86::MOVDQArm: 4423202878Srdivacky case X86::MOVDQUrm: 4424226633Sdim // AVX load instructions 4425226633Sdim case X86::VMOVSSrm: 4426226633Sdim case X86::VMOVSDrm: 4427226633Sdim case X86::FsVMOVAPSrm: 4428226633Sdim case X86::FsVMOVAPDrm: 4429226633Sdim case X86::VMOVAPSrm: 4430226633Sdim case X86::VMOVUPSrm: 4431226633Sdim case X86::VMOVAPDrm: 4432226633Sdim case X86::VMOVDQArm: 4433226633Sdim case X86::VMOVDQUrm: 4434224145Sdim case X86::VMOVAPSYrm: 4435224145Sdim case X86::VMOVUPSYrm: 4436224145Sdim case X86::VMOVAPDYrm: 4437224145Sdim case X86::VMOVDQAYrm: 4438224145Sdim case X86::VMOVDQUYrm: 4439202878Srdivacky break; 4440202878Srdivacky } 4441202878Srdivacky 4442202878Srdivacky // Check if chain operands and base addresses match. 4443202878Srdivacky if (Load1->getOperand(0) != Load2->getOperand(0) || 4444202878Srdivacky Load1->getOperand(5) != Load2->getOperand(5)) 4445202878Srdivacky return false; 4446202878Srdivacky // Segment operands should match as well. 4447202878Srdivacky if (Load1->getOperand(4) != Load2->getOperand(4)) 4448202878Srdivacky return false; 4449202878Srdivacky // Scale should be 1, Index should be Reg0. 4450202878Srdivacky if (Load1->getOperand(1) == Load2->getOperand(1) && 4451202878Srdivacky Load1->getOperand(2) == Load2->getOperand(2)) { 4452202878Srdivacky if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4453202878Srdivacky return false; 4454202878Srdivacky 4455202878Srdivacky // Now let's examine the displacements. 4456202878Srdivacky if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4457202878Srdivacky isa<ConstantSDNode>(Load2->getOperand(3))) { 4458202878Srdivacky Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4459202878Srdivacky Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4460202878Srdivacky return true; 4461202878Srdivacky } 4462202878Srdivacky } 4463202878Srdivacky return false; 4464202878Srdivacky} 4465202878Srdivacky 4466202878Srdivackybool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4467202878Srdivacky int64_t Offset1, int64_t Offset2, 4468202878Srdivacky unsigned NumLoads) const { 4469202878Srdivacky assert(Offset2 > Offset1); 4470202878Srdivacky if ((Offset2 - Offset1) / 8 > 64) 4471202878Srdivacky return false; 4472202878Srdivacky 4473202878Srdivacky unsigned Opc1 = Load1->getMachineOpcode(); 4474202878Srdivacky unsigned Opc2 = Load2->getMachineOpcode(); 4475202878Srdivacky if (Opc1 != Opc2) 4476202878Srdivacky return false; // FIXME: overly conservative? 4477202878Srdivacky 4478202878Srdivacky switch (Opc1) { 4479202878Srdivacky default: break; 4480202878Srdivacky case X86::LD_Fp32m: 4481202878Srdivacky case X86::LD_Fp64m: 4482202878Srdivacky case X86::LD_Fp80m: 4483202878Srdivacky case X86::MMX_MOVD64rm: 4484202878Srdivacky case X86::MMX_MOVQ64rm: 4485202878Srdivacky return false; 4486202878Srdivacky } 4487202878Srdivacky 4488202878Srdivacky EVT VT = Load1->getValueType(0); 4489202878Srdivacky switch (VT.getSimpleVT().SimpleTy) { 4490210299Sed default: 4491202878Srdivacky // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4492202878Srdivacky // have 16 of them to play with. 4493202878Srdivacky if (TM.getSubtargetImpl()->is64Bit()) { 4494202878Srdivacky if (NumLoads >= 3) 4495202878Srdivacky return false; 4496210299Sed } else if (NumLoads) { 4497202878Srdivacky return false; 4498210299Sed } 4499202878Srdivacky break; 4500202878Srdivacky case MVT::i8: 4501202878Srdivacky case MVT::i16: 4502202878Srdivacky case MVT::i32: 4503202878Srdivacky case MVT::i64: 4504202878Srdivacky case MVT::f32: 4505202878Srdivacky case MVT::f64: 4506202878Srdivacky if (NumLoads) 4507202878Srdivacky return false; 4508210299Sed break; 4509202878Srdivacky } 4510202878Srdivacky 4511202878Srdivacky return true; 4512202878Srdivacky} 4513202878Srdivacky 4514202878Srdivacky 4515193323Sedbool X86InstrInfo:: 4516193323SedReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4517193323Sed assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 4518193323Sed X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 4519193323Sed if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 4520193323Sed return true; 4521193323Sed Cond[0].setImm(GetOppositeBranchCondition(CC)); 4522193323Sed return false; 4523193323Sed} 4524193323Sed 4525193323Sedbool X86InstrInfo:: 4526193323SedisSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 4527193323Sed // FIXME: Return false for x87 stack register classes for now. We can't 4528193323Sed // allow any loads of these registers before FpGet_ST0_80. 4529193323Sed return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 4530193323Sed RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 4531193323Sed} 4532193323Sed 4533193323Sed/// getGlobalBaseReg - Return a virtual register initialized with the 4534193323Sed/// the global base register value. Output instructions required to 4535193323Sed/// initialize the register in the function entry block, if necessary. 4536193323Sed/// 4537210299Sed/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 4538210299Sed/// 4539193323Sedunsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 4540193323Sed assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 4541193323Sed "X86-64 PIC uses RIP relative addressing"); 4542193323Sed 4543193323Sed X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 4544193323Sed unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4545193323Sed if (GlobalBaseReg != 0) 4546193323Sed return GlobalBaseReg; 4547193323Sed 4548210299Sed // Create the register. The code to initialize it is inserted 4549210299Sed // later, by the CGBR pass (below). 4550193323Sed MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4551239462Sdim GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4552193323Sed X86FI->setGlobalBaseReg(GlobalBaseReg); 4553193323Sed return GlobalBaseReg; 4554193323Sed} 4555206083Srdivacky 4556206083Srdivacky// These are the replaceable SSE instructions. Some of these have Int variants 4557206083Srdivacky// that we don't include here. We don't want to replace instructions selected 4558206083Srdivacky// by intrinsics. 4559234353Sdimstatic const uint16_t ReplaceableInstrs[][3] = { 4560212904Sdim //PackedSingle PackedDouble PackedInt 4561206083Srdivacky { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 4562206083Srdivacky { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 4563206083Srdivacky { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 4564206083Srdivacky { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 4565206083Srdivacky { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 4566206083Srdivacky { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 4567206083Srdivacky { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 4568206083Srdivacky { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 4569206083Srdivacky { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 4570206083Srdivacky { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 4571206083Srdivacky { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 4572206083Srdivacky { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 4573206083Srdivacky { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 4574206083Srdivacky { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 4575212904Sdim // AVX 128-bit support 4576212904Sdim { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 4577212904Sdim { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 4578212904Sdim { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 4579212904Sdim { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 4580212904Sdim { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 4581212904Sdim { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 4582212904Sdim { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 4583212904Sdim { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 4584212904Sdim { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 4585212904Sdim { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 4586212904Sdim { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 4587212904Sdim { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 4588212904Sdim { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 4589212904Sdim { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 4590224145Sdim // AVX 256-bit support 4591224145Sdim { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 4592224145Sdim { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 4593224145Sdim { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 4594224145Sdim { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 4595224145Sdim { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 4596234353Sdim { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 4597206083Srdivacky}; 4598206083Srdivacky 4599234353Sdimstatic const uint16_t ReplaceableInstrsAVX2[][3] = { 4600234353Sdim //PackedSingle PackedDouble PackedInt 4601234353Sdim { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 4602234353Sdim { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 4603234353Sdim { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 4604234353Sdim { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 4605234353Sdim { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 4606234353Sdim { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 4607234353Sdim { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 4608234353Sdim { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 4609234353Sdim { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 4610234353Sdim { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 4611234353Sdim { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 4612234353Sdim { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 4613234353Sdim { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 4614234353Sdim { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr } 4615234353Sdim}; 4616234353Sdim 4617206083Srdivacky// FIXME: Some shuffle and unpack instructions have equivalents in different 4618206083Srdivacky// domains, but they require a bit more work than just switching opcodes. 4619206083Srdivacky 4620234353Sdimstatic const uint16_t *lookup(unsigned opcode, unsigned domain) { 4621206083Srdivacky for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 4622206083Srdivacky if (ReplaceableInstrs[i][domain-1] == opcode) 4623206083Srdivacky return ReplaceableInstrs[i]; 4624206083Srdivacky return 0; 4625206083Srdivacky} 4626206083Srdivacky 4627234353Sdimstatic const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 4628234353Sdim for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 4629234353Sdim if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 4630234353Sdim return ReplaceableInstrsAVX2[i]; 4631234353Sdim return 0; 4632234353Sdim} 4633234353Sdim 4634206083Srdivackystd::pair<uint16_t, uint16_t> 4635226633SdimX86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 4636206083Srdivacky uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4637234353Sdim bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2(); 4638234353Sdim uint16_t validDomains = 0; 4639234353Sdim if (domain && lookup(MI->getOpcode(), domain)) 4640234353Sdim validDomains = 0xe; 4641234353Sdim else if (domain && lookupAVX2(MI->getOpcode(), domain)) 4642234353Sdim validDomains = hasAVX2 ? 0xe : 0x6; 4643234353Sdim return std::make_pair(domain, validDomains); 4644206083Srdivacky} 4645206083Srdivacky 4646226633Sdimvoid X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4647206083Srdivacky assert(Domain>0 && Domain<4 && "Invalid execution domain"); 4648206083Srdivacky uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4649206083Srdivacky assert(dom && "Not an SSE instruction"); 4650234353Sdim const uint16_t *table = lookup(MI->getOpcode(), dom); 4651234353Sdim if (!table) { // try the other table 4652234353Sdim assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) && 4653234353Sdim "256-bit vector operations only available in AVX2"); 4654234353Sdim table = lookupAVX2(MI->getOpcode(), dom); 4655234353Sdim } 4656206083Srdivacky assert(table && "Cannot change domain"); 4657206083Srdivacky MI->setDesc(get(table[Domain-1])); 4658206083Srdivacky} 4659207618Srdivacky 4660207618Srdivacky/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 4661207618Srdivackyvoid X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 4662207618Srdivacky NopInst.setOpcode(X86::NOOP); 4663207618Srdivacky} 4664207618Srdivacky 4665221345Sdimbool X86InstrInfo::isHighLatencyDef(int opc) const { 4666221345Sdim switch (opc) { 4667218893Sdim default: return false; 4668218893Sdim case X86::DIVSDrm: 4669218893Sdim case X86::DIVSDrm_Int: 4670218893Sdim case X86::DIVSDrr: 4671218893Sdim case X86::DIVSDrr_Int: 4672218893Sdim case X86::DIVSSrm: 4673218893Sdim case X86::DIVSSrm_Int: 4674218893Sdim case X86::DIVSSrr: 4675218893Sdim case X86::DIVSSrr_Int: 4676218893Sdim case X86::SQRTPDm: 4677218893Sdim case X86::SQRTPDr: 4678218893Sdim case X86::SQRTPSm: 4679218893Sdim case X86::SQRTPSr: 4680218893Sdim case X86::SQRTSDm: 4681218893Sdim case X86::SQRTSDm_Int: 4682218893Sdim case X86::SQRTSDr: 4683218893Sdim case X86::SQRTSDr_Int: 4684218893Sdim case X86::SQRTSSm: 4685218893Sdim case X86::SQRTSSm_Int: 4686218893Sdim case X86::SQRTSSr: 4687218893Sdim case X86::SQRTSSr_Int: 4688226633Sdim // AVX instructions with high latency 4689226633Sdim case X86::VDIVSDrm: 4690226633Sdim case X86::VDIVSDrm_Int: 4691226633Sdim case X86::VDIVSDrr: 4692226633Sdim case X86::VDIVSDrr_Int: 4693226633Sdim case X86::VDIVSSrm: 4694226633Sdim case X86::VDIVSSrm_Int: 4695226633Sdim case X86::VDIVSSrr: 4696226633Sdim case X86::VDIVSSrr_Int: 4697226633Sdim case X86::VSQRTPDm: 4698226633Sdim case X86::VSQRTPDr: 4699226633Sdim case X86::VSQRTPSm: 4700226633Sdim case X86::VSQRTPSr: 4701226633Sdim case X86::VSQRTSDm: 4702226633Sdim case X86::VSQRTSDm_Int: 4703226633Sdim case X86::VSQRTSDr: 4704226633Sdim case X86::VSQRTSSm: 4705226633Sdim case X86::VSQRTSSm_Int: 4706226633Sdim case X86::VSQRTSSr: 4707218893Sdim return true; 4708218893Sdim } 4709218893Sdim} 4710218893Sdim 4711221345Sdimbool X86InstrInfo:: 4712221345SdimhasHighOperandLatency(const InstrItineraryData *ItinData, 4713221345Sdim const MachineRegisterInfo *MRI, 4714221345Sdim const MachineInstr *DefMI, unsigned DefIdx, 4715221345Sdim const MachineInstr *UseMI, unsigned UseIdx) const { 4716221345Sdim return isHighLatencyDef(DefMI->getOpcode()); 4717221345Sdim} 4718221345Sdim 4719210299Sednamespace { 4720210299Sed /// CGBR - Create Global Base Reg pass. This initializes the PIC 4721210299Sed /// global base register for x86-32. 4722210299Sed struct CGBR : public MachineFunctionPass { 4723210299Sed static char ID; 4724212904Sdim CGBR() : MachineFunctionPass(ID) {} 4725210299Sed 4726210299Sed virtual bool runOnMachineFunction(MachineFunction &MF) { 4727210299Sed const X86TargetMachine *TM = 4728210299Sed static_cast<const X86TargetMachine *>(&MF.getTarget()); 4729210299Sed 4730210299Sed assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 4731210299Sed "X86-64 PIC uses RIP relative addressing"); 4732210299Sed 4733210299Sed // Only emit a global base reg in PIC mode. 4734210299Sed if (TM->getRelocationModel() != Reloc::PIC_) 4735210299Sed return false; 4736210299Sed 4737218893Sdim X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 4738218893Sdim unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4739218893Sdim 4740218893Sdim // If we didn't need a GlobalBaseReg, don't insert code. 4741218893Sdim if (GlobalBaseReg == 0) 4742218893Sdim return false; 4743218893Sdim 4744210299Sed // Insert the set of GlobalBaseReg into the first MBB of the function 4745210299Sed MachineBasicBlock &FirstMBB = MF.front(); 4746210299Sed MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 4747210299Sed DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 4748210299Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4749210299Sed const X86InstrInfo *TII = TM->getInstrInfo(); 4750210299Sed 4751210299Sed unsigned PC; 4752210299Sed if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 4753239462Sdim PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4754210299Sed else 4755218893Sdim PC = GlobalBaseReg; 4756218893Sdim 4757210299Sed // Operand of MovePCtoStack is completely ignored by asm printer. It's 4758210299Sed // only used in JIT code emission as displacement to pc. 4759210299Sed BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 4760218893Sdim 4761210299Sed // If we're using vanilla 'GOT' PIC style, we should use relative addressing 4762210299Sed // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 4763210299Sed if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 4764210299Sed // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 4765210299Sed BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 4766210299Sed .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 4767210299Sed X86II::MO_GOT_ABSOLUTE_ADDRESS); 4768210299Sed } 4769210299Sed 4770210299Sed return true; 4771210299Sed } 4772210299Sed 4773210299Sed virtual const char *getPassName() const { 4774210299Sed return "X86 PIC Global Base Reg Initialization"; 4775210299Sed } 4776210299Sed 4777210299Sed virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4778210299Sed AU.setPreservesCFG(); 4779210299Sed MachineFunctionPass::getAnalysisUsage(AU); 4780210299Sed } 4781210299Sed }; 4782210299Sed} 4783210299Sed 4784210299Sedchar CGBR::ID = 0; 4785210299SedFunctionPass* 4786210299Sedllvm::createGlobalBaseRegPass() { return new CGBR(); } 4787239462Sdim 4788239462Sdimnamespace { 4789239462Sdim struct LDTLSCleanup : public MachineFunctionPass { 4790239462Sdim static char ID; 4791239462Sdim LDTLSCleanup() : MachineFunctionPass(ID) {} 4792239462Sdim 4793239462Sdim virtual bool runOnMachineFunction(MachineFunction &MF) { 4794239462Sdim X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 4795239462Sdim if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 4796239462Sdim // No point folding accesses if there isn't at least two. 4797239462Sdim return false; 4798239462Sdim } 4799239462Sdim 4800239462Sdim MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 4801239462Sdim return VisitNode(DT->getRootNode(), 0); 4802239462Sdim } 4803239462Sdim 4804239462Sdim // Visit the dominator subtree rooted at Node in pre-order. 4805239462Sdim // If TLSBaseAddrReg is non-null, then use that to replace any 4806239462Sdim // TLS_base_addr instructions. Otherwise, create the register 4807239462Sdim // when the first such instruction is seen, and then use it 4808239462Sdim // as we encounter more instructions. 4809239462Sdim bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 4810239462Sdim MachineBasicBlock *BB = Node->getBlock(); 4811239462Sdim bool Changed = false; 4812239462Sdim 4813239462Sdim // Traverse the current block. 4814239462Sdim for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 4815239462Sdim ++I) { 4816239462Sdim switch (I->getOpcode()) { 4817239462Sdim case X86::TLS_base_addr32: 4818239462Sdim case X86::TLS_base_addr64: 4819239462Sdim if (TLSBaseAddrReg) 4820239462Sdim I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 4821239462Sdim else 4822239462Sdim I = SetRegister(I, &TLSBaseAddrReg); 4823239462Sdim Changed = true; 4824239462Sdim break; 4825239462Sdim default: 4826239462Sdim break; 4827239462Sdim } 4828239462Sdim } 4829239462Sdim 4830239462Sdim // Visit the children of this block in the dominator tree. 4831239462Sdim for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 4832239462Sdim I != E; ++I) { 4833239462Sdim Changed |= VisitNode(*I, TLSBaseAddrReg); 4834239462Sdim } 4835239462Sdim 4836239462Sdim return Changed; 4837239462Sdim } 4838239462Sdim 4839239462Sdim // Replace the TLS_base_addr instruction I with a copy from 4840239462Sdim // TLSBaseAddrReg, returning the new instruction. 4841239462Sdim MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 4842239462Sdim unsigned TLSBaseAddrReg) { 4843239462Sdim MachineFunction *MF = I->getParent()->getParent(); 4844239462Sdim const X86TargetMachine *TM = 4845239462Sdim static_cast<const X86TargetMachine *>(&MF->getTarget()); 4846239462Sdim const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4847239462Sdim const X86InstrInfo *TII = TM->getInstrInfo(); 4848239462Sdim 4849239462Sdim // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 4850239462Sdim MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 4851239462Sdim TII->get(TargetOpcode::COPY), 4852239462Sdim is64Bit ? X86::RAX : X86::EAX) 4853239462Sdim .addReg(TLSBaseAddrReg); 4854239462Sdim 4855239462Sdim // Erase the TLS_base_addr instruction. 4856239462Sdim I->eraseFromParent(); 4857239462Sdim 4858239462Sdim return Copy; 4859239462Sdim } 4860239462Sdim 4861239462Sdim // Create a virtal register in *TLSBaseAddrReg, and populate it by 4862239462Sdim // inserting a copy instruction after I. Returns the new instruction. 4863239462Sdim MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 4864239462Sdim MachineFunction *MF = I->getParent()->getParent(); 4865239462Sdim const X86TargetMachine *TM = 4866239462Sdim static_cast<const X86TargetMachine *>(&MF->getTarget()); 4867239462Sdim const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4868239462Sdim const X86InstrInfo *TII = TM->getInstrInfo(); 4869239462Sdim 4870239462Sdim // Create a virtual register for the TLS base address. 4871239462Sdim MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4872239462Sdim *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 4873239462Sdim ? &X86::GR64RegClass 4874239462Sdim : &X86::GR32RegClass); 4875239462Sdim 4876239462Sdim // Insert a copy from RAX/EAX to TLSBaseAddrReg. 4877239462Sdim MachineInstr *Next = I->getNextNode(); 4878239462Sdim MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 4879239462Sdim TII->get(TargetOpcode::COPY), 4880239462Sdim *TLSBaseAddrReg) 4881239462Sdim .addReg(is64Bit ? X86::RAX : X86::EAX); 4882239462Sdim 4883239462Sdim return Copy; 4884239462Sdim } 4885239462Sdim 4886239462Sdim virtual const char *getPassName() const { 4887239462Sdim return "Local Dynamic TLS Access Clean-up"; 4888239462Sdim } 4889239462Sdim 4890239462Sdim virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4891239462Sdim AU.setPreservesCFG(); 4892239462Sdim AU.addRequired<MachineDominatorTree>(); 4893239462Sdim MachineFunctionPass::getAnalysisUsage(AU); 4894239462Sdim } 4895239462Sdim }; 4896239462Sdim} 4897239462Sdim 4898239462Sdimchar LDTLSCleanup::ID = 0; 4899239462SdimFunctionPass* 4900239462Sdimllvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 4901