X86InstrInfo.cpp revision 243830
1234353Sdim//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the X86 implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "X86InstrInfo.h" 15193323Sed#include "X86.h" 16193323Sed#include "X86InstrBuilder.h" 17193323Sed#include "X86MachineFunctionInfo.h" 18193323Sed#include "X86Subtarget.h" 19193323Sed#include "X86TargetMachine.h" 20193323Sed#include "llvm/DerivedTypes.h" 21198090Srdivacky#include "llvm/LLVMContext.h" 22193323Sed#include "llvm/ADT/STLExtras.h" 23193323Sed#include "llvm/CodeGen/MachineConstantPool.h" 24239462Sdim#include "llvm/CodeGen/MachineDominators.h" 25193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 26193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 27193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 28193323Sed#include "llvm/CodeGen/LiveVariables.h" 29234353Sdim#include "llvm/MC/MCAsmInfo.h" 30207618Srdivacky#include "llvm/MC/MCInst.h" 31193323Sed#include "llvm/Support/CommandLine.h" 32202375Srdivacky#include "llvm/Support/Debug.h" 33198090Srdivacky#include "llvm/Support/ErrorHandling.h" 34198090Srdivacky#include "llvm/Support/raw_ostream.h" 35193323Sed#include "llvm/Target/TargetOptions.h" 36199481Srdivacky#include <limits> 37199481Srdivacky 38224145Sdim#define GET_INSTRINFO_CTOR 39224145Sdim#include "X86GenInstrInfo.inc" 40224145Sdim 41193323Sedusing namespace llvm; 42193323Sed 43198090Srdivackystatic cl::opt<bool> 44198090SrdivackyNoFusing("disable-spill-fusing", 45198090Srdivacky cl::desc("Disable fusing of spill code into instructions")); 46198090Srdivackystatic cl::opt<bool> 47198090SrdivackyPrintFailedFusing("print-failed-fuse-candidates", 48198090Srdivacky cl::desc("Print instructions that the allocator wants to" 49198090Srdivacky " fuse, but the X86 backend currently can't"), 50198090Srdivacky cl::Hidden); 51198090Srdivackystatic cl::opt<bool> 52198090SrdivackyReMatPICStubLoad("remat-pic-stub-load", 53198090Srdivacky cl::desc("Re-materialize load from stub in PIC mode"), 54198090Srdivacky cl::init(false), cl::Hidden); 55193323Sed 56226633Sdimenum { 57226633Sdim // Select which memory operand is being unfolded. 58239462Sdim // (stored in bits 0 - 3) 59226633Sdim TB_INDEX_0 = 0, 60226633Sdim TB_INDEX_1 = 1, 61226633Sdim TB_INDEX_2 = 2, 62239462Sdim TB_INDEX_3 = 3, 63239462Sdim TB_INDEX_MASK = 0xf, 64226633Sdim 65239462Sdim // Do not insert the reverse map (MemOp -> RegOp) into the table. 66239462Sdim // This may be needed because there is a many -> one mapping. 67239462Sdim TB_NO_REVERSE = 1 << 4, 68239462Sdim 69239462Sdim // Do not insert the forward map (RegOp -> MemOp) into the table. 70239462Sdim // This is needed for Native Client, which prohibits branch 71239462Sdim // instructions from using a memory operand. 72239462Sdim TB_NO_FORWARD = 1 << 5, 73239462Sdim 74239462Sdim TB_FOLDED_LOAD = 1 << 6, 75239462Sdim TB_FOLDED_STORE = 1 << 7, 76239462Sdim 77226633Sdim // Minimum alignment required for load/store. 78226633Sdim // Used for RegOp->MemOp conversion. 79226633Sdim // (stored in bits 8 - 15) 80226633Sdim TB_ALIGN_SHIFT = 8, 81226633Sdim TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 82226633Sdim TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 83226633Sdim TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 84239462Sdim TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 85226633Sdim}; 86226633Sdim 87234353Sdimstruct X86OpTblEntry { 88234353Sdim uint16_t RegOp; 89234353Sdim uint16_t MemOp; 90239462Sdim uint16_t Flags; 91234353Sdim}; 92234353Sdim 93193323SedX86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 94224145Sdim : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 95224145Sdim ? X86::ADJCALLSTACKDOWN64 96224145Sdim : X86::ADJCALLSTACKDOWN32), 97224145Sdim (tm.getSubtarget<X86Subtarget>().is64Bit() 98224145Sdim ? X86::ADJCALLSTACKUP64 99224145Sdim : X86::ADJCALLSTACKUP32)), 100193323Sed TM(tm), RI(tm, *this) { 101218893Sdim 102234353Sdim static const X86OpTblEntry OpTbl2Addr[] = { 103226633Sdim { X86::ADC32ri, X86::ADC32mi, 0 }, 104226633Sdim { X86::ADC32ri8, X86::ADC32mi8, 0 }, 105226633Sdim { X86::ADC32rr, X86::ADC32mr, 0 }, 106226633Sdim { X86::ADC64ri32, X86::ADC64mi32, 0 }, 107226633Sdim { X86::ADC64ri8, X86::ADC64mi8, 0 }, 108226633Sdim { X86::ADC64rr, X86::ADC64mr, 0 }, 109226633Sdim { X86::ADD16ri, X86::ADD16mi, 0 }, 110226633Sdim { X86::ADD16ri8, X86::ADD16mi8, 0 }, 111226633Sdim { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 112226633Sdim { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 113226633Sdim { X86::ADD16rr, X86::ADD16mr, 0 }, 114226633Sdim { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 115226633Sdim { X86::ADD32ri, X86::ADD32mi, 0 }, 116226633Sdim { X86::ADD32ri8, X86::ADD32mi8, 0 }, 117226633Sdim { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 118226633Sdim { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 119226633Sdim { X86::ADD32rr, X86::ADD32mr, 0 }, 120226633Sdim { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 121226633Sdim { X86::ADD64ri32, X86::ADD64mi32, 0 }, 122226633Sdim { X86::ADD64ri8, X86::ADD64mi8, 0 }, 123226633Sdim { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 124226633Sdim { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 125226633Sdim { X86::ADD64rr, X86::ADD64mr, 0 }, 126226633Sdim { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 127226633Sdim { X86::ADD8ri, X86::ADD8mi, 0 }, 128226633Sdim { X86::ADD8rr, X86::ADD8mr, 0 }, 129226633Sdim { X86::AND16ri, X86::AND16mi, 0 }, 130226633Sdim { X86::AND16ri8, X86::AND16mi8, 0 }, 131226633Sdim { X86::AND16rr, X86::AND16mr, 0 }, 132226633Sdim { X86::AND32ri, X86::AND32mi, 0 }, 133226633Sdim { X86::AND32ri8, X86::AND32mi8, 0 }, 134226633Sdim { X86::AND32rr, X86::AND32mr, 0 }, 135226633Sdim { X86::AND64ri32, X86::AND64mi32, 0 }, 136226633Sdim { X86::AND64ri8, X86::AND64mi8, 0 }, 137226633Sdim { X86::AND64rr, X86::AND64mr, 0 }, 138226633Sdim { X86::AND8ri, X86::AND8mi, 0 }, 139226633Sdim { X86::AND8rr, X86::AND8mr, 0 }, 140226633Sdim { X86::DEC16r, X86::DEC16m, 0 }, 141226633Sdim { X86::DEC32r, X86::DEC32m, 0 }, 142226633Sdim { X86::DEC64_16r, X86::DEC64_16m, 0 }, 143226633Sdim { X86::DEC64_32r, X86::DEC64_32m, 0 }, 144226633Sdim { X86::DEC64r, X86::DEC64m, 0 }, 145226633Sdim { X86::DEC8r, X86::DEC8m, 0 }, 146226633Sdim { X86::INC16r, X86::INC16m, 0 }, 147226633Sdim { X86::INC32r, X86::INC32m, 0 }, 148226633Sdim { X86::INC64_16r, X86::INC64_16m, 0 }, 149226633Sdim { X86::INC64_32r, X86::INC64_32m, 0 }, 150226633Sdim { X86::INC64r, X86::INC64m, 0 }, 151226633Sdim { X86::INC8r, X86::INC8m, 0 }, 152226633Sdim { X86::NEG16r, X86::NEG16m, 0 }, 153226633Sdim { X86::NEG32r, X86::NEG32m, 0 }, 154226633Sdim { X86::NEG64r, X86::NEG64m, 0 }, 155226633Sdim { X86::NEG8r, X86::NEG8m, 0 }, 156226633Sdim { X86::NOT16r, X86::NOT16m, 0 }, 157226633Sdim { X86::NOT32r, X86::NOT32m, 0 }, 158226633Sdim { X86::NOT64r, X86::NOT64m, 0 }, 159226633Sdim { X86::NOT8r, X86::NOT8m, 0 }, 160226633Sdim { X86::OR16ri, X86::OR16mi, 0 }, 161226633Sdim { X86::OR16ri8, X86::OR16mi8, 0 }, 162226633Sdim { X86::OR16rr, X86::OR16mr, 0 }, 163226633Sdim { X86::OR32ri, X86::OR32mi, 0 }, 164226633Sdim { X86::OR32ri8, X86::OR32mi8, 0 }, 165226633Sdim { X86::OR32rr, X86::OR32mr, 0 }, 166226633Sdim { X86::OR64ri32, X86::OR64mi32, 0 }, 167226633Sdim { X86::OR64ri8, X86::OR64mi8, 0 }, 168226633Sdim { X86::OR64rr, X86::OR64mr, 0 }, 169226633Sdim { X86::OR8ri, X86::OR8mi, 0 }, 170226633Sdim { X86::OR8rr, X86::OR8mr, 0 }, 171226633Sdim { X86::ROL16r1, X86::ROL16m1, 0 }, 172226633Sdim { X86::ROL16rCL, X86::ROL16mCL, 0 }, 173226633Sdim { X86::ROL16ri, X86::ROL16mi, 0 }, 174226633Sdim { X86::ROL32r1, X86::ROL32m1, 0 }, 175226633Sdim { X86::ROL32rCL, X86::ROL32mCL, 0 }, 176226633Sdim { X86::ROL32ri, X86::ROL32mi, 0 }, 177226633Sdim { X86::ROL64r1, X86::ROL64m1, 0 }, 178226633Sdim { X86::ROL64rCL, X86::ROL64mCL, 0 }, 179226633Sdim { X86::ROL64ri, X86::ROL64mi, 0 }, 180226633Sdim { X86::ROL8r1, X86::ROL8m1, 0 }, 181226633Sdim { X86::ROL8rCL, X86::ROL8mCL, 0 }, 182226633Sdim { X86::ROL8ri, X86::ROL8mi, 0 }, 183226633Sdim { X86::ROR16r1, X86::ROR16m1, 0 }, 184226633Sdim { X86::ROR16rCL, X86::ROR16mCL, 0 }, 185226633Sdim { X86::ROR16ri, X86::ROR16mi, 0 }, 186226633Sdim { X86::ROR32r1, X86::ROR32m1, 0 }, 187226633Sdim { X86::ROR32rCL, X86::ROR32mCL, 0 }, 188226633Sdim { X86::ROR32ri, X86::ROR32mi, 0 }, 189226633Sdim { X86::ROR64r1, X86::ROR64m1, 0 }, 190226633Sdim { X86::ROR64rCL, X86::ROR64mCL, 0 }, 191226633Sdim { X86::ROR64ri, X86::ROR64mi, 0 }, 192226633Sdim { X86::ROR8r1, X86::ROR8m1, 0 }, 193226633Sdim { X86::ROR8rCL, X86::ROR8mCL, 0 }, 194226633Sdim { X86::ROR8ri, X86::ROR8mi, 0 }, 195226633Sdim { X86::SAR16r1, X86::SAR16m1, 0 }, 196226633Sdim { X86::SAR16rCL, X86::SAR16mCL, 0 }, 197226633Sdim { X86::SAR16ri, X86::SAR16mi, 0 }, 198226633Sdim { X86::SAR32r1, X86::SAR32m1, 0 }, 199226633Sdim { X86::SAR32rCL, X86::SAR32mCL, 0 }, 200226633Sdim { X86::SAR32ri, X86::SAR32mi, 0 }, 201226633Sdim { X86::SAR64r1, X86::SAR64m1, 0 }, 202226633Sdim { X86::SAR64rCL, X86::SAR64mCL, 0 }, 203226633Sdim { X86::SAR64ri, X86::SAR64mi, 0 }, 204226633Sdim { X86::SAR8r1, X86::SAR8m1, 0 }, 205226633Sdim { X86::SAR8rCL, X86::SAR8mCL, 0 }, 206226633Sdim { X86::SAR8ri, X86::SAR8mi, 0 }, 207226633Sdim { X86::SBB32ri, X86::SBB32mi, 0 }, 208226633Sdim { X86::SBB32ri8, X86::SBB32mi8, 0 }, 209226633Sdim { X86::SBB32rr, X86::SBB32mr, 0 }, 210226633Sdim { X86::SBB64ri32, X86::SBB64mi32, 0 }, 211226633Sdim { X86::SBB64ri8, X86::SBB64mi8, 0 }, 212226633Sdim { X86::SBB64rr, X86::SBB64mr, 0 }, 213226633Sdim { X86::SHL16rCL, X86::SHL16mCL, 0 }, 214226633Sdim { X86::SHL16ri, X86::SHL16mi, 0 }, 215226633Sdim { X86::SHL32rCL, X86::SHL32mCL, 0 }, 216226633Sdim { X86::SHL32ri, X86::SHL32mi, 0 }, 217226633Sdim { X86::SHL64rCL, X86::SHL64mCL, 0 }, 218226633Sdim { X86::SHL64ri, X86::SHL64mi, 0 }, 219226633Sdim { X86::SHL8rCL, X86::SHL8mCL, 0 }, 220226633Sdim { X86::SHL8ri, X86::SHL8mi, 0 }, 221226633Sdim { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 222226633Sdim { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 223226633Sdim { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 224226633Sdim { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 225226633Sdim { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 226226633Sdim { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 227226633Sdim { X86::SHR16r1, X86::SHR16m1, 0 }, 228226633Sdim { X86::SHR16rCL, X86::SHR16mCL, 0 }, 229226633Sdim { X86::SHR16ri, X86::SHR16mi, 0 }, 230226633Sdim { X86::SHR32r1, X86::SHR32m1, 0 }, 231226633Sdim { X86::SHR32rCL, X86::SHR32mCL, 0 }, 232226633Sdim { X86::SHR32ri, X86::SHR32mi, 0 }, 233226633Sdim { X86::SHR64r1, X86::SHR64m1, 0 }, 234226633Sdim { X86::SHR64rCL, X86::SHR64mCL, 0 }, 235226633Sdim { X86::SHR64ri, X86::SHR64mi, 0 }, 236226633Sdim { X86::SHR8r1, X86::SHR8m1, 0 }, 237226633Sdim { X86::SHR8rCL, X86::SHR8mCL, 0 }, 238226633Sdim { X86::SHR8ri, X86::SHR8mi, 0 }, 239226633Sdim { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 240226633Sdim { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 241226633Sdim { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 242226633Sdim { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 243226633Sdim { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 244226633Sdim { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 245226633Sdim { X86::SUB16ri, X86::SUB16mi, 0 }, 246226633Sdim { X86::SUB16ri8, X86::SUB16mi8, 0 }, 247226633Sdim { X86::SUB16rr, X86::SUB16mr, 0 }, 248226633Sdim { X86::SUB32ri, X86::SUB32mi, 0 }, 249226633Sdim { X86::SUB32ri8, X86::SUB32mi8, 0 }, 250226633Sdim { X86::SUB32rr, X86::SUB32mr, 0 }, 251226633Sdim { X86::SUB64ri32, X86::SUB64mi32, 0 }, 252226633Sdim { X86::SUB64ri8, X86::SUB64mi8, 0 }, 253226633Sdim { X86::SUB64rr, X86::SUB64mr, 0 }, 254226633Sdim { X86::SUB8ri, X86::SUB8mi, 0 }, 255226633Sdim { X86::SUB8rr, X86::SUB8mr, 0 }, 256226633Sdim { X86::XOR16ri, X86::XOR16mi, 0 }, 257226633Sdim { X86::XOR16ri8, X86::XOR16mi8, 0 }, 258226633Sdim { X86::XOR16rr, X86::XOR16mr, 0 }, 259226633Sdim { X86::XOR32ri, X86::XOR32mi, 0 }, 260226633Sdim { X86::XOR32ri8, X86::XOR32mi8, 0 }, 261226633Sdim { X86::XOR32rr, X86::XOR32mr, 0 }, 262226633Sdim { X86::XOR64ri32, X86::XOR64mi32, 0 }, 263226633Sdim { X86::XOR64ri8, X86::XOR64mi8, 0 }, 264226633Sdim { X86::XOR64rr, X86::XOR64mr, 0 }, 265226633Sdim { X86::XOR8ri, X86::XOR8mi, 0 }, 266226633Sdim { X86::XOR8rr, X86::XOR8mr, 0 } 267193323Sed }; 268193323Sed 269193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 270234353Sdim unsigned RegOp = OpTbl2Addr[i].RegOp; 271234353Sdim unsigned MemOp = OpTbl2Addr[i].MemOp; 272234353Sdim unsigned Flags = OpTbl2Addr[i].Flags; 273226633Sdim AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 274226633Sdim RegOp, MemOp, 275226633Sdim // Index 0, folded load and store, no alignment requirement. 276226633Sdim Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 277193323Sed } 278193323Sed 279234353Sdim static const X86OpTblEntry OpTbl0[] = { 280226633Sdim { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 281226633Sdim { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 282226633Sdim { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 283226633Sdim { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 284226633Sdim { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 285226633Sdim { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 286226633Sdim { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 287226633Sdim { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 288226633Sdim { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 289226633Sdim { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 290226633Sdim { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 291226633Sdim { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 292226633Sdim { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 293226633Sdim { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 294226633Sdim { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 295226633Sdim { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 296226633Sdim { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 297226633Sdim { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 298226633Sdim { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 299226633Sdim { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 300226633Sdim { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 301226633Sdim { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 302226633Sdim { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 303226633Sdim { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304226633Sdim { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305226633Sdim { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306226633Sdim { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307226633Sdim { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308226633Sdim { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309226633Sdim { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310226633Sdim { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311226633Sdim { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312226633Sdim { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313226633Sdim { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314226633Sdim { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315226633Sdim { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316226633Sdim { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317226633Sdim { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318226633Sdim { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319226633Sdim { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320226633Sdim { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321226633Sdim { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322226633Sdim { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323226633Sdim { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324226633Sdim { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325226633Sdim { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326226633Sdim { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327226633Sdim { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328226633Sdim { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329226633Sdim { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330226633Sdim { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331226633Sdim { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332226633Sdim { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333226633Sdim { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334226633Sdim { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335226633Sdim { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 336226633Sdim { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 337226633Sdim { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 338226633Sdim { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 339226633Sdim { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 340226633Sdim { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 341226633Sdim { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 342226633Sdim { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 343226633Sdim { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 344226633Sdim { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 345226633Sdim { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 346226633Sdim { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 347226633Sdim { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 348226633Sdim { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 349226633Sdim { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 350226633Sdim { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 351226633Sdim { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 352226633Sdim { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 353226633Sdim { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 354226633Sdim { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 355226633Sdim { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 356226633Sdim { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 357226633Sdim // AVX 128-bit versions of foldable instructions 358226633Sdim { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 359226633Sdim { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 360226633Sdim { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 361234353Sdim { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362226633Sdim { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363226633Sdim { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364226633Sdim { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365226633Sdim { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 366226633Sdim { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 367226633Sdim { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 368226633Sdim { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 369226633Sdim { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 370226633Sdim { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 371226633Sdim // AVX 256-bit foldable instructions 372234353Sdim { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 373226633Sdim { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374226633Sdim { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375226633Sdim { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376226633Sdim { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 377226633Sdim { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE } 378193323Sed }; 379193323Sed 380193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 381234353Sdim unsigned RegOp = OpTbl0[i].RegOp; 382234353Sdim unsigned MemOp = OpTbl0[i].MemOp; 383234353Sdim unsigned Flags = OpTbl0[i].Flags; 384226633Sdim AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 385226633Sdim RegOp, MemOp, TB_INDEX_0 | Flags); 386193323Sed } 387193323Sed 388234353Sdim static const X86OpTblEntry OpTbl1[] = { 389226633Sdim { X86::CMP16rr, X86::CMP16rm, 0 }, 390226633Sdim { X86::CMP32rr, X86::CMP32rm, 0 }, 391226633Sdim { X86::CMP64rr, X86::CMP64rm, 0 }, 392226633Sdim { X86::CMP8rr, X86::CMP8rm, 0 }, 393226633Sdim { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 394226633Sdim { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 395226633Sdim { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 396226633Sdim { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 397226633Sdim { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 398226633Sdim { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 399226633Sdim { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 400226633Sdim { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 401226633Sdim { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 402226633Sdim { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 403226633Sdim { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE }, 404226633Sdim { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE }, 405226633Sdim { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 406226633Sdim { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 407226633Sdim { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 408226633Sdim { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 409226633Sdim { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 410226633Sdim { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 411226633Sdim { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 412226633Sdim { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 413226633Sdim { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 414226633Sdim { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 415239462Sdim { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 416239462Sdim { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 417226633Sdim { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 418226633Sdim { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 419226633Sdim { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 420226633Sdim { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 421226633Sdim { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 422226633Sdim { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 423226633Sdim { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 424226633Sdim { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 425226633Sdim { X86::MOV16rr, X86::MOV16rm, 0 }, 426226633Sdim { X86::MOV32rr, X86::MOV32rm, 0 }, 427226633Sdim { X86::MOV64rr, X86::MOV64rm, 0 }, 428226633Sdim { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 429226633Sdim { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 430226633Sdim { X86::MOV8rr, X86::MOV8rm, 0 }, 431226633Sdim { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 432226633Sdim { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 433226633Sdim { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 434226633Sdim { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 435226633Sdim { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 436226633Sdim { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 437226633Sdim { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 438226633Sdim { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 439226633Sdim { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 440226633Sdim { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 441226633Sdim { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 442226633Sdim { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 443226633Sdim { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 444226633Sdim { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 445226633Sdim { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 446226633Sdim { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 447226633Sdim { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 448226633Sdim { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449226633Sdim { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450226633Sdim { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451226633Sdim { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452226633Sdim { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453226633Sdim { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454226633Sdim { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 455226633Sdim { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 456226633Sdim { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 457234353Sdim { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 458234353Sdim { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 459234353Sdim { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 460226633Sdim { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 461226633Sdim { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 462226633Sdim { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 463226633Sdim { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 464226633Sdim { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 465226633Sdim { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 466226633Sdim { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 467226633Sdim { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 468226633Sdim { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 469226633Sdim { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 470226633Sdim { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 }, 471226633Sdim { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 472226633Sdim { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 }, 473226633Sdim { X86::SQRTSDr, X86::SQRTSDm, 0 }, 474226633Sdim { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 475226633Sdim { X86::SQRTSSr, X86::SQRTSSm, 0 }, 476226633Sdim { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 477226633Sdim { X86::TEST16rr, X86::TEST16rm, 0 }, 478226633Sdim { X86::TEST32rr, X86::TEST32rm, 0 }, 479226633Sdim { X86::TEST64rr, X86::TEST64rm, 0 }, 480226633Sdim { X86::TEST8rr, X86::TEST8rm, 0 }, 481193323Sed // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 482226633Sdim { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 483226633Sdim { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 484226633Sdim // AVX 128-bit versions of foldable instructions 485226633Sdim { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 486226633Sdim { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 487226633Sdim { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 488226633Sdim { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 489239462Sdim { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 490239462Sdim { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 491239462Sdim { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 492239462Sdim { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 493239462Sdim { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 494239462Sdim { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 495239462Sdim { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 496239462Sdim { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 497239462Sdim { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 498239462Sdim { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 499239462Sdim { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 500239462Sdim { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 501226633Sdim { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE }, 502226633Sdim { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE }, 503226633Sdim { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 504226633Sdim { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 505226633Sdim { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 506226633Sdim { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 507226633Sdim { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 508226633Sdim { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 509226633Sdim { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 510226633Sdim { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 511226633Sdim { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 512226633Sdim { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 513226633Sdim { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 }, 514226633Sdim { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 515226633Sdim { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 }, 516226633Sdim { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 517226633Sdim { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 518234353Sdim { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 }, 519234353Sdim { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 }, 520234353Sdim { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 }, 521234353Sdim { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 }, 522234353Sdim { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 }, 523226633Sdim { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 }, 524226633Sdim { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 }, 525226633Sdim { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 }, 526226633Sdim { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 }, 527226633Sdim { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 }, 528226633Sdim { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 }, 529226633Sdim { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 }, 530226633Sdim { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 }, 531226633Sdim { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 }, 532226633Sdim { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 }, 533226633Sdim { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 }, 534226633Sdim { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 535226633Sdim { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 536239462Sdim { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 537239462Sdim 538226633Sdim // AVX 256-bit foldable instructions 539226633Sdim { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 540226633Sdim { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 541234353Sdim { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 542226633Sdim { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 543234353Sdim { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 544234353Sdim { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 }, 545234353Sdim { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 }, 546239462Sdim 547234353Sdim // AVX2 foldable instructions 548234353Sdim { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 }, 549234353Sdim { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 }, 550234353Sdim { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 }, 551234353Sdim { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 }, 552234353Sdim { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 }, 553234353Sdim { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 }, 554234353Sdim { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 }, 555234353Sdim { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 }, 556234353Sdim { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 }, 557234353Sdim { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 }, 558234353Sdim { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 }, 559234353Sdim { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 }, 560234353Sdim { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 }, 561234353Sdim { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 }, 562239462Sdim { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 563239462Sdim { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 564243830Sdim 565243830Sdim // BMI/BMI2 foldable instructions 566243830Sdim { X86::RORX32ri, X86::RORX32mi, 0 }, 567243830Sdim { X86::RORX64ri, X86::RORX64mi, 0 }, 568243830Sdim { X86::SARX32rr, X86::SARX32rm, 0 }, 569243830Sdim { X86::SARX64rr, X86::SARX64rm, 0 }, 570243830Sdim { X86::SHRX32rr, X86::SHRX32rm, 0 }, 571243830Sdim { X86::SHRX64rr, X86::SHRX64rm, 0 }, 572243830Sdim { X86::SHLX32rr, X86::SHLX32rm, 0 }, 573243830Sdim { X86::SHLX64rr, X86::SHLX64rm, 0 }, 574193323Sed }; 575193323Sed 576193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 577234353Sdim unsigned RegOp = OpTbl1[i].RegOp; 578234353Sdim unsigned MemOp = OpTbl1[i].MemOp; 579234353Sdim unsigned Flags = OpTbl1[i].Flags; 580226633Sdim AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 581226633Sdim RegOp, MemOp, 582226633Sdim // Index 1, folded load 583226633Sdim Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 584193323Sed } 585193323Sed 586234353Sdim static const X86OpTblEntry OpTbl2[] = { 587226633Sdim { X86::ADC32rr, X86::ADC32rm, 0 }, 588226633Sdim { X86::ADC64rr, X86::ADC64rm, 0 }, 589226633Sdim { X86::ADD16rr, X86::ADD16rm, 0 }, 590226633Sdim { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 591226633Sdim { X86::ADD32rr, X86::ADD32rm, 0 }, 592226633Sdim { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 593226633Sdim { X86::ADD64rr, X86::ADD64rm, 0 }, 594226633Sdim { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 595226633Sdim { X86::ADD8rr, X86::ADD8rm, 0 }, 596226633Sdim { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 597226633Sdim { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 598226633Sdim { X86::ADDSDrr, X86::ADDSDrm, 0 }, 599226633Sdim { X86::ADDSSrr, X86::ADDSSrm, 0 }, 600226633Sdim { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 601226633Sdim { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 602226633Sdim { X86::AND16rr, X86::AND16rm, 0 }, 603226633Sdim { X86::AND32rr, X86::AND32rm, 0 }, 604226633Sdim { X86::AND64rr, X86::AND64rm, 0 }, 605226633Sdim { X86::AND8rr, X86::AND8rm, 0 }, 606226633Sdim { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 607226633Sdim { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 608226633Sdim { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 609226633Sdim { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 610234353Sdim { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 611234353Sdim { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 612234353Sdim { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 613234353Sdim { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 614226633Sdim { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 615226633Sdim { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 616226633Sdim { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 617226633Sdim { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 618226633Sdim { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 619226633Sdim { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 620226633Sdim { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 621226633Sdim { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 622226633Sdim { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 623226633Sdim { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 624226633Sdim { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 625226633Sdim { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 626226633Sdim { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 627226633Sdim { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 628226633Sdim { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 629226633Sdim { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 630226633Sdim { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 631226633Sdim { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 632226633Sdim { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 633226633Sdim { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 634226633Sdim { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 635226633Sdim { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 636226633Sdim { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 637226633Sdim { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 638226633Sdim { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 639226633Sdim { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 640226633Sdim { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 641226633Sdim { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 642226633Sdim { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 643226633Sdim { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 644226633Sdim { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 645226633Sdim { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 646226633Sdim { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 647226633Sdim { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 648226633Sdim { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 649226633Sdim { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 650226633Sdim { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 651226633Sdim { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 652226633Sdim { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 653226633Sdim { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 654226633Sdim { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 655226633Sdim { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 656226633Sdim { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 657226633Sdim { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 658226633Sdim { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 659226633Sdim { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 660226633Sdim { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 661226633Sdim { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 662226633Sdim { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 663226633Sdim { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 664226633Sdim { X86::CMPSDrr, X86::CMPSDrm, 0 }, 665226633Sdim { X86::CMPSSrr, X86::CMPSSrm, 0 }, 666226633Sdim { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 667226633Sdim { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 668226633Sdim { X86::DIVSDrr, X86::DIVSDrm, 0 }, 669226633Sdim { X86::DIVSSrr, X86::DIVSSrm, 0 }, 670226633Sdim { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 671226633Sdim { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 672226633Sdim { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 673226633Sdim { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 674226633Sdim { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 675226633Sdim { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 676226633Sdim { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 677226633Sdim { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 678226633Sdim { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 679226633Sdim { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 680226633Sdim { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 681226633Sdim { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 682226633Sdim { X86::IMUL16rr, X86::IMUL16rm, 0 }, 683226633Sdim { X86::IMUL32rr, X86::IMUL32rm, 0 }, 684226633Sdim { X86::IMUL64rr, X86::IMUL64rm, 0 }, 685226633Sdim { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 686226633Sdim { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 687239462Sdim { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 688239462Sdim { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 689239462Sdim { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 690239462Sdim { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 691239462Sdim { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 692239462Sdim { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 693226633Sdim { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 694226633Sdim { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 }, 695226633Sdim { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 696226633Sdim { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 }, 697226633Sdim { X86::MAXSDrr, X86::MAXSDrm, 0 }, 698226633Sdim { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 699226633Sdim { X86::MAXSSrr, X86::MAXSSrm, 0 }, 700226633Sdim { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 701226633Sdim { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 702226633Sdim { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 }, 703226633Sdim { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 704226633Sdim { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 }, 705226633Sdim { X86::MINSDrr, X86::MINSDrm, 0 }, 706226633Sdim { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 707226633Sdim { X86::MINSSrr, X86::MINSSrm, 0 }, 708226633Sdim { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 709234353Sdim { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 710226633Sdim { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 711226633Sdim { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 712226633Sdim { X86::MULSDrr, X86::MULSDrm, 0 }, 713226633Sdim { X86::MULSSrr, X86::MULSSrm, 0 }, 714226633Sdim { X86::OR16rr, X86::OR16rm, 0 }, 715226633Sdim { X86::OR32rr, X86::OR32rm, 0 }, 716226633Sdim { X86::OR64rr, X86::OR64rm, 0 }, 717226633Sdim { X86::OR8rr, X86::OR8rm, 0 }, 718226633Sdim { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 719226633Sdim { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 720226633Sdim { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 721226633Sdim { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 722234353Sdim { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 723226633Sdim { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 724226633Sdim { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 725226633Sdim { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 726226633Sdim { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 727226633Sdim { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 728226633Sdim { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 729234353Sdim { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 730234353Sdim { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 731226633Sdim { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 732234353Sdim { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 733226633Sdim { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 734226633Sdim { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 735226633Sdim { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 736226633Sdim { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 737234353Sdim { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 738226633Sdim { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 739226633Sdim { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 740234353Sdim { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 741226633Sdim { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 742226633Sdim { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 743226633Sdim { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 744234353Sdim { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 745226633Sdim { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 746234353Sdim { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 747234353Sdim { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 748234353Sdim { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 749234353Sdim { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 750234353Sdim { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 751234353Sdim { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 752226633Sdim { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 753234353Sdim { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 754226633Sdim { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 755226633Sdim { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 756226633Sdim { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 757226633Sdim { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 758226633Sdim { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 759226633Sdim { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 760234353Sdim { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 761226633Sdim { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 762226633Sdim { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 763226633Sdim { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 764226633Sdim { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 765226633Sdim { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 766226633Sdim { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 767226633Sdim { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 768234353Sdim { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 769234353Sdim { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 770234353Sdim { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 771234353Sdim { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 772226633Sdim { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 773226633Sdim { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 774226633Sdim { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 775226633Sdim { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 776226633Sdim { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 777226633Sdim { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 778226633Sdim { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 779226633Sdim { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 780226633Sdim { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 781226633Sdim { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 782226633Sdim { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 783226633Sdim { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 784226633Sdim { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 785226633Sdim { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 786226633Sdim { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 787226633Sdim { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 788226633Sdim { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 789226633Sdim { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 790226633Sdim { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 791226633Sdim { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 792226633Sdim { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 793226633Sdim { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 794226633Sdim { X86::SBB32rr, X86::SBB32rm, 0 }, 795226633Sdim { X86::SBB64rr, X86::SBB64rm, 0 }, 796226633Sdim { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 797226633Sdim { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 798226633Sdim { X86::SUB16rr, X86::SUB16rm, 0 }, 799226633Sdim { X86::SUB32rr, X86::SUB32rm, 0 }, 800226633Sdim { X86::SUB64rr, X86::SUB64rm, 0 }, 801226633Sdim { X86::SUB8rr, X86::SUB8rm, 0 }, 802226633Sdim { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 803226633Sdim { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 804226633Sdim { X86::SUBSDrr, X86::SUBSDrm, 0 }, 805226633Sdim { X86::SUBSSrr, X86::SUBSSrm, 0 }, 806193323Sed // FIXME: TEST*rr -> swapped operand of TEST*mr. 807226633Sdim { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 808226633Sdim { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 809226633Sdim { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 810226633Sdim { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 811226633Sdim { X86::XOR16rr, X86::XOR16rm, 0 }, 812226633Sdim { X86::XOR32rr, X86::XOR32rm, 0 }, 813226633Sdim { X86::XOR64rr, X86::XOR64rm, 0 }, 814226633Sdim { X86::XOR8rr, X86::XOR8rm, 0 }, 815226633Sdim { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 816226633Sdim { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 817226633Sdim // AVX 128-bit versions of foldable instructions 818226633Sdim { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 819226633Sdim { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 820226633Sdim { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 821226633Sdim { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 822226633Sdim { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 823226633Sdim { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 824226633Sdim { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 825226633Sdim { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 826226633Sdim { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 827226633Sdim { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 828226633Sdim { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 829226633Sdim { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 830239462Sdim { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, TB_ALIGN_16 }, 831226633Sdim { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 }, 832226633Sdim { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 833226633Sdim { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 834226633Sdim { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 835226633Sdim { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 }, 836226633Sdim { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 }, 837226633Sdim { X86::VADDSDrr, X86::VADDSDrm, 0 }, 838226633Sdim { X86::VADDSSrr, X86::VADDSSrm, 0 }, 839226633Sdim { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 }, 840226633Sdim { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 }, 841226633Sdim { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 }, 842226633Sdim { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 }, 843226633Sdim { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 }, 844226633Sdim { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 }, 845234353Sdim { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 }, 846234353Sdim { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 }, 847234353Sdim { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 }, 848234353Sdim { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 }, 849226633Sdim { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 }, 850226633Sdim { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 }, 851226633Sdim { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 852226633Sdim { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 853226633Sdim { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 }, 854226633Sdim { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 }, 855226633Sdim { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 856226633Sdim { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 857226633Sdim { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 858226633Sdim { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 859226633Sdim { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 860226633Sdim { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 861226633Sdim { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 862226633Sdim { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 863226633Sdim { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 864226633Sdim { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 865226633Sdim { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 }, 866226633Sdim { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 }, 867226633Sdim { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 }, 868226633Sdim { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 }, 869226633Sdim { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 870226633Sdim { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 871226633Sdim { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 }, 872226633Sdim { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 }, 873226633Sdim { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 }, 874226633Sdim { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 }, 875226633Sdim { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 876226633Sdim { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 }, 877226633Sdim { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 878226633Sdim { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 }, 879226633Sdim { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 }, 880226633Sdim { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 }, 881226633Sdim { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 }, 882226633Sdim { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 }, 883226633Sdim { X86::VMINSDrr, X86::VMINSDrm, 0 }, 884226633Sdim { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 }, 885226633Sdim { X86::VMINSSrr, X86::VMINSSrm, 0 }, 886226633Sdim { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 }, 887234353Sdim { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 }, 888226633Sdim { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 }, 889226633Sdim { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 }, 890226633Sdim { X86::VMULSDrr, X86::VMULSDrm, 0 }, 891226633Sdim { X86::VMULSSrr, X86::VMULSSrm, 0 }, 892226633Sdim { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 }, 893226633Sdim { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 }, 894226633Sdim { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 }, 895226633Sdim { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 }, 896234353Sdim { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 }, 897226633Sdim { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 }, 898226633Sdim { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 }, 899226633Sdim { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 }, 900226633Sdim { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 }, 901226633Sdim { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 }, 902226633Sdim { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 }, 903234353Sdim { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 }, 904234353Sdim { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 }, 905226633Sdim { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 }, 906234353Sdim { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 }, 907226633Sdim { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 }, 908226633Sdim { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 }, 909234353Sdim { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 }, 910234353Sdim { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 }, 911234353Sdim { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 }, 912226633Sdim { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 }, 913226633Sdim { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 }, 914234353Sdim { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 }, 915226633Sdim { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 }, 916226633Sdim { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 }, 917226633Sdim { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 }, 918234353Sdim { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 }, 919226633Sdim { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 }, 920234353Sdim { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 }, 921234353Sdim { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 }, 922234353Sdim { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 }, 923234353Sdim { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 }, 924234353Sdim { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 }, 925234353Sdim { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 }, 926234353Sdim { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 }, 927234353Sdim { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 }, 928226633Sdim { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 }, 929234353Sdim { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 }, 930226633Sdim { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 }, 931226633Sdim { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 }, 932226633Sdim { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 }, 933226633Sdim { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 }, 934226633Sdim { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 }, 935226633Sdim { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 }, 936234353Sdim { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 }, 937226633Sdim { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 }, 938226633Sdim { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 }, 939226633Sdim { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 }, 940226633Sdim { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 }, 941226633Sdim { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 }, 942226633Sdim { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 }, 943226633Sdim { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 }, 944234353Sdim { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 }, 945234353Sdim { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 }, 946234353Sdim { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 }, 947234353Sdim { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 }, 948226633Sdim { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 }, 949226633Sdim { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 }, 950226633Sdim { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 }, 951226633Sdim { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 }, 952226633Sdim { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 }, 953226633Sdim { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 }, 954226633Sdim { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 }, 955226633Sdim { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 }, 956226633Sdim { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 }, 957226633Sdim { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 }, 958226633Sdim { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 }, 959226633Sdim { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 }, 960226633Sdim { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 }, 961226633Sdim { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 }, 962226633Sdim { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 }, 963226633Sdim { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 }, 964226633Sdim { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 }, 965226633Sdim { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 }, 966226633Sdim { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 }, 967226633Sdim { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 }, 968226633Sdim { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 }, 969226633Sdim { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 }, 970226633Sdim { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 }, 971226633Sdim { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 }, 972226633Sdim { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 }, 973226633Sdim { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 }, 974226633Sdim { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 975226633Sdim { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 976226633Sdim { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 }, 977226633Sdim { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 }, 978226633Sdim { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 }, 979226633Sdim { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 }, 980226633Sdim { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 }, 981234353Sdim { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 }, 982234353Sdim // AVX 256-bit foldable instructions 983234353Sdim { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 }, 984234353Sdim { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 }, 985234353Sdim { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 }, 986234353Sdim { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 }, 987234353Sdim { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 }, 988234353Sdim { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 }, 989234353Sdim { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 }, 990234353Sdim { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 }, 991234353Sdim { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 }, 992234353Sdim { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 }, 993234353Sdim { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 }, 994234353Sdim { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 }, 995234353Sdim { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 }, 996234353Sdim { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 }, 997234353Sdim { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 }, 998234353Sdim { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 }, 999234353Sdim { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 }, 1000234353Sdim { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 }, 1001234353Sdim { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 }, 1002234353Sdim { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 }, 1003234353Sdim { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 }, 1004234353Sdim { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 }, 1005234353Sdim { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 }, 1006234353Sdim { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 }, 1007234353Sdim { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 }, 1008234353Sdim { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 }, 1009234353Sdim { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 }, 1010234353Sdim { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 }, 1011234353Sdim { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 }, 1012234353Sdim { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 }, 1013234353Sdim { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 }, 1014234353Sdim { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 }, 1015234353Sdim { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 }, 1016234353Sdim { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 }, 1017234353Sdim { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 }, 1018234353Sdim { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 }, 1019234353Sdim { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 }, 1020234353Sdim { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 }, 1021234353Sdim { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 }, 1022234353Sdim { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 }, 1023234353Sdim { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 }, 1024234353Sdim { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 }, 1025234353Sdim { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 }, 1026234353Sdim { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 }, 1027234353Sdim { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 }, 1028234353Sdim { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 }, 1029234353Sdim // AVX2 foldable instructions 1030234353Sdim { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 }, 1031234353Sdim { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 }, 1032234353Sdim { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 }, 1033234353Sdim { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 }, 1034234353Sdim { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 }, 1035234353Sdim { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 }, 1036234353Sdim { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 }, 1037234353Sdim { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 }, 1038234353Sdim { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 }, 1039234353Sdim { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 }, 1040234353Sdim { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 }, 1041234353Sdim { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 }, 1042234353Sdim { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 }, 1043234353Sdim { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 }, 1044234353Sdim { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 }, 1045234353Sdim { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 }, 1046234353Sdim { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 }, 1047234353Sdim { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 }, 1048234353Sdim { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 }, 1049234353Sdim { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 }, 1050234353Sdim { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 }, 1051234353Sdim { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 }, 1052234353Sdim { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 }, 1053234353Sdim { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 }, 1054234353Sdim { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 }, 1055234353Sdim { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 }, 1056234353Sdim { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 }, 1057234353Sdim { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 }, 1058234353Sdim { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 }, 1059234353Sdim { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 }, 1060234353Sdim { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 }, 1061234982Sdim { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 }, 1062234353Sdim { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 }, 1063234982Sdim { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 }, 1064234353Sdim { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 }, 1065234353Sdim { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 }, 1066234353Sdim { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 }, 1067234353Sdim { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 }, 1068234353Sdim { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 }, 1069234353Sdim { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 }, 1070234353Sdim { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 }, 1071234353Sdim { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 }, 1072234353Sdim { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 }, 1073234353Sdim { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 }, 1074234353Sdim { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 }, 1075234353Sdim { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 }, 1076234353Sdim { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 }, 1077234353Sdim { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 }, 1078234353Sdim { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 }, 1079234353Sdim { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 }, 1080234353Sdim { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 }, 1081234353Sdim { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 }, 1082234353Sdim { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 }, 1083234353Sdim { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 }, 1084234353Sdim { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 }, 1085234353Sdim { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 }, 1086234353Sdim { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 }, 1087234353Sdim { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 }, 1088234353Sdim { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 }, 1089234353Sdim { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 }, 1090234353Sdim { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 }, 1091234353Sdim { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 }, 1092234353Sdim { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 }, 1093234353Sdim { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 }, 1094234353Sdim { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 }, 1095234353Sdim { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 }, 1096234353Sdim { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 }, 1097234353Sdim { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 }, 1098234353Sdim { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 }, 1099234353Sdim { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 }, 1100234353Sdim { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 }, 1101234353Sdim { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 }, 1102234353Sdim { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 }, 1103234353Sdim { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 }, 1104234353Sdim { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 }, 1105234353Sdim { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 }, 1106234353Sdim { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 }, 1107234353Sdim { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 }, 1108234353Sdim { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 }, 1109234353Sdim { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 }, 1110234353Sdim { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 }, 1111234353Sdim { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 }, 1112234353Sdim { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 }, 1113234353Sdim { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 }, 1114234353Sdim { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 }, 1115234353Sdim { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 }, 1116234353Sdim { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 }, 1117234353Sdim { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 }, 1118234353Sdim { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 }, 1119234353Sdim { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 }, 1120234353Sdim { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 }, 1121234353Sdim { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 }, 1122226633Sdim // FIXME: add AVX 256-bit foldable instructions 1123243830Sdim 1124243830Sdim // FMA4 foldable patterns 1125243830Sdim { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 }, 1126243830Sdim { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 }, 1127243830Sdim { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1128243830Sdim { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1129243830Sdim { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1130243830Sdim { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1131243830Sdim { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 }, 1132243830Sdim { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 }, 1133243830Sdim { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1134243830Sdim { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1135243830Sdim { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1136243830Sdim { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1137243830Sdim { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 }, 1138243830Sdim { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 }, 1139243830Sdim { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1140243830Sdim { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1141243830Sdim { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1142243830Sdim { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1143243830Sdim { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 }, 1144243830Sdim { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 }, 1145243830Sdim { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1146243830Sdim { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1147243830Sdim { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1148243830Sdim { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1149243830Sdim { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1150243830Sdim { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1151243830Sdim { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1152243830Sdim { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1153243830Sdim { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1154243830Sdim { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1155243830Sdim { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1156243830Sdim { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1157243830Sdim 1158243830Sdim // BMI/BMI2 foldable instructions 1159243830Sdim { X86::MULX32rr, X86::MULX32rm, 0 }, 1160243830Sdim { X86::MULX64rr, X86::MULX64rm, 0 }, 1161193323Sed }; 1162193323Sed 1163193323Sed for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1164234353Sdim unsigned RegOp = OpTbl2[i].RegOp; 1165234353Sdim unsigned MemOp = OpTbl2[i].MemOp; 1166234353Sdim unsigned Flags = OpTbl2[i].Flags; 1167226633Sdim AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1168226633Sdim RegOp, MemOp, 1169226633Sdim // Index 2, folded load 1170226633Sdim Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1171226633Sdim } 1172239462Sdim 1173239462Sdim static const X86OpTblEntry OpTbl3[] = { 1174239462Sdim // FMA foldable instructions 1175239462Sdim { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 }, 1176239462Sdim { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 }, 1177239462Sdim { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 }, 1178239462Sdim { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 }, 1179239462Sdim { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 }, 1180239462Sdim { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 }, 1181239462Sdim { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 }, 1182239462Sdim { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 }, 1183239462Sdim 1184239462Sdim { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 }, 1185239462Sdim { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 }, 1186239462Sdim { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 }, 1187239462Sdim { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 }, 1188239462Sdim { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 }, 1189239462Sdim { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 }, 1190239462Sdim { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 }, 1191239462Sdim { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 }, 1192239462Sdim { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 }, 1193239462Sdim { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 }, 1194239462Sdim { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 }, 1195239462Sdim { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 }, 1196239462Sdim 1197239462Sdim { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 }, 1198239462Sdim { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 }, 1199239462Sdim { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 }, 1200239462Sdim { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 }, 1201239462Sdim { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 }, 1202239462Sdim { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 }, 1203239462Sdim { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 }, 1204239462Sdim { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 }, 1205239462Sdim 1206239462Sdim { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 }, 1207239462Sdim { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 }, 1208239462Sdim { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 }, 1209239462Sdim { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 }, 1210239462Sdim { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 }, 1211239462Sdim { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 }, 1212239462Sdim { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 }, 1213239462Sdim { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 }, 1214239462Sdim { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 }, 1215239462Sdim { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 }, 1216239462Sdim { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 }, 1217239462Sdim { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 }, 1218239462Sdim 1219239462Sdim { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 }, 1220239462Sdim { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 }, 1221239462Sdim { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 }, 1222239462Sdim { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 }, 1223239462Sdim { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 }, 1224239462Sdim { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 }, 1225239462Sdim { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 }, 1226239462Sdim { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 }, 1227239462Sdim 1228239462Sdim { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 }, 1229239462Sdim { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 }, 1230239462Sdim { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 }, 1231239462Sdim { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 }, 1232239462Sdim { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 }, 1233239462Sdim { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 }, 1234239462Sdim { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 }, 1235239462Sdim { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 }, 1236239462Sdim { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 }, 1237239462Sdim { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 }, 1238239462Sdim { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 }, 1239239462Sdim { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 }, 1240239462Sdim 1241239462Sdim { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 }, 1242239462Sdim { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 }, 1243239462Sdim { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 }, 1244239462Sdim { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 }, 1245239462Sdim { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 }, 1246239462Sdim { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 }, 1247239462Sdim { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 }, 1248239462Sdim { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 }, 1249239462Sdim 1250239462Sdim { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 }, 1251239462Sdim { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 }, 1252239462Sdim { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 }, 1253239462Sdim { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 }, 1254239462Sdim { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 }, 1255239462Sdim { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 }, 1256239462Sdim { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 }, 1257239462Sdim { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 }, 1258239462Sdim { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 }, 1259239462Sdim { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 }, 1260239462Sdim { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 }, 1261239462Sdim { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 }, 1262239462Sdim 1263239462Sdim { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 }, 1264239462Sdim { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 }, 1265239462Sdim { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 }, 1266239462Sdim { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 }, 1267239462Sdim { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 }, 1268239462Sdim { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 }, 1269239462Sdim { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 }, 1270239462Sdim { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 }, 1271239462Sdim { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 }, 1272239462Sdim { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 }, 1273239462Sdim { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 }, 1274239462Sdim { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 }, 1275239462Sdim 1276239462Sdim { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 }, 1277239462Sdim { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 }, 1278239462Sdim { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 }, 1279239462Sdim { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 }, 1280239462Sdim { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 }, 1281239462Sdim { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 }, 1282239462Sdim { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 }, 1283239462Sdim { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 }, 1284239462Sdim { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 }, 1285239462Sdim { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 }, 1286239462Sdim { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 }, 1287239462Sdim { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 }, 1288243830Sdim 1289243830Sdim // FMA4 foldable patterns 1290243830Sdim { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 }, 1291243830Sdim { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 }, 1292243830Sdim { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1293243830Sdim { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1294243830Sdim { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1295243830Sdim { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1296243830Sdim { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 }, 1297243830Sdim { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 }, 1298243830Sdim { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1299243830Sdim { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1300243830Sdim { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1301243830Sdim { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1302243830Sdim { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 }, 1303243830Sdim { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 }, 1304243830Sdim { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1305243830Sdim { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1306243830Sdim { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1307243830Sdim { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1308243830Sdim { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 }, 1309243830Sdim { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 }, 1310243830Sdim { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1311243830Sdim { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1312243830Sdim { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1313243830Sdim { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1314243830Sdim { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1315243830Sdim { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1316243830Sdim { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1317243830Sdim { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1318243830Sdim { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1319243830Sdim { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1320243830Sdim { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1321243830Sdim { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1322239462Sdim }; 1323239462Sdim 1324239462Sdim for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1325239462Sdim unsigned RegOp = OpTbl3[i].RegOp; 1326239462Sdim unsigned MemOp = OpTbl3[i].MemOp; 1327239462Sdim unsigned Flags = OpTbl3[i].Flags; 1328239462Sdim AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1329239462Sdim RegOp, MemOp, 1330239462Sdim // Index 3, folded load 1331239462Sdim Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1332239462Sdim } 1333239462Sdim 1334226633Sdim} 1335218893Sdim 1336226633Sdimvoid 1337226633SdimX86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1338226633Sdim MemOp2RegOpTableType &M2RTable, 1339226633Sdim unsigned RegOp, unsigned MemOp, unsigned Flags) { 1340226633Sdim if ((Flags & TB_NO_FORWARD) == 0) { 1341226633Sdim assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1342226633Sdim R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1343226633Sdim } 1344226633Sdim if ((Flags & TB_NO_REVERSE) == 0) { 1345226633Sdim assert(!M2RTable.count(MemOp) && 1346218893Sdim "Duplicated entries in unfolding maps?"); 1347226633Sdim M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1348226633Sdim } 1349193323Sed} 1350193323Sed 1351202375Srdivackybool 1352202375SrdivackyX86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1353202375Srdivacky unsigned &SrcReg, unsigned &DstReg, 1354202375Srdivacky unsigned &SubIdx) const { 1355202375Srdivacky switch (MI.getOpcode()) { 1356202375Srdivacky default: break; 1357202375Srdivacky case X86::MOVSX16rr8: 1358202375Srdivacky case X86::MOVZX16rr8: 1359202375Srdivacky case X86::MOVSX32rr8: 1360202375Srdivacky case X86::MOVZX32rr8: 1361202375Srdivacky case X86::MOVSX64rr8: 1362202375Srdivacky case X86::MOVZX64rr8: 1363202375Srdivacky if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1364202375Srdivacky // It's not always legal to reference the low 8-bit of the larger 1365202375Srdivacky // register in 32-bit mode. 1366202375Srdivacky return false; 1367202375Srdivacky case X86::MOVSX32rr16: 1368202375Srdivacky case X86::MOVZX32rr16: 1369202375Srdivacky case X86::MOVSX64rr16: 1370202375Srdivacky case X86::MOVZX64rr16: 1371202375Srdivacky case X86::MOVSX64rr32: 1372202375Srdivacky case X86::MOVZX64rr32: { 1373202375Srdivacky if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1374202375Srdivacky // Be conservative. 1375202375Srdivacky return false; 1376202375Srdivacky SrcReg = MI.getOperand(1).getReg(); 1377202375Srdivacky DstReg = MI.getOperand(0).getReg(); 1378202375Srdivacky switch (MI.getOpcode()) { 1379243830Sdim default: llvm_unreachable("Unreachable!"); 1380202375Srdivacky case X86::MOVSX16rr8: 1381202375Srdivacky case X86::MOVZX16rr8: 1382202375Srdivacky case X86::MOVSX32rr8: 1383202375Srdivacky case X86::MOVZX32rr8: 1384202375Srdivacky case X86::MOVSX64rr8: 1385202375Srdivacky case X86::MOVZX64rr8: 1386208599Srdivacky SubIdx = X86::sub_8bit; 1387202375Srdivacky break; 1388202375Srdivacky case X86::MOVSX32rr16: 1389202375Srdivacky case X86::MOVZX32rr16: 1390202375Srdivacky case X86::MOVSX64rr16: 1391202375Srdivacky case X86::MOVZX64rr16: 1392208599Srdivacky SubIdx = X86::sub_16bit; 1393202375Srdivacky break; 1394202375Srdivacky case X86::MOVSX64rr32: 1395202375Srdivacky case X86::MOVZX64rr32: 1396208599Srdivacky SubIdx = X86::sub_32bit; 1397202375Srdivacky break; 1398202375Srdivacky } 1399202375Srdivacky return true; 1400202375Srdivacky } 1401202375Srdivacky } 1402202375Srdivacky return false; 1403202375Srdivacky} 1404202375Srdivacky 1405199481Srdivacky/// isFrameOperand - Return true and the FrameIndex if the specified 1406199481Srdivacky/// operand and follow operands form a reference to the stack frame. 1407199481Srdivackybool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1408199481Srdivacky int &FrameIndex) const { 1409199481Srdivacky if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 1410199481Srdivacky MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 1411199481Srdivacky MI->getOperand(Op+1).getImm() == 1 && 1412199481Srdivacky MI->getOperand(Op+2).getReg() == 0 && 1413199481Srdivacky MI->getOperand(Op+3).getImm() == 0) { 1414199481Srdivacky FrameIndex = MI->getOperand(Op).getIndex(); 1415199481Srdivacky return true; 1416199481Srdivacky } 1417199481Srdivacky return false; 1418199481Srdivacky} 1419199481Srdivacky 1420199481Srdivackystatic bool isFrameLoadOpcode(int Opcode) { 1421199481Srdivacky switch (Opcode) { 1422234353Sdim default: 1423234353Sdim return false; 1424193323Sed case X86::MOV8rm: 1425193323Sed case X86::MOV16rm: 1426193323Sed case X86::MOV32rm: 1427193323Sed case X86::MOV64rm: 1428193323Sed case X86::LD_Fp64m: 1429193323Sed case X86::MOVSSrm: 1430193323Sed case X86::MOVSDrm: 1431193323Sed case X86::MOVAPSrm: 1432193323Sed case X86::MOVAPDrm: 1433193323Sed case X86::MOVDQArm: 1434226633Sdim case X86::VMOVSSrm: 1435226633Sdim case X86::VMOVSDrm: 1436226633Sdim case X86::VMOVAPSrm: 1437226633Sdim case X86::VMOVAPDrm: 1438226633Sdim case X86::VMOVDQArm: 1439224145Sdim case X86::VMOVAPSYrm: 1440224145Sdim case X86::VMOVAPDYrm: 1441224145Sdim case X86::VMOVDQAYrm: 1442193323Sed case X86::MMX_MOVD64rm: 1443193323Sed case X86::MMX_MOVQ64rm: 1444199481Srdivacky return true; 1445193323Sed } 1446193323Sed} 1447193323Sed 1448199481Srdivackystatic bool isFrameStoreOpcode(int Opcode) { 1449199481Srdivacky switch (Opcode) { 1450193323Sed default: break; 1451193323Sed case X86::MOV8mr: 1452193323Sed case X86::MOV16mr: 1453193323Sed case X86::MOV32mr: 1454193323Sed case X86::MOV64mr: 1455193323Sed case X86::ST_FpP64m: 1456193323Sed case X86::MOVSSmr: 1457193323Sed case X86::MOVSDmr: 1458193323Sed case X86::MOVAPSmr: 1459193323Sed case X86::MOVAPDmr: 1460193323Sed case X86::MOVDQAmr: 1461226633Sdim case X86::VMOVSSmr: 1462226633Sdim case X86::VMOVSDmr: 1463226633Sdim case X86::VMOVAPSmr: 1464226633Sdim case X86::VMOVAPDmr: 1465226633Sdim case X86::VMOVDQAmr: 1466224145Sdim case X86::VMOVAPSYmr: 1467224145Sdim case X86::VMOVAPDYmr: 1468224145Sdim case X86::VMOVDQAYmr: 1469193323Sed case X86::MMX_MOVD64mr: 1470193323Sed case X86::MMX_MOVQ64mr: 1471193323Sed case X86::MMX_MOVNTQmr: 1472199481Srdivacky return true; 1473199481Srdivacky } 1474199481Srdivacky return false; 1475199481Srdivacky} 1476199481Srdivacky 1477218893Sdimunsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1478199481Srdivacky int &FrameIndex) const { 1479199481Srdivacky if (isFrameLoadOpcode(MI->getOpcode())) 1480212904Sdim if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1481199481Srdivacky return MI->getOperand(0).getReg(); 1482199481Srdivacky return 0; 1483199481Srdivacky} 1484199481Srdivacky 1485218893Sdimunsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1486199481Srdivacky int &FrameIndex) const { 1487199481Srdivacky if (isFrameLoadOpcode(MI->getOpcode())) { 1488199481Srdivacky unsigned Reg; 1489199481Srdivacky if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1490199481Srdivacky return Reg; 1491199481Srdivacky // Check for post-frame index elimination operations 1492200581Srdivacky const MachineMemOperand *Dummy; 1493200581Srdivacky return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1494199481Srdivacky } 1495199481Srdivacky return 0; 1496199481Srdivacky} 1497199481Srdivacky 1498199481Srdivackyunsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1499199481Srdivacky int &FrameIndex) const { 1500199481Srdivacky if (isFrameStoreOpcode(MI->getOpcode())) 1501212904Sdim if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1502212904Sdim isFrameOperand(MI, 0, FrameIndex)) 1503210299Sed return MI->getOperand(X86::AddrNumOperands).getReg(); 1504199481Srdivacky return 0; 1505199481Srdivacky} 1506199481Srdivacky 1507199481Srdivackyunsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1508199481Srdivacky int &FrameIndex) const { 1509199481Srdivacky if (isFrameStoreOpcode(MI->getOpcode())) { 1510199481Srdivacky unsigned Reg; 1511199481Srdivacky if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1512199481Srdivacky return Reg; 1513199481Srdivacky // Check for post-frame index elimination operations 1514200581Srdivacky const MachineMemOperand *Dummy; 1515200581Srdivacky return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1516193323Sed } 1517193323Sed return 0; 1518193323Sed} 1519193323Sed 1520193323Sed/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1521193323Sed/// X86::MOVPC32r. 1522193323Sedstatic bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1523239462Sdim // Don't waste compile time scanning use-def chains of physregs. 1524239462Sdim if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1525239462Sdim return false; 1526193323Sed bool isPICBase = false; 1527193323Sed for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1528193323Sed E = MRI.def_end(); I != E; ++I) { 1529193323Sed MachineInstr *DefMI = I.getOperand().getParent(); 1530193323Sed if (DefMI->getOpcode() != X86::MOVPC32r) 1531193323Sed return false; 1532193323Sed assert(!isPICBase && "More than one PIC base?"); 1533193323Sed isPICBase = true; 1534193323Sed } 1535193323Sed return isPICBase; 1536193323Sed} 1537193323Sed 1538193323Sedbool 1539198090SrdivackyX86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1540198090Srdivacky AliasAnalysis *AA) const { 1541193323Sed switch (MI->getOpcode()) { 1542193323Sed default: break; 1543243830Sdim case X86::MOV8rm: 1544243830Sdim case X86::MOV16rm: 1545243830Sdim case X86::MOV32rm: 1546243830Sdim case X86::MOV64rm: 1547243830Sdim case X86::LD_Fp64m: 1548243830Sdim case X86::MOVSSrm: 1549243830Sdim case X86::MOVSDrm: 1550243830Sdim case X86::MOVAPSrm: 1551243830Sdim case X86::MOVUPSrm: 1552243830Sdim case X86::MOVAPDrm: 1553243830Sdim case X86::MOVDQArm: 1554243830Sdim case X86::VMOVSSrm: 1555243830Sdim case X86::VMOVSDrm: 1556243830Sdim case X86::VMOVAPSrm: 1557243830Sdim case X86::VMOVUPSrm: 1558243830Sdim case X86::VMOVAPDrm: 1559243830Sdim case X86::VMOVDQArm: 1560243830Sdim case X86::VMOVAPSYrm: 1561243830Sdim case X86::VMOVUPSYrm: 1562243830Sdim case X86::VMOVAPDYrm: 1563243830Sdim case X86::VMOVDQAYrm: 1564243830Sdim case X86::MMX_MOVD64rm: 1565243830Sdim case X86::MMX_MOVQ64rm: 1566243830Sdim case X86::FsVMOVAPSrm: 1567243830Sdim case X86::FsVMOVAPDrm: 1568243830Sdim case X86::FsMOVAPSrm: 1569243830Sdim case X86::FsMOVAPDrm: { 1570243830Sdim // Loads from constant pools are trivially rematerializable. 1571243830Sdim if (MI->getOperand(1).isReg() && 1572243830Sdim MI->getOperand(2).isImm() && 1573243830Sdim MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1574243830Sdim MI->isInvariantLoad(AA)) { 1575243830Sdim unsigned BaseReg = MI->getOperand(1).getReg(); 1576243830Sdim if (BaseReg == 0 || BaseReg == X86::RIP) 1577243830Sdim return true; 1578243830Sdim // Allow re-materialization of PIC load. 1579243830Sdim if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 1580243830Sdim return false; 1581243830Sdim const MachineFunction &MF = *MI->getParent()->getParent(); 1582243830Sdim const MachineRegisterInfo &MRI = MF.getRegInfo(); 1583243830Sdim return regIsPICBase(BaseReg, MRI); 1584193323Sed } 1585243830Sdim return false; 1586243830Sdim } 1587218893Sdim 1588243830Sdim case X86::LEA32r: 1589243830Sdim case X86::LEA64r: { 1590243830Sdim if (MI->getOperand(2).isImm() && 1591243830Sdim MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1592243830Sdim !MI->getOperand(4).isReg()) { 1593243830Sdim // lea fi#, lea GV, etc. are all rematerializable. 1594243830Sdim if (!MI->getOperand(1).isReg()) 1595243830Sdim return true; 1596243830Sdim unsigned BaseReg = MI->getOperand(1).getReg(); 1597243830Sdim if (BaseReg == 0) 1598243830Sdim return true; 1599243830Sdim // Allow re-materialization of lea PICBase + x. 1600243830Sdim const MachineFunction &MF = *MI->getParent()->getParent(); 1601243830Sdim const MachineRegisterInfo &MRI = MF.getRegInfo(); 1602243830Sdim return regIsPICBase(BaseReg, MRI); 1603243830Sdim } 1604243830Sdim return false; 1605193323Sed } 1606243830Sdim } 1607193323Sed 1608193323Sed // All other instructions marked M_REMATERIALIZABLE are always trivially 1609193323Sed // rematerializable. 1610193323Sed return true; 1611193323Sed} 1612193323Sed 1613193323Sed/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 1614193323Sed/// would clobber the EFLAGS condition register. Note the result may be 1615193323Sed/// conservative. If it cannot definitely determine the safety after visiting 1616198090Srdivacky/// a few instructions in each direction it assumes it's not safe. 1617193323Sedstatic bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1618193323Sed MachineBasicBlock::iterator I) { 1619206083Srdivacky MachineBasicBlock::iterator E = MBB.end(); 1620206083Srdivacky 1621193323Sed // For compile time consideration, if we are not able to determine the 1622198090Srdivacky // safety after visiting 4 instructions in each direction, we will assume 1623198090Srdivacky // it's not safe. 1624198090Srdivacky MachineBasicBlock::iterator Iter = I; 1625226633Sdim for (unsigned i = 0; Iter != E && i < 4; ++i) { 1626193323Sed bool SeenDef = false; 1627198090Srdivacky for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1628198090Srdivacky MachineOperand &MO = Iter->getOperand(j); 1629234353Sdim if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1630234353Sdim SeenDef = true; 1631193323Sed if (!MO.isReg()) 1632193323Sed continue; 1633193323Sed if (MO.getReg() == X86::EFLAGS) { 1634193323Sed if (MO.isUse()) 1635193323Sed return false; 1636193323Sed SeenDef = true; 1637193323Sed } 1638193323Sed } 1639193323Sed 1640193323Sed if (SeenDef) 1641193323Sed // This instruction defines EFLAGS, no need to look any further. 1642193323Sed return true; 1643198090Srdivacky ++Iter; 1644206083Srdivacky // Skip over DBG_VALUE. 1645206083Srdivacky while (Iter != E && Iter->isDebugValue()) 1646206083Srdivacky ++Iter; 1647226633Sdim } 1648193323Sed 1649226633Sdim // It is safe to clobber EFLAGS at the end of a block of no successor has it 1650226633Sdim // live in. 1651226633Sdim if (Iter == E) { 1652226633Sdim for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1653226633Sdim SE = MBB.succ_end(); SI != SE; ++SI) 1654226633Sdim if ((*SI)->isLiveIn(X86::EFLAGS)) 1655226633Sdim return false; 1656226633Sdim return true; 1657193323Sed } 1658193323Sed 1659206083Srdivacky MachineBasicBlock::iterator B = MBB.begin(); 1660198090Srdivacky Iter = I; 1661198090Srdivacky for (unsigned i = 0; i < 4; ++i) { 1662198090Srdivacky // If we make it to the beginning of the block, it's safe to clobber 1663198090Srdivacky // EFLAGS iff EFLAGS is not live-in. 1664206083Srdivacky if (Iter == B) 1665198090Srdivacky return !MBB.isLiveIn(X86::EFLAGS); 1666198090Srdivacky 1667198090Srdivacky --Iter; 1668206083Srdivacky // Skip over DBG_VALUE. 1669206083Srdivacky while (Iter != B && Iter->isDebugValue()) 1670206083Srdivacky --Iter; 1671206083Srdivacky 1672198090Srdivacky bool SawKill = false; 1673198090Srdivacky for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1674198090Srdivacky MachineOperand &MO = Iter->getOperand(j); 1675234353Sdim // A register mask may clobber EFLAGS, but we should still look for a 1676234353Sdim // live EFLAGS def. 1677234353Sdim if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1678234353Sdim SawKill = true; 1679198090Srdivacky if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1680198090Srdivacky if (MO.isDef()) return MO.isDead(); 1681198090Srdivacky if (MO.isKill()) SawKill = true; 1682198090Srdivacky } 1683198090Srdivacky } 1684198090Srdivacky 1685198090Srdivacky if (SawKill) 1686198090Srdivacky // This instruction kills EFLAGS and doesn't redefine it, so 1687198090Srdivacky // there's no need to look further. 1688198090Srdivacky return true; 1689198090Srdivacky } 1690198090Srdivacky 1691193323Sed // Conservative answer. 1692193323Sed return false; 1693193323Sed} 1694193323Sed 1695193323Sedvoid X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1696193323Sed MachineBasicBlock::iterator I, 1697198090Srdivacky unsigned DestReg, unsigned SubIdx, 1698199481Srdivacky const MachineInstr *Orig, 1699210299Sed const TargetRegisterInfo &TRI) const { 1700208599Srdivacky DebugLoc DL = Orig->getDebugLoc(); 1701193323Sed 1702193323Sed // MOV32r0 etc. are implemented with xor which clobbers condition code. 1703193323Sed // Re-materialize them as movri instructions to avoid side effects. 1704198090Srdivacky bool Clone = true; 1705198090Srdivacky unsigned Opc = Orig->getOpcode(); 1706198090Srdivacky switch (Opc) { 1707193323Sed default: break; 1708193323Sed case X86::MOV8r0: 1709202375Srdivacky case X86::MOV16r0: 1710202375Srdivacky case X86::MOV32r0: 1711202375Srdivacky case X86::MOV64r0: { 1712193323Sed if (!isSafeToClobberEFLAGS(MBB, I)) { 1713198090Srdivacky switch (Opc) { 1714243830Sdim default: llvm_unreachable("Unreachable!"); 1715193323Sed case X86::MOV8r0: Opc = X86::MOV8ri; break; 1716202375Srdivacky case X86::MOV16r0: Opc = X86::MOV16ri; break; 1717193323Sed case X86::MOV32r0: Opc = X86::MOV32ri; break; 1718204642Srdivacky case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1719193323Sed } 1720198090Srdivacky Clone = false; 1721193323Sed } 1722193323Sed break; 1723193323Sed } 1724193323Sed } 1725193323Sed 1726198090Srdivacky if (Clone) { 1727193323Sed MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1728193323Sed MBB.insert(I, MI); 1729198090Srdivacky } else { 1730210299Sed BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1731193323Sed } 1732193323Sed 1733198090Srdivacky MachineInstr *NewMI = prior(I); 1734210299Sed NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1735193323Sed} 1736193323Sed 1737193323Sed/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1738193323Sed/// is not marked dead. 1739193323Sedstatic bool hasLiveCondCodeDef(MachineInstr *MI) { 1740193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1741193323Sed MachineOperand &MO = MI->getOperand(i); 1742193323Sed if (MO.isReg() && MO.isDef() && 1743193323Sed MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1744193323Sed return true; 1745193323Sed } 1746193323Sed } 1747193323Sed return false; 1748193323Sed} 1749193323Sed 1750200581Srdivacky/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1751200581Srdivacky/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1752200581Srdivacky/// to a 32-bit superregister and then truncating back down to a 16-bit 1753200581Srdivacky/// subregister. 1754200581SrdivackyMachineInstr * 1755200581SrdivackyX86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1756200581Srdivacky MachineFunction::iterator &MFI, 1757200581Srdivacky MachineBasicBlock::iterator &MBBI, 1758200581Srdivacky LiveVariables *LV) const { 1759200581Srdivacky MachineInstr *MI = MBBI; 1760200581Srdivacky unsigned Dest = MI->getOperand(0).getReg(); 1761200581Srdivacky unsigned Src = MI->getOperand(1).getReg(); 1762200581Srdivacky bool isDead = MI->getOperand(0).isDead(); 1763200581Srdivacky bool isKill = MI->getOperand(1).isKill(); 1764200581Srdivacky 1765200581Srdivacky unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1766200581Srdivacky ? X86::LEA64_32r : X86::LEA32r; 1767200581Srdivacky MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1768218893Sdim unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1769200581Srdivacky unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1770218893Sdim 1771200581Srdivacky // Build and insert into an implicit UNDEF value. This is OK because 1772218893Sdim // well be shifting and then extracting the lower 16-bits. 1773200581Srdivacky // This has the potential to cause partial register stall. e.g. 1774200581Srdivacky // movw (%rbp,%rcx,2), %dx 1775200581Srdivacky // leal -65(%rdx), %esi 1776200581Srdivacky // But testing has shown this *does* help performance in 64-bit mode (at 1777200581Srdivacky // least on modern x86 machines). 1778200581Srdivacky BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1779200581Srdivacky MachineInstr *InsMI = 1780210299Sed BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1781210299Sed .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1782210299Sed .addReg(Src, getKillRegState(isKill)); 1783200581Srdivacky 1784200581Srdivacky MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1785200581Srdivacky get(Opc), leaOutReg); 1786200581Srdivacky switch (MIOpc) { 1787243830Sdim default: llvm_unreachable("Unreachable!"); 1788200581Srdivacky case X86::SHL16ri: { 1789200581Srdivacky unsigned ShAmt = MI->getOperand(2).getImm(); 1790200581Srdivacky MIB.addReg(0).addImm(1 << ShAmt) 1791210299Sed .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1792200581Srdivacky break; 1793200581Srdivacky } 1794200581Srdivacky case X86::INC16r: 1795200581Srdivacky case X86::INC64_16r: 1796210299Sed addRegOffset(MIB, leaInReg, true, 1); 1797200581Srdivacky break; 1798200581Srdivacky case X86::DEC16r: 1799200581Srdivacky case X86::DEC64_16r: 1800210299Sed addRegOffset(MIB, leaInReg, true, -1); 1801200581Srdivacky break; 1802200581Srdivacky case X86::ADD16ri: 1803200581Srdivacky case X86::ADD16ri8: 1804218893Sdim case X86::ADD16ri_DB: 1805218893Sdim case X86::ADD16ri8_DB: 1806218893Sdim addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1807200581Srdivacky break; 1808218893Sdim case X86::ADD16rr: 1809218893Sdim case X86::ADD16rr_DB: { 1810200581Srdivacky unsigned Src2 = MI->getOperand(2).getReg(); 1811200581Srdivacky bool isKill2 = MI->getOperand(2).isKill(); 1812200581Srdivacky unsigned leaInReg2 = 0; 1813200581Srdivacky MachineInstr *InsMI2 = 0; 1814200581Srdivacky if (Src == Src2) { 1815200581Srdivacky // ADD16rr %reg1028<kill>, %reg1028 1816200581Srdivacky // just a single insert_subreg. 1817200581Srdivacky addRegReg(MIB, leaInReg, true, leaInReg, false); 1818200581Srdivacky } else { 1819218893Sdim leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1820200581Srdivacky // Build and insert into an implicit UNDEF value. This is OK because 1821218893Sdim // well be shifting and then extracting the lower 16-bits. 1822234353Sdim BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1823200581Srdivacky InsMI2 = 1824234353Sdim BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1825210299Sed .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1826210299Sed .addReg(Src2, getKillRegState(isKill2)); 1827200581Srdivacky addRegReg(MIB, leaInReg, true, leaInReg2, true); 1828200581Srdivacky } 1829200581Srdivacky if (LV && isKill2 && InsMI2) 1830200581Srdivacky LV->replaceKillInstruction(Src2, MI, InsMI2); 1831200581Srdivacky break; 1832200581Srdivacky } 1833200581Srdivacky } 1834200581Srdivacky 1835200581Srdivacky MachineInstr *NewMI = MIB; 1836200581Srdivacky MachineInstr *ExtMI = 1837210299Sed BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1838200581Srdivacky .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1839210299Sed .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1840200581Srdivacky 1841200581Srdivacky if (LV) { 1842200581Srdivacky // Update live variables 1843200581Srdivacky LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1844200581Srdivacky LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1845200581Srdivacky if (isKill) 1846200581Srdivacky LV->replaceKillInstruction(Src, MI, InsMI); 1847200581Srdivacky if (isDead) 1848200581Srdivacky LV->replaceKillInstruction(Dest, MI, ExtMI); 1849200581Srdivacky } 1850200581Srdivacky 1851200581Srdivacky return ExtMI; 1852200581Srdivacky} 1853200581Srdivacky 1854193323Sed/// convertToThreeAddress - This method must be implemented by targets that 1855193323Sed/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1856193323Sed/// may be able to convert a two-address instruction into a true 1857193323Sed/// three-address instruction on demand. This allows the X86 target (for 1858193323Sed/// example) to convert ADD and SHL instructions into LEA instructions if they 1859193323Sed/// would require register copies due to two-addressness. 1860193323Sed/// 1861193323Sed/// This method returns a null pointer if the transformation cannot be 1862193323Sed/// performed, otherwise it returns the new instruction. 1863193323Sed/// 1864193323SedMachineInstr * 1865193323SedX86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1866193323Sed MachineBasicBlock::iterator &MBBI, 1867193323Sed LiveVariables *LV) const { 1868193323Sed MachineInstr *MI = MBBI; 1869193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 1870193323Sed // All instructions input are two-addr instructions. Get the known operands. 1871243830Sdim const MachineOperand &Dest = MI->getOperand(0); 1872243830Sdim const MachineOperand &Src = MI->getOperand(1); 1873193323Sed 1874193323Sed MachineInstr *NewMI = NULL; 1875193323Sed // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1876193323Sed // we have better subtarget support, enable the 16-bit LEA generation here. 1877200581Srdivacky // 16-bit LEA is also slow on Core2. 1878193323Sed bool DisableLEA16 = true; 1879200581Srdivacky bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1880193323Sed 1881193323Sed unsigned MIOpc = MI->getOpcode(); 1882193323Sed switch (MIOpc) { 1883193323Sed case X86::SHUFPSrri: { 1884193323Sed assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1885193323Sed if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1886218893Sdim 1887193323Sed unsigned B = MI->getOperand(1).getReg(); 1888193323Sed unsigned C = MI->getOperand(2).getReg(); 1889193323Sed if (B != C) return 0; 1890193323Sed unsigned M = MI->getOperand(3).getImm(); 1891193323Sed NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1892243830Sdim .addOperand(Dest).addOperand(Src).addImm(M); 1893193323Sed break; 1894193323Sed } 1895234353Sdim case X86::SHUFPDrri: { 1896234353Sdim assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 1897234353Sdim if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1898234353Sdim 1899234353Sdim unsigned B = MI->getOperand(1).getReg(); 1900234353Sdim unsigned C = MI->getOperand(2).getReg(); 1901234353Sdim if (B != C) return 0; 1902234353Sdim unsigned M = MI->getOperand(3).getImm(); 1903234353Sdim 1904234353Sdim // Convert to PSHUFD mask. 1905234353Sdim M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 1906234353Sdim 1907234353Sdim NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1908243830Sdim .addOperand(Dest).addOperand(Src).addImm(M); 1909234353Sdim break; 1910234353Sdim } 1911193323Sed case X86::SHL64ri: { 1912193323Sed assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1913193323Sed // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1914193323Sed // the flags produced by a shift yet, so this is safe. 1915193323Sed unsigned ShAmt = MI->getOperand(2).getImm(); 1916193323Sed if (ShAmt == 0 || ShAmt >= 4) return 0; 1917193323Sed 1918218893Sdim // LEA can't handle RSP. 1919243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1920243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), 1921243830Sdim &X86::GR64_NOSPRegClass)) 1922218893Sdim return 0; 1923218893Sdim 1924193323Sed NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1925243830Sdim .addOperand(Dest) 1926243830Sdim .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1927193323Sed break; 1928193323Sed } 1929193323Sed case X86::SHL32ri: { 1930193323Sed assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1931193323Sed // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1932193323Sed // the flags produced by a shift yet, so this is safe. 1933193323Sed unsigned ShAmt = MI->getOperand(2).getImm(); 1934193323Sed if (ShAmt == 0 || ShAmt >= 4) return 0; 1935193323Sed 1936218893Sdim // LEA can't handle ESP. 1937243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1938243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), 1939243830Sdim &X86::GR32_NOSPRegClass)) 1940218893Sdim return 0; 1941218893Sdim 1942200581Srdivacky unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1943193323Sed NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1944243830Sdim .addOperand(Dest) 1945243830Sdim .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1946193323Sed break; 1947193323Sed } 1948193323Sed case X86::SHL16ri: { 1949193323Sed assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1950193323Sed // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1951193323Sed // the flags produced by a shift yet, so this is safe. 1952193323Sed unsigned ShAmt = MI->getOperand(2).getImm(); 1953193323Sed if (ShAmt == 0 || ShAmt >= 4) return 0; 1954193323Sed 1955200581Srdivacky if (DisableLEA16) 1956200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1957200581Srdivacky NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1958243830Sdim .addOperand(Dest) 1959243830Sdim .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1960193323Sed break; 1961193323Sed } 1962193323Sed default: { 1963193323Sed // The following opcodes also sets the condition code register(s). Only 1964193323Sed // convert them to equivalent lea if the condition code register def's 1965193323Sed // are dead! 1966193323Sed if (hasLiveCondCodeDef(MI)) 1967193323Sed return 0; 1968193323Sed 1969193323Sed switch (MIOpc) { 1970193323Sed default: return 0; 1971193323Sed case X86::INC64r: 1972193323Sed case X86::INC32r: 1973193323Sed case X86::INC64_32r: { 1974193323Sed assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1975193323Sed unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1976193323Sed : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1977239462Sdim const TargetRegisterClass *RC = MIOpc == X86::INC64r ? 1978239462Sdim (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 1979239462Sdim (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 1980218893Sdim 1981218893Sdim // LEA can't handle RSP. 1982243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1983243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 1984218893Sdim return 0; 1985218893Sdim 1986243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1987243830Sdim .addOperand(Dest).addOperand(Src), 1); 1988193323Sed break; 1989193323Sed } 1990193323Sed case X86::INC16r: 1991193323Sed case X86::INC64_16r: 1992200581Srdivacky if (DisableLEA16) 1993200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1994193323Sed assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1995243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1996243830Sdim .addOperand(Dest).addOperand(Src), 1); 1997193323Sed break; 1998193323Sed case X86::DEC64r: 1999193323Sed case X86::DEC32r: 2000193323Sed case X86::DEC64_32r: { 2001193323Sed assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2002193323Sed unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2003193323Sed : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2004239462Sdim const TargetRegisterClass *RC = MIOpc == X86::DEC64r ? 2005239462Sdim (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 2006239462Sdim (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 2007218893Sdim // LEA can't handle RSP. 2008243830Sdim if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2009243830Sdim !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 2010218893Sdim return 0; 2011218893Sdim 2012243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2013243830Sdim .addOperand(Dest).addOperand(Src), -1); 2014193323Sed break; 2015193323Sed } 2016193323Sed case X86::DEC16r: 2017193323Sed case X86::DEC64_16r: 2018200581Srdivacky if (DisableLEA16) 2019200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2020193323Sed assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2021243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2022243830Sdim .addOperand(Dest).addOperand(Src), -1); 2023193323Sed break; 2024193323Sed case X86::ADD64rr: 2025218893Sdim case X86::ADD64rr_DB: 2026218893Sdim case X86::ADD32rr: 2027218893Sdim case X86::ADD32rr_DB: { 2028193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2029218893Sdim unsigned Opc; 2030234353Sdim const TargetRegisterClass *RC; 2031218893Sdim if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) { 2032218893Sdim Opc = X86::LEA64r; 2033239462Sdim RC = &X86::GR64_NOSPRegClass; 2034218893Sdim } else { 2035218893Sdim Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2036239462Sdim RC = &X86::GR32_NOSPRegClass; 2037218893Sdim } 2038218893Sdim 2039218893Sdim 2040193323Sed unsigned Src2 = MI->getOperand(2).getReg(); 2041193323Sed bool isKill2 = MI->getOperand(2).isKill(); 2042218893Sdim 2043218893Sdim // LEA can't handle RSP. 2044218893Sdim if (TargetRegisterInfo::isVirtualRegister(Src2) && 2045218893Sdim !MF.getRegInfo().constrainRegClass(Src2, RC)) 2046218893Sdim return 0; 2047218893Sdim 2048193323Sed NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2049243830Sdim .addOperand(Dest), 2050243830Sdim Src.getReg(), Src.isKill(), Src2, isKill2); 2051239462Sdim 2052239462Sdim // Preserve undefness of the operands. 2053239462Sdim bool isUndef = MI->getOperand(1).isUndef(); 2054239462Sdim bool isUndef2 = MI->getOperand(2).isUndef(); 2055239462Sdim NewMI->getOperand(1).setIsUndef(isUndef); 2056239462Sdim NewMI->getOperand(3).setIsUndef(isUndef2); 2057239462Sdim 2058193323Sed if (LV && isKill2) 2059193323Sed LV->replaceKillInstruction(Src2, MI, NewMI); 2060193323Sed break; 2061193323Sed } 2062218893Sdim case X86::ADD16rr: 2063218893Sdim case X86::ADD16rr_DB: { 2064200581Srdivacky if (DisableLEA16) 2065200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2066193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2067193323Sed unsigned Src2 = MI->getOperand(2).getReg(); 2068193323Sed bool isKill2 = MI->getOperand(2).isKill(); 2069193323Sed NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2070243830Sdim .addOperand(Dest), 2071243830Sdim Src.getReg(), Src.isKill(), Src2, isKill2); 2072243830Sdim 2073243830Sdim // Preserve undefness of the operands. 2074243830Sdim bool isUndef = MI->getOperand(1).isUndef(); 2075243830Sdim bool isUndef2 = MI->getOperand(2).isUndef(); 2076243830Sdim NewMI->getOperand(1).setIsUndef(isUndef); 2077243830Sdim NewMI->getOperand(3).setIsUndef(isUndef2); 2078243830Sdim 2079193323Sed if (LV && isKill2) 2080193323Sed LV->replaceKillInstruction(Src2, MI, NewMI); 2081193323Sed break; 2082193323Sed } 2083193323Sed case X86::ADD64ri32: 2084193323Sed case X86::ADD64ri8: 2085218893Sdim case X86::ADD64ri32_DB: 2086218893Sdim case X86::ADD64ri8_DB: 2087193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2088243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2089243830Sdim .addOperand(Dest).addOperand(Src), 2090243830Sdim MI->getOperand(2).getImm()); 2091193323Sed break; 2092193323Sed case X86::ADD32ri: 2093218893Sdim case X86::ADD32ri8: 2094218893Sdim case X86::ADD32ri_DB: 2095218893Sdim case X86::ADD32ri8_DB: { 2096193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2097200581Srdivacky unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2098243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2099243830Sdim .addOperand(Dest).addOperand(Src), 2100243830Sdim MI->getOperand(2).getImm()); 2101193323Sed break; 2102200581Srdivacky } 2103193323Sed case X86::ADD16ri: 2104193323Sed case X86::ADD16ri8: 2105218893Sdim case X86::ADD16ri_DB: 2106218893Sdim case X86::ADD16ri8_DB: 2107200581Srdivacky if (DisableLEA16) 2108200581Srdivacky return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2109193323Sed assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2110243830Sdim NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2111243830Sdim .addOperand(Dest).addOperand(Src), 2112243830Sdim MI->getOperand(2).getImm()); 2113193323Sed break; 2114193323Sed } 2115193323Sed } 2116193323Sed } 2117193323Sed 2118193323Sed if (!NewMI) return 0; 2119193323Sed 2120193323Sed if (LV) { // Update live variables 2121243830Sdim if (Src.isKill()) 2122243830Sdim LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2123243830Sdim if (Dest.isDead()) 2124243830Sdim LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2125193323Sed } 2126193323Sed 2127218893Sdim MFI->insert(MBBI, NewMI); // Insert the new inst 2128193323Sed return NewMI; 2129193323Sed} 2130193323Sed 2131193323Sed/// commuteInstruction - We have a few instructions that must be hacked on to 2132193323Sed/// commute them. 2133193323Sed/// 2134193323SedMachineInstr * 2135193323SedX86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2136193323Sed switch (MI->getOpcode()) { 2137193323Sed case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2138193323Sed case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2139193323Sed case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2140193323Sed case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2141193323Sed case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2142193323Sed case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2143193323Sed unsigned Opc; 2144193323Sed unsigned Size; 2145193323Sed switch (MI->getOpcode()) { 2146198090Srdivacky default: llvm_unreachable("Unreachable!"); 2147193323Sed case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2148193323Sed case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2149193323Sed case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2150193323Sed case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2151193323Sed case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2152193323Sed case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2153193323Sed } 2154193323Sed unsigned Amt = MI->getOperand(3).getImm(); 2155193323Sed if (NewMI) { 2156193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 2157193323Sed MI = MF.CloneMachineInstr(MI); 2158193323Sed NewMI = false; 2159193323Sed } 2160193323Sed MI->setDesc(get(Opc)); 2161193323Sed MI->getOperand(3).setImm(Size-Amt); 2162193323Sed return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 2163193323Sed } 2164243830Sdim case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2165243830Sdim case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2166243830Sdim case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2167243830Sdim case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2168243830Sdim case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2169243830Sdim case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2170243830Sdim case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2171243830Sdim case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2172243830Sdim case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2173243830Sdim case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2174243830Sdim case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2175243830Sdim case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2176243830Sdim case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2177243830Sdim case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2178243830Sdim case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2179243830Sdim case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2180243830Sdim unsigned Opc; 2181193323Sed switch (MI->getOpcode()) { 2182243830Sdim default: llvm_unreachable("Unreachable!"); 2183193323Sed case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2184193323Sed case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2185193323Sed case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2186193323Sed case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2187193323Sed case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2188193323Sed case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2189193323Sed case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2190193323Sed case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2191193323Sed case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2192193323Sed case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2193193323Sed case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2194193323Sed case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2195193323Sed case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2196193323Sed case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2197193323Sed case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2198193323Sed case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2199193323Sed case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2200193323Sed case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2201193323Sed case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2202193323Sed case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2203193323Sed case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2204193323Sed case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2205193323Sed case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2206193323Sed case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2207193323Sed case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2208193323Sed case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2209193323Sed case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2210193323Sed case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2211193323Sed case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2212193323Sed case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2213193323Sed case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2214193323Sed case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2215193323Sed case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2216193323Sed case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2217193323Sed case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2218193323Sed case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2219193323Sed case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2220193323Sed case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2221193323Sed case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2222193323Sed case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2223193323Sed case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2224193323Sed case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2225193323Sed case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2226193323Sed case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2227193323Sed case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2228193323Sed case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2229193323Sed case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2230193323Sed case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2231193323Sed } 2232193323Sed if (NewMI) { 2233193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 2234193323Sed MI = MF.CloneMachineInstr(MI); 2235193323Sed NewMI = false; 2236193323Sed } 2237193323Sed MI->setDesc(get(Opc)); 2238193323Sed // Fallthrough intended. 2239193323Sed } 2240193323Sed default: 2241193323Sed return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 2242193323Sed } 2243193323Sed} 2244193323Sed 2245239462Sdimstatic X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2246193323Sed switch (BrOpc) { 2247193323Sed default: return X86::COND_INVALID; 2248203954Srdivacky case X86::JE_4: return X86::COND_E; 2249203954Srdivacky case X86::JNE_4: return X86::COND_NE; 2250203954Srdivacky case X86::JL_4: return X86::COND_L; 2251203954Srdivacky case X86::JLE_4: return X86::COND_LE; 2252203954Srdivacky case X86::JG_4: return X86::COND_G; 2253203954Srdivacky case X86::JGE_4: return X86::COND_GE; 2254203954Srdivacky case X86::JB_4: return X86::COND_B; 2255203954Srdivacky case X86::JBE_4: return X86::COND_BE; 2256203954Srdivacky case X86::JA_4: return X86::COND_A; 2257203954Srdivacky case X86::JAE_4: return X86::COND_AE; 2258203954Srdivacky case X86::JS_4: return X86::COND_S; 2259203954Srdivacky case X86::JNS_4: return X86::COND_NS; 2260203954Srdivacky case X86::JP_4: return X86::COND_P; 2261203954Srdivacky case X86::JNP_4: return X86::COND_NP; 2262203954Srdivacky case X86::JO_4: return X86::COND_O; 2263203954Srdivacky case X86::JNO_4: return X86::COND_NO; 2264193323Sed } 2265193323Sed} 2266193323Sed 2267239462Sdim/// getCondFromSETOpc - return condition code of a SET opcode. 2268239462Sdimstatic X86::CondCode getCondFromSETOpc(unsigned Opc) { 2269239462Sdim switch (Opc) { 2270239462Sdim default: return X86::COND_INVALID; 2271239462Sdim case X86::SETAr: case X86::SETAm: return X86::COND_A; 2272239462Sdim case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2273239462Sdim case X86::SETBr: case X86::SETBm: return X86::COND_B; 2274239462Sdim case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2275239462Sdim case X86::SETEr: case X86::SETEm: return X86::COND_E; 2276239462Sdim case X86::SETGr: case X86::SETGm: return X86::COND_G; 2277239462Sdim case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2278239462Sdim case X86::SETLr: case X86::SETLm: return X86::COND_L; 2279239462Sdim case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2280239462Sdim case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2281239462Sdim case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2282239462Sdim case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2283239462Sdim case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2284239462Sdim case X86::SETOr: case X86::SETOm: return X86::COND_O; 2285239462Sdim case X86::SETPr: case X86::SETPm: return X86::COND_P; 2286239462Sdim case X86::SETSr: case X86::SETSm: return X86::COND_S; 2287239462Sdim } 2288239462Sdim} 2289239462Sdim 2290239462Sdim/// getCondFromCmovOpc - return condition code of a CMov opcode. 2291243830SdimX86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2292239462Sdim switch (Opc) { 2293239462Sdim default: return X86::COND_INVALID; 2294239462Sdim case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2295239462Sdim case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2296239462Sdim return X86::COND_A; 2297239462Sdim case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2298239462Sdim case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2299239462Sdim return X86::COND_AE; 2300239462Sdim case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2301239462Sdim case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2302239462Sdim return X86::COND_B; 2303239462Sdim case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2304239462Sdim case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2305239462Sdim return X86::COND_BE; 2306239462Sdim case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2307239462Sdim case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2308239462Sdim return X86::COND_E; 2309239462Sdim case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2310239462Sdim case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2311239462Sdim return X86::COND_G; 2312239462Sdim case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2313239462Sdim case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2314239462Sdim return X86::COND_GE; 2315239462Sdim case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2316239462Sdim case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2317239462Sdim return X86::COND_L; 2318239462Sdim case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2319239462Sdim case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2320239462Sdim return X86::COND_LE; 2321239462Sdim case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2322239462Sdim case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2323239462Sdim return X86::COND_NE; 2324239462Sdim case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2325239462Sdim case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2326239462Sdim return X86::COND_NO; 2327239462Sdim case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2328239462Sdim case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2329239462Sdim return X86::COND_NP; 2330239462Sdim case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2331239462Sdim case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2332239462Sdim return X86::COND_NS; 2333239462Sdim case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2334239462Sdim case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2335239462Sdim return X86::COND_O; 2336239462Sdim case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2337239462Sdim case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2338239462Sdim return X86::COND_P; 2339239462Sdim case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2340239462Sdim case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2341239462Sdim return X86::COND_S; 2342239462Sdim } 2343239462Sdim} 2344239462Sdim 2345193323Sedunsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2346193323Sed switch (CC) { 2347198090Srdivacky default: llvm_unreachable("Illegal condition code!"); 2348203954Srdivacky case X86::COND_E: return X86::JE_4; 2349203954Srdivacky case X86::COND_NE: return X86::JNE_4; 2350203954Srdivacky case X86::COND_L: return X86::JL_4; 2351203954Srdivacky case X86::COND_LE: return X86::JLE_4; 2352203954Srdivacky case X86::COND_G: return X86::JG_4; 2353203954Srdivacky case X86::COND_GE: return X86::JGE_4; 2354203954Srdivacky case X86::COND_B: return X86::JB_4; 2355203954Srdivacky case X86::COND_BE: return X86::JBE_4; 2356203954Srdivacky case X86::COND_A: return X86::JA_4; 2357203954Srdivacky case X86::COND_AE: return X86::JAE_4; 2358203954Srdivacky case X86::COND_S: return X86::JS_4; 2359203954Srdivacky case X86::COND_NS: return X86::JNS_4; 2360203954Srdivacky case X86::COND_P: return X86::JP_4; 2361203954Srdivacky case X86::COND_NP: return X86::JNP_4; 2362203954Srdivacky case X86::COND_O: return X86::JO_4; 2363203954Srdivacky case X86::COND_NO: return X86::JNO_4; 2364193323Sed } 2365193323Sed} 2366193323Sed 2367193323Sed/// GetOppositeBranchCondition - Return the inverse of the specified condition, 2368193323Sed/// e.g. turning COND_E to COND_NE. 2369193323SedX86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2370193323Sed switch (CC) { 2371198090Srdivacky default: llvm_unreachable("Illegal condition code!"); 2372193323Sed case X86::COND_E: return X86::COND_NE; 2373193323Sed case X86::COND_NE: return X86::COND_E; 2374193323Sed case X86::COND_L: return X86::COND_GE; 2375193323Sed case X86::COND_LE: return X86::COND_G; 2376193323Sed case X86::COND_G: return X86::COND_LE; 2377193323Sed case X86::COND_GE: return X86::COND_L; 2378193323Sed case X86::COND_B: return X86::COND_AE; 2379193323Sed case X86::COND_BE: return X86::COND_A; 2380193323Sed case X86::COND_A: return X86::COND_BE; 2381193323Sed case X86::COND_AE: return X86::COND_B; 2382193323Sed case X86::COND_S: return X86::COND_NS; 2383193323Sed case X86::COND_NS: return X86::COND_S; 2384193323Sed case X86::COND_P: return X86::COND_NP; 2385193323Sed case X86::COND_NP: return X86::COND_P; 2386193323Sed case X86::COND_O: return X86::COND_NO; 2387193323Sed case X86::COND_NO: return X86::COND_O; 2388193323Sed } 2389193323Sed} 2390193323Sed 2391239462Sdim/// getSwappedCondition - assume the flags are set by MI(a,b), return 2392239462Sdim/// the condition code if we modify the instructions such that flags are 2393239462Sdim/// set by MI(b,a). 2394239462Sdimstatic X86::CondCode getSwappedCondition(X86::CondCode CC) { 2395239462Sdim switch (CC) { 2396239462Sdim default: return X86::COND_INVALID; 2397239462Sdim case X86::COND_E: return X86::COND_E; 2398239462Sdim case X86::COND_NE: return X86::COND_NE; 2399239462Sdim case X86::COND_L: return X86::COND_G; 2400239462Sdim case X86::COND_LE: return X86::COND_GE; 2401239462Sdim case X86::COND_G: return X86::COND_L; 2402239462Sdim case X86::COND_GE: return X86::COND_LE; 2403239462Sdim case X86::COND_B: return X86::COND_A; 2404239462Sdim case X86::COND_BE: return X86::COND_AE; 2405239462Sdim case X86::COND_A: return X86::COND_B; 2406239462Sdim case X86::COND_AE: return X86::COND_BE; 2407239462Sdim } 2408239462Sdim} 2409239462Sdim 2410239462Sdim/// getSETFromCond - Return a set opcode for the given condition and 2411239462Sdim/// whether it has memory operand. 2412239462Sdimstatic unsigned getSETFromCond(X86::CondCode CC, 2413239462Sdim bool HasMemoryOperand) { 2414243830Sdim static const uint16_t Opc[16][2] = { 2415239462Sdim { X86::SETAr, X86::SETAm }, 2416239462Sdim { X86::SETAEr, X86::SETAEm }, 2417239462Sdim { X86::SETBr, X86::SETBm }, 2418239462Sdim { X86::SETBEr, X86::SETBEm }, 2419239462Sdim { X86::SETEr, X86::SETEm }, 2420239462Sdim { X86::SETGr, X86::SETGm }, 2421239462Sdim { X86::SETGEr, X86::SETGEm }, 2422239462Sdim { X86::SETLr, X86::SETLm }, 2423239462Sdim { X86::SETLEr, X86::SETLEm }, 2424239462Sdim { X86::SETNEr, X86::SETNEm }, 2425239462Sdim { X86::SETNOr, X86::SETNOm }, 2426239462Sdim { X86::SETNPr, X86::SETNPm }, 2427239462Sdim { X86::SETNSr, X86::SETNSm }, 2428239462Sdim { X86::SETOr, X86::SETOm }, 2429239462Sdim { X86::SETPr, X86::SETPm }, 2430239462Sdim { X86::SETSr, X86::SETSm } 2431239462Sdim }; 2432239462Sdim 2433239462Sdim assert(CC < 16 && "Can only handle standard cond codes"); 2434239462Sdim return Opc[CC][HasMemoryOperand ? 1 : 0]; 2435239462Sdim} 2436239462Sdim 2437239462Sdim/// getCMovFromCond - Return a cmov opcode for the given condition, 2438239462Sdim/// register size in bytes, and operand type. 2439239462Sdimstatic unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, 2440239462Sdim bool HasMemoryOperand) { 2441243830Sdim static const uint16_t Opc[32][3] = { 2442239462Sdim { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2443239462Sdim { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2444239462Sdim { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2445239462Sdim { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2446239462Sdim { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2447239462Sdim { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2448239462Sdim { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2449239462Sdim { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2450239462Sdim { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2451239462Sdim { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2452239462Sdim { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2453239462Sdim { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2454239462Sdim { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2455239462Sdim { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2456239462Sdim { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2457239462Sdim { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2458239462Sdim { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2459239462Sdim { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2460239462Sdim { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2461239462Sdim { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2462239462Sdim { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2463239462Sdim { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2464239462Sdim { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2465239462Sdim { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2466239462Sdim { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2467239462Sdim { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2468239462Sdim { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2469239462Sdim { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2470239462Sdim { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2471239462Sdim { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2472239462Sdim { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2473239462Sdim { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2474239462Sdim }; 2475239462Sdim 2476239462Sdim assert(CC < 16 && "Can only handle standard cond codes"); 2477239462Sdim unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2478239462Sdim switch(RegBytes) { 2479239462Sdim default: llvm_unreachable("Illegal register size!"); 2480239462Sdim case 2: return Opc[Idx][0]; 2481239462Sdim case 4: return Opc[Idx][1]; 2482239462Sdim case 8: return Opc[Idx][2]; 2483239462Sdim } 2484239462Sdim} 2485239462Sdim 2486193323Sedbool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2487234353Sdim if (!MI->isTerminator()) return false; 2488218893Sdim 2489193323Sed // Conditional branch is a special case. 2490234353Sdim if (MI->isBranch() && !MI->isBarrier()) 2491193323Sed return true; 2492234353Sdim if (!MI->isPredicable()) 2493193323Sed return true; 2494193323Sed return !isPredicated(MI); 2495193323Sed} 2496193323Sed 2497218893Sdimbool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2498193323Sed MachineBasicBlock *&TBB, 2499193323Sed MachineBasicBlock *&FBB, 2500193323Sed SmallVectorImpl<MachineOperand> &Cond, 2501193323Sed bool AllowModify) const { 2502193323Sed // Start from the bottom of the block and work up, examining the 2503193323Sed // terminator instructions. 2504193323Sed MachineBasicBlock::iterator I = MBB.end(); 2505207618Srdivacky MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2506193323Sed while (I != MBB.begin()) { 2507193323Sed --I; 2508206083Srdivacky if (I->isDebugValue()) 2509206083Srdivacky continue; 2510200581Srdivacky 2511200581Srdivacky // Working from the bottom, when we see a non-terminator instruction, we're 2512200581Srdivacky // done. 2513212904Sdim if (!isUnpredicatedTerminator(I)) 2514193323Sed break; 2515200581Srdivacky 2516200581Srdivacky // A terminator that isn't a branch can't easily be handled by this 2517200581Srdivacky // analysis. 2518234353Sdim if (!I->isBranch()) 2519193323Sed return true; 2520200581Srdivacky 2521193323Sed // Handle unconditional branches. 2522203954Srdivacky if (I->getOpcode() == X86::JMP_4) { 2523207618Srdivacky UnCondBrIter = I; 2524207618Srdivacky 2525193323Sed if (!AllowModify) { 2526193323Sed TBB = I->getOperand(0).getMBB(); 2527193323Sed continue; 2528193323Sed } 2529193323Sed 2530193323Sed // If the block has any instructions after a JMP, delete them. 2531200581Srdivacky while (llvm::next(I) != MBB.end()) 2532200581Srdivacky llvm::next(I)->eraseFromParent(); 2533200581Srdivacky 2534193323Sed Cond.clear(); 2535193323Sed FBB = 0; 2536200581Srdivacky 2537193323Sed // Delete the JMP if it's equivalent to a fall-through. 2538193323Sed if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2539193323Sed TBB = 0; 2540193323Sed I->eraseFromParent(); 2541193323Sed I = MBB.end(); 2542207618Srdivacky UnCondBrIter = MBB.end(); 2543193323Sed continue; 2544193323Sed } 2545200581Srdivacky 2546207618Srdivacky // TBB is used to indicate the unconditional destination. 2547193323Sed TBB = I->getOperand(0).getMBB(); 2548193323Sed continue; 2549193323Sed } 2550200581Srdivacky 2551193323Sed // Handle conditional branches. 2552239462Sdim X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2553193323Sed if (BranchCode == X86::COND_INVALID) 2554193323Sed return true; // Can't handle indirect branch. 2555200581Srdivacky 2556193323Sed // Working from the bottom, handle the first conditional branch. 2557193323Sed if (Cond.empty()) { 2558207618Srdivacky MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2559207618Srdivacky if (AllowModify && UnCondBrIter != MBB.end() && 2560207618Srdivacky MBB.isLayoutSuccessor(TargetBB)) { 2561207618Srdivacky // If we can modify the code and it ends in something like: 2562207618Srdivacky // 2563207618Srdivacky // jCC L1 2564207618Srdivacky // jmp L2 2565207618Srdivacky // L1: 2566207618Srdivacky // ... 2567207618Srdivacky // L2: 2568207618Srdivacky // 2569207618Srdivacky // Then we can change this to: 2570207618Srdivacky // 2571207618Srdivacky // jnCC L2 2572207618Srdivacky // L1: 2573207618Srdivacky // ... 2574207618Srdivacky // L2: 2575207618Srdivacky // 2576207618Srdivacky // Which is a bit more efficient. 2577207618Srdivacky // We conditionally jump to the fall-through block. 2578207618Srdivacky BranchCode = GetOppositeBranchCondition(BranchCode); 2579207618Srdivacky unsigned JNCC = GetCondBranchFromCond(BranchCode); 2580207618Srdivacky MachineBasicBlock::iterator OldInst = I; 2581207618Srdivacky 2582207618Srdivacky BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2583207618Srdivacky .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2584207618Srdivacky BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2585207618Srdivacky .addMBB(TargetBB); 2586207618Srdivacky 2587207618Srdivacky OldInst->eraseFromParent(); 2588207618Srdivacky UnCondBrIter->eraseFromParent(); 2589207618Srdivacky 2590207618Srdivacky // Restart the analysis. 2591207618Srdivacky UnCondBrIter = MBB.end(); 2592207618Srdivacky I = MBB.end(); 2593207618Srdivacky continue; 2594207618Srdivacky } 2595207618Srdivacky 2596193323Sed FBB = TBB; 2597193323Sed TBB = I->getOperand(0).getMBB(); 2598193323Sed Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2599193323Sed continue; 2600193323Sed } 2601200581Srdivacky 2602200581Srdivacky // Handle subsequent conditional branches. Only handle the case where all 2603200581Srdivacky // conditional branches branch to the same destination and their condition 2604200581Srdivacky // opcodes fit one of the special multi-branch idioms. 2605193323Sed assert(Cond.size() == 1); 2606193323Sed assert(TBB); 2607200581Srdivacky 2608200581Srdivacky // Only handle the case where all conditional branches branch to the same 2609200581Srdivacky // destination. 2610193323Sed if (TBB != I->getOperand(0).getMBB()) 2611193323Sed return true; 2612200581Srdivacky 2613200581Srdivacky // If the conditions are the same, we can leave them alone. 2614193323Sed X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2615193323Sed if (OldBranchCode == BranchCode) 2616193323Sed continue; 2617200581Srdivacky 2618200581Srdivacky // If they differ, see if they fit one of the known patterns. Theoretically, 2619200581Srdivacky // we could handle more patterns here, but we shouldn't expect to see them 2620200581Srdivacky // if instruction selection has done a reasonable job. 2621193323Sed if ((OldBranchCode == X86::COND_NP && 2622193323Sed BranchCode == X86::COND_E) || 2623193323Sed (OldBranchCode == X86::COND_E && 2624193323Sed BranchCode == X86::COND_NP)) 2625193323Sed BranchCode = X86::COND_NP_OR_E; 2626193323Sed else if ((OldBranchCode == X86::COND_P && 2627193323Sed BranchCode == X86::COND_NE) || 2628193323Sed (OldBranchCode == X86::COND_NE && 2629193323Sed BranchCode == X86::COND_P)) 2630193323Sed BranchCode = X86::COND_NE_OR_P; 2631193323Sed else 2632193323Sed return true; 2633200581Srdivacky 2634193323Sed // Update the MachineOperand. 2635193323Sed Cond[0].setImm(BranchCode); 2636193323Sed } 2637193323Sed 2638193323Sed return false; 2639193323Sed} 2640193323Sed 2641193323Sedunsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2642193323Sed MachineBasicBlock::iterator I = MBB.end(); 2643193323Sed unsigned Count = 0; 2644193323Sed 2645193323Sed while (I != MBB.begin()) { 2646193323Sed --I; 2647206083Srdivacky if (I->isDebugValue()) 2648206083Srdivacky continue; 2649203954Srdivacky if (I->getOpcode() != X86::JMP_4 && 2650239462Sdim getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2651193323Sed break; 2652193323Sed // Remove the branch. 2653193323Sed I->eraseFromParent(); 2654193323Sed I = MBB.end(); 2655193323Sed ++Count; 2656193323Sed } 2657218893Sdim 2658193323Sed return Count; 2659193323Sed} 2660193323Sed 2661193323Sedunsigned 2662193323SedX86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2663193323Sed MachineBasicBlock *FBB, 2664210299Sed const SmallVectorImpl<MachineOperand> &Cond, 2665210299Sed DebugLoc DL) const { 2666193323Sed // Shouldn't be a fall through. 2667193323Sed assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2668193323Sed assert((Cond.size() == 1 || Cond.size() == 0) && 2669193323Sed "X86 branch conditions have one component!"); 2670193323Sed 2671193323Sed if (Cond.empty()) { 2672193323Sed // Unconditional branch? 2673193323Sed assert(!FBB && "Unconditional branch with multiple successors!"); 2674210299Sed BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2675193323Sed return 1; 2676193323Sed } 2677193323Sed 2678193323Sed // Conditional branch. 2679193323Sed unsigned Count = 0; 2680193323Sed X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2681193323Sed switch (CC) { 2682193323Sed case X86::COND_NP_OR_E: 2683193323Sed // Synthesize NP_OR_E with two branches. 2684210299Sed BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2685193323Sed ++Count; 2686210299Sed BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2687193323Sed ++Count; 2688193323Sed break; 2689193323Sed case X86::COND_NE_OR_P: 2690193323Sed // Synthesize NE_OR_P with two branches. 2691210299Sed BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2692193323Sed ++Count; 2693210299Sed BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2694193323Sed ++Count; 2695193323Sed break; 2696193323Sed default: { 2697193323Sed unsigned Opc = GetCondBranchFromCond(CC); 2698210299Sed BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2699193323Sed ++Count; 2700193323Sed } 2701193323Sed } 2702193323Sed if (FBB) { 2703193323Sed // Two-way Conditional branch. Insert the second branch. 2704210299Sed BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2705193323Sed ++Count; 2706193323Sed } 2707193323Sed return Count; 2708193323Sed} 2709193323Sed 2710239462Sdimbool X86InstrInfo:: 2711239462SdimcanInsertSelect(const MachineBasicBlock &MBB, 2712239462Sdim const SmallVectorImpl<MachineOperand> &Cond, 2713239462Sdim unsigned TrueReg, unsigned FalseReg, 2714239462Sdim int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2715239462Sdim // Not all subtargets have cmov instructions. 2716239462Sdim if (!TM.getSubtarget<X86Subtarget>().hasCMov()) 2717239462Sdim return false; 2718239462Sdim if (Cond.size() != 1) 2719239462Sdim return false; 2720239462Sdim // We cannot do the composite conditions, at least not in SSA form. 2721239462Sdim if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2722239462Sdim return false; 2723239462Sdim 2724239462Sdim // Check register classes. 2725239462Sdim const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2726239462Sdim const TargetRegisterClass *RC = 2727239462Sdim RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2728239462Sdim if (!RC) 2729239462Sdim return false; 2730239462Sdim 2731239462Sdim // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2732239462Sdim if (X86::GR16RegClass.hasSubClassEq(RC) || 2733239462Sdim X86::GR32RegClass.hasSubClassEq(RC) || 2734239462Sdim X86::GR64RegClass.hasSubClassEq(RC)) { 2735239462Sdim // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2736239462Sdim // Bridge. Probably Ivy Bridge as well. 2737239462Sdim CondCycles = 2; 2738239462Sdim TrueCycles = 2; 2739239462Sdim FalseCycles = 2; 2740239462Sdim return true; 2741239462Sdim } 2742239462Sdim 2743239462Sdim // Can't do vectors. 2744239462Sdim return false; 2745239462Sdim} 2746239462Sdim 2747239462Sdimvoid X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 2748239462Sdim MachineBasicBlock::iterator I, DebugLoc DL, 2749239462Sdim unsigned DstReg, 2750239462Sdim const SmallVectorImpl<MachineOperand> &Cond, 2751239462Sdim unsigned TrueReg, unsigned FalseReg) const { 2752239462Sdim MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2753239462Sdim assert(Cond.size() == 1 && "Invalid Cond array"); 2754239462Sdim unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 2755239462Sdim MRI.getRegClass(DstReg)->getSize(), 2756239462Sdim false/*HasMemoryOperand*/); 2757239462Sdim BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 2758239462Sdim} 2759239462Sdim 2760193323Sed/// isHReg - Test if the given register is a physical h register. 2761193323Sedstatic bool isHReg(unsigned Reg) { 2762193323Sed return X86::GR8_ABCD_HRegClass.contains(Reg); 2763193323Sed} 2764193323Sed 2765212904Sdim// Try and copy between VR128/VR64 and GR64 registers. 2766226633Sdimstatic unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 2767226633Sdim bool HasAVX) { 2768212904Sdim // SrcReg(VR128) -> DestReg(GR64) 2769212904Sdim // SrcReg(VR64) -> DestReg(GR64) 2770212904Sdim // SrcReg(GR64) -> DestReg(VR128) 2771212904Sdim // SrcReg(GR64) -> DestReg(VR64) 2772212904Sdim 2773212904Sdim if (X86::GR64RegClass.contains(DestReg)) { 2774243830Sdim if (X86::VR128RegClass.contains(SrcReg)) 2775212904Sdim // Copy from a VR128 register to a GR64 register. 2776226633Sdim return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr; 2777243830Sdim if (X86::VR64RegClass.contains(SrcReg)) 2778212904Sdim // Copy from a VR64 register to a GR64 register. 2779212904Sdim return X86::MOVSDto64rr; 2780212904Sdim } else if (X86::GR64RegClass.contains(SrcReg)) { 2781212904Sdim // Copy from a GR64 register to a VR128 register. 2782212904Sdim if (X86::VR128RegClass.contains(DestReg)) 2783226633Sdim return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr; 2784212904Sdim // Copy from a GR64 register to a VR64 register. 2785243830Sdim if (X86::VR64RegClass.contains(DestReg)) 2786212904Sdim return X86::MOV64toSDrr; 2787212904Sdim } 2788212904Sdim 2789226633Sdim // SrcReg(FR32) -> DestReg(GR32) 2790226633Sdim // SrcReg(GR32) -> DestReg(FR32) 2791226633Sdim 2792226633Sdim if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg)) 2793243830Sdim // Copy from a FR32 register to a GR32 register. 2794243830Sdim return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr; 2795226633Sdim 2796226633Sdim if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 2797243830Sdim // Copy from a GR32 register to a FR32 register. 2798243830Sdim return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr; 2799226633Sdim 2800212904Sdim return 0; 2801212904Sdim} 2802212904Sdim 2803210299Sedvoid X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 2804210299Sed MachineBasicBlock::iterator MI, DebugLoc DL, 2805210299Sed unsigned DestReg, unsigned SrcReg, 2806210299Sed bool KillSrc) const { 2807210299Sed // First deal with the normal symmetric copies. 2808226633Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2809243830Sdim unsigned Opc; 2810210299Sed if (X86::GR64RegClass.contains(DestReg, SrcReg)) 2811210299Sed Opc = X86::MOV64rr; 2812210299Sed else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 2813210299Sed Opc = X86::MOV32rr; 2814210299Sed else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 2815210299Sed Opc = X86::MOV16rr; 2816210299Sed else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 2817210299Sed // Copying to or from a physical H register on x86-64 requires a NOREX 2818210299Sed // move. Otherwise use a normal move. 2819210299Sed if ((isHReg(DestReg) || isHReg(SrcReg)) && 2820226633Sdim TM.getSubtarget<X86Subtarget>().is64Bit()) { 2821210299Sed Opc = X86::MOV8rr_NOREX; 2822226633Sdim // Both operands must be encodable without an REX prefix. 2823226633Sdim assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 2824226633Sdim "8-bit H register can not be copied outside GR8_NOREX"); 2825226633Sdim } else 2826210299Sed Opc = X86::MOV8rr; 2827210299Sed } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 2828226633Sdim Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 2829224145Sdim else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 2830224145Sdim Opc = X86::VMOVAPSYrr; 2831210299Sed else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 2832210299Sed Opc = X86::MMX_MOVQ64rr; 2833212904Sdim else 2834226633Sdim Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX); 2835193323Sed 2836210299Sed if (Opc) { 2837210299Sed BuildMI(MBB, MI, DL, get(Opc), DestReg) 2838210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 2839210299Sed return; 2840193323Sed } 2841198090Srdivacky 2842193323Sed // Moving EFLAGS to / from another register requires a push and a pop. 2843210299Sed if (SrcReg == X86::EFLAGS) { 2844210299Sed if (X86::GR64RegClass.contains(DestReg)) { 2845208599Srdivacky BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 2846193323Sed BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 2847210299Sed return; 2848243830Sdim } 2849243830Sdim if (X86::GR32RegClass.contains(DestReg)) { 2850208599Srdivacky BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 2851193323Sed BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 2852210299Sed return; 2853193323Sed } 2854210299Sed } 2855210299Sed if (DestReg == X86::EFLAGS) { 2856210299Sed if (X86::GR64RegClass.contains(SrcReg)) { 2857210299Sed BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 2858210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 2859208599Srdivacky BuildMI(MBB, MI, DL, get(X86::POPF64)); 2860210299Sed return; 2861243830Sdim } 2862243830Sdim if (X86::GR32RegClass.contains(SrcReg)) { 2863210299Sed BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2864210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 2865208599Srdivacky BuildMI(MBB, MI, DL, get(X86::POPF32)); 2866210299Sed return; 2867193323Sed } 2868193323Sed } 2869193323Sed 2870210299Sed DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2871210299Sed << " to " << RI.getName(DestReg) << '\n'); 2872210299Sed llvm_unreachable("Cannot emit physreg copy instruction"); 2873193323Sed} 2874193323Sed 2875210299Sedstatic unsigned getLoadStoreRegOpcode(unsigned Reg, 2876210299Sed const TargetRegisterClass *RC, 2877210299Sed bool isStackAligned, 2878210299Sed const TargetMachine &TM, 2879210299Sed bool load) { 2880226633Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2881223017Sdim switch (RC->getSize()) { 2882210299Sed default: 2883223017Sdim llvm_unreachable("Unknown spill size"); 2884223017Sdim case 1: 2885223017Sdim assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 2886223017Sdim if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2887223017Sdim // Copying to or from a physical H register on x86-64 requires a NOREX 2888223017Sdim // move. Otherwise use a normal move. 2889223017Sdim if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 2890223017Sdim return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2891223017Sdim return load ? X86::MOV8rm : X86::MOV8mr; 2892223017Sdim case 2: 2893223017Sdim assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 2894210299Sed return load ? X86::MOV16rm : X86::MOV16mr; 2895223017Sdim case 4: 2896223017Sdim if (X86::GR32RegClass.hasSubClassEq(RC)) 2897223017Sdim return load ? X86::MOV32rm : X86::MOV32mr; 2898223017Sdim if (X86::FR32RegClass.hasSubClassEq(RC)) 2899226633Sdim return load ? 2900226633Sdim (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 2901226633Sdim (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 2902223017Sdim if (X86::RFP32RegClass.hasSubClassEq(RC)) 2903223017Sdim return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2904223017Sdim llvm_unreachable("Unknown 4-byte regclass"); 2905223017Sdim case 8: 2906223017Sdim if (X86::GR64RegClass.hasSubClassEq(RC)) 2907223017Sdim return load ? X86::MOV64rm : X86::MOV64mr; 2908223017Sdim if (X86::FR64RegClass.hasSubClassEq(RC)) 2909226633Sdim return load ? 2910226633Sdim (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 2911226633Sdim (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 2912223017Sdim if (X86::VR64RegClass.hasSubClassEq(RC)) 2913223017Sdim return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2914223017Sdim if (X86::RFP64RegClass.hasSubClassEq(RC)) 2915223017Sdim return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2916223017Sdim llvm_unreachable("Unknown 8-byte regclass"); 2917223017Sdim case 10: 2918223017Sdim assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 2919210299Sed return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2920226633Sdim case 16: { 2921223017Sdim assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); 2922193323Sed // If stack is realigned we can use aligned stores. 2923210299Sed if (isStackAligned) 2924226633Sdim return load ? 2925226633Sdim (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 2926226633Sdim (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 2927210299Sed else 2928226633Sdim return load ? 2929226633Sdim (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 2930226633Sdim (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 2931226633Sdim } 2932224145Sdim case 32: 2933224145Sdim assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 2934224145Sdim // If stack is realigned we can use aligned stores. 2935224145Sdim if (isStackAligned) 2936224145Sdim return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 2937224145Sdim else 2938224145Sdim return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 2939193323Sed } 2940210299Sed} 2941193323Sed 2942210299Sedstatic unsigned getStoreRegOpcode(unsigned SrcReg, 2943210299Sed const TargetRegisterClass *RC, 2944210299Sed bool isStackAligned, 2945210299Sed TargetMachine &TM) { 2946210299Sed return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2947193323Sed} 2948193323Sed 2949210299Sed 2950210299Sedstatic unsigned getLoadRegOpcode(unsigned DestReg, 2951210299Sed const TargetRegisterClass *RC, 2952210299Sed bool isStackAligned, 2953210299Sed const TargetMachine &TM) { 2954210299Sed return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2955210299Sed} 2956210299Sed 2957193323Sedvoid X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2958193323Sed MachineBasicBlock::iterator MI, 2959193323Sed unsigned SrcReg, bool isKill, int FrameIdx, 2960208599Srdivacky const TargetRegisterClass *RC, 2961208599Srdivacky const TargetRegisterInfo *TRI) const { 2962193323Sed const MachineFunction &MF = *MBB.getParent(); 2963212904Sdim assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2964212904Sdim "Stack slot too small for store"); 2965226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2966226633Sdim bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2967224145Sdim RI.canRealignStack(MF); 2968193323Sed unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2969203954Srdivacky DebugLoc DL = MBB.findDebugLoc(MI); 2970193323Sed addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2971193323Sed .addReg(SrcReg, getKillRegState(isKill)); 2972193323Sed} 2973193323Sed 2974193323Sedvoid X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2975193323Sed bool isKill, 2976193323Sed SmallVectorImpl<MachineOperand> &Addr, 2977193323Sed const TargetRegisterClass *RC, 2978198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 2979198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 2980193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const { 2981226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2982226633Sdim bool isAligned = MMOBegin != MMOEnd && 2983226633Sdim (*MMOBegin)->getAlignment() >= Alignment; 2984193323Sed unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2985206124Srdivacky DebugLoc DL; 2986193323Sed MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2987193323Sed for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2988193323Sed MIB.addOperand(Addr[i]); 2989193323Sed MIB.addReg(SrcReg, getKillRegState(isKill)); 2990198090Srdivacky (*MIB).setMemRefs(MMOBegin, MMOEnd); 2991193323Sed NewMIs.push_back(MIB); 2992193323Sed} 2993193323Sed 2994193323Sed 2995193323Sedvoid X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2996193323Sed MachineBasicBlock::iterator MI, 2997193323Sed unsigned DestReg, int FrameIdx, 2998208599Srdivacky const TargetRegisterClass *RC, 2999208599Srdivacky const TargetRegisterInfo *TRI) const { 3000193323Sed const MachineFunction &MF = *MBB.getParent(); 3001226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3002226633Sdim bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 3003224145Sdim RI.canRealignStack(MF); 3004193323Sed unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3005203954Srdivacky DebugLoc DL = MBB.findDebugLoc(MI); 3006193323Sed addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 3007193323Sed} 3008193323Sed 3009193323Sedvoid X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3010193323Sed SmallVectorImpl<MachineOperand> &Addr, 3011193323Sed const TargetRegisterClass *RC, 3012198090Srdivacky MachineInstr::mmo_iterator MMOBegin, 3013198090Srdivacky MachineInstr::mmo_iterator MMOEnd, 3014193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const { 3015226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3016226633Sdim bool isAligned = MMOBegin != MMOEnd && 3017226633Sdim (*MMOBegin)->getAlignment() >= Alignment; 3018193323Sed unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3019206124Srdivacky DebugLoc DL; 3020193323Sed MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3021193323Sed for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3022193323Sed MIB.addOperand(Addr[i]); 3023198090Srdivacky (*MIB).setMemRefs(MMOBegin, MMOEnd); 3024193323Sed NewMIs.push_back(MIB); 3025193323Sed} 3026193323Sed 3027239462Sdimbool X86InstrInfo:: 3028239462SdimanalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3029239462Sdim int &CmpMask, int &CmpValue) const { 3030239462Sdim switch (MI->getOpcode()) { 3031239462Sdim default: break; 3032239462Sdim case X86::CMP64ri32: 3033239462Sdim case X86::CMP64ri8: 3034239462Sdim case X86::CMP32ri: 3035239462Sdim case X86::CMP32ri8: 3036239462Sdim case X86::CMP16ri: 3037239462Sdim case X86::CMP16ri8: 3038239462Sdim case X86::CMP8ri: 3039239462Sdim SrcReg = MI->getOperand(0).getReg(); 3040239462Sdim SrcReg2 = 0; 3041239462Sdim CmpMask = ~0; 3042239462Sdim CmpValue = MI->getOperand(1).getImm(); 3043239462Sdim return true; 3044239462Sdim // A SUB can be used to perform comparison. 3045239462Sdim case X86::SUB64rm: 3046239462Sdim case X86::SUB32rm: 3047239462Sdim case X86::SUB16rm: 3048239462Sdim case X86::SUB8rm: 3049239462Sdim SrcReg = MI->getOperand(1).getReg(); 3050239462Sdim SrcReg2 = 0; 3051239462Sdim CmpMask = ~0; 3052239462Sdim CmpValue = 0; 3053239462Sdim return true; 3054239462Sdim case X86::SUB64rr: 3055239462Sdim case X86::SUB32rr: 3056239462Sdim case X86::SUB16rr: 3057239462Sdim case X86::SUB8rr: 3058239462Sdim SrcReg = MI->getOperand(1).getReg(); 3059239462Sdim SrcReg2 = MI->getOperand(2).getReg(); 3060239462Sdim CmpMask = ~0; 3061239462Sdim CmpValue = 0; 3062239462Sdim return true; 3063239462Sdim case X86::SUB64ri32: 3064239462Sdim case X86::SUB64ri8: 3065239462Sdim case X86::SUB32ri: 3066239462Sdim case X86::SUB32ri8: 3067239462Sdim case X86::SUB16ri: 3068239462Sdim case X86::SUB16ri8: 3069239462Sdim case X86::SUB8ri: 3070239462Sdim SrcReg = MI->getOperand(1).getReg(); 3071239462Sdim SrcReg2 = 0; 3072239462Sdim CmpMask = ~0; 3073239462Sdim CmpValue = MI->getOperand(2).getImm(); 3074239462Sdim return true; 3075239462Sdim case X86::CMP64rr: 3076239462Sdim case X86::CMP32rr: 3077239462Sdim case X86::CMP16rr: 3078239462Sdim case X86::CMP8rr: 3079239462Sdim SrcReg = MI->getOperand(0).getReg(); 3080239462Sdim SrcReg2 = MI->getOperand(1).getReg(); 3081239462Sdim CmpMask = ~0; 3082239462Sdim CmpValue = 0; 3083239462Sdim return true; 3084239462Sdim case X86::TEST8rr: 3085239462Sdim case X86::TEST16rr: 3086239462Sdim case X86::TEST32rr: 3087239462Sdim case X86::TEST64rr: 3088239462Sdim SrcReg = MI->getOperand(0).getReg(); 3089239462Sdim if (MI->getOperand(1).getReg() != SrcReg) return false; 3090239462Sdim // Compare against zero. 3091239462Sdim SrcReg2 = 0; 3092239462Sdim CmpMask = ~0; 3093239462Sdim CmpValue = 0; 3094239462Sdim return true; 3095239462Sdim } 3096239462Sdim return false; 3097239462Sdim} 3098239462Sdim 3099239462Sdim/// isRedundantFlagInstr - check whether the first instruction, whose only 3100239462Sdim/// purpose is to update flags, can be made redundant. 3101239462Sdim/// CMPrr can be made redundant by SUBrr if the operands are the same. 3102239462Sdim/// This function can be extended later on. 3103239462Sdim/// SrcReg, SrcRegs: register operands for FlagI. 3104239462Sdim/// ImmValue: immediate for FlagI if it takes an immediate. 3105239462Sdiminline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3106239462Sdim unsigned SrcReg2, int ImmValue, 3107239462Sdim MachineInstr *OI) { 3108239462Sdim if (((FlagI->getOpcode() == X86::CMP64rr && 3109239462Sdim OI->getOpcode() == X86::SUB64rr) || 3110239462Sdim (FlagI->getOpcode() == X86::CMP32rr && 3111239462Sdim OI->getOpcode() == X86::SUB32rr)|| 3112239462Sdim (FlagI->getOpcode() == X86::CMP16rr && 3113239462Sdim OI->getOpcode() == X86::SUB16rr)|| 3114239462Sdim (FlagI->getOpcode() == X86::CMP8rr && 3115239462Sdim OI->getOpcode() == X86::SUB8rr)) && 3116239462Sdim ((OI->getOperand(1).getReg() == SrcReg && 3117239462Sdim OI->getOperand(2).getReg() == SrcReg2) || 3118239462Sdim (OI->getOperand(1).getReg() == SrcReg2 && 3119239462Sdim OI->getOperand(2).getReg() == SrcReg))) 3120239462Sdim return true; 3121239462Sdim 3122239462Sdim if (((FlagI->getOpcode() == X86::CMP64ri32 && 3123239462Sdim OI->getOpcode() == X86::SUB64ri32) || 3124239462Sdim (FlagI->getOpcode() == X86::CMP64ri8 && 3125239462Sdim OI->getOpcode() == X86::SUB64ri8) || 3126239462Sdim (FlagI->getOpcode() == X86::CMP32ri && 3127239462Sdim OI->getOpcode() == X86::SUB32ri) || 3128239462Sdim (FlagI->getOpcode() == X86::CMP32ri8 && 3129239462Sdim OI->getOpcode() == X86::SUB32ri8) || 3130239462Sdim (FlagI->getOpcode() == X86::CMP16ri && 3131239462Sdim OI->getOpcode() == X86::SUB16ri) || 3132239462Sdim (FlagI->getOpcode() == X86::CMP16ri8 && 3133239462Sdim OI->getOpcode() == X86::SUB16ri8) || 3134239462Sdim (FlagI->getOpcode() == X86::CMP8ri && 3135239462Sdim OI->getOpcode() == X86::SUB8ri)) && 3136239462Sdim OI->getOperand(1).getReg() == SrcReg && 3137239462Sdim OI->getOperand(2).getImm() == ImmValue) 3138239462Sdim return true; 3139239462Sdim return false; 3140239462Sdim} 3141239462Sdim 3142239462Sdim/// isDefConvertible - check whether the definition can be converted 3143239462Sdim/// to remove a comparison against zero. 3144239462Sdiminline static bool isDefConvertible(MachineInstr *MI) { 3145239462Sdim switch (MI->getOpcode()) { 3146239462Sdim default: return false; 3147239462Sdim case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3148239462Sdim case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3149239462Sdim case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3150239462Sdim case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3151239462Sdim case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3152243830Sdim case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3153243830Sdim case X86::DEC64m: case X86::DEC32m: case X86::DEC16m: case X86::DEC8m: 3154243830Sdim case X86::DEC64_32r: case X86::DEC64_16r: 3155243830Sdim case X86::DEC64_32m: case X86::DEC64_16m: 3156239462Sdim case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3157239462Sdim case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3158239462Sdim case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3159239462Sdim case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3160239462Sdim case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3161243830Sdim case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3162243830Sdim case X86::INC64m: case X86::INC32m: case X86::INC16m: case X86::INC8m: 3163243830Sdim case X86::INC64_32r: case X86::INC64_16r: 3164243830Sdim case X86::INC64_32m: case X86::INC64_16m: 3165239462Sdim case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3166239462Sdim case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3167239462Sdim case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3168239462Sdim case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3169239462Sdim case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3170239462Sdim case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3171239462Sdim case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3172239462Sdim case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3173239462Sdim case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3174239462Sdim case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3175239462Sdim case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3176239462Sdim case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3177239462Sdim case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3178239462Sdim case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3179239462Sdim case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3180239462Sdim return true; 3181239462Sdim } 3182239462Sdim} 3183239462Sdim 3184239462Sdim/// optimizeCompareInstr - Check if there exists an earlier instruction that 3185239462Sdim/// operates on the same source operands and sets flags in the same way as 3186239462Sdim/// Compare; remove Compare if possible. 3187239462Sdimbool X86InstrInfo:: 3188239462SdimoptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3189239462Sdim int CmpMask, int CmpValue, 3190239462Sdim const MachineRegisterInfo *MRI) const { 3191239462Sdim // Check whether we can replace SUB with CMP. 3192239462Sdim unsigned NewOpcode = 0; 3193239462Sdim switch (CmpInstr->getOpcode()) { 3194239462Sdim default: break; 3195239462Sdim case X86::SUB64ri32: 3196239462Sdim case X86::SUB64ri8: 3197239462Sdim case X86::SUB32ri: 3198239462Sdim case X86::SUB32ri8: 3199239462Sdim case X86::SUB16ri: 3200239462Sdim case X86::SUB16ri8: 3201239462Sdim case X86::SUB8ri: 3202239462Sdim case X86::SUB64rm: 3203239462Sdim case X86::SUB32rm: 3204239462Sdim case X86::SUB16rm: 3205239462Sdim case X86::SUB8rm: 3206239462Sdim case X86::SUB64rr: 3207239462Sdim case X86::SUB32rr: 3208239462Sdim case X86::SUB16rr: 3209239462Sdim case X86::SUB8rr: { 3210239462Sdim if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3211239462Sdim return false; 3212239462Sdim // There is no use of the destination register, we can replace SUB with CMP. 3213239462Sdim switch (CmpInstr->getOpcode()) { 3214243830Sdim default: llvm_unreachable("Unreachable!"); 3215239462Sdim case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3216239462Sdim case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3217239462Sdim case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3218239462Sdim case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3219239462Sdim case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3220239462Sdim case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3221239462Sdim case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3222239462Sdim case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3223239462Sdim case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3224239462Sdim case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3225239462Sdim case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3226239462Sdim case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3227239462Sdim case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3228239462Sdim case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3229239462Sdim case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3230239462Sdim } 3231239462Sdim CmpInstr->setDesc(get(NewOpcode)); 3232239462Sdim CmpInstr->RemoveOperand(0); 3233239462Sdim // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3234239462Sdim if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3235239462Sdim NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3236239462Sdim return false; 3237239462Sdim } 3238239462Sdim } 3239239462Sdim 3240239462Sdim // Get the unique definition of SrcReg. 3241239462Sdim MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3242239462Sdim if (!MI) return false; 3243239462Sdim 3244239462Sdim // CmpInstr is the first instruction of the BB. 3245239462Sdim MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3246239462Sdim 3247239462Sdim // If we are comparing against zero, check whether we can use MI to update 3248239462Sdim // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3249239462Sdim bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3250239462Sdim if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() || 3251239462Sdim !isDefConvertible(MI))) 3252239462Sdim return false; 3253239462Sdim 3254239462Sdim // We are searching for an earlier instruction that can make CmpInstr 3255239462Sdim // redundant and that instruction will be saved in Sub. 3256239462Sdim MachineInstr *Sub = NULL; 3257239462Sdim const TargetRegisterInfo *TRI = &getRegisterInfo(); 3258239462Sdim 3259239462Sdim // We iterate backward, starting from the instruction before CmpInstr and 3260239462Sdim // stop when reaching the definition of a source register or done with the BB. 3261239462Sdim // RI points to the instruction before CmpInstr. 3262239462Sdim // If the definition is in this basic block, RE points to the definition; 3263239462Sdim // otherwise, RE is the rend of the basic block. 3264239462Sdim MachineBasicBlock::reverse_iterator 3265239462Sdim RI = MachineBasicBlock::reverse_iterator(I), 3266239462Sdim RE = CmpInstr->getParent() == MI->getParent() ? 3267239462Sdim MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3268239462Sdim CmpInstr->getParent()->rend(); 3269239462Sdim MachineInstr *Movr0Inst = 0; 3270239462Sdim for (; RI != RE; ++RI) { 3271239462Sdim MachineInstr *Instr = &*RI; 3272239462Sdim // Check whether CmpInstr can be made redundant by the current instruction. 3273239462Sdim if (!IsCmpZero && 3274239462Sdim isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3275239462Sdim Sub = Instr; 3276239462Sdim break; 3277239462Sdim } 3278239462Sdim 3279239462Sdim if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3280239462Sdim Instr->readsRegister(X86::EFLAGS, TRI)) { 3281239462Sdim // This instruction modifies or uses EFLAGS. 3282239462Sdim 3283239462Sdim // MOV32r0 etc. are implemented with xor which clobbers condition code. 3284239462Sdim // They are safe to move up, if the definition to EFLAGS is dead and 3285239462Sdim // earlier instructions do not read or write EFLAGS. 3286239462Sdim if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 || 3287239462Sdim Instr->getOpcode() == X86::MOV16r0 || 3288239462Sdim Instr->getOpcode() == X86::MOV32r0 || 3289239462Sdim Instr->getOpcode() == X86::MOV64r0) && 3290239462Sdim Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3291239462Sdim Movr0Inst = Instr; 3292239462Sdim continue; 3293239462Sdim } 3294239462Sdim 3295239462Sdim // We can't remove CmpInstr. 3296239462Sdim return false; 3297239462Sdim } 3298239462Sdim } 3299239462Sdim 3300239462Sdim // Return false if no candidates exist. 3301239462Sdim if (!IsCmpZero && !Sub) 3302239462Sdim return false; 3303239462Sdim 3304239462Sdim bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3305239462Sdim Sub->getOperand(2).getReg() == SrcReg); 3306239462Sdim 3307239462Sdim // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3308239462Sdim // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3309239462Sdim // If we are done with the basic block, we need to check whether EFLAGS is 3310239462Sdim // live-out. 3311239462Sdim bool IsSafe = false; 3312239462Sdim SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3313239462Sdim MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3314239462Sdim for (++I; I != E; ++I) { 3315239462Sdim const MachineInstr &Instr = *I; 3316239462Sdim bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3317239462Sdim bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3318239462Sdim // We should check the usage if this instruction uses and updates EFLAGS. 3319239462Sdim if (!UseEFLAGS && ModifyEFLAGS) { 3320239462Sdim // It is safe to remove CmpInstr if EFLAGS is updated again. 3321239462Sdim IsSafe = true; 3322239462Sdim break; 3323239462Sdim } 3324239462Sdim if (!UseEFLAGS && !ModifyEFLAGS) 3325239462Sdim continue; 3326239462Sdim 3327239462Sdim // EFLAGS is used by this instruction. 3328239462Sdim X86::CondCode OldCC; 3329239462Sdim bool OpcIsSET = false; 3330239462Sdim if (IsCmpZero || IsSwapped) { 3331239462Sdim // We decode the condition code from opcode. 3332239462Sdim if (Instr.isBranch()) 3333239462Sdim OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3334239462Sdim else { 3335239462Sdim OldCC = getCondFromSETOpc(Instr.getOpcode()); 3336239462Sdim if (OldCC != X86::COND_INVALID) 3337239462Sdim OpcIsSET = true; 3338239462Sdim else 3339243830Sdim OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3340239462Sdim } 3341239462Sdim if (OldCC == X86::COND_INVALID) return false; 3342239462Sdim } 3343239462Sdim if (IsCmpZero) { 3344239462Sdim switch (OldCC) { 3345239462Sdim default: break; 3346239462Sdim case X86::COND_A: case X86::COND_AE: 3347239462Sdim case X86::COND_B: case X86::COND_BE: 3348239462Sdim case X86::COND_G: case X86::COND_GE: 3349239462Sdim case X86::COND_L: case X86::COND_LE: 3350239462Sdim case X86::COND_O: case X86::COND_NO: 3351239462Sdim // CF and OF are used, we can't perform this optimization. 3352239462Sdim return false; 3353239462Sdim } 3354239462Sdim } else if (IsSwapped) { 3355239462Sdim // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3356239462Sdim // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3357239462Sdim // We swap the condition code and synthesize the new opcode. 3358239462Sdim X86::CondCode NewCC = getSwappedCondition(OldCC); 3359239462Sdim if (NewCC == X86::COND_INVALID) return false; 3360239462Sdim 3361239462Sdim // Synthesize the new opcode. 3362239462Sdim bool HasMemoryOperand = Instr.hasOneMemOperand(); 3363239462Sdim unsigned NewOpc; 3364239462Sdim if (Instr.isBranch()) 3365239462Sdim NewOpc = GetCondBranchFromCond(NewCC); 3366239462Sdim else if(OpcIsSET) 3367239462Sdim NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3368239462Sdim else { 3369239462Sdim unsigned DstReg = Instr.getOperand(0).getReg(); 3370239462Sdim NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3371239462Sdim HasMemoryOperand); 3372239462Sdim } 3373239462Sdim 3374239462Sdim // Push the MachineInstr to OpsToUpdate. 3375239462Sdim // If it is safe to remove CmpInstr, the condition code of these 3376239462Sdim // instructions will be modified. 3377239462Sdim OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3378239462Sdim } 3379239462Sdim if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3380239462Sdim // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3381239462Sdim IsSafe = true; 3382239462Sdim break; 3383239462Sdim } 3384239462Sdim } 3385239462Sdim 3386239462Sdim // If EFLAGS is not killed nor re-defined, we should check whether it is 3387239462Sdim // live-out. If it is live-out, do not optimize. 3388239462Sdim if ((IsCmpZero || IsSwapped) && !IsSafe) { 3389239462Sdim MachineBasicBlock *MBB = CmpInstr->getParent(); 3390239462Sdim for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3391239462Sdim SE = MBB->succ_end(); SI != SE; ++SI) 3392239462Sdim if ((*SI)->isLiveIn(X86::EFLAGS)) 3393239462Sdim return false; 3394239462Sdim } 3395239462Sdim 3396239462Sdim // The instruction to be updated is either Sub or MI. 3397239462Sdim Sub = IsCmpZero ? MI : Sub; 3398239462Sdim // Move Movr0Inst to the place right before Sub. 3399239462Sdim if (Movr0Inst) { 3400239462Sdim Sub->getParent()->remove(Movr0Inst); 3401239462Sdim Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst); 3402239462Sdim } 3403239462Sdim 3404243830Sdim // Make sure Sub instruction defines EFLAGS and mark the def live. 3405243830Sdim unsigned LastOperand = Sub->getNumOperands() - 1; 3406239462Sdim assert(Sub->getNumOperands() >= 2 && 3407243830Sdim Sub->getOperand(LastOperand).isReg() && 3408243830Sdim Sub->getOperand(LastOperand).getReg() == X86::EFLAGS && 3409239462Sdim "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND"); 3410243830Sdim Sub->getOperand(LastOperand).setIsDef(true); 3411243830Sdim Sub->getOperand(LastOperand).setIsDead(false); 3412239462Sdim CmpInstr->eraseFromParent(); 3413239462Sdim 3414239462Sdim // Modify the condition code of instructions in OpsToUpdate. 3415239462Sdim for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3416239462Sdim OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3417239462Sdim return true; 3418239462Sdim} 3419239462Sdim 3420239462Sdim/// optimizeLoadInstr - Try to remove the load by folding it to a register 3421239462Sdim/// operand at the use. We fold the load instructions if load defines a virtual 3422239462Sdim/// register, the virtual register is used once in the same BB, and the 3423239462Sdim/// instructions in-between do not load or store, and have no side effects. 3424239462SdimMachineInstr* X86InstrInfo:: 3425239462SdimoptimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3426239462Sdim unsigned &FoldAsLoadDefReg, 3427239462Sdim MachineInstr *&DefMI) const { 3428239462Sdim if (FoldAsLoadDefReg == 0) 3429239462Sdim return 0; 3430239462Sdim // To be conservative, if there exists another load, clear the load candidate. 3431239462Sdim if (MI->mayLoad()) { 3432239462Sdim FoldAsLoadDefReg = 0; 3433239462Sdim return 0; 3434239462Sdim } 3435239462Sdim 3436239462Sdim // Check whether we can move DefMI here. 3437239462Sdim DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3438239462Sdim assert(DefMI); 3439239462Sdim bool SawStore = false; 3440239462Sdim if (!DefMI->isSafeToMove(this, 0, SawStore)) 3441239462Sdim return 0; 3442239462Sdim 3443239462Sdim // We try to commute MI if possible. 3444239462Sdim unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3445239462Sdim for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3446239462Sdim // Collect information about virtual register operands of MI. 3447239462Sdim unsigned SrcOperandId = 0; 3448239462Sdim bool FoundSrcOperand = false; 3449239462Sdim for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3450239462Sdim MachineOperand &MO = MI->getOperand(i); 3451239462Sdim if (!MO.isReg()) 3452239462Sdim continue; 3453239462Sdim unsigned Reg = MO.getReg(); 3454239462Sdim if (Reg != FoldAsLoadDefReg) 3455239462Sdim continue; 3456239462Sdim // Do not fold if we have a subreg use or a def or multiple uses. 3457239462Sdim if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3458239462Sdim return 0; 3459239462Sdim 3460239462Sdim SrcOperandId = i; 3461239462Sdim FoundSrcOperand = true; 3462239462Sdim } 3463239462Sdim if (!FoundSrcOperand) return 0; 3464239462Sdim 3465239462Sdim // Check whether we can fold the def into SrcOperandId. 3466239462Sdim SmallVector<unsigned, 8> Ops; 3467239462Sdim Ops.push_back(SrcOperandId); 3468239462Sdim MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3469239462Sdim if (FoldMI) { 3470239462Sdim FoldAsLoadDefReg = 0; 3471239462Sdim return FoldMI; 3472239462Sdim } 3473239462Sdim 3474239462Sdim if (Idx == 1) { 3475239462Sdim // MI was changed but it didn't help, commute it back! 3476239462Sdim commuteInstruction(MI, false); 3477239462Sdim return 0; 3478239462Sdim } 3479239462Sdim 3480239462Sdim // Check whether we can commute MI and enable folding. 3481239462Sdim if (MI->isCommutable()) { 3482239462Sdim MachineInstr *NewMI = commuteInstruction(MI, false); 3483239462Sdim // Unable to commute. 3484239462Sdim if (!NewMI) return 0; 3485239462Sdim if (NewMI != MI) { 3486239462Sdim // New instruction. It doesn't need to be kept. 3487239462Sdim NewMI->eraseFromParent(); 3488239462Sdim return 0; 3489239462Sdim } 3490239462Sdim } 3491239462Sdim } 3492239462Sdim return 0; 3493239462Sdim} 3494239462Sdim 3495226633Sdim/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3496226633Sdim/// instruction with two undef reads of the register being defined. This is 3497226633Sdim/// used for mapping: 3498226633Sdim/// %xmm4 = V_SET0 3499226633Sdim/// to: 3500226633Sdim/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3501226633Sdim/// 3502226633Sdimstatic bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) { 3503226633Sdim assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3504226633Sdim unsigned Reg = MI->getOperand(0).getReg(); 3505226633Sdim MI->setDesc(Desc); 3506226633Sdim 3507226633Sdim // MachineInstr::addOperand() will insert explicit operands before any 3508226633Sdim // implicit operands. 3509226633Sdim MachineInstrBuilder(MI).addReg(Reg, RegState::Undef) 3510226633Sdim .addReg(Reg, RegState::Undef); 3511226633Sdim // But we don't trust that. 3512226633Sdim assert(MI->getOperand(1).getReg() == Reg && 3513226633Sdim MI->getOperand(2).getReg() == Reg && "Misplaced operand"); 3514226633Sdim return true; 3515226633Sdim} 3516226633Sdim 3517226633Sdimbool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3518226633Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3519226633Sdim switch (MI->getOpcode()) { 3520243830Sdim case X86::SETB_C8r: 3521243830Sdim return Expand2AddrUndef(MI, get(X86::SBB8rr)); 3522243830Sdim case X86::SETB_C16r: 3523243830Sdim return Expand2AddrUndef(MI, get(X86::SBB16rr)); 3524243830Sdim case X86::SETB_C32r: 3525243830Sdim return Expand2AddrUndef(MI, get(X86::SBB32rr)); 3526243830Sdim case X86::SETB_C64r: 3527243830Sdim return Expand2AddrUndef(MI, get(X86::SBB64rr)); 3528226633Sdim case X86::V_SET0: 3529234353Sdim case X86::FsFLD0SS: 3530234353Sdim case X86::FsFLD0SD: 3531234353Sdim return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3532243830Sdim case X86::AVX_SET0: 3533243830Sdim assert(HasAVX && "AVX not supported"); 3534243830Sdim return Expand2AddrUndef(MI, get(X86::VXORPSYrr)); 3535243830Sdim case X86::V_SETALLONES: 3536243830Sdim return Expand2AddrUndef(MI, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 3537243830Sdim case X86::AVX2_SETALLONES: 3538243830Sdim return Expand2AddrUndef(MI, get(X86::VPCMPEQDYrr)); 3539226633Sdim case X86::TEST8ri_NOREX: 3540226633Sdim MI->setDesc(get(X86::TEST8ri)); 3541226633Sdim return true; 3542226633Sdim } 3543226633Sdim return false; 3544226633Sdim} 3545226633Sdim 3546207618SrdivackyMachineInstr* 3547207618SrdivackyX86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 3548207618Srdivacky int FrameIx, uint64_t Offset, 3549207618Srdivacky const MDNode *MDPtr, 3550207618Srdivacky DebugLoc DL) const { 3551207618Srdivacky X86AddressMode AM; 3552207618Srdivacky AM.BaseType = X86AddressMode::FrameIndexBase; 3553207618Srdivacky AM.Base.FrameIndex = FrameIx; 3554207618Srdivacky MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 3555207618Srdivacky addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 3556207618Srdivacky return &*MIB; 3557207618Srdivacky} 3558207618Srdivacky 3559193323Sedstatic MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 3560193323Sed const SmallVectorImpl<MachineOperand> &MOs, 3561193323Sed MachineInstr *MI, 3562193323Sed const TargetInstrInfo &TII) { 3563193323Sed // Create the base instruction with the memory operand as the first part. 3564193323Sed MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3565193323Sed MI->getDebugLoc(), true); 3566193323Sed MachineInstrBuilder MIB(NewMI); 3567193323Sed unsigned NumAddrOps = MOs.size(); 3568193323Sed for (unsigned i = 0; i != NumAddrOps; ++i) 3569193323Sed MIB.addOperand(MOs[i]); 3570193323Sed if (NumAddrOps < 4) // FrameIndex only 3571193323Sed addOffset(MIB, 0); 3572218893Sdim 3573193323Sed // Loop over the rest of the ri operands, converting them over. 3574193323Sed unsigned NumOps = MI->getDesc().getNumOperands()-2; 3575193323Sed for (unsigned i = 0; i != NumOps; ++i) { 3576193323Sed MachineOperand &MO = MI->getOperand(i+2); 3577193323Sed MIB.addOperand(MO); 3578193323Sed } 3579193323Sed for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 3580193323Sed MachineOperand &MO = MI->getOperand(i); 3581193323Sed MIB.addOperand(MO); 3582193323Sed } 3583193323Sed return MIB; 3584193323Sed} 3585193323Sed 3586193323Sedstatic MachineInstr *FuseInst(MachineFunction &MF, 3587193323Sed unsigned Opcode, unsigned OpNo, 3588193323Sed const SmallVectorImpl<MachineOperand> &MOs, 3589193323Sed MachineInstr *MI, const TargetInstrInfo &TII) { 3590193323Sed MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3591193323Sed MI->getDebugLoc(), true); 3592193323Sed MachineInstrBuilder MIB(NewMI); 3593218893Sdim 3594193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3595193323Sed MachineOperand &MO = MI->getOperand(i); 3596193323Sed if (i == OpNo) { 3597193323Sed assert(MO.isReg() && "Expected to fold into reg operand!"); 3598193323Sed unsigned NumAddrOps = MOs.size(); 3599193323Sed for (unsigned i = 0; i != NumAddrOps; ++i) 3600193323Sed MIB.addOperand(MOs[i]); 3601193323Sed if (NumAddrOps < 4) // FrameIndex only 3602193323Sed addOffset(MIB, 0); 3603193323Sed } else { 3604193323Sed MIB.addOperand(MO); 3605193323Sed } 3606193323Sed } 3607193323Sed return MIB; 3608193323Sed} 3609193323Sed 3610193323Sedstatic MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 3611193323Sed const SmallVectorImpl<MachineOperand> &MOs, 3612193323Sed MachineInstr *MI) { 3613193323Sed MachineFunction &MF = *MI->getParent()->getParent(); 3614193323Sed MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 3615193323Sed 3616193323Sed unsigned NumAddrOps = MOs.size(); 3617193323Sed for (unsigned i = 0; i != NumAddrOps; ++i) 3618193323Sed MIB.addOperand(MOs[i]); 3619193323Sed if (NumAddrOps < 4) // FrameIndex only 3620193323Sed addOffset(MIB, 0); 3621193323Sed return MIB.addImm(0); 3622193323Sed} 3623193323Sed 3624193323SedMachineInstr* 3625193323SedX86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3626193323Sed MachineInstr *MI, unsigned i, 3627198090Srdivacky const SmallVectorImpl<MachineOperand> &MOs, 3628198090Srdivacky unsigned Size, unsigned Align) const { 3629218893Sdim const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3630193323Sed bool isTwoAddrFold = false; 3631193323Sed unsigned NumOps = MI->getDesc().getNumOperands(); 3632193323Sed bool isTwoAddr = NumOps > 1 && 3633224145Sdim MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3634193323Sed 3635221345Sdim // FIXME: AsmPrinter doesn't know how to handle 3636221345Sdim // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3637221345Sdim if (MI->getOpcode() == X86::ADD32ri && 3638221345Sdim MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3639221345Sdim return NULL; 3640221345Sdim 3641193323Sed MachineInstr *NewMI = NULL; 3642193323Sed // Folding a memory location into the two-address part of a two-address 3643193323Sed // instruction is different than folding it other places. It requires 3644193323Sed // replacing the *two* registers with the memory location. 3645193323Sed if (isTwoAddr && NumOps >= 2 && i < 2 && 3646193323Sed MI->getOperand(0).isReg() && 3647193323Sed MI->getOperand(1).isReg() && 3648218893Sdim MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 3649193323Sed OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3650193323Sed isTwoAddrFold = true; 3651193323Sed } else if (i == 0) { // If operand 0 3652243830Sdim unsigned Opc = 0; 3653243830Sdim switch (MI->getOpcode()) { 3654243830Sdim default: break; 3655243830Sdim case X86::MOV64r0: Opc = X86::MOV64mi32; break; 3656243830Sdim case X86::MOV32r0: Opc = X86::MOV32mi; break; 3657243830Sdim case X86::MOV16r0: Opc = X86::MOV16mi; break; 3658243830Sdim case X86::MOV8r0: Opc = X86::MOV8mi; break; 3659243830Sdim } 3660243830Sdim if (Opc) 3661243830Sdim NewMI = MakeM0Inst(*this, Opc, MOs, MI); 3662193323Sed if (NewMI) 3663193323Sed return NewMI; 3664218893Sdim 3665193323Sed OpcodeTablePtr = &RegOp2MemOpTable0; 3666193323Sed } else if (i == 1) { 3667193323Sed OpcodeTablePtr = &RegOp2MemOpTable1; 3668193323Sed } else if (i == 2) { 3669193323Sed OpcodeTablePtr = &RegOp2MemOpTable2; 3670239462Sdim } else if (i == 3) { 3671239462Sdim OpcodeTablePtr = &RegOp2MemOpTable3; 3672193323Sed } 3673218893Sdim 3674193323Sed // If table selected... 3675193323Sed if (OpcodeTablePtr) { 3676193323Sed // Find the Opcode to fuse 3677218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3678218893Sdim OpcodeTablePtr->find(MI->getOpcode()); 3679193323Sed if (I != OpcodeTablePtr->end()) { 3680198090Srdivacky unsigned Opcode = I->second.first; 3681226633Sdim unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 3682198090Srdivacky if (Align < MinAlign) 3683198090Srdivacky return NULL; 3684198090Srdivacky bool NarrowToMOV32rm = false; 3685198090Srdivacky if (Size) { 3686239462Sdim unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 3687198090Srdivacky if (Size < RCSize) { 3688198090Srdivacky // Check if it's safe to fold the load. If the size of the object is 3689198090Srdivacky // narrower than the load width, then it's not. 3690198090Srdivacky if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 3691198090Srdivacky return NULL; 3692198090Srdivacky // If this is a 64-bit load, but the spill slot is 32, then we can do 3693198090Srdivacky // a 32-bit load which is implicitly zero-extended. This likely is due 3694198090Srdivacky // to liveintervalanalysis remat'ing a load from stack slot. 3695198090Srdivacky if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 3696198090Srdivacky return NULL; 3697198090Srdivacky Opcode = X86::MOV32rm; 3698198090Srdivacky NarrowToMOV32rm = true; 3699198090Srdivacky } 3700198090Srdivacky } 3701198090Srdivacky 3702193323Sed if (isTwoAddrFold) 3703198090Srdivacky NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 3704193323Sed else 3705198090Srdivacky NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 3706198090Srdivacky 3707198090Srdivacky if (NarrowToMOV32rm) { 3708198090Srdivacky // If this is the special case where we use a MOV32rm to load a 32-bit 3709198090Srdivacky // value and zero-extend the top bits. Change the destination register 3710198090Srdivacky // to a 32-bit one. 3711198090Srdivacky unsigned DstReg = NewMI->getOperand(0).getReg(); 3712198090Srdivacky if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 3713198090Srdivacky NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 3714208599Srdivacky X86::sub_32bit)); 3715198090Srdivacky else 3716208599Srdivacky NewMI->getOperand(0).setSubReg(X86::sub_32bit); 3717198090Srdivacky } 3718193323Sed return NewMI; 3719193323Sed } 3720193323Sed } 3721218893Sdim 3722218893Sdim // No fusion 3723210299Sed if (PrintFailedFusing && !MI->isCopy()) 3724202375Srdivacky dbgs() << "We failed to fuse operand " << i << " in " << *MI; 3725193323Sed return NULL; 3726193323Sed} 3727193323Sed 3728226633Sdim/// hasPartialRegUpdate - Return true for all instructions that only update 3729226633Sdim/// the first 32 or 64-bits of the destination register and leave the rest 3730226633Sdim/// unmodified. This can be used to avoid folding loads if the instructions 3731226633Sdim/// only update part of the destination register, and the non-updated part is 3732226633Sdim/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 3733226633Sdim/// instructions breaks the partial register dependency and it can improve 3734226633Sdim/// performance. e.g.: 3735226633Sdim/// 3736226633Sdim/// movss (%rdi), %xmm0 3737226633Sdim/// cvtss2sd %xmm0, %xmm0 3738226633Sdim/// 3739226633Sdim/// Instead of 3740226633Sdim/// cvtss2sd (%rdi), %xmm0 3741226633Sdim/// 3742226633Sdim/// FIXME: This should be turned into a TSFlags. 3743226633Sdim/// 3744226633Sdimstatic bool hasPartialRegUpdate(unsigned Opcode) { 3745226633Sdim switch (Opcode) { 3746234353Sdim case X86::CVTSI2SSrr: 3747234353Sdim case X86::CVTSI2SS64rr: 3748234353Sdim case X86::CVTSI2SDrr: 3749234353Sdim case X86::CVTSI2SD64rr: 3750226633Sdim case X86::CVTSD2SSrr: 3751226633Sdim case X86::Int_CVTSD2SSrr: 3752226633Sdim case X86::CVTSS2SDrr: 3753226633Sdim case X86::Int_CVTSS2SDrr: 3754226633Sdim case X86::RCPSSr: 3755226633Sdim case X86::RCPSSr_Int: 3756226633Sdim case X86::ROUNDSDr: 3757234353Sdim case X86::ROUNDSDr_Int: 3758226633Sdim case X86::ROUNDSSr: 3759234353Sdim case X86::ROUNDSSr_Int: 3760226633Sdim case X86::RSQRTSSr: 3761226633Sdim case X86::RSQRTSSr_Int: 3762226633Sdim case X86::SQRTSSr: 3763226633Sdim case X86::SQRTSSr_Int: 3764226633Sdim // AVX encoded versions 3765226633Sdim case X86::VCVTSD2SSrr: 3766226633Sdim case X86::Int_VCVTSD2SSrr: 3767226633Sdim case X86::VCVTSS2SDrr: 3768226633Sdim case X86::Int_VCVTSS2SDrr: 3769226633Sdim case X86::VRCPSSr: 3770226633Sdim case X86::VROUNDSDr: 3771234353Sdim case X86::VROUNDSDr_Int: 3772226633Sdim case X86::VROUNDSSr: 3773234353Sdim case X86::VROUNDSSr_Int: 3774226633Sdim case X86::VRSQRTSSr: 3775226633Sdim case X86::VSQRTSSr: 3776226633Sdim return true; 3777226633Sdim } 3778193323Sed 3779226633Sdim return false; 3780226633Sdim} 3781226633Sdim 3782234353Sdim/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 3783234353Sdim/// instructions we would like before a partial register update. 3784234353Sdimunsigned X86InstrInfo:: 3785234353SdimgetPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3786234353Sdim const TargetRegisterInfo *TRI) const { 3787234353Sdim if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 3788234353Sdim return 0; 3789234353Sdim 3790234353Sdim // If MI is marked as reading Reg, the partial register update is wanted. 3791234353Sdim const MachineOperand &MO = MI->getOperand(0); 3792234353Sdim unsigned Reg = MO.getReg(); 3793234353Sdim if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3794234353Sdim if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 3795234353Sdim return 0; 3796234353Sdim } else { 3797234353Sdim if (MI->readsRegister(Reg, TRI)) 3798234353Sdim return 0; 3799234353Sdim } 3800234353Sdim 3801234353Sdim // If any of the preceding 16 instructions are reading Reg, insert a 3802234353Sdim // dependency breaking instruction. The magic number is based on a few 3803234353Sdim // Nehalem experiments. 3804234353Sdim return 16; 3805234353Sdim} 3806234353Sdim 3807234353Sdimvoid X86InstrInfo:: 3808234353SdimbreakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 3809234353Sdim const TargetRegisterInfo *TRI) const { 3810234353Sdim unsigned Reg = MI->getOperand(OpNum).getReg(); 3811234353Sdim if (X86::VR128RegClass.contains(Reg)) { 3812234353Sdim // These instructions are all floating point domain, so xorps is the best 3813234353Sdim // choice. 3814234353Sdim bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3815234353Sdim unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 3816234353Sdim BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 3817234353Sdim .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3818234353Sdim } else if (X86::VR256RegClass.contains(Reg)) { 3819234353Sdim // Use vxorps to clear the full ymm register. 3820234353Sdim // It wants to read and write the xmm sub-register. 3821234353Sdim unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 3822234353Sdim BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 3823234353Sdim .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 3824234353Sdim .addReg(Reg, RegState::ImplicitDefine); 3825234353Sdim } else 3826234353Sdim return; 3827234353Sdim MI->addRegisterKilled(Reg, TRI, true); 3828234353Sdim} 3829234353Sdim 3830193323SedMachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3831193323Sed MachineInstr *MI, 3832198090Srdivacky const SmallVectorImpl<unsigned> &Ops, 3833193323Sed int FrameIndex) const { 3834218893Sdim // Check switch flag 3835193323Sed if (NoFusing) return NULL; 3836193323Sed 3837226633Sdim // Unless optimizing for size, don't fold to avoid partial 3838226633Sdim // register update stalls 3839243830Sdim if (!MF.getFunction()->getFnAttributes(). 3840243830Sdim hasAttribute(Attributes::OptimizeForSize) && 3841226633Sdim hasPartialRegUpdate(MI->getOpcode())) 3842226633Sdim return 0; 3843201360Srdivacky 3844193323Sed const MachineFrameInfo *MFI = MF.getFrameInfo(); 3845198090Srdivacky unsigned Size = MFI->getObjectSize(FrameIndex); 3846193323Sed unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 3847193323Sed if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3848193323Sed unsigned NewOpc = 0; 3849198090Srdivacky unsigned RCSize = 0; 3850193323Sed switch (MI->getOpcode()) { 3851193323Sed default: return NULL; 3852198090Srdivacky case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 3853208599Srdivacky case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 3854208599Srdivacky case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 3855208599Srdivacky case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 3856193323Sed } 3857198090Srdivacky // Check if it's safe to fold the load. If the size of the object is 3858198090Srdivacky // narrower than the load width, then it's not. 3859198090Srdivacky if (Size < RCSize) 3860198090Srdivacky return NULL; 3861193323Sed // Change to CMPXXri r, 0 first. 3862193323Sed MI->setDesc(get(NewOpc)); 3863193323Sed MI->getOperand(1).ChangeToImmediate(0); 3864193323Sed } else if (Ops.size() != 1) 3865193323Sed return NULL; 3866193323Sed 3867193323Sed SmallVector<MachineOperand,4> MOs; 3868193323Sed MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 3869198090Srdivacky return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 3870193323Sed} 3871193323Sed 3872193323SedMachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3873193323Sed MachineInstr *MI, 3874198090Srdivacky const SmallVectorImpl<unsigned> &Ops, 3875193323Sed MachineInstr *LoadMI) const { 3876218893Sdim // Check switch flag 3877193323Sed if (NoFusing) return NULL; 3878193323Sed 3879226633Sdim // Unless optimizing for size, don't fold to avoid partial 3880226633Sdim // register update stalls 3881243830Sdim if (!MF.getFunction()->getFnAttributes(). 3882243830Sdim hasAttribute(Attributes::OptimizeForSize) && 3883226633Sdim hasPartialRegUpdate(MI->getOpcode())) 3884226633Sdim return 0; 3885201360Srdivacky 3886193323Sed // Determine the alignment of the load. 3887193323Sed unsigned Alignment = 0; 3888193323Sed if (LoadMI->hasOneMemOperand()) 3889198090Srdivacky Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 3890198090Srdivacky else 3891198090Srdivacky switch (LoadMI->getOpcode()) { 3892234353Sdim case X86::AVX2_SETALLONES: 3893243830Sdim case X86::AVX_SET0: 3894212904Sdim Alignment = 32; 3895212904Sdim break; 3896226633Sdim case X86::V_SET0: 3897198090Srdivacky case X86::V_SETALLONES: 3898198090Srdivacky Alignment = 16; 3899198090Srdivacky break; 3900198090Srdivacky case X86::FsFLD0SD: 3901198090Srdivacky Alignment = 8; 3902198090Srdivacky break; 3903198090Srdivacky case X86::FsFLD0SS: 3904198090Srdivacky Alignment = 4; 3905198090Srdivacky break; 3906198090Srdivacky default: 3907223017Sdim return 0; 3908193323Sed } 3909193323Sed if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3910193323Sed unsigned NewOpc = 0; 3911193323Sed switch (MI->getOpcode()) { 3912193323Sed default: return NULL; 3913193323Sed case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 3914208599Srdivacky case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 3915208599Srdivacky case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 3916208599Srdivacky case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 3917193323Sed } 3918193323Sed // Change to CMPXXri r, 0 first. 3919193323Sed MI->setDesc(get(NewOpc)); 3920193323Sed MI->getOperand(1).ChangeToImmediate(0); 3921193323Sed } else if (Ops.size() != 1) 3922193323Sed return NULL; 3923193323Sed 3924212904Sdim // Make sure the subregisters match. 3925212904Sdim // Otherwise we risk changing the size of the load. 3926212904Sdim if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 3927212904Sdim return NULL; 3928212904Sdim 3929210299Sed SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 3930198090Srdivacky switch (LoadMI->getOpcode()) { 3931226633Sdim case X86::V_SET0: 3932198090Srdivacky case X86::V_SETALLONES: 3933234353Sdim case X86::AVX2_SETALLONES: 3934243830Sdim case X86::AVX_SET0: 3935198090Srdivacky case X86::FsFLD0SD: 3936234353Sdim case X86::FsFLD0SS: { 3937226633Sdim // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 3938193323Sed // Create a constant-pool entry and operands to load from it. 3939193323Sed 3940204961Srdivacky // Medium and large mode can't fold loads this way. 3941204961Srdivacky if (TM.getCodeModel() != CodeModel::Small && 3942204961Srdivacky TM.getCodeModel() != CodeModel::Kernel) 3943204961Srdivacky return NULL; 3944204961Srdivacky 3945193323Sed // x86-32 PIC requires a PIC base register for constant pools. 3946193323Sed unsigned PICBase = 0; 3947198090Srdivacky if (TM.getRelocationModel() == Reloc::PIC_) { 3948198090Srdivacky if (TM.getSubtarget<X86Subtarget>().is64Bit()) 3949198090Srdivacky PICBase = X86::RIP; 3950198090Srdivacky else 3951210299Sed // FIXME: PICBase = getGlobalBaseReg(&MF); 3952198090Srdivacky // This doesn't work for several reasons. 3953198090Srdivacky // 1. GlobalBaseReg may have been spilled. 3954198090Srdivacky // 2. It may not be live at MI. 3955198090Srdivacky return NULL; 3956198090Srdivacky } 3957193323Sed 3958198090Srdivacky // Create a constant-pool entry. 3959193323Sed MachineConstantPool &MCP = *MF.getConstantPool(); 3960226633Sdim Type *Ty; 3961212904Sdim unsigned Opc = LoadMI->getOpcode(); 3962234353Sdim if (Opc == X86::FsFLD0SS) 3963198090Srdivacky Ty = Type::getFloatTy(MF.getFunction()->getContext()); 3964234353Sdim else if (Opc == X86::FsFLD0SD) 3965198090Srdivacky Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 3966243830Sdim else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 3967234353Sdim Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 3968198090Srdivacky else 3969198090Srdivacky Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 3970226633Sdim 3971243830Sdim bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 3972226633Sdim const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 3973226633Sdim Constant::getNullValue(Ty); 3974198090Srdivacky unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 3975193323Sed 3976193323Sed // Create operands to load from the constant pool entry. 3977193323Sed MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 3978193323Sed MOs.push_back(MachineOperand::CreateImm(1)); 3979193323Sed MOs.push_back(MachineOperand::CreateReg(0, false)); 3980193323Sed MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 3981193323Sed MOs.push_back(MachineOperand::CreateReg(0, false)); 3982198090Srdivacky break; 3983198090Srdivacky } 3984198090Srdivacky default: { 3985193323Sed // Folding a normal load. Just copy the load's address operands. 3986193323Sed unsigned NumOps = LoadMI->getDesc().getNumOperands(); 3987210299Sed for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 3988193323Sed MOs.push_back(LoadMI->getOperand(i)); 3989198090Srdivacky break; 3990193323Sed } 3991198090Srdivacky } 3992198090Srdivacky return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 3993193323Sed} 3994193323Sed 3995193323Sed 3996193323Sedbool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 3997193323Sed const SmallVectorImpl<unsigned> &Ops) const { 3998218893Sdim // Check switch flag 3999193323Sed if (NoFusing) return 0; 4000193323Sed 4001193323Sed if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4002193323Sed switch (MI->getOpcode()) { 4003193323Sed default: return false; 4004218893Sdim case X86::TEST8rr: 4005193323Sed case X86::TEST16rr: 4006193323Sed case X86::TEST32rr: 4007193323Sed case X86::TEST64rr: 4008193323Sed return true; 4009221345Sdim case X86::ADD32ri: 4010221345Sdim // FIXME: AsmPrinter doesn't know how to handle 4011221345Sdim // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4012221345Sdim if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4013221345Sdim return false; 4014221345Sdim break; 4015193323Sed } 4016193323Sed } 4017193323Sed 4018193323Sed if (Ops.size() != 1) 4019193323Sed return false; 4020193323Sed 4021193323Sed unsigned OpNum = Ops[0]; 4022193323Sed unsigned Opc = MI->getOpcode(); 4023193323Sed unsigned NumOps = MI->getDesc().getNumOperands(); 4024193323Sed bool isTwoAddr = NumOps > 1 && 4025224145Sdim MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4026193323Sed 4027193323Sed // Folding a memory location into the two-address part of a two-address 4028193323Sed // instruction is different than folding it other places. It requires 4029193323Sed // replacing the *two* registers with the memory location. 4030218893Sdim const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 4031218893Sdim if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4032193323Sed OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4033193323Sed } else if (OpNum == 0) { // If operand 0 4034193323Sed switch (Opc) { 4035198090Srdivacky case X86::MOV8r0: 4036202375Srdivacky case X86::MOV16r0: 4037193323Sed case X86::MOV32r0: 4038218893Sdim case X86::MOV64r0: return true; 4039193323Sed default: break; 4040193323Sed } 4041193323Sed OpcodeTablePtr = &RegOp2MemOpTable0; 4042193323Sed } else if (OpNum == 1) { 4043193323Sed OpcodeTablePtr = &RegOp2MemOpTable1; 4044193323Sed } else if (OpNum == 2) { 4045193323Sed OpcodeTablePtr = &RegOp2MemOpTable2; 4046243830Sdim } else if (OpNum == 3) { 4047243830Sdim OpcodeTablePtr = &RegOp2MemOpTable3; 4048193323Sed } 4049218893Sdim 4050218893Sdim if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4051218893Sdim return true; 4052210299Sed return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); 4053193323Sed} 4054193323Sed 4055193323Sedbool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4056193323Sed unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4057193323Sed SmallVectorImpl<MachineInstr*> &NewMIs) const { 4058218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4059218893Sdim MemOp2RegOpTable.find(MI->getOpcode()); 4060193323Sed if (I == MemOp2RegOpTable.end()) 4061193323Sed return false; 4062193323Sed unsigned Opc = I->second.first; 4063226633Sdim unsigned Index = I->second.second & TB_INDEX_MASK; 4064226633Sdim bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4065226633Sdim bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4066193323Sed if (UnfoldLoad && !FoldedLoad) 4067193323Sed return false; 4068193323Sed UnfoldLoad &= FoldedLoad; 4069193323Sed if (UnfoldStore && !FoldedStore) 4070193323Sed return false; 4071193323Sed UnfoldStore &= FoldedStore; 4072193323Sed 4073224145Sdim const MCInstrDesc &MCID = get(Opc); 4074239462Sdim const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4075210299Sed if (!MI->hasOneMemOperand() && 4076210299Sed RC == &X86::VR128RegClass && 4077210299Sed !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4078210299Sed // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4079210299Sed // conservatively assume the address is unaligned. That's bad for 4080210299Sed // performance. 4081210299Sed return false; 4082210299Sed SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4083193323Sed SmallVector<MachineOperand,2> BeforeOps; 4084193323Sed SmallVector<MachineOperand,2> AfterOps; 4085193323Sed SmallVector<MachineOperand,4> ImpOps; 4086193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4087193323Sed MachineOperand &Op = MI->getOperand(i); 4088210299Sed if (i >= Index && i < Index + X86::AddrNumOperands) 4089193323Sed AddrOps.push_back(Op); 4090193323Sed else if (Op.isReg() && Op.isImplicit()) 4091193323Sed ImpOps.push_back(Op); 4092193323Sed else if (i < Index) 4093193323Sed BeforeOps.push_back(Op); 4094193323Sed else if (i > Index) 4095193323Sed AfterOps.push_back(Op); 4096193323Sed } 4097193323Sed 4098193323Sed // Emit the load instruction. 4099193323Sed if (UnfoldLoad) { 4100198090Srdivacky std::pair<MachineInstr::mmo_iterator, 4101198090Srdivacky MachineInstr::mmo_iterator> MMOs = 4102198090Srdivacky MF.extractLoadMemRefs(MI->memoperands_begin(), 4103198090Srdivacky MI->memoperands_end()); 4104198090Srdivacky loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4105193323Sed if (UnfoldStore) { 4106193323Sed // Address operands cannot be marked isKill. 4107210299Sed for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4108193323Sed MachineOperand &MO = NewMIs[0]->getOperand(i); 4109193323Sed if (MO.isReg()) 4110193323Sed MO.setIsKill(false); 4111193323Sed } 4112193323Sed } 4113193323Sed } 4114193323Sed 4115193323Sed // Emit the data processing instruction. 4116224145Sdim MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4117193323Sed MachineInstrBuilder MIB(DataMI); 4118218893Sdim 4119193323Sed if (FoldedStore) 4120193323Sed MIB.addReg(Reg, RegState::Define); 4121193323Sed for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4122193323Sed MIB.addOperand(BeforeOps[i]); 4123193323Sed if (FoldedLoad) 4124193323Sed MIB.addReg(Reg); 4125193323Sed for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4126193323Sed MIB.addOperand(AfterOps[i]); 4127193323Sed for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4128193323Sed MachineOperand &MO = ImpOps[i]; 4129193323Sed MIB.addReg(MO.getReg(), 4130193323Sed getDefRegState(MO.isDef()) | 4131193323Sed RegState::Implicit | 4132193323Sed getKillRegState(MO.isKill()) | 4133195340Sed getDeadRegState(MO.isDead()) | 4134195340Sed getUndefRegState(MO.isUndef())); 4135193323Sed } 4136193323Sed // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4137193323Sed switch (DataMI->getOpcode()) { 4138193323Sed default: break; 4139193323Sed case X86::CMP64ri32: 4140208599Srdivacky case X86::CMP64ri8: 4141193323Sed case X86::CMP32ri: 4142208599Srdivacky case X86::CMP32ri8: 4143193323Sed case X86::CMP16ri: 4144208599Srdivacky case X86::CMP16ri8: 4145193323Sed case X86::CMP8ri: { 4146193323Sed MachineOperand &MO0 = DataMI->getOperand(0); 4147193323Sed MachineOperand &MO1 = DataMI->getOperand(1); 4148193323Sed if (MO1.getImm() == 0) { 4149243830Sdim unsigned NewOpc; 4150193323Sed switch (DataMI->getOpcode()) { 4151243830Sdim default: llvm_unreachable("Unreachable!"); 4152208599Srdivacky case X86::CMP64ri8: 4153193323Sed case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4154208599Srdivacky case X86::CMP32ri8: 4155193323Sed case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4156208599Srdivacky case X86::CMP16ri8: 4157193323Sed case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4158193323Sed case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4159193323Sed } 4160193323Sed DataMI->setDesc(get(NewOpc)); 4161193323Sed MO1.ChangeToRegister(MO0.getReg(), false); 4162193323Sed } 4163193323Sed } 4164193323Sed } 4165193323Sed NewMIs.push_back(DataMI); 4166193323Sed 4167193323Sed // Emit the store instruction. 4168193323Sed if (UnfoldStore) { 4169239462Sdim const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4170198090Srdivacky std::pair<MachineInstr::mmo_iterator, 4171198090Srdivacky MachineInstr::mmo_iterator> MMOs = 4172198090Srdivacky MF.extractStoreMemRefs(MI->memoperands_begin(), 4173198090Srdivacky MI->memoperands_end()); 4174198090Srdivacky storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4175193323Sed } 4176193323Sed 4177193323Sed return true; 4178193323Sed} 4179193323Sed 4180193323Sedbool 4181193323SedX86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4182193323Sed SmallVectorImpl<SDNode*> &NewNodes) const { 4183193323Sed if (!N->isMachineOpcode()) 4184193323Sed return false; 4185193323Sed 4186218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4187218893Sdim MemOp2RegOpTable.find(N->getMachineOpcode()); 4188193323Sed if (I == MemOp2RegOpTable.end()) 4189193323Sed return false; 4190193323Sed unsigned Opc = I->second.first; 4191226633Sdim unsigned Index = I->second.second & TB_INDEX_MASK; 4192226633Sdim bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4193226633Sdim bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4194224145Sdim const MCInstrDesc &MCID = get(Opc); 4195239462Sdim MachineFunction &MF = DAG.getMachineFunction(); 4196239462Sdim const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4197224145Sdim unsigned NumDefs = MCID.NumDefs; 4198193323Sed std::vector<SDValue> AddrOps; 4199193323Sed std::vector<SDValue> BeforeOps; 4200193323Sed std::vector<SDValue> AfterOps; 4201193323Sed DebugLoc dl = N->getDebugLoc(); 4202193323Sed unsigned NumOps = N->getNumOperands(); 4203193323Sed for (unsigned i = 0; i != NumOps-1; ++i) { 4204193323Sed SDValue Op = N->getOperand(i); 4205210299Sed if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4206193323Sed AddrOps.push_back(Op); 4207193323Sed else if (i < Index-NumDefs) 4208193323Sed BeforeOps.push_back(Op); 4209193323Sed else if (i > Index-NumDefs) 4210193323Sed AfterOps.push_back(Op); 4211193323Sed } 4212193323Sed SDValue Chain = N->getOperand(NumOps-1); 4213193323Sed AddrOps.push_back(Chain); 4214193323Sed 4215193323Sed // Emit the load instruction. 4216193323Sed SDNode *Load = 0; 4217193323Sed if (FoldedLoad) { 4218198090Srdivacky EVT VT = *RC->vt_begin(); 4219199481Srdivacky std::pair<MachineInstr::mmo_iterator, 4220199481Srdivacky MachineInstr::mmo_iterator> MMOs = 4221199481Srdivacky MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4222199481Srdivacky cast<MachineSDNode>(N)->memoperands_end()); 4223210299Sed if (!(*MMOs.first) && 4224210299Sed RC == &X86::VR128RegClass && 4225210299Sed !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4226210299Sed // Do not introduce a slow unaligned load. 4227210299Sed return false; 4228226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4229226633Sdim bool isAligned = (*MMOs.first) && 4230226633Sdim (*MMOs.first)->getAlignment() >= Alignment; 4231198090Srdivacky Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 4232198090Srdivacky VT, MVT::Other, &AddrOps[0], AddrOps.size()); 4233193323Sed NewNodes.push_back(Load); 4234198090Srdivacky 4235198090Srdivacky // Preserve memory reference information. 4236198090Srdivacky cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4237193323Sed } 4238193323Sed 4239193323Sed // Emit the data processing instruction. 4240198090Srdivacky std::vector<EVT> VTs; 4241193323Sed const TargetRegisterClass *DstRC = 0; 4242224145Sdim if (MCID.getNumDefs() > 0) { 4243239462Sdim DstRC = getRegClass(MCID, 0, &RI, MF); 4244193323Sed VTs.push_back(*DstRC->vt_begin()); 4245193323Sed } 4246193323Sed for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4247198090Srdivacky EVT VT = N->getValueType(i); 4248224145Sdim if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4249193323Sed VTs.push_back(VT); 4250193323Sed } 4251193323Sed if (Load) 4252193323Sed BeforeOps.push_back(SDValue(Load, 0)); 4253193323Sed std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4254198090Srdivacky SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 4255198090Srdivacky BeforeOps.size()); 4256193323Sed NewNodes.push_back(NewNode); 4257193323Sed 4258193323Sed // Emit the store instruction. 4259193323Sed if (FoldedStore) { 4260193323Sed AddrOps.pop_back(); 4261193323Sed AddrOps.push_back(SDValue(NewNode, 0)); 4262193323Sed AddrOps.push_back(Chain); 4263199481Srdivacky std::pair<MachineInstr::mmo_iterator, 4264199481Srdivacky MachineInstr::mmo_iterator> MMOs = 4265199481Srdivacky MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4266199481Srdivacky cast<MachineSDNode>(N)->memoperands_end()); 4267210299Sed if (!(*MMOs.first) && 4268210299Sed RC == &X86::VR128RegClass && 4269210299Sed !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4270210299Sed // Do not introduce a slow unaligned store. 4271210299Sed return false; 4272226633Sdim unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4273226633Sdim bool isAligned = (*MMOs.first) && 4274226633Sdim (*MMOs.first)->getAlignment() >= Alignment; 4275198090Srdivacky SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 4276198090Srdivacky isAligned, TM), 4277198090Srdivacky dl, MVT::Other, 4278198090Srdivacky &AddrOps[0], AddrOps.size()); 4279193323Sed NewNodes.push_back(Store); 4280198090Srdivacky 4281198090Srdivacky // Preserve memory reference information. 4282198090Srdivacky cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4283193323Sed } 4284193323Sed 4285193323Sed return true; 4286193323Sed} 4287193323Sed 4288193323Sedunsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4289198892Srdivacky bool UnfoldLoad, bool UnfoldStore, 4290198892Srdivacky unsigned *LoadRegIndex) const { 4291218893Sdim DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4292218893Sdim MemOp2RegOpTable.find(Opc); 4293193323Sed if (I == MemOp2RegOpTable.end()) 4294193323Sed return 0; 4295226633Sdim bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4296226633Sdim bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4297193323Sed if (UnfoldLoad && !FoldedLoad) 4298193323Sed return 0; 4299193323Sed if (UnfoldStore && !FoldedStore) 4300193323Sed return 0; 4301198892Srdivacky if (LoadRegIndex) 4302226633Sdim *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4303193323Sed return I->second.first; 4304193323Sed} 4305193323Sed 4306202878Srdivackybool 4307202878SrdivackyX86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4308202878Srdivacky int64_t &Offset1, int64_t &Offset2) const { 4309202878Srdivacky if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4310202878Srdivacky return false; 4311202878Srdivacky unsigned Opc1 = Load1->getMachineOpcode(); 4312202878Srdivacky unsigned Opc2 = Load2->getMachineOpcode(); 4313202878Srdivacky switch (Opc1) { 4314202878Srdivacky default: return false; 4315202878Srdivacky case X86::MOV8rm: 4316202878Srdivacky case X86::MOV16rm: 4317202878Srdivacky case X86::MOV32rm: 4318202878Srdivacky case X86::MOV64rm: 4319202878Srdivacky case X86::LD_Fp32m: 4320202878Srdivacky case X86::LD_Fp64m: 4321202878Srdivacky case X86::LD_Fp80m: 4322202878Srdivacky case X86::MOVSSrm: 4323202878Srdivacky case X86::MOVSDrm: 4324202878Srdivacky case X86::MMX_MOVD64rm: 4325202878Srdivacky case X86::MMX_MOVQ64rm: 4326202878Srdivacky case X86::FsMOVAPSrm: 4327202878Srdivacky case X86::FsMOVAPDrm: 4328202878Srdivacky case X86::MOVAPSrm: 4329202878Srdivacky case X86::MOVUPSrm: 4330202878Srdivacky case X86::MOVAPDrm: 4331202878Srdivacky case X86::MOVDQArm: 4332202878Srdivacky case X86::MOVDQUrm: 4333226633Sdim // AVX load instructions 4334226633Sdim case X86::VMOVSSrm: 4335226633Sdim case X86::VMOVSDrm: 4336226633Sdim case X86::FsVMOVAPSrm: 4337226633Sdim case X86::FsVMOVAPDrm: 4338226633Sdim case X86::VMOVAPSrm: 4339226633Sdim case X86::VMOVUPSrm: 4340226633Sdim case X86::VMOVAPDrm: 4341226633Sdim case X86::VMOVDQArm: 4342226633Sdim case X86::VMOVDQUrm: 4343224145Sdim case X86::VMOVAPSYrm: 4344224145Sdim case X86::VMOVUPSYrm: 4345224145Sdim case X86::VMOVAPDYrm: 4346224145Sdim case X86::VMOVDQAYrm: 4347224145Sdim case X86::VMOVDQUYrm: 4348202878Srdivacky break; 4349202878Srdivacky } 4350202878Srdivacky switch (Opc2) { 4351202878Srdivacky default: return false; 4352202878Srdivacky case X86::MOV8rm: 4353202878Srdivacky case X86::MOV16rm: 4354202878Srdivacky case X86::MOV32rm: 4355202878Srdivacky case X86::MOV64rm: 4356202878Srdivacky case X86::LD_Fp32m: 4357202878Srdivacky case X86::LD_Fp64m: 4358202878Srdivacky case X86::LD_Fp80m: 4359202878Srdivacky case X86::MOVSSrm: 4360202878Srdivacky case X86::MOVSDrm: 4361202878Srdivacky case X86::MMX_MOVD64rm: 4362202878Srdivacky case X86::MMX_MOVQ64rm: 4363202878Srdivacky case X86::FsMOVAPSrm: 4364202878Srdivacky case X86::FsMOVAPDrm: 4365202878Srdivacky case X86::MOVAPSrm: 4366202878Srdivacky case X86::MOVUPSrm: 4367202878Srdivacky case X86::MOVAPDrm: 4368202878Srdivacky case X86::MOVDQArm: 4369202878Srdivacky case X86::MOVDQUrm: 4370226633Sdim // AVX load instructions 4371226633Sdim case X86::VMOVSSrm: 4372226633Sdim case X86::VMOVSDrm: 4373226633Sdim case X86::FsVMOVAPSrm: 4374226633Sdim case X86::FsVMOVAPDrm: 4375226633Sdim case X86::VMOVAPSrm: 4376226633Sdim case X86::VMOVUPSrm: 4377226633Sdim case X86::VMOVAPDrm: 4378226633Sdim case X86::VMOVDQArm: 4379226633Sdim case X86::VMOVDQUrm: 4380224145Sdim case X86::VMOVAPSYrm: 4381224145Sdim case X86::VMOVUPSYrm: 4382224145Sdim case X86::VMOVAPDYrm: 4383224145Sdim case X86::VMOVDQAYrm: 4384224145Sdim case X86::VMOVDQUYrm: 4385202878Srdivacky break; 4386202878Srdivacky } 4387202878Srdivacky 4388202878Srdivacky // Check if chain operands and base addresses match. 4389202878Srdivacky if (Load1->getOperand(0) != Load2->getOperand(0) || 4390202878Srdivacky Load1->getOperand(5) != Load2->getOperand(5)) 4391202878Srdivacky return false; 4392202878Srdivacky // Segment operands should match as well. 4393202878Srdivacky if (Load1->getOperand(4) != Load2->getOperand(4)) 4394202878Srdivacky return false; 4395202878Srdivacky // Scale should be 1, Index should be Reg0. 4396202878Srdivacky if (Load1->getOperand(1) == Load2->getOperand(1) && 4397202878Srdivacky Load1->getOperand(2) == Load2->getOperand(2)) { 4398202878Srdivacky if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4399202878Srdivacky return false; 4400202878Srdivacky 4401202878Srdivacky // Now let's examine the displacements. 4402202878Srdivacky if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4403202878Srdivacky isa<ConstantSDNode>(Load2->getOperand(3))) { 4404202878Srdivacky Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4405202878Srdivacky Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4406202878Srdivacky return true; 4407202878Srdivacky } 4408202878Srdivacky } 4409202878Srdivacky return false; 4410202878Srdivacky} 4411202878Srdivacky 4412202878Srdivackybool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4413202878Srdivacky int64_t Offset1, int64_t Offset2, 4414202878Srdivacky unsigned NumLoads) const { 4415202878Srdivacky assert(Offset2 > Offset1); 4416202878Srdivacky if ((Offset2 - Offset1) / 8 > 64) 4417202878Srdivacky return false; 4418202878Srdivacky 4419202878Srdivacky unsigned Opc1 = Load1->getMachineOpcode(); 4420202878Srdivacky unsigned Opc2 = Load2->getMachineOpcode(); 4421202878Srdivacky if (Opc1 != Opc2) 4422202878Srdivacky return false; // FIXME: overly conservative? 4423202878Srdivacky 4424202878Srdivacky switch (Opc1) { 4425202878Srdivacky default: break; 4426202878Srdivacky case X86::LD_Fp32m: 4427202878Srdivacky case X86::LD_Fp64m: 4428202878Srdivacky case X86::LD_Fp80m: 4429202878Srdivacky case X86::MMX_MOVD64rm: 4430202878Srdivacky case X86::MMX_MOVQ64rm: 4431202878Srdivacky return false; 4432202878Srdivacky } 4433202878Srdivacky 4434202878Srdivacky EVT VT = Load1->getValueType(0); 4435202878Srdivacky switch (VT.getSimpleVT().SimpleTy) { 4436210299Sed default: 4437202878Srdivacky // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4438202878Srdivacky // have 16 of them to play with. 4439202878Srdivacky if (TM.getSubtargetImpl()->is64Bit()) { 4440202878Srdivacky if (NumLoads >= 3) 4441202878Srdivacky return false; 4442210299Sed } else if (NumLoads) { 4443202878Srdivacky return false; 4444210299Sed } 4445202878Srdivacky break; 4446202878Srdivacky case MVT::i8: 4447202878Srdivacky case MVT::i16: 4448202878Srdivacky case MVT::i32: 4449202878Srdivacky case MVT::i64: 4450202878Srdivacky case MVT::f32: 4451202878Srdivacky case MVT::f64: 4452202878Srdivacky if (NumLoads) 4453202878Srdivacky return false; 4454210299Sed break; 4455202878Srdivacky } 4456202878Srdivacky 4457202878Srdivacky return true; 4458202878Srdivacky} 4459202878Srdivacky 4460202878Srdivacky 4461193323Sedbool X86InstrInfo:: 4462193323SedReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4463193323Sed assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 4464193323Sed X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 4465193323Sed if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 4466193323Sed return true; 4467193323Sed Cond[0].setImm(GetOppositeBranchCondition(CC)); 4468193323Sed return false; 4469193323Sed} 4470193323Sed 4471193323Sedbool X86InstrInfo:: 4472193323SedisSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 4473193323Sed // FIXME: Return false for x87 stack register classes for now. We can't 4474193323Sed // allow any loads of these registers before FpGet_ST0_80. 4475193323Sed return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 4476193323Sed RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 4477193323Sed} 4478193323Sed 4479193323Sed/// getGlobalBaseReg - Return a virtual register initialized with the 4480193323Sed/// the global base register value. Output instructions required to 4481193323Sed/// initialize the register in the function entry block, if necessary. 4482193323Sed/// 4483210299Sed/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 4484210299Sed/// 4485193323Sedunsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 4486193323Sed assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 4487193323Sed "X86-64 PIC uses RIP relative addressing"); 4488193323Sed 4489193323Sed X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 4490193323Sed unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4491193323Sed if (GlobalBaseReg != 0) 4492193323Sed return GlobalBaseReg; 4493193323Sed 4494210299Sed // Create the register. The code to initialize it is inserted 4495210299Sed // later, by the CGBR pass (below). 4496193323Sed MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4497239462Sdim GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4498193323Sed X86FI->setGlobalBaseReg(GlobalBaseReg); 4499193323Sed return GlobalBaseReg; 4500193323Sed} 4501206083Srdivacky 4502206083Srdivacky// These are the replaceable SSE instructions. Some of these have Int variants 4503206083Srdivacky// that we don't include here. We don't want to replace instructions selected 4504206083Srdivacky// by intrinsics. 4505234353Sdimstatic const uint16_t ReplaceableInstrs[][3] = { 4506212904Sdim //PackedSingle PackedDouble PackedInt 4507206083Srdivacky { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 4508206083Srdivacky { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 4509206083Srdivacky { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 4510206083Srdivacky { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 4511206083Srdivacky { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 4512206083Srdivacky { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 4513206083Srdivacky { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 4514206083Srdivacky { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 4515206083Srdivacky { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 4516206083Srdivacky { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 4517206083Srdivacky { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 4518206083Srdivacky { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 4519206083Srdivacky { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 4520206083Srdivacky { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 4521212904Sdim // AVX 128-bit support 4522212904Sdim { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 4523212904Sdim { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 4524212904Sdim { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 4525212904Sdim { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 4526212904Sdim { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 4527212904Sdim { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 4528212904Sdim { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 4529212904Sdim { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 4530212904Sdim { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 4531212904Sdim { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 4532212904Sdim { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 4533212904Sdim { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 4534212904Sdim { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 4535212904Sdim { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 4536224145Sdim // AVX 256-bit support 4537224145Sdim { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 4538224145Sdim { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 4539224145Sdim { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 4540224145Sdim { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 4541224145Sdim { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 4542234353Sdim { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 4543206083Srdivacky}; 4544206083Srdivacky 4545234353Sdimstatic const uint16_t ReplaceableInstrsAVX2[][3] = { 4546234353Sdim //PackedSingle PackedDouble PackedInt 4547234353Sdim { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 4548234353Sdim { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 4549234353Sdim { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 4550234353Sdim { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 4551234353Sdim { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 4552234353Sdim { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 4553234353Sdim { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 4554234353Sdim { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 4555234353Sdim { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 4556234353Sdim { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 4557234353Sdim { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 4558234353Sdim { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 4559234353Sdim { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 4560234353Sdim { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr } 4561234353Sdim}; 4562234353Sdim 4563206083Srdivacky// FIXME: Some shuffle and unpack instructions have equivalents in different 4564206083Srdivacky// domains, but they require a bit more work than just switching opcodes. 4565206083Srdivacky 4566234353Sdimstatic const uint16_t *lookup(unsigned opcode, unsigned domain) { 4567206083Srdivacky for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 4568206083Srdivacky if (ReplaceableInstrs[i][domain-1] == opcode) 4569206083Srdivacky return ReplaceableInstrs[i]; 4570206083Srdivacky return 0; 4571206083Srdivacky} 4572206083Srdivacky 4573234353Sdimstatic const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 4574234353Sdim for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 4575234353Sdim if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 4576234353Sdim return ReplaceableInstrsAVX2[i]; 4577234353Sdim return 0; 4578234353Sdim} 4579234353Sdim 4580206083Srdivackystd::pair<uint16_t, uint16_t> 4581226633SdimX86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 4582206083Srdivacky uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4583234353Sdim bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2(); 4584234353Sdim uint16_t validDomains = 0; 4585234353Sdim if (domain && lookup(MI->getOpcode(), domain)) 4586234353Sdim validDomains = 0xe; 4587234353Sdim else if (domain && lookupAVX2(MI->getOpcode(), domain)) 4588234353Sdim validDomains = hasAVX2 ? 0xe : 0x6; 4589234353Sdim return std::make_pair(domain, validDomains); 4590206083Srdivacky} 4591206083Srdivacky 4592226633Sdimvoid X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4593206083Srdivacky assert(Domain>0 && Domain<4 && "Invalid execution domain"); 4594206083Srdivacky uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4595206083Srdivacky assert(dom && "Not an SSE instruction"); 4596234353Sdim const uint16_t *table = lookup(MI->getOpcode(), dom); 4597234353Sdim if (!table) { // try the other table 4598234353Sdim assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) && 4599234353Sdim "256-bit vector operations only available in AVX2"); 4600234353Sdim table = lookupAVX2(MI->getOpcode(), dom); 4601234353Sdim } 4602206083Srdivacky assert(table && "Cannot change domain"); 4603206083Srdivacky MI->setDesc(get(table[Domain-1])); 4604206083Srdivacky} 4605207618Srdivacky 4606207618Srdivacky/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 4607207618Srdivackyvoid X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 4608207618Srdivacky NopInst.setOpcode(X86::NOOP); 4609207618Srdivacky} 4610207618Srdivacky 4611221345Sdimbool X86InstrInfo::isHighLatencyDef(int opc) const { 4612221345Sdim switch (opc) { 4613218893Sdim default: return false; 4614218893Sdim case X86::DIVSDrm: 4615218893Sdim case X86::DIVSDrm_Int: 4616218893Sdim case X86::DIVSDrr: 4617218893Sdim case X86::DIVSDrr_Int: 4618218893Sdim case X86::DIVSSrm: 4619218893Sdim case X86::DIVSSrm_Int: 4620218893Sdim case X86::DIVSSrr: 4621218893Sdim case X86::DIVSSrr_Int: 4622218893Sdim case X86::SQRTPDm: 4623218893Sdim case X86::SQRTPDm_Int: 4624218893Sdim case X86::SQRTPDr: 4625218893Sdim case X86::SQRTPDr_Int: 4626218893Sdim case X86::SQRTPSm: 4627218893Sdim case X86::SQRTPSm_Int: 4628218893Sdim case X86::SQRTPSr: 4629218893Sdim case X86::SQRTPSr_Int: 4630218893Sdim case X86::SQRTSDm: 4631218893Sdim case X86::SQRTSDm_Int: 4632218893Sdim case X86::SQRTSDr: 4633218893Sdim case X86::SQRTSDr_Int: 4634218893Sdim case X86::SQRTSSm: 4635218893Sdim case X86::SQRTSSm_Int: 4636218893Sdim case X86::SQRTSSr: 4637218893Sdim case X86::SQRTSSr_Int: 4638226633Sdim // AVX instructions with high latency 4639226633Sdim case X86::VDIVSDrm: 4640226633Sdim case X86::VDIVSDrm_Int: 4641226633Sdim case X86::VDIVSDrr: 4642226633Sdim case X86::VDIVSDrr_Int: 4643226633Sdim case X86::VDIVSSrm: 4644226633Sdim case X86::VDIVSSrm_Int: 4645226633Sdim case X86::VDIVSSrr: 4646226633Sdim case X86::VDIVSSrr_Int: 4647226633Sdim case X86::VSQRTPDm: 4648226633Sdim case X86::VSQRTPDm_Int: 4649226633Sdim case X86::VSQRTPDr: 4650226633Sdim case X86::VSQRTPDr_Int: 4651226633Sdim case X86::VSQRTPSm: 4652226633Sdim case X86::VSQRTPSm_Int: 4653226633Sdim case X86::VSQRTPSr: 4654226633Sdim case X86::VSQRTPSr_Int: 4655226633Sdim case X86::VSQRTSDm: 4656226633Sdim case X86::VSQRTSDm_Int: 4657226633Sdim case X86::VSQRTSDr: 4658226633Sdim case X86::VSQRTSSm: 4659226633Sdim case X86::VSQRTSSm_Int: 4660226633Sdim case X86::VSQRTSSr: 4661218893Sdim return true; 4662218893Sdim } 4663218893Sdim} 4664218893Sdim 4665221345Sdimbool X86InstrInfo:: 4666221345SdimhasHighOperandLatency(const InstrItineraryData *ItinData, 4667221345Sdim const MachineRegisterInfo *MRI, 4668221345Sdim const MachineInstr *DefMI, unsigned DefIdx, 4669221345Sdim const MachineInstr *UseMI, unsigned UseIdx) const { 4670221345Sdim return isHighLatencyDef(DefMI->getOpcode()); 4671221345Sdim} 4672221345Sdim 4673210299Sednamespace { 4674210299Sed /// CGBR - Create Global Base Reg pass. This initializes the PIC 4675210299Sed /// global base register for x86-32. 4676210299Sed struct CGBR : public MachineFunctionPass { 4677210299Sed static char ID; 4678212904Sdim CGBR() : MachineFunctionPass(ID) {} 4679210299Sed 4680210299Sed virtual bool runOnMachineFunction(MachineFunction &MF) { 4681210299Sed const X86TargetMachine *TM = 4682210299Sed static_cast<const X86TargetMachine *>(&MF.getTarget()); 4683210299Sed 4684210299Sed assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 4685210299Sed "X86-64 PIC uses RIP relative addressing"); 4686210299Sed 4687210299Sed // Only emit a global base reg in PIC mode. 4688210299Sed if (TM->getRelocationModel() != Reloc::PIC_) 4689210299Sed return false; 4690210299Sed 4691218893Sdim X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 4692218893Sdim unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4693218893Sdim 4694218893Sdim // If we didn't need a GlobalBaseReg, don't insert code. 4695218893Sdim if (GlobalBaseReg == 0) 4696218893Sdim return false; 4697218893Sdim 4698210299Sed // Insert the set of GlobalBaseReg into the first MBB of the function 4699210299Sed MachineBasicBlock &FirstMBB = MF.front(); 4700210299Sed MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 4701210299Sed DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 4702210299Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4703210299Sed const X86InstrInfo *TII = TM->getInstrInfo(); 4704210299Sed 4705210299Sed unsigned PC; 4706210299Sed if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 4707239462Sdim PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4708210299Sed else 4709218893Sdim PC = GlobalBaseReg; 4710218893Sdim 4711210299Sed // Operand of MovePCtoStack is completely ignored by asm printer. It's 4712210299Sed // only used in JIT code emission as displacement to pc. 4713210299Sed BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 4714218893Sdim 4715210299Sed // If we're using vanilla 'GOT' PIC style, we should use relative addressing 4716210299Sed // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 4717210299Sed if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 4718210299Sed // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 4719210299Sed BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 4720210299Sed .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 4721210299Sed X86II::MO_GOT_ABSOLUTE_ADDRESS); 4722210299Sed } 4723210299Sed 4724210299Sed return true; 4725210299Sed } 4726210299Sed 4727210299Sed virtual const char *getPassName() const { 4728210299Sed return "X86 PIC Global Base Reg Initialization"; 4729210299Sed } 4730210299Sed 4731210299Sed virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4732210299Sed AU.setPreservesCFG(); 4733210299Sed MachineFunctionPass::getAnalysisUsage(AU); 4734210299Sed } 4735210299Sed }; 4736210299Sed} 4737210299Sed 4738210299Sedchar CGBR::ID = 0; 4739210299SedFunctionPass* 4740210299Sedllvm::createGlobalBaseRegPass() { return new CGBR(); } 4741239462Sdim 4742239462Sdimnamespace { 4743239462Sdim struct LDTLSCleanup : public MachineFunctionPass { 4744239462Sdim static char ID; 4745239462Sdim LDTLSCleanup() : MachineFunctionPass(ID) {} 4746239462Sdim 4747239462Sdim virtual bool runOnMachineFunction(MachineFunction &MF) { 4748239462Sdim X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 4749239462Sdim if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 4750239462Sdim // No point folding accesses if there isn't at least two. 4751239462Sdim return false; 4752239462Sdim } 4753239462Sdim 4754239462Sdim MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 4755239462Sdim return VisitNode(DT->getRootNode(), 0); 4756239462Sdim } 4757239462Sdim 4758239462Sdim // Visit the dominator subtree rooted at Node in pre-order. 4759239462Sdim // If TLSBaseAddrReg is non-null, then use that to replace any 4760239462Sdim // TLS_base_addr instructions. Otherwise, create the register 4761239462Sdim // when the first such instruction is seen, and then use it 4762239462Sdim // as we encounter more instructions. 4763239462Sdim bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 4764239462Sdim MachineBasicBlock *BB = Node->getBlock(); 4765239462Sdim bool Changed = false; 4766239462Sdim 4767239462Sdim // Traverse the current block. 4768239462Sdim for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 4769239462Sdim ++I) { 4770239462Sdim switch (I->getOpcode()) { 4771239462Sdim case X86::TLS_base_addr32: 4772239462Sdim case X86::TLS_base_addr64: 4773239462Sdim if (TLSBaseAddrReg) 4774239462Sdim I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 4775239462Sdim else 4776239462Sdim I = SetRegister(I, &TLSBaseAddrReg); 4777239462Sdim Changed = true; 4778239462Sdim break; 4779239462Sdim default: 4780239462Sdim break; 4781239462Sdim } 4782239462Sdim } 4783239462Sdim 4784239462Sdim // Visit the children of this block in the dominator tree. 4785239462Sdim for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 4786239462Sdim I != E; ++I) { 4787239462Sdim Changed |= VisitNode(*I, TLSBaseAddrReg); 4788239462Sdim } 4789239462Sdim 4790239462Sdim return Changed; 4791239462Sdim } 4792239462Sdim 4793239462Sdim // Replace the TLS_base_addr instruction I with a copy from 4794239462Sdim // TLSBaseAddrReg, returning the new instruction. 4795239462Sdim MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 4796239462Sdim unsigned TLSBaseAddrReg) { 4797239462Sdim MachineFunction *MF = I->getParent()->getParent(); 4798239462Sdim const X86TargetMachine *TM = 4799239462Sdim static_cast<const X86TargetMachine *>(&MF->getTarget()); 4800239462Sdim const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4801239462Sdim const X86InstrInfo *TII = TM->getInstrInfo(); 4802239462Sdim 4803239462Sdim // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 4804239462Sdim MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 4805239462Sdim TII->get(TargetOpcode::COPY), 4806239462Sdim is64Bit ? X86::RAX : X86::EAX) 4807239462Sdim .addReg(TLSBaseAddrReg); 4808239462Sdim 4809239462Sdim // Erase the TLS_base_addr instruction. 4810239462Sdim I->eraseFromParent(); 4811239462Sdim 4812239462Sdim return Copy; 4813239462Sdim } 4814239462Sdim 4815239462Sdim // Create a virtal register in *TLSBaseAddrReg, and populate it by 4816239462Sdim // inserting a copy instruction after I. Returns the new instruction. 4817239462Sdim MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 4818239462Sdim MachineFunction *MF = I->getParent()->getParent(); 4819239462Sdim const X86TargetMachine *TM = 4820239462Sdim static_cast<const X86TargetMachine *>(&MF->getTarget()); 4821239462Sdim const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4822239462Sdim const X86InstrInfo *TII = TM->getInstrInfo(); 4823239462Sdim 4824239462Sdim // Create a virtual register for the TLS base address. 4825239462Sdim MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4826239462Sdim *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 4827239462Sdim ? &X86::GR64RegClass 4828239462Sdim : &X86::GR32RegClass); 4829239462Sdim 4830239462Sdim // Insert a copy from RAX/EAX to TLSBaseAddrReg. 4831239462Sdim MachineInstr *Next = I->getNextNode(); 4832239462Sdim MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 4833239462Sdim TII->get(TargetOpcode::COPY), 4834239462Sdim *TLSBaseAddrReg) 4835239462Sdim .addReg(is64Bit ? X86::RAX : X86::EAX); 4836239462Sdim 4837239462Sdim return Copy; 4838239462Sdim } 4839239462Sdim 4840239462Sdim virtual const char *getPassName() const { 4841239462Sdim return "Local Dynamic TLS Access Clean-up"; 4842239462Sdim } 4843239462Sdim 4844239462Sdim virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4845239462Sdim AU.setPreservesCFG(); 4846239462Sdim AU.addRequired<MachineDominatorTree>(); 4847239462Sdim MachineFunctionPass::getAnalysisUsage(AU); 4848239462Sdim } 4849239462Sdim }; 4850239462Sdim} 4851239462Sdim 4852239462Sdimchar LDTLSCleanup::ID = 0; 4853239462SdimFunctionPass* 4854239462Sdimllvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 4855