X86InstrInfo.cpp revision 234353 
151852Sbp//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
251852Sbp//
351852Sbp//                     The LLVM Compiler Infrastructure
451852Sbp//
551852Sbp// This file is distributed under the University of Illinois Open Source
651852Sbp// License. See LICENSE.TXT for details.
751852Sbp//
851852Sbp//===----------------------------------------------------------------------===//
951852Sbp//
1051852Sbp// This file contains the X86 implementation of the TargetInstrInfo class.
1151852Sbp//
1251852Sbp//===----------------------------------------------------------------------===//
1351852Sbp
1451852Sbp#include "X86InstrInfo.h"
1551852Sbp#include "X86.h"
1651852Sbp#include "X86InstrBuilder.h"
1751852Sbp#include "X86MachineFunctionInfo.h"
1851852Sbp#include "X86Subtarget.h"
1951852Sbp#include "X86TargetMachine.h"
2051852Sbp#include "llvm/DerivedTypes.h"
2151852Sbp#include "llvm/LLVMContext.h"
2251852Sbp#include "llvm/ADT/STLExtras.h"
2351852Sbp#include "llvm/CodeGen/MachineConstantPool.h"
2451852Sbp#include "llvm/CodeGen/MachineFrameInfo.h"
2551852Sbp#include "llvm/CodeGen/MachineInstrBuilder.h"
2651852Sbp#include "llvm/CodeGen/MachineRegisterInfo.h"
2751852Sbp#include "llvm/CodeGen/LiveVariables.h"
2851852Sbp#include "llvm/MC/MCAsmInfo.h"
2951852Sbp#include "llvm/MC/MCInst.h"
3051852Sbp#include "llvm/Support/CommandLine.h"
3151852Sbp#include "llvm/Support/Debug.h"
3251852Sbp#include "llvm/Support/ErrorHandling.h"
3351852Sbp#include "llvm/Support/raw_ostream.h"
3451852Sbp#include "llvm/Target/TargetOptions.h"
3551852Sbp#include <limits>
3651852Sbp
3751852Sbp#define GET_INSTRINFO_CTOR
3851852Sbp#include "X86GenInstrInfo.inc"
3951852Sbp
4051852Sbpusing namespace llvm;
4151852Sbp
4251852Sbpstatic cl::opt<bool>
4351852SbpNoFusing("disable-spill-fusing",
4451852Sbp         cl::desc("Disable fusing of spill code into instructions"));
4551852Sbpstatic cl::opt<bool>
4651852SbpPrintFailedFusing("print-failed-fuse-candidates",
4751852Sbp                  cl::desc("Print instructions that the allocator wants to"
4851852Sbp                           " fuse, but the X86 backend currently can't"),
4951852Sbp                  cl::Hidden);
5051852Sbpstatic cl::opt<bool>
5151852SbpReMatPICStubLoad("remat-pic-stub-load",
5251852Sbp                 cl::desc("Re-materialize load from stub in PIC mode"),
5351852Sbp                 cl::init(false), cl::Hidden);
5451852Sbp
5551852Sbpenum {
5651852Sbp  // Select which memory operand is being unfolded.
5751852Sbp  // (stored in bits 0 - 7)
5851852Sbp  TB_INDEX_0    = 0,
5951852Sbp  TB_INDEX_1    = 1,
6051852Sbp  TB_INDEX_2    = 2,
6151852Sbp  TB_INDEX_MASK = 0xff,
6251852Sbp
6351852Sbp  // Minimum alignment required for load/store.
6451852Sbp  // Used for RegOp->MemOp conversion.
6551852Sbp  // (stored in bits 8 - 15)
6651852Sbp  TB_ALIGN_SHIFT = 8,
6751852Sbp  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
6851852Sbp  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
6951852Sbp  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
7051852Sbp  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT,
7151852Sbp
7251852Sbp  // Do not insert the reverse map (MemOp -> RegOp) into the table.
7351852Sbp  // This may be needed because there is a many -> one mapping.
7451852Sbp  TB_NO_REVERSE   = 1 << 16,
7551852Sbp
7651852Sbp  // Do not insert the forward map (RegOp -> MemOp) into the table.
7751852Sbp  // This is needed for Native Client, which prohibits branch
7851852Sbp  // instructions from using a memory operand.
7951852Sbp  TB_NO_FORWARD   = 1 << 17,
8051852Sbp
8151852Sbp  TB_FOLDED_LOAD  = 1 << 18,
8251852Sbp  TB_FOLDED_STORE = 1 << 19
8351852Sbp};
8451852Sbp
8551852Sbpstruct X86OpTblEntry {
8651852Sbp  uint16_t RegOp;
8751852Sbp  uint16_t MemOp;
8851852Sbp  uint32_t Flags;
8951852Sbp};
9051852Sbp
9151852SbpX86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
9251852Sbp  : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
9351852Sbp                     ? X86::ADJCALLSTACKDOWN64
9451852Sbp                     : X86::ADJCALLSTACKDOWN32),
9551852Sbp                    (tm.getSubtarget<X86Subtarget>().is64Bit()
9651852Sbp                     ? X86::ADJCALLSTACKUP64
9751852Sbp                     : X86::ADJCALLSTACKUP32)),
9851852Sbp    TM(tm), RI(tm, *this) {
9951852Sbp
10051852Sbp  static const X86OpTblEntry OpTbl2Addr[] = {
10151852Sbp    { X86::ADC32ri,     X86::ADC32mi,    0 },
10251852Sbp    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
10351852Sbp    { X86::ADC32rr,     X86::ADC32mr,    0 },
10451852Sbp    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
10551852Sbp    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
10651852Sbp    { X86::ADC64rr,     X86::ADC64mr,    0 },
10751852Sbp    { X86::ADD16ri,     X86::ADD16mi,    0 },
10851852Sbp    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
10951852Sbp    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
11051852Sbp    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
11151852Sbp    { X86::ADD16rr,     X86::ADD16mr,    0 },
11251852Sbp    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
11351852Sbp    { X86::ADD32ri,     X86::ADD32mi,    0 },
11451852Sbp    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
11551852Sbp    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
11651852Sbp    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
11751852Sbp    { X86::ADD32rr,     X86::ADD32mr,    0 },
11851852Sbp    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
11951852Sbp    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
12051852Sbp    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
12151852Sbp    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
12251852Sbp    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
12351852Sbp    { X86::ADD64rr,     X86::ADD64mr,    0 },
12451852Sbp    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
12551852Sbp    { X86::ADD8ri,      X86::ADD8mi,     0 },
12651852Sbp    { X86::ADD8rr,      X86::ADD8mr,     0 },
12751852Sbp    { X86::AND16ri,     X86::AND16mi,    0 },
12851852Sbp    { X86::AND16ri8,    X86::AND16mi8,   0 },
12951852Sbp    { X86::AND16rr,     X86::AND16mr,    0 },
13051852Sbp    { X86::AND32ri,     X86::AND32mi,    0 },
13151852Sbp    { X86::AND32ri8,    X86::AND32mi8,   0 },
13251852Sbp    { X86::AND32rr,     X86::AND32mr,    0 },
13351852Sbp    { X86::AND64ri32,   X86::AND64mi32,  0 },
13451852Sbp    { X86::AND64ri8,    X86::AND64mi8,   0 },
13551852Sbp    { X86::AND64rr,     X86::AND64mr,    0 },
13651852Sbp    { X86::AND8ri,      X86::AND8mi,     0 },
13751852Sbp    { X86::AND8rr,      X86::AND8mr,     0 },
13851852Sbp    { X86::DEC16r,      X86::DEC16m,     0 },
13951852Sbp    { X86::DEC32r,      X86::DEC32m,     0 },
14051852Sbp    { X86::DEC64_16r,   X86::DEC64_16m,  0 },
14151852Sbp    { X86::DEC64_32r,   X86::DEC64_32m,  0 },
14251852Sbp    { X86::DEC64r,      X86::DEC64m,     0 },
14351852Sbp    { X86::DEC8r,       X86::DEC8m,      0 },
14451852Sbp    { X86::INC16r,      X86::INC16m,     0 },
14551852Sbp    { X86::INC32r,      X86::INC32m,     0 },
14651852Sbp    { X86::INC64_16r,   X86::INC64_16m,  0 },
14751852Sbp    { X86::INC64_32r,   X86::INC64_32m,  0 },
14851852Sbp    { X86::INC64r,      X86::INC64m,     0 },
14951852Sbp    { X86::INC8r,       X86::INC8m,      0 },
15051852Sbp    { X86::NEG16r,      X86::NEG16m,     0 },
15151852Sbp    { X86::NEG32r,      X86::NEG32m,     0 },
15251852Sbp    { X86::NEG64r,      X86::NEG64m,     0 },
15351852Sbp    { X86::NEG8r,       X86::NEG8m,      0 },
15451852Sbp    { X86::NOT16r,      X86::NOT16m,     0 },
15551852Sbp    { X86::NOT32r,      X86::NOT32m,     0 },
15651852Sbp    { X86::NOT64r,      X86::NOT64m,     0 },
15751852Sbp    { X86::NOT8r,       X86::NOT8m,      0 },
15851852Sbp    { X86::OR16ri,      X86::OR16mi,     0 },
15951852Sbp    { X86::OR16ri8,     X86::OR16mi8,    0 },
16051852Sbp    { X86::OR16rr,      X86::OR16mr,     0 },
16151852Sbp    { X86::OR32ri,      X86::OR32mi,     0 },
16251852Sbp    { X86::OR32ri8,     X86::OR32mi8,    0 },
16351852Sbp    { X86::OR32rr,      X86::OR32mr,     0 },
16451852Sbp    { X86::OR64ri32,    X86::OR64mi32,   0 },
16551852Sbp    { X86::OR64ri8,     X86::OR64mi8,    0 },
16651852Sbp    { X86::OR64rr,      X86::OR64mr,     0 },
16751852Sbp    { X86::OR8ri,       X86::OR8mi,      0 },
16851852Sbp    { X86::OR8rr,       X86::OR8mr,      0 },
16951852Sbp    { X86::ROL16r1,     X86::ROL16m1,    0 },
17051852Sbp    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
17151852Sbp    { X86::ROL16ri,     X86::ROL16mi,    0 },
17251852Sbp    { X86::ROL32r1,     X86::ROL32m1,    0 },
17351852Sbp    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
17451852Sbp    { X86::ROL32ri,     X86::ROL32mi,    0 },
17551852Sbp    { X86::ROL64r1,     X86::ROL64m1,    0 },
17651852Sbp    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
17751852Sbp    { X86::ROL64ri,     X86::ROL64mi,    0 },
17851852Sbp    { X86::ROL8r1,      X86::ROL8m1,     0 },
17951852Sbp    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
18051852Sbp    { X86::ROL8ri,      X86::ROL8mi,     0 },
18151852Sbp    { X86::ROR16r1,     X86::ROR16m1,    0 },
18251852Sbp    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
18351852Sbp    { X86::ROR16ri,     X86::ROR16mi,    0 },
18451852Sbp    { X86::ROR32r1,     X86::ROR32m1,    0 },
18551852Sbp    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
18651852Sbp    { X86::ROR32ri,     X86::ROR32mi,    0 },
18751852Sbp    { X86::ROR64r1,     X86::ROR64m1,    0 },
18851852Sbp    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
18951852Sbp    { X86::ROR64ri,     X86::ROR64mi,    0 },
19051852Sbp    { X86::ROR8r1,      X86::ROR8m1,     0 },
19151852Sbp    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
19251852Sbp    { X86::ROR8ri,      X86::ROR8mi,     0 },
19351852Sbp    { X86::SAR16r1,     X86::SAR16m1,    0 },
19451852Sbp    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
19551852Sbp    { X86::SAR16ri,     X86::SAR16mi,    0 },
19651852Sbp    { X86::SAR32r1,     X86::SAR32m1,    0 },
19751852Sbp    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
19851852Sbp    { X86::SAR32ri,     X86::SAR32mi,    0 },
19951852Sbp    { X86::SAR64r1,     X86::SAR64m1,    0 },
20051852Sbp    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
20151852Sbp    { X86::SAR64ri,     X86::SAR64mi,    0 },
20251852Sbp    { X86::SAR8r1,      X86::SAR8m1,     0 },
20351852Sbp    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
20451852Sbp    { X86::SAR8ri,      X86::SAR8mi,     0 },
20551852Sbp    { X86::SBB32ri,     X86::SBB32mi,    0 },
20651852Sbp    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
20751852Sbp    { X86::SBB32rr,     X86::SBB32mr,    0 },
20851852Sbp    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
20951852Sbp    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
21051852Sbp    { X86::SBB64rr,     X86::SBB64mr,    0 },
21151852Sbp    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
21251852Sbp    { X86::SHL16ri,     X86::SHL16mi,    0 },
21351852Sbp    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
21451852Sbp    { X86::SHL32ri,     X86::SHL32mi,    0 },
21551852Sbp    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
21651852Sbp    { X86::SHL64ri,     X86::SHL64mi,    0 },
21751852Sbp    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
21851852Sbp    { X86::SHL8ri,      X86::SHL8mi,     0 },
21951852Sbp    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
22051852Sbp    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
22151852Sbp    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
22251852Sbp    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
22351852Sbp    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
22451852Sbp    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
22551852Sbp    { X86::SHR16r1,     X86::SHR16m1,    0 },
22651852Sbp    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
22751852Sbp    { X86::SHR16ri,     X86::SHR16mi,    0 },
22851852Sbp    { X86::SHR32r1,     X86::SHR32m1,    0 },
22951852Sbp    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
23051852Sbp    { X86::SHR32ri,     X86::SHR32mi,    0 },
23151852Sbp    { X86::SHR64r1,     X86::SHR64m1,    0 },
23251852Sbp    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
23351852Sbp    { X86::SHR64ri,     X86::SHR64mi,    0 },
23451852Sbp    { X86::SHR8r1,      X86::SHR8m1,     0 },
23551852Sbp    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
23651852Sbp    { X86::SHR8ri,      X86::SHR8mi,     0 },
23751852Sbp    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
23851852Sbp    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
23951852Sbp    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
24051852Sbp    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
24151852Sbp    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
24251852Sbp    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
24351852Sbp    { X86::SUB16ri,     X86::SUB16mi,    0 },
24451852Sbp    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
24551852Sbp    { X86::SUB16rr,     X86::SUB16mr,    0 },
24651852Sbp    { X86::SUB32ri,     X86::SUB32mi,    0 },
24751852Sbp    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
24851852Sbp    { X86::SUB32rr,     X86::SUB32mr,    0 },
24951852Sbp    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
25051852Sbp    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
25151852Sbp    { X86::SUB64rr,     X86::SUB64mr,    0 },
25251852Sbp    { X86::SUB8ri,      X86::SUB8mi,     0 },
25351852Sbp    { X86::SUB8rr,      X86::SUB8mr,     0 },
25451852Sbp    { X86::XOR16ri,     X86::XOR16mi,    0 },
25551852Sbp    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
25651852Sbp    { X86::XOR16rr,     X86::XOR16mr,    0 },
25751852Sbp    { X86::XOR32ri,     X86::XOR32mi,    0 },
25851852Sbp    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
25951852Sbp    { X86::XOR32rr,     X86::XOR32mr,    0 },
26051852Sbp    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
26151852Sbp    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
26251852Sbp    { X86::XOR64rr,     X86::XOR64mr,    0 },
26351852Sbp    { X86::XOR8ri,      X86::XOR8mi,     0 },
26451852Sbp    { X86::XOR8rr,      X86::XOR8mr,     0 }
26551852Sbp  };
26651852Sbp
26751852Sbp  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
26851852Sbp    unsigned RegOp = OpTbl2Addr[i].RegOp;
26951852Sbp    unsigned MemOp = OpTbl2Addr[i].MemOp;
27051852Sbp    unsigned Flags = OpTbl2Addr[i].Flags;
27151852Sbp    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
27251852Sbp                  RegOp, MemOp,
27351852Sbp                  // Index 0, folded load and store, no alignment requirement.
27451852Sbp                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
27551852Sbp  }
27651852Sbp
27751852Sbp  static const X86OpTblEntry OpTbl0[] = {
27851852Sbp    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
279    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
280    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
281    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
282    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
283    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
284    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
285    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
286    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
287    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
288    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
289    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
290    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
291    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
292    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
293    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
294    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
295    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
296    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
297    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
298    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },
299    { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
300    { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
301    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
302    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
303    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
304    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
305    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
306    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
307    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
308    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
309    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
310    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
311    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
312    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
313    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
314    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
315    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
316    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
317    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
318    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
319    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
320    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
321    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
322    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
324    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
325    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
326    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
327    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
328    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
329    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
330    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
331    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
332    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
333    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
334    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
335    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
336    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
337    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
338    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
339    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
340    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
341    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
342    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
343    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
344    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
345    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
346    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
347    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
348    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
349    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
350    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
351    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
352    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
353    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
354    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
355    // AVX 128-bit versions of foldable instructions
356    { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE | TB_ALIGN_16 },
357    { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
358    { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
359    { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
360    { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
361    { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
362    { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
363    { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
364    { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
365    { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
366    { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
367    { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
368    { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
369    // AVX 256-bit foldable instructions
370    { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
371    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
372    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
373    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
374    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
375    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE }
376  };
377
378  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
379    unsigned RegOp      = OpTbl0[i].RegOp;
380    unsigned MemOp      = OpTbl0[i].MemOp;
381    unsigned Flags      = OpTbl0[i].Flags;
382    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
383                  RegOp, MemOp, TB_INDEX_0 | Flags);
384  }
385
386  static const X86OpTblEntry OpTbl1[] = {
387    { X86::CMP16rr,         X86::CMP16rm,             0 },
388    { X86::CMP32rr,         X86::CMP32rm,             0 },
389    { X86::CMP64rr,         X86::CMP64rm,             0 },
390    { X86::CMP8rr,          X86::CMP8rm,              0 },
391    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
392    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
393    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
394    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
395    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
396    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
397    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
398    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
399    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
400    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
401    { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
402    { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
403    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
404    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
405    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
406    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
407    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
408    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
409    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
410    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
411    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm,      TB_ALIGN_16 },
412    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm,      TB_ALIGN_16 },
413    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm,      TB_ALIGN_16 },
414    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm,      TB_ALIGN_16 },
415    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm,      TB_ALIGN_16 },
416    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm,      0 },
417    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
418    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
419    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
420    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
421    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
422    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
423    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
424    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
425    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
426    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
427    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
428    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
429    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
430    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
431    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
432    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
433    { X86::MOV16rr,         X86::MOV16rm,             0 },
434    { X86::MOV32rr,         X86::MOV32rm,             0 },
435    { X86::MOV64rr,         X86::MOV64rm,             0 },
436    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
437    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
438    { X86::MOV8rr,          X86::MOV8rm,              0 },
439    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
440    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
441    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
442    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
443    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
444    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
445    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
446    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
447    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
448    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
449    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
450    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
451    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
452    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
453    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
454    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
455    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
456    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
457    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
458    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
459    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
460    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
461    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
462    { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
463    { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
464    { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
465    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
466    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
467    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
468    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
469    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
470    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
471    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
472    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
473    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
474    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
475    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
476    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
477    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
478    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int,         TB_ALIGN_16 },
479    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
480    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int,         TB_ALIGN_16 },
481    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
482    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
483    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
484    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
485    { X86::TEST16rr,        X86::TEST16rm,            0 },
486    { X86::TEST32rr,        X86::TEST32rm,            0 },
487    { X86::TEST64rr,        X86::TEST64rm,            0 },
488    { X86::TEST8rr,         X86::TEST8rm,             0 },
489    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
490    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
491    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
492    // AVX 128-bit versions of foldable instructions
493    { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
494    { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
495    { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm,     TB_ALIGN_16 },
496    { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm,     TB_ALIGN_16 },
497    { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm,     TB_ALIGN_16 },
498    { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm,     TB_ALIGN_16 },
499    { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm,     TB_ALIGN_16 },
500    { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm,     0 },
501    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
502    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
503    { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
504    { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
505    { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
506    { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
507    { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
508    { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
509    { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
510    { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
511    { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
512    { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
513    { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
514    { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
515    { X86::VMOVUPDrr,       X86::VMOVUPDrm,           TB_ALIGN_16 },
516    { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
517    { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
518    { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
519    { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
520    { X86::VPABSBrr128,     X86::VPABSBrm128,         TB_ALIGN_16 },
521    { X86::VPABSDrr128,     X86::VPABSDrm128,         TB_ALIGN_16 },
522    { X86::VPABSWrr128,     X86::VPABSWrm128,         TB_ALIGN_16 },
523    { X86::VPERMILPDri,     X86::VPERMILPDmi,         TB_ALIGN_16 },
524    { X86::VPERMILPSri,     X86::VPERMILPSmi,         TB_ALIGN_16 },
525    { X86::VPSHUFDri,       X86::VPSHUFDmi,           TB_ALIGN_16 },
526    { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          TB_ALIGN_16 },
527    { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          TB_ALIGN_16 },
528    { X86::VRCPPSr,         X86::VRCPPSm,             TB_ALIGN_16 },
529    { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         TB_ALIGN_16 },
530    { X86::VRSQRTPSr,       X86::VRSQRTPSm,           TB_ALIGN_16 },
531    { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       TB_ALIGN_16 },
532    { X86::VSQRTPDr,        X86::VSQRTPDm,            TB_ALIGN_16 },
533    { X86::VSQRTPDr_Int,    X86::VSQRTPDm_Int,        TB_ALIGN_16 },
534    { X86::VSQRTPSr,        X86::VSQRTPSm,            TB_ALIGN_16 },
535    { X86::VSQRTPSr_Int,    X86::VSQRTPSm_Int,        TB_ALIGN_16 },
536    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
537    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
538    // AVX 256-bit foldable instructions
539    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
540    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
541    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
542    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
543    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
544    { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        TB_ALIGN_32 },
545    { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        TB_ALIGN_32 },
546    // AVX2 foldable instructions
547    { X86::VPABSBrr256,     X86::VPABSBrm256,         TB_ALIGN_32 },
548    { X86::VPABSDrr256,     X86::VPABSDrm256,         TB_ALIGN_32 },
549    { X86::VPABSWrr256,     X86::VPABSWrm256,         TB_ALIGN_32 },
550    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          TB_ALIGN_32 },
551    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         TB_ALIGN_32 },
552    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         TB_ALIGN_32 },
553    { X86::VRCPPSYr,        X86::VRCPPSYm,            TB_ALIGN_32 },
554    { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        TB_ALIGN_32 },
555    { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          TB_ALIGN_32 },
556    { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      TB_ALIGN_32 },
557    { X86::VSQRTPDYr,       X86::VSQRTPDYm,           TB_ALIGN_32 },
558    { X86::VSQRTPDYr_Int,   X86::VSQRTPDYm_Int,       TB_ALIGN_32 },
559    { X86::VSQRTPSYr,       X86::VSQRTPSYm,           TB_ALIGN_32 },
560    { X86::VSQRTPSYr_Int,   X86::VSQRTPSYm_Int,       TB_ALIGN_32 },
561  };
562
563  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
564    unsigned RegOp = OpTbl1[i].RegOp;
565    unsigned MemOp = OpTbl1[i].MemOp;
566    unsigned Flags = OpTbl1[i].Flags;
567    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
568                  RegOp, MemOp,
569                  // Index 1, folded load
570                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
571  }
572
573  static const X86OpTblEntry OpTbl2[] = {
574    { X86::ADC32rr,         X86::ADC32rm,       0 },
575    { X86::ADC64rr,         X86::ADC64rm,       0 },
576    { X86::ADD16rr,         X86::ADD16rm,       0 },
577    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
578    { X86::ADD32rr,         X86::ADD32rm,       0 },
579    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
580    { X86::ADD64rr,         X86::ADD64rm,       0 },
581    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
582    { X86::ADD8rr,          X86::ADD8rm,        0 },
583    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
584    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
585    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
586    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
587    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
588    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
589    { X86::AND16rr,         X86::AND16rm,       0 },
590    { X86::AND32rr,         X86::AND32rm,       0 },
591    { X86::AND64rr,         X86::AND64rm,       0 },
592    { X86::AND8rr,          X86::AND8rm,        0 },
593    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
594    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
595    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
596    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
597    { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
598    { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
599    { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
600    { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
601    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
602    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
603    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
604    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
605    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
606    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
607    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
608    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
609    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
610    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
611    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
612    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
613    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
614    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
615    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
616    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
617    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
618    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
619    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
620    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
621    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
622    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
623    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
624    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
625    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
626    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
627    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
628    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
629    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
630    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
631    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
632    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
633    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
634    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
635    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
636    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
637    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
638    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
639    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
640    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
641    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
642    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
643    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
644    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
645    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
646    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
647    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
648    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
649    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
650    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
651    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
652    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
653    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
654    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
655    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
656    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
657    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
658    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
659    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
660    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
661    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
662    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
663    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
664    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
665    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
666    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
667    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
668    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
669    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
670    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
671    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
672    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
673    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
674    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
675    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int,   TB_ALIGN_16 },
676    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
677    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int,   TB_ALIGN_16 },
678    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
679    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
680    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
681    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
682    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
683    { X86::MINPDrr_Int,     X86::MINPDrm_Int,   TB_ALIGN_16 },
684    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
685    { X86::MINPSrr_Int,     X86::MINPSrm_Int,   TB_ALIGN_16 },
686    { X86::MINSDrr,         X86::MINSDrm,       0 },
687    { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
688    { X86::MINSSrr,         X86::MINSSrm,       0 },
689    { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
690    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
691    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
692    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
693    { X86::MULSDrr,         X86::MULSDrm,       0 },
694    { X86::MULSSrr,         X86::MULSSrm,       0 },
695    { X86::OR16rr,          X86::OR16rm,        0 },
696    { X86::OR32rr,          X86::OR32rm,        0 },
697    { X86::OR64rr,          X86::OR64rm,        0 },
698    { X86::OR8rr,           X86::OR8rm,         0 },
699    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
700    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
701    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
702    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
703    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
704    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
705    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
706    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
707    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
708    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
709    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
710    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
711    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
712    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
713    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
714    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
715    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
716    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
717    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
718    { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
719    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
720    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
721    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
722    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
723    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
724    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
725    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
726    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
727    { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
728    { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
729    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
730    { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
731    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
732    { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
733    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
734    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
735    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
736    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
737    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
738    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
739    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
740    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
741    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
742    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
743    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
744    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
745    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
746    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
747    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
748    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
749    { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
750    { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
751    { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
752    { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
753    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
754    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
755    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
756    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
757    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
758    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
759    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
760    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
761    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
762    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
763    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
764    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
765    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
766    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
767    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
768    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
769    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
770    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
771    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
772    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
773    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
774    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
775    { X86::SBB32rr,         X86::SBB32rm,       0 },
776    { X86::SBB64rr,         X86::SBB64rm,       0 },
777    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
778    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
779    { X86::SUB16rr,         X86::SUB16rm,       0 },
780    { X86::SUB32rr,         X86::SUB32rm,       0 },
781    { X86::SUB64rr,         X86::SUB64rm,       0 },
782    { X86::SUB8rr,          X86::SUB8rm,        0 },
783    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
784    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
785    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
786    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
787    // FIXME: TEST*rr -> swapped operand of TEST*mr.
788    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
789    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
790    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
791    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
792    { X86::XOR16rr,         X86::XOR16rm,       0 },
793    { X86::XOR32rr,         X86::XOR32rm,       0 },
794    { X86::XOR64rr,         X86::XOR64rm,       0 },
795    { X86::XOR8rr,          X86::XOR8rm,        0 },
796    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
797    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
798    // AVX 128-bit versions of foldable instructions
799    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
800    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
801    { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
802    { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
803    { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
804    { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
805    { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
806    { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
807    { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
808    { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
809    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
810    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
811    { X86::VCVTTSD2SI64rr,    X86::VCVTTSD2SI64rm,     0 },
812    { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
813    { X86::VCVTTSD2SIrr,      X86::VCVTTSD2SIrm,       0 },
814    { X86::Int_VCVTTSD2SIrr,  X86::Int_VCVTTSD2SIrm,   0 },
815    { X86::VCVTTSS2SI64rr,    X86::VCVTTSS2SI64rm,     0 },
816    { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
817    { X86::VCVTTSS2SIrr,      X86::VCVTTSS2SIrm,       0 },
818    { X86::Int_VCVTTSS2SIrr,  X86::Int_VCVTTSS2SIrm,   0 },
819    { X86::VCVTSD2SI64rr,     X86::VCVTSD2SI64rm,      0 },
820    { X86::VCVTSD2SIrr,       X86::VCVTSD2SIrm,        0 },
821    { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQrm,       TB_ALIGN_16 },
822    { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       TB_ALIGN_16 },
823    { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
824    { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
825    { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
826    { X86::VADDPDrr,          X86::VADDPDrm,           TB_ALIGN_16 },
827    { X86::VADDPSrr,          X86::VADDPSrm,           TB_ALIGN_16 },
828    { X86::VADDSDrr,          X86::VADDSDrm,           0 },
829    { X86::VADDSSrr,          X86::VADDSSrm,           0 },
830    { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        TB_ALIGN_16 },
831    { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        TB_ALIGN_16 },
832    { X86::VANDNPDrr,         X86::VANDNPDrm,          TB_ALIGN_16 },
833    { X86::VANDNPSrr,         X86::VANDNPSrm,          TB_ALIGN_16 },
834    { X86::VANDPDrr,          X86::VANDPDrm,           TB_ALIGN_16 },
835    { X86::VANDPSrr,          X86::VANDPSrm,           TB_ALIGN_16 },
836    { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        TB_ALIGN_16 },
837    { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        TB_ALIGN_16 },
838    { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        TB_ALIGN_16 },
839    { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        TB_ALIGN_16 },
840    { X86::VCMPPDrri,         X86::VCMPPDrmi,          TB_ALIGN_16 },
841    { X86::VCMPPSrri,         X86::VCMPPSrmi,          TB_ALIGN_16 },
842    { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
843    { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
844    { X86::VDIVPDrr,          X86::VDIVPDrm,           TB_ALIGN_16 },
845    { X86::VDIVPSrr,          X86::VDIVPSrm,           TB_ALIGN_16 },
846    { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
847    { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
848    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
849    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
850    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
851    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
852    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
853    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
854    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
855    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
856    { X86::VHADDPDrr,         X86::VHADDPDrm,          TB_ALIGN_16 },
857    { X86::VHADDPSrr,         X86::VHADDPSrm,          TB_ALIGN_16 },
858    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          TB_ALIGN_16 },
859    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          TB_ALIGN_16 },
860    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
861    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
862    { X86::VMAXPDrr,          X86::VMAXPDrm,           TB_ALIGN_16 },
863    { X86::VMAXPDrr_Int,      X86::VMAXPDrm_Int,       TB_ALIGN_16 },
864    { X86::VMAXPSrr,          X86::VMAXPSrm,           TB_ALIGN_16 },
865    { X86::VMAXPSrr_Int,      X86::VMAXPSrm_Int,       TB_ALIGN_16 },
866    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
867    { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
868    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
869    { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
870    { X86::VMINPDrr,          X86::VMINPDrm,           TB_ALIGN_16 },
871    { X86::VMINPDrr_Int,      X86::VMINPDrm_Int,       TB_ALIGN_16 },
872    { X86::VMINPSrr,          X86::VMINPSrm,           TB_ALIGN_16 },
873    { X86::VMINPSrr_Int,      X86::VMINPSrm_Int,       TB_ALIGN_16 },
874    { X86::VMINSDrr,          X86::VMINSDrm,           0 },
875    { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
876    { X86::VMINSSrr,          X86::VMINSSrm,           0 },
877    { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
878    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        TB_ALIGN_16 },
879    { X86::VMULPDrr,          X86::VMULPDrm,           TB_ALIGN_16 },
880    { X86::VMULPSrr,          X86::VMULPSrm,           TB_ALIGN_16 },
881    { X86::VMULSDrr,          X86::VMULSDrm,           0 },
882    { X86::VMULSSrr,          X86::VMULSSrm,           0 },
883    { X86::VORPDrr,           X86::VORPDrm,            TB_ALIGN_16 },
884    { X86::VORPSrr,           X86::VORPSrm,            TB_ALIGN_16 },
885    { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        TB_ALIGN_16 },
886    { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        TB_ALIGN_16 },
887    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        TB_ALIGN_16 },
888    { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        TB_ALIGN_16 },
889    { X86::VPADDBrr,          X86::VPADDBrm,           TB_ALIGN_16 },
890    { X86::VPADDDrr,          X86::VPADDDrm,           TB_ALIGN_16 },
891    { X86::VPADDQrr,          X86::VPADDQrm,           TB_ALIGN_16 },
892    { X86::VPADDSBrr,         X86::VPADDSBrm,          TB_ALIGN_16 },
893    { X86::VPADDSWrr,         X86::VPADDSWrm,          TB_ALIGN_16 },
894    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         TB_ALIGN_16 },
895    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         TB_ALIGN_16 },
896    { X86::VPADDWrr,          X86::VPADDWrm,           TB_ALIGN_16 },
897    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      TB_ALIGN_16 },
898    { X86::VPANDNrr,          X86::VPANDNrm,           TB_ALIGN_16 },
899    { X86::VPANDrr,           X86::VPANDrm,            TB_ALIGN_16 },
900    { X86::VPAVGBrr,          X86::VPAVGBrm,           TB_ALIGN_16 },
901    { X86::VPAVGWrr,          X86::VPAVGWrm,           TB_ALIGN_16 },
902    { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        TB_ALIGN_16 },
903    { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         TB_ALIGN_16 },
904    { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         TB_ALIGN_16 },
905    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         TB_ALIGN_16 },
906    { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         TB_ALIGN_16 },
907    { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         TB_ALIGN_16 },
908    { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         TB_ALIGN_16 },
909    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         TB_ALIGN_16 },
910    { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         TB_ALIGN_16 },
911    { X86::VPHADDDrr,         X86::VPHADDDrm,          TB_ALIGN_16 },
912    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      TB_ALIGN_16 },
913    { X86::VPHADDWrr,         X86::VPHADDWrm,          TB_ALIGN_16 },
914    { X86::VPHSUBDrr,         X86::VPHSUBDrm,          TB_ALIGN_16 },
915    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      TB_ALIGN_16 },
916    { X86::VPHSUBWrr,         X86::VPHSUBWrm,          TB_ALIGN_16 },
917    { X86::VPERMILPDrr,       X86::VPERMILPDrm,        TB_ALIGN_16 },
918    { X86::VPERMILPSrr,       X86::VPERMILPSrm,        TB_ALIGN_16 },
919    { X86::VPINSRWrri,        X86::VPINSRWrmi,         TB_ALIGN_16 },
920    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    TB_ALIGN_16 },
921    { X86::VPMADDWDrr,        X86::VPMADDWDrm,         TB_ALIGN_16 },
922    { X86::VPMAXSWrr,         X86::VPMAXSWrm,          TB_ALIGN_16 },
923    { X86::VPMAXUBrr,         X86::VPMAXUBrm,          TB_ALIGN_16 },
924    { X86::VPMINSWrr,         X86::VPMINSWrm,          TB_ALIGN_16 },
925    { X86::VPMINUBrr,         X86::VPMINUBrm,          TB_ALIGN_16 },
926    { X86::VPMULDQrr,         X86::VPMULDQrm,          TB_ALIGN_16 },
927    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     TB_ALIGN_16 },
928    { X86::VPMULHUWrr,        X86::VPMULHUWrm,         TB_ALIGN_16 },
929    { X86::VPMULHWrr,         X86::VPMULHWrm,          TB_ALIGN_16 },
930    { X86::VPMULLDrr,         X86::VPMULLDrm,          TB_ALIGN_16 },
931    { X86::VPMULLWrr,         X86::VPMULLWrm,          TB_ALIGN_16 },
932    { X86::VPMULUDQrr,        X86::VPMULUDQrm,         TB_ALIGN_16 },
933    { X86::VPORrr,            X86::VPORrm,             TB_ALIGN_16 },
934    { X86::VPSADBWrr,         X86::VPSADBWrm,          TB_ALIGN_16 },
935    { X86::VPSHUFBrr,         X86::VPSHUFBrm,          TB_ALIGN_16 },
936    { X86::VPSIGNBrr,         X86::VPSIGNBrm,          TB_ALIGN_16 },
937    { X86::VPSIGNWrr,         X86::VPSIGNWrm,          TB_ALIGN_16 },
938    { X86::VPSIGNDrr,         X86::VPSIGNDrm,          TB_ALIGN_16 },
939    { X86::VPSLLDrr,          X86::VPSLLDrm,           TB_ALIGN_16 },
940    { X86::VPSLLQrr,          X86::VPSLLQrm,           TB_ALIGN_16 },
941    { X86::VPSLLWrr,          X86::VPSLLWrm,           TB_ALIGN_16 },
942    { X86::VPSRADrr,          X86::VPSRADrm,           TB_ALIGN_16 },
943    { X86::VPSRAWrr,          X86::VPSRAWrm,           TB_ALIGN_16 },
944    { X86::VPSRLDrr,          X86::VPSRLDrm,           TB_ALIGN_16 },
945    { X86::VPSRLQrr,          X86::VPSRLQrm,           TB_ALIGN_16 },
946    { X86::VPSRLWrr,          X86::VPSRLWrm,           TB_ALIGN_16 },
947    { X86::VPSUBBrr,          X86::VPSUBBrm,           TB_ALIGN_16 },
948    { X86::VPSUBDrr,          X86::VPSUBDrm,           TB_ALIGN_16 },
949    { X86::VPSUBSBrr,         X86::VPSUBSBrm,          TB_ALIGN_16 },
950    { X86::VPSUBSWrr,         X86::VPSUBSWrm,          TB_ALIGN_16 },
951    { X86::VPSUBWrr,          X86::VPSUBWrm,           TB_ALIGN_16 },
952    { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       TB_ALIGN_16 },
953    { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       TB_ALIGN_16 },
954    { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      TB_ALIGN_16 },
955    { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       TB_ALIGN_16 },
956    { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       TB_ALIGN_16 },
957    { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       TB_ALIGN_16 },
958    { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      TB_ALIGN_16 },
959    { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       TB_ALIGN_16 },
960    { X86::VPXORrr,           X86::VPXORrm,            TB_ALIGN_16 },
961    { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         TB_ALIGN_16 },
962    { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         TB_ALIGN_16 },
963    { X86::VSUBPDrr,          X86::VSUBPDrm,           TB_ALIGN_16 },
964    { X86::VSUBPSrr,          X86::VSUBPSrm,           TB_ALIGN_16 },
965    { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
966    { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
967    { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        TB_ALIGN_16 },
968    { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        TB_ALIGN_16 },
969    { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        TB_ALIGN_16 },
970    { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        TB_ALIGN_16 },
971    { X86::VXORPDrr,          X86::VXORPDrm,           TB_ALIGN_16 },
972    { X86::VXORPSrr,          X86::VXORPSrm,           TB_ALIGN_16 },
973    // AVX 256-bit foldable instructions
974    { X86::VADDPDYrr,         X86::VADDPDYrm,          TB_ALIGN_32 },
975    { X86::VADDPSYrr,         X86::VADDPSYrm,          TB_ALIGN_32 },
976    { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       TB_ALIGN_32 },
977    { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       TB_ALIGN_32 },
978    { X86::VANDNPDYrr,        X86::VANDNPDYrm,         TB_ALIGN_32 },
979    { X86::VANDNPSYrr,        X86::VANDNPSYrm,         TB_ALIGN_32 },
980    { X86::VANDPDYrr,         X86::VANDPDYrm,          TB_ALIGN_32 },
981    { X86::VANDPSYrr,         X86::VANDPSYrm,          TB_ALIGN_32 },
982    { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       TB_ALIGN_32 },
983    { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       TB_ALIGN_32 },
984    { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       TB_ALIGN_32 },
985    { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       TB_ALIGN_32 },
986    { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         TB_ALIGN_32 },
987    { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         TB_ALIGN_32 },
988    { X86::VDIVPDYrr,         X86::VDIVPDYrm,          TB_ALIGN_32 },
989    { X86::VDIVPSYrr,         X86::VDIVPSYrm,          TB_ALIGN_32 },
990    { X86::VHADDPDYrr,        X86::VHADDPDYrm,         TB_ALIGN_32 },
991    { X86::VHADDPSYrr,        X86::VHADDPSYrm,         TB_ALIGN_32 },
992    { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         TB_ALIGN_32 },
993    { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         TB_ALIGN_32 },
994    { X86::VINSERTF128rr,     X86::VINSERTF128rm,      TB_ALIGN_32 },
995    { X86::VMAXPDYrr,         X86::VMAXPDYrm,          TB_ALIGN_32 },
996    { X86::VMAXPDYrr_Int,     X86::VMAXPDYrm_Int,      TB_ALIGN_32 },
997    { X86::VMAXPSYrr,         X86::VMAXPSYrm,          TB_ALIGN_32 },
998    { X86::VMAXPSYrr_Int,     X86::VMAXPSYrm_Int,      TB_ALIGN_32 },
999    { X86::VMINPDYrr,         X86::VMINPDYrm,          TB_ALIGN_32 },
1000    { X86::VMINPDYrr_Int,     X86::VMINPDYrm_Int,      TB_ALIGN_32 },
1001    { X86::VMINPSYrr,         X86::VMINPSYrm,          TB_ALIGN_32 },
1002    { X86::VMINPSYrr_Int,     X86::VMINPSYrm_Int,      TB_ALIGN_32 },
1003    { X86::VMULPDYrr,         X86::VMULPDYrm,          TB_ALIGN_32 },
1004    { X86::VMULPSYrr,         X86::VMULPSYrm,          TB_ALIGN_32 },
1005    { X86::VORPDYrr,          X86::VORPDYrm,           TB_ALIGN_32 },
1006    { X86::VORPSYrr,          X86::VORPSYrm,           TB_ALIGN_32 },
1007    { X86::VPERM2F128rr,      X86::VPERM2F128rm,       TB_ALIGN_32 },
1008    { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       TB_ALIGN_32 },
1009    { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       TB_ALIGN_32 },
1010    { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        TB_ALIGN_32 },
1011    { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        TB_ALIGN_32 },
1012    { X86::VSUBPDYrr,         X86::VSUBPDYrm,          TB_ALIGN_32 },
1013    { X86::VSUBPSYrr,         X86::VSUBPSYrm,          TB_ALIGN_32 },
1014    { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       TB_ALIGN_32 },
1015    { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       TB_ALIGN_32 },
1016    { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       TB_ALIGN_32 },
1017    { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       TB_ALIGN_32 },
1018    { X86::VXORPDYrr,         X86::VXORPDYrm,          TB_ALIGN_32 },
1019    { X86::VXORPSYrr,         X86::VXORPSYrm,          TB_ALIGN_32 },
1020    // AVX2 foldable instructions
1021    { X86::VINSERTI128rr,     X86::VINSERTI128rm,      TB_ALIGN_16 },
1022    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       TB_ALIGN_32 },
1023    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       TB_ALIGN_32 },
1024    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       TB_ALIGN_32 },
1025    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       TB_ALIGN_32 },
1026    { X86::VPADDBYrr,         X86::VPADDBYrm,          TB_ALIGN_32 },
1027    { X86::VPADDDYrr,         X86::VPADDDYrm,          TB_ALIGN_32 },
1028    { X86::VPADDQYrr,         X86::VPADDQYrm,          TB_ALIGN_32 },
1029    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         TB_ALIGN_32 },
1030    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         TB_ALIGN_32 },
1031    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        TB_ALIGN_32 },
1032    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        TB_ALIGN_32 },
1033    { X86::VPADDWYrr,         X86::VPADDWYrm,          TB_ALIGN_32 },
1034    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      TB_ALIGN_32 },
1035    { X86::VPANDNYrr,         X86::VPANDNYrm,          TB_ALIGN_32 },
1036    { X86::VPANDYrr,          X86::VPANDYrm,           TB_ALIGN_32 },
1037    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          TB_ALIGN_32 },
1038    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          TB_ALIGN_32 },
1039    { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        TB_ALIGN_32 },
1040    { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       TB_ALIGN_32 },
1041    { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       TB_ALIGN_32 },
1042    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        TB_ALIGN_32 },
1043    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        TB_ALIGN_32 },
1044    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        TB_ALIGN_32 },
1045    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        TB_ALIGN_32 },
1046    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        TB_ALIGN_32 },
1047    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        TB_ALIGN_32 },
1048    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        TB_ALIGN_32 },
1049    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        TB_ALIGN_32 },
1050    { X86::VPERM2I128rr,      X86::VPERM2I128rm,       TB_ALIGN_32 },
1051    { X86::VPERMDYrr,         X86::VPERMDYrm,          TB_ALIGN_32 },
1052    { X86::VPERMPDYrr,        X86::VPERMPDYrm,         TB_ALIGN_32 },
1053    { X86::VPERMPSYrr,        X86::VPERMPSYrm,         TB_ALIGN_32 },
1054    { X86::VPERMQYrr,         X86::VPERMQYrm,          TB_ALIGN_32 },
1055    { X86::VPHADDDYrr,        X86::VPHADDDYrm,         TB_ALIGN_32 },
1056    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      TB_ALIGN_32 },
1057    { X86::VPHADDWYrr,        X86::VPHADDWYrm,         TB_ALIGN_32 },
1058    { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         TB_ALIGN_32 },
1059    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      TB_ALIGN_32 },
1060    { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         TB_ALIGN_32 },
1061    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    TB_ALIGN_32 },
1062    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        TB_ALIGN_32 },
1063    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         TB_ALIGN_32 },
1064    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         TB_ALIGN_32 },
1065    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         TB_ALIGN_32 },
1066    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         TB_ALIGN_32 },
1067    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       TB_ALIGN_32 },
1068    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         TB_ALIGN_32 },
1069    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     TB_ALIGN_32 },
1070    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        TB_ALIGN_32 },
1071    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         TB_ALIGN_32 },
1072    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         TB_ALIGN_32 },
1073    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         TB_ALIGN_32 },
1074    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        TB_ALIGN_32 },
1075    { X86::VPORYrr,           X86::VPORYrm,            TB_ALIGN_32 },
1076    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         TB_ALIGN_32 },
1077    { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         TB_ALIGN_32 },
1078    { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         TB_ALIGN_32 },
1079    { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         TB_ALIGN_32 },
1080    { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         TB_ALIGN_32 },
1081    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          TB_ALIGN_16 },
1082    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          TB_ALIGN_16 },
1083    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          TB_ALIGN_16 },
1084    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          TB_ALIGN_16 },
1085    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         TB_ALIGN_32 },
1086    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          TB_ALIGN_16 },
1087    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         TB_ALIGN_32 },
1088    { X86::VPSRADYrr,         X86::VPSRADYrm,          TB_ALIGN_16 },
1089    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          TB_ALIGN_16 },
1090    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          TB_ALIGN_16 },
1091    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         TB_ALIGN_32 },
1092    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          TB_ALIGN_16 },
1093    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          TB_ALIGN_16 },
1094    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          TB_ALIGN_16 },
1095    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          TB_ALIGN_16 },
1096    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         TB_ALIGN_32 },
1097    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          TB_ALIGN_16 },
1098    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         TB_ALIGN_32 },
1099    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          TB_ALIGN_32 },
1100    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          TB_ALIGN_32 },
1101    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         TB_ALIGN_32 },
1102    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         TB_ALIGN_32 },
1103    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          TB_ALIGN_32 },
1104    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      TB_ALIGN_32 },
1105    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      TB_ALIGN_32 },
1106    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     TB_ALIGN_16 },
1107    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      TB_ALIGN_32 },
1108    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      TB_ALIGN_32 },
1109    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      TB_ALIGN_32 },
1110    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     TB_ALIGN_32 },
1111    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      TB_ALIGN_32 },
1112    { X86::VPXORYrr,          X86::VPXORYrm,           TB_ALIGN_32 },
1113    // FIXME: add AVX 256-bit foldable instructions
1114  };
1115
1116  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1117    unsigned RegOp = OpTbl2[i].RegOp;
1118    unsigned MemOp = OpTbl2[i].MemOp;
1119    unsigned Flags = OpTbl2[i].Flags;
1120    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1121                  RegOp, MemOp,
1122                  // Index 2, folded load
1123                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1124  }
1125}
1126
1127void
1128X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1129                            MemOp2RegOpTableType &M2RTable,
1130                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
1131    if ((Flags & TB_NO_FORWARD) == 0) {
1132      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1133      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1134    }
1135    if ((Flags & TB_NO_REVERSE) == 0) {
1136      assert(!M2RTable.count(MemOp) &&
1137           "Duplicated entries in unfolding maps?");
1138      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1139    }
1140}
1141
1142bool
1143X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1144                                    unsigned &SrcReg, unsigned &DstReg,
1145                                    unsigned &SubIdx) const {
1146  switch (MI.getOpcode()) {
1147  default: break;
1148  case X86::MOVSX16rr8:
1149  case X86::MOVZX16rr8:
1150  case X86::MOVSX32rr8:
1151  case X86::MOVZX32rr8:
1152  case X86::MOVSX64rr8:
1153  case X86::MOVZX64rr8:
1154    if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1155      // It's not always legal to reference the low 8-bit of the larger
1156      // register in 32-bit mode.
1157      return false;
1158  case X86::MOVSX32rr16:
1159  case X86::MOVZX32rr16:
1160  case X86::MOVSX64rr16:
1161  case X86::MOVZX64rr16:
1162  case X86::MOVSX64rr32:
1163  case X86::MOVZX64rr32: {
1164    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1165      // Be conservative.
1166      return false;
1167    SrcReg = MI.getOperand(1).getReg();
1168    DstReg = MI.getOperand(0).getReg();
1169    switch (MI.getOpcode()) {
1170    default:
1171      llvm_unreachable(0);
1172    case X86::MOVSX16rr8:
1173    case X86::MOVZX16rr8:
1174    case X86::MOVSX32rr8:
1175    case X86::MOVZX32rr8:
1176    case X86::MOVSX64rr8:
1177    case X86::MOVZX64rr8:
1178      SubIdx = X86::sub_8bit;
1179      break;
1180    case X86::MOVSX32rr16:
1181    case X86::MOVZX32rr16:
1182    case X86::MOVSX64rr16:
1183    case X86::MOVZX64rr16:
1184      SubIdx = X86::sub_16bit;
1185      break;
1186    case X86::MOVSX64rr32:
1187    case X86::MOVZX64rr32:
1188      SubIdx = X86::sub_32bit;
1189      break;
1190    }
1191    return true;
1192  }
1193  }
1194  return false;
1195}
1196
1197/// isFrameOperand - Return true and the FrameIndex if the specified
1198/// operand and follow operands form a reference to the stack frame.
1199bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1200                                  int &FrameIndex) const {
1201  if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1202      MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1203      MI->getOperand(Op+1).getImm() == 1 &&
1204      MI->getOperand(Op+2).getReg() == 0 &&
1205      MI->getOperand(Op+3).getImm() == 0) {
1206    FrameIndex = MI->getOperand(Op).getIndex();
1207    return true;
1208  }
1209  return false;
1210}
1211
1212static bool isFrameLoadOpcode(int Opcode) {
1213  switch (Opcode) {
1214  default:
1215    return false;
1216  case X86::MOV8rm:
1217  case X86::MOV16rm:
1218  case X86::MOV32rm:
1219  case X86::MOV64rm:
1220  case X86::LD_Fp64m:
1221  case X86::MOVSSrm:
1222  case X86::MOVSDrm:
1223  case X86::MOVAPSrm:
1224  case X86::MOVAPDrm:
1225  case X86::MOVDQArm:
1226  case X86::VMOVSSrm:
1227  case X86::VMOVSDrm:
1228  case X86::VMOVAPSrm:
1229  case X86::VMOVAPDrm:
1230  case X86::VMOVDQArm:
1231  case X86::VMOVAPSYrm:
1232  case X86::VMOVAPDYrm:
1233  case X86::VMOVDQAYrm:
1234  case X86::MMX_MOVD64rm:
1235  case X86::MMX_MOVQ64rm:
1236    return true;
1237  }
1238}
1239
1240static bool isFrameStoreOpcode(int Opcode) {
1241  switch (Opcode) {
1242  default: break;
1243  case X86::MOV8mr:
1244  case X86::MOV16mr:
1245  case X86::MOV32mr:
1246  case X86::MOV64mr:
1247  case X86::ST_FpP64m:
1248  case X86::MOVSSmr:
1249  case X86::MOVSDmr:
1250  case X86::MOVAPSmr:
1251  case X86::MOVAPDmr:
1252  case X86::MOVDQAmr:
1253  case X86::VMOVSSmr:
1254  case X86::VMOVSDmr:
1255  case X86::VMOVAPSmr:
1256  case X86::VMOVAPDmr:
1257  case X86::VMOVDQAmr:
1258  case X86::VMOVAPSYmr:
1259  case X86::VMOVAPDYmr:
1260  case X86::VMOVDQAYmr:
1261  case X86::MMX_MOVD64mr:
1262  case X86::MMX_MOVQ64mr:
1263  case X86::MMX_MOVNTQmr:
1264    return true;
1265  }
1266  return false;
1267}
1268
1269unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1270                                           int &FrameIndex) const {
1271  if (isFrameLoadOpcode(MI->getOpcode()))
1272    if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1273      return MI->getOperand(0).getReg();
1274  return 0;
1275}
1276
1277unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1278                                                 int &FrameIndex) const {
1279  if (isFrameLoadOpcode(MI->getOpcode())) {
1280    unsigned Reg;
1281    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1282      return Reg;
1283    // Check for post-frame index elimination operations
1284    const MachineMemOperand *Dummy;
1285    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1286  }
1287  return 0;
1288}
1289
1290unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1291                                          int &FrameIndex) const {
1292  if (isFrameStoreOpcode(MI->getOpcode()))
1293    if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1294        isFrameOperand(MI, 0, FrameIndex))
1295      return MI->getOperand(X86::AddrNumOperands).getReg();
1296  return 0;
1297}
1298
1299unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1300                                                int &FrameIndex) const {
1301  if (isFrameStoreOpcode(MI->getOpcode())) {
1302    unsigned Reg;
1303    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1304      return Reg;
1305    // Check for post-frame index elimination operations
1306    const MachineMemOperand *Dummy;
1307    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1308  }
1309  return 0;
1310}
1311
1312/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1313/// X86::MOVPC32r.
1314static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1315  bool isPICBase = false;
1316  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1317         E = MRI.def_end(); I != E; ++I) {
1318    MachineInstr *DefMI = I.getOperand().getParent();
1319    if (DefMI->getOpcode() != X86::MOVPC32r)
1320      return false;
1321    assert(!isPICBase && "More than one PIC base?");
1322    isPICBase = true;
1323  }
1324  return isPICBase;
1325}
1326
1327bool
1328X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1329                                                AliasAnalysis *AA) const {
1330  switch (MI->getOpcode()) {
1331  default: break;
1332    case X86::MOV8rm:
1333    case X86::MOV16rm:
1334    case X86::MOV32rm:
1335    case X86::MOV64rm:
1336    case X86::LD_Fp64m:
1337    case X86::MOVSSrm:
1338    case X86::MOVSDrm:
1339    case X86::MOVAPSrm:
1340    case X86::MOVUPSrm:
1341    case X86::MOVAPDrm:
1342    case X86::MOVDQArm:
1343    case X86::VMOVSSrm:
1344    case X86::VMOVSDrm:
1345    case X86::VMOVAPSrm:
1346    case X86::VMOVUPSrm:
1347    case X86::VMOVAPDrm:
1348    case X86::VMOVDQArm:
1349    case X86::VMOVAPSYrm:
1350    case X86::VMOVUPSYrm:
1351    case X86::VMOVAPDYrm:
1352    case X86::VMOVDQAYrm:
1353    case X86::MMX_MOVD64rm:
1354    case X86::MMX_MOVQ64rm:
1355    case X86::FsVMOVAPSrm:
1356    case X86::FsVMOVAPDrm:
1357    case X86::FsMOVAPSrm:
1358    case X86::FsMOVAPDrm: {
1359      // Loads from constant pools are trivially rematerializable.
1360      if (MI->getOperand(1).isReg() &&
1361          MI->getOperand(2).isImm() &&
1362          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1363          MI->isInvariantLoad(AA)) {
1364        unsigned BaseReg = MI->getOperand(1).getReg();
1365        if (BaseReg == 0 || BaseReg == X86::RIP)
1366          return true;
1367        // Allow re-materialization of PIC load.
1368        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1369          return false;
1370        const MachineFunction &MF = *MI->getParent()->getParent();
1371        const MachineRegisterInfo &MRI = MF.getRegInfo();
1372        bool isPICBase = false;
1373        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1374               E = MRI.def_end(); I != E; ++I) {
1375          MachineInstr *DefMI = I.getOperand().getParent();
1376          if (DefMI->getOpcode() != X86::MOVPC32r)
1377            return false;
1378          assert(!isPICBase && "More than one PIC base?");
1379          isPICBase = true;
1380        }
1381        return isPICBase;
1382      }
1383      return false;
1384    }
1385
1386     case X86::LEA32r:
1387     case X86::LEA64r: {
1388       if (MI->getOperand(2).isImm() &&
1389           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1390           !MI->getOperand(4).isReg()) {
1391         // lea fi#, lea GV, etc. are all rematerializable.
1392         if (!MI->getOperand(1).isReg())
1393           return true;
1394         unsigned BaseReg = MI->getOperand(1).getReg();
1395         if (BaseReg == 0)
1396           return true;
1397         // Allow re-materialization of lea PICBase + x.
1398         const MachineFunction &MF = *MI->getParent()->getParent();
1399         const MachineRegisterInfo &MRI = MF.getRegInfo();
1400         return regIsPICBase(BaseReg, MRI);
1401       }
1402       return false;
1403     }
1404  }
1405
1406  // All other instructions marked M_REMATERIALIZABLE are always trivially
1407  // rematerializable.
1408  return true;
1409}
1410
1411/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1412/// would clobber the EFLAGS condition register. Note the result may be
1413/// conservative. If it cannot definitely determine the safety after visiting
1414/// a few instructions in each direction it assumes it's not safe.
1415static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1416                                  MachineBasicBlock::iterator I) {
1417  MachineBasicBlock::iterator E = MBB.end();
1418
1419  // For compile time consideration, if we are not able to determine the
1420  // safety after visiting 4 instructions in each direction, we will assume
1421  // it's not safe.
1422  MachineBasicBlock::iterator Iter = I;
1423  for (unsigned i = 0; Iter != E && i < 4; ++i) {
1424    bool SeenDef = false;
1425    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1426      MachineOperand &MO = Iter->getOperand(j);
1427      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1428        SeenDef = true;
1429      if (!MO.isReg())
1430        continue;
1431      if (MO.getReg() == X86::EFLAGS) {
1432        if (MO.isUse())
1433          return false;
1434        SeenDef = true;
1435      }
1436    }
1437
1438    if (SeenDef)
1439      // This instruction defines EFLAGS, no need to look any further.
1440      return true;
1441    ++Iter;
1442    // Skip over DBG_VALUE.
1443    while (Iter != E && Iter->isDebugValue())
1444      ++Iter;
1445  }
1446
1447  // It is safe to clobber EFLAGS at the end of a block of no successor has it
1448  // live in.
1449  if (Iter == E) {
1450    for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1451           SE = MBB.succ_end(); SI != SE; ++SI)
1452      if ((*SI)->isLiveIn(X86::EFLAGS))
1453        return false;
1454    return true;
1455  }
1456
1457  MachineBasicBlock::iterator B = MBB.begin();
1458  Iter = I;
1459  for (unsigned i = 0; i < 4; ++i) {
1460    // If we make it to the beginning of the block, it's safe to clobber
1461    // EFLAGS iff EFLAGS is not live-in.
1462    if (Iter == B)
1463      return !MBB.isLiveIn(X86::EFLAGS);
1464
1465    --Iter;
1466    // Skip over DBG_VALUE.
1467    while (Iter != B && Iter->isDebugValue())
1468      --Iter;
1469
1470    bool SawKill = false;
1471    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1472      MachineOperand &MO = Iter->getOperand(j);
1473      // A register mask may clobber EFLAGS, but we should still look for a
1474      // live EFLAGS def.
1475      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1476        SawKill = true;
1477      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1478        if (MO.isDef()) return MO.isDead();
1479        if (MO.isKill()) SawKill = true;
1480      }
1481    }
1482
1483    if (SawKill)
1484      // This instruction kills EFLAGS and doesn't redefine it, so
1485      // there's no need to look further.
1486      return true;
1487  }
1488
1489  // Conservative answer.
1490  return false;
1491}
1492
1493void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1494                                 MachineBasicBlock::iterator I,
1495                                 unsigned DestReg, unsigned SubIdx,
1496                                 const MachineInstr *Orig,
1497                                 const TargetRegisterInfo &TRI) const {
1498  DebugLoc DL = Orig->getDebugLoc();
1499
1500  // MOV32r0 etc. are implemented with xor which clobbers condition code.
1501  // Re-materialize them as movri instructions to avoid side effects.
1502  bool Clone = true;
1503  unsigned Opc = Orig->getOpcode();
1504  switch (Opc) {
1505  default: break;
1506  case X86::MOV8r0:
1507  case X86::MOV16r0:
1508  case X86::MOV32r0:
1509  case X86::MOV64r0: {
1510    if (!isSafeToClobberEFLAGS(MBB, I)) {
1511      switch (Opc) {
1512      default: break;
1513      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
1514      case X86::MOV16r0: Opc = X86::MOV16ri; break;
1515      case X86::MOV32r0: Opc = X86::MOV32ri; break;
1516      case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1517      }
1518      Clone = false;
1519    }
1520    break;
1521  }
1522  }
1523
1524  if (Clone) {
1525    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1526    MBB.insert(I, MI);
1527  } else {
1528    BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1529  }
1530
1531  MachineInstr *NewMI = prior(I);
1532  NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1533}
1534
1535/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1536/// is not marked dead.
1537static bool hasLiveCondCodeDef(MachineInstr *MI) {
1538  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1539    MachineOperand &MO = MI->getOperand(i);
1540    if (MO.isReg() && MO.isDef() &&
1541        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1542      return true;
1543    }
1544  }
1545  return false;
1546}
1547
1548/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1549/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1550/// to a 32-bit superregister and then truncating back down to a 16-bit
1551/// subregister.
1552MachineInstr *
1553X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1554                                           MachineFunction::iterator &MFI,
1555                                           MachineBasicBlock::iterator &MBBI,
1556                                           LiveVariables *LV) const {
1557  MachineInstr *MI = MBBI;
1558  unsigned Dest = MI->getOperand(0).getReg();
1559  unsigned Src = MI->getOperand(1).getReg();
1560  bool isDead = MI->getOperand(0).isDead();
1561  bool isKill = MI->getOperand(1).isKill();
1562
1563  unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1564    ? X86::LEA64_32r : X86::LEA32r;
1565  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1566  unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1567  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1568
1569  // Build and insert into an implicit UNDEF value. This is OK because
1570  // well be shifting and then extracting the lower 16-bits.
1571  // This has the potential to cause partial register stall. e.g.
1572  //   movw    (%rbp,%rcx,2), %dx
1573  //   leal    -65(%rdx), %esi
1574  // But testing has shown this *does* help performance in 64-bit mode (at
1575  // least on modern x86 machines).
1576  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1577  MachineInstr *InsMI =
1578    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1579    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1580    .addReg(Src, getKillRegState(isKill));
1581
1582  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1583                                    get(Opc), leaOutReg);
1584  switch (MIOpc) {
1585  default:
1586    llvm_unreachable(0);
1587  case X86::SHL16ri: {
1588    unsigned ShAmt = MI->getOperand(2).getImm();
1589    MIB.addReg(0).addImm(1 << ShAmt)
1590       .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1591    break;
1592  }
1593  case X86::INC16r:
1594  case X86::INC64_16r:
1595    addRegOffset(MIB, leaInReg, true, 1);
1596    break;
1597  case X86::DEC16r:
1598  case X86::DEC64_16r:
1599    addRegOffset(MIB, leaInReg, true, -1);
1600    break;
1601  case X86::ADD16ri:
1602  case X86::ADD16ri8:
1603  case X86::ADD16ri_DB:
1604  case X86::ADD16ri8_DB:
1605    addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1606    break;
1607  case X86::ADD16rr:
1608  case X86::ADD16rr_DB: {
1609    unsigned Src2 = MI->getOperand(2).getReg();
1610    bool isKill2 = MI->getOperand(2).isKill();
1611    unsigned leaInReg2 = 0;
1612    MachineInstr *InsMI2 = 0;
1613    if (Src == Src2) {
1614      // ADD16rr %reg1028<kill>, %reg1028
1615      // just a single insert_subreg.
1616      addRegReg(MIB, leaInReg, true, leaInReg, false);
1617    } else {
1618      leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1619      // Build and insert into an implicit UNDEF value. This is OK because
1620      // well be shifting and then extracting the lower 16-bits.
1621      BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1622      InsMI2 =
1623        BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1624        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1625        .addReg(Src2, getKillRegState(isKill2));
1626      addRegReg(MIB, leaInReg, true, leaInReg2, true);
1627    }
1628    if (LV && isKill2 && InsMI2)
1629      LV->replaceKillInstruction(Src2, MI, InsMI2);
1630    break;
1631  }
1632  }
1633
1634  MachineInstr *NewMI = MIB;
1635  MachineInstr *ExtMI =
1636    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1637    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1638    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1639
1640  if (LV) {
1641    // Update live variables
1642    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1643    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1644    if (isKill)
1645      LV->replaceKillInstruction(Src, MI, InsMI);
1646    if (isDead)
1647      LV->replaceKillInstruction(Dest, MI, ExtMI);
1648  }
1649
1650  return ExtMI;
1651}
1652
1653/// convertToThreeAddress - This method must be implemented by targets that
1654/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1655/// may be able to convert a two-address instruction into a true
1656/// three-address instruction on demand.  This allows the X86 target (for
1657/// example) to convert ADD and SHL instructions into LEA instructions if they
1658/// would require register copies due to two-addressness.
1659///
1660/// This method returns a null pointer if the transformation cannot be
1661/// performed, otherwise it returns the new instruction.
1662///
1663MachineInstr *
1664X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1665                                    MachineBasicBlock::iterator &MBBI,
1666                                    LiveVariables *LV) const {
1667  MachineInstr *MI = MBBI;
1668  MachineFunction &MF = *MI->getParent()->getParent();
1669  // All instructions input are two-addr instructions.  Get the known operands.
1670  unsigned Dest = MI->getOperand(0).getReg();
1671  unsigned Src = MI->getOperand(1).getReg();
1672  bool isDead = MI->getOperand(0).isDead();
1673  bool isKill = MI->getOperand(1).isKill();
1674
1675  MachineInstr *NewMI = NULL;
1676  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1677  // we have better subtarget support, enable the 16-bit LEA generation here.
1678  // 16-bit LEA is also slow on Core2.
1679  bool DisableLEA16 = true;
1680  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1681
1682  unsigned MIOpc = MI->getOpcode();
1683  switch (MIOpc) {
1684  case X86::SHUFPSrri: {
1685    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1686    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1687
1688    unsigned B = MI->getOperand(1).getReg();
1689    unsigned C = MI->getOperand(2).getReg();
1690    if (B != C) return 0;
1691    unsigned A = MI->getOperand(0).getReg();
1692    unsigned M = MI->getOperand(3).getImm();
1693    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1694      .addReg(A, RegState::Define | getDeadRegState(isDead))
1695      .addReg(B, getKillRegState(isKill)).addImm(M);
1696    break;
1697  }
1698  case X86::SHUFPDrri: {
1699    assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1700    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1701
1702    unsigned B = MI->getOperand(1).getReg();
1703    unsigned C = MI->getOperand(2).getReg();
1704    if (B != C) return 0;
1705    unsigned A = MI->getOperand(0).getReg();
1706    unsigned M = MI->getOperand(3).getImm();
1707
1708    // Convert to PSHUFD mask.
1709    M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1710
1711    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1712      .addReg(A, RegState::Define | getDeadRegState(isDead))
1713      .addReg(B, getKillRegState(isKill)).addImm(M);
1714    break;
1715  }
1716  case X86::SHL64ri: {
1717    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1718    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1719    // the flags produced by a shift yet, so this is safe.
1720    unsigned ShAmt = MI->getOperand(2).getImm();
1721    if (ShAmt == 0 || ShAmt >= 4) return 0;
1722
1723    // LEA can't handle RSP.
1724    if (TargetRegisterInfo::isVirtualRegister(Src) &&
1725        !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1726      return 0;
1727
1728    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1729      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1730      .addReg(0).addImm(1 << ShAmt)
1731      .addReg(Src, getKillRegState(isKill))
1732      .addImm(0).addReg(0);
1733    break;
1734  }
1735  case X86::SHL32ri: {
1736    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1737    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1738    // the flags produced by a shift yet, so this is safe.
1739    unsigned ShAmt = MI->getOperand(2).getImm();
1740    if (ShAmt == 0 || ShAmt >= 4) return 0;
1741
1742    // LEA can't handle ESP.
1743    if (TargetRegisterInfo::isVirtualRegister(Src) &&
1744        !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1745      return 0;
1746
1747    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1748    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1749      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1750      .addReg(0).addImm(1 << ShAmt)
1751      .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1752    break;
1753  }
1754  case X86::SHL16ri: {
1755    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1756    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1757    // the flags produced by a shift yet, so this is safe.
1758    unsigned ShAmt = MI->getOperand(2).getImm();
1759    if (ShAmt == 0 || ShAmt >= 4) return 0;
1760
1761    if (DisableLEA16)
1762      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1763    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1764      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1765      .addReg(0).addImm(1 << ShAmt)
1766      .addReg(Src, getKillRegState(isKill))
1767      .addImm(0).addReg(0);
1768    break;
1769  }
1770  default: {
1771    // The following opcodes also sets the condition code register(s). Only
1772    // convert them to equivalent lea if the condition code register def's
1773    // are dead!
1774    if (hasLiveCondCodeDef(MI))
1775      return 0;
1776
1777    switch (MIOpc) {
1778    default: return 0;
1779    case X86::INC64r:
1780    case X86::INC32r:
1781    case X86::INC64_32r: {
1782      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1783      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1784        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1785
1786      // LEA can't handle RSP.
1787      if (TargetRegisterInfo::isVirtualRegister(Src) &&
1788          !MF.getRegInfo().constrainRegClass(Src,
1789                            MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1790                                                   X86::GR32_NOSPRegisterClass))
1791        return 0;
1792
1793      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1794                              .addReg(Dest, RegState::Define |
1795                                      getDeadRegState(isDead)),
1796                              Src, isKill, 1);
1797      break;
1798    }
1799    case X86::INC16r:
1800    case X86::INC64_16r:
1801      if (DisableLEA16)
1802        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1803      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1804      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1805                           .addReg(Dest, RegState::Define |
1806                                   getDeadRegState(isDead)),
1807                           Src, isKill, 1);
1808      break;
1809    case X86::DEC64r:
1810    case X86::DEC32r:
1811    case X86::DEC64_32r: {
1812      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1813      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1814        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1815      // LEA can't handle RSP.
1816      if (TargetRegisterInfo::isVirtualRegister(Src) &&
1817          !MF.getRegInfo().constrainRegClass(Src,
1818                            MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1819                                                   X86::GR32_NOSPRegisterClass))
1820        return 0;
1821
1822      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1823                              .addReg(Dest, RegState::Define |
1824                                      getDeadRegState(isDead)),
1825                              Src, isKill, -1);
1826      break;
1827    }
1828    case X86::DEC16r:
1829    case X86::DEC64_16r:
1830      if (DisableLEA16)
1831        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1832      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1833      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1834                           .addReg(Dest, RegState::Define |
1835                                   getDeadRegState(isDead)),
1836                           Src, isKill, -1);
1837      break;
1838    case X86::ADD64rr:
1839    case X86::ADD64rr_DB:
1840    case X86::ADD32rr:
1841    case X86::ADD32rr_DB: {
1842      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1843      unsigned Opc;
1844      const TargetRegisterClass *RC;
1845      if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1846        Opc = X86::LEA64r;
1847        RC = X86::GR64_NOSPRegisterClass;
1848      } else {
1849        Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1850        RC = X86::GR32_NOSPRegisterClass;
1851      }
1852
1853
1854      unsigned Src2 = MI->getOperand(2).getReg();
1855      bool isKill2 = MI->getOperand(2).isKill();
1856
1857      // LEA can't handle RSP.
1858      if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1859          !MF.getRegInfo().constrainRegClass(Src2, RC))
1860        return 0;
1861
1862      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1863                        .addReg(Dest, RegState::Define |
1864                                getDeadRegState(isDead)),
1865                        Src, isKill, Src2, isKill2);
1866      if (LV && isKill2)
1867        LV->replaceKillInstruction(Src2, MI, NewMI);
1868      break;
1869    }
1870    case X86::ADD16rr:
1871    case X86::ADD16rr_DB: {
1872      if (DisableLEA16)
1873        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1874      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1875      unsigned Src2 = MI->getOperand(2).getReg();
1876      bool isKill2 = MI->getOperand(2).isKill();
1877      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1878                        .addReg(Dest, RegState::Define |
1879                                getDeadRegState(isDead)),
1880                        Src, isKill, Src2, isKill2);
1881      if (LV && isKill2)
1882        LV->replaceKillInstruction(Src2, MI, NewMI);
1883      break;
1884    }
1885    case X86::ADD64ri32:
1886    case X86::ADD64ri8:
1887    case X86::ADD64ri32_DB:
1888    case X86::ADD64ri8_DB:
1889      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1890      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1891                              .addReg(Dest, RegState::Define |
1892                                      getDeadRegState(isDead)),
1893                              Src, isKill, MI->getOperand(2).getImm());
1894      break;
1895    case X86::ADD32ri:
1896    case X86::ADD32ri8:
1897    case X86::ADD32ri_DB:
1898    case X86::ADD32ri8_DB: {
1899      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1900      unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1901      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1902                              .addReg(Dest, RegState::Define |
1903                                      getDeadRegState(isDead)),
1904                                Src, isKill, MI->getOperand(2).getImm());
1905      break;
1906    }
1907    case X86::ADD16ri:
1908    case X86::ADD16ri8:
1909    case X86::ADD16ri_DB:
1910    case X86::ADD16ri8_DB:
1911      if (DisableLEA16)
1912        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1913      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1914      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1915                              .addReg(Dest, RegState::Define |
1916                                      getDeadRegState(isDead)),
1917                              Src, isKill, MI->getOperand(2).getImm());
1918      break;
1919    }
1920  }
1921  }
1922
1923  if (!NewMI) return 0;
1924
1925  if (LV) {  // Update live variables
1926    if (isKill)
1927      LV->replaceKillInstruction(Src, MI, NewMI);
1928    if (isDead)
1929      LV->replaceKillInstruction(Dest, MI, NewMI);
1930  }
1931
1932  MFI->insert(MBBI, NewMI);          // Insert the new inst
1933  return NewMI;
1934}
1935
1936/// commuteInstruction - We have a few instructions that must be hacked on to
1937/// commute them.
1938///
1939MachineInstr *
1940X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1941  switch (MI->getOpcode()) {
1942  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1943  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1944  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1945  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1946  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1947  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1948    unsigned Opc;
1949    unsigned Size;
1950    switch (MI->getOpcode()) {
1951    default: llvm_unreachable("Unreachable!");
1952    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1953    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1954    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1955    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1956    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1957    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1958    }
1959    unsigned Amt = MI->getOperand(3).getImm();
1960    if (NewMI) {
1961      MachineFunction &MF = *MI->getParent()->getParent();
1962      MI = MF.CloneMachineInstr(MI);
1963      NewMI = false;
1964    }
1965    MI->setDesc(get(Opc));
1966    MI->getOperand(3).setImm(Size-Amt);
1967    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1968  }
1969  case X86::CMOVB16rr:
1970  case X86::CMOVB32rr:
1971  case X86::CMOVB64rr:
1972  case X86::CMOVAE16rr:
1973  case X86::CMOVAE32rr:
1974  case X86::CMOVAE64rr:
1975  case X86::CMOVE16rr:
1976  case X86::CMOVE32rr:
1977  case X86::CMOVE64rr:
1978  case X86::CMOVNE16rr:
1979  case X86::CMOVNE32rr:
1980  case X86::CMOVNE64rr:
1981  case X86::CMOVBE16rr:
1982  case X86::CMOVBE32rr:
1983  case X86::CMOVBE64rr:
1984  case X86::CMOVA16rr:
1985  case X86::CMOVA32rr:
1986  case X86::CMOVA64rr:
1987  case X86::CMOVL16rr:
1988  case X86::CMOVL32rr:
1989  case X86::CMOVL64rr:
1990  case X86::CMOVGE16rr:
1991  case X86::CMOVGE32rr:
1992  case X86::CMOVGE64rr:
1993  case X86::CMOVLE16rr:
1994  case X86::CMOVLE32rr:
1995  case X86::CMOVLE64rr:
1996  case X86::CMOVG16rr:
1997  case X86::CMOVG32rr:
1998  case X86::CMOVG64rr:
1999  case X86::CMOVS16rr:
2000  case X86::CMOVS32rr:
2001  case X86::CMOVS64rr:
2002  case X86::CMOVNS16rr:
2003  case X86::CMOVNS32rr:
2004  case X86::CMOVNS64rr:
2005  case X86::CMOVP16rr:
2006  case X86::CMOVP32rr:
2007  case X86::CMOVP64rr:
2008  case X86::CMOVNP16rr:
2009  case X86::CMOVNP32rr:
2010  case X86::CMOVNP64rr:
2011  case X86::CMOVO16rr:
2012  case X86::CMOVO32rr:
2013  case X86::CMOVO64rr:
2014  case X86::CMOVNO16rr:
2015  case X86::CMOVNO32rr:
2016  case X86::CMOVNO64rr: {
2017    unsigned Opc = 0;
2018    switch (MI->getOpcode()) {
2019    default: break;
2020    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2021    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2022    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2023    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2024    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2025    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2026    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2027    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2028    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2029    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2030    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2031    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2032    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2033    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2034    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2035    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2036    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2037    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2038    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2039    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2040    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2041    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2042    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2043    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2044    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2045    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2046    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2047    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2048    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2049    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2050    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2051    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2052    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2053    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2054    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2055    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2056    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2057    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2058    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2059    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2060    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2061    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2062    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2063    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2064    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2065    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2066    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2067    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2068    }
2069    if (NewMI) {
2070      MachineFunction &MF = *MI->getParent()->getParent();
2071      MI = MF.CloneMachineInstr(MI);
2072      NewMI = false;
2073    }
2074    MI->setDesc(get(Opc));
2075    // Fallthrough intended.
2076  }
2077  default:
2078    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2079  }
2080}
2081
2082static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
2083  switch (BrOpc) {
2084  default: return X86::COND_INVALID;
2085  case X86::JE_4:  return X86::COND_E;
2086  case X86::JNE_4: return X86::COND_NE;
2087  case X86::JL_4:  return X86::COND_L;
2088  case X86::JLE_4: return X86::COND_LE;
2089  case X86::JG_4:  return X86::COND_G;
2090  case X86::JGE_4: return X86::COND_GE;
2091  case X86::JB_4:  return X86::COND_B;
2092  case X86::JBE_4: return X86::COND_BE;
2093  case X86::JA_4:  return X86::COND_A;
2094  case X86::JAE_4: return X86::COND_AE;
2095  case X86::JS_4:  return X86::COND_S;
2096  case X86::JNS_4: return X86::COND_NS;
2097  case X86::JP_4:  return X86::COND_P;
2098  case X86::JNP_4: return X86::COND_NP;
2099  case X86::JO_4:  return X86::COND_O;
2100  case X86::JNO_4: return X86::COND_NO;
2101  }
2102}
2103
2104unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2105  switch (CC) {
2106  default: llvm_unreachable("Illegal condition code!");
2107  case X86::COND_E:  return X86::JE_4;
2108  case X86::COND_NE: return X86::JNE_4;
2109  case X86::COND_L:  return X86::JL_4;
2110  case X86::COND_LE: return X86::JLE_4;
2111  case X86::COND_G:  return X86::JG_4;
2112  case X86::COND_GE: return X86::JGE_4;
2113  case X86::COND_B:  return X86::JB_4;
2114  case X86::COND_BE: return X86::JBE_4;
2115  case X86::COND_A:  return X86::JA_4;
2116  case X86::COND_AE: return X86::JAE_4;
2117  case X86::COND_S:  return X86::JS_4;
2118  case X86::COND_NS: return X86::JNS_4;
2119  case X86::COND_P:  return X86::JP_4;
2120  case X86::COND_NP: return X86::JNP_4;
2121  case X86::COND_O:  return X86::JO_4;
2122  case X86::COND_NO: return X86::JNO_4;
2123  }
2124}
2125
2126/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2127/// e.g. turning COND_E to COND_NE.
2128X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2129  switch (CC) {
2130  default: llvm_unreachable("Illegal condition code!");
2131  case X86::COND_E:  return X86::COND_NE;
2132  case X86::COND_NE: return X86::COND_E;
2133  case X86::COND_L:  return X86::COND_GE;
2134  case X86::COND_LE: return X86::COND_G;
2135  case X86::COND_G:  return X86::COND_LE;
2136  case X86::COND_GE: return X86::COND_L;
2137  case X86::COND_B:  return X86::COND_AE;
2138  case X86::COND_BE: return X86::COND_A;
2139  case X86::COND_A:  return X86::COND_BE;
2140  case X86::COND_AE: return X86::COND_B;
2141  case X86::COND_S:  return X86::COND_NS;
2142  case X86::COND_NS: return X86::COND_S;
2143  case X86::COND_P:  return X86::COND_NP;
2144  case X86::COND_NP: return X86::COND_P;
2145  case X86::COND_O:  return X86::COND_NO;
2146  case X86::COND_NO: return X86::COND_O;
2147  }
2148}
2149
2150bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2151  if (!MI->isTerminator()) return false;
2152
2153  // Conditional branch is a special case.
2154  if (MI->isBranch() && !MI->isBarrier())
2155    return true;
2156  if (!MI->isPredicable())
2157    return true;
2158  return !isPredicated(MI);
2159}
2160
2161bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2162                                 MachineBasicBlock *&TBB,
2163                                 MachineBasicBlock *&FBB,
2164                                 SmallVectorImpl<MachineOperand> &Cond,
2165                                 bool AllowModify) const {
2166  // Start from the bottom of the block and work up, examining the
2167  // terminator instructions.
2168  MachineBasicBlock::iterator I = MBB.end();
2169  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2170  while (I != MBB.begin()) {
2171    --I;
2172    if (I->isDebugValue())
2173      continue;
2174
2175    // Working from the bottom, when we see a non-terminator instruction, we're
2176    // done.
2177    if (!isUnpredicatedTerminator(I))
2178      break;
2179
2180    // A terminator that isn't a branch can't easily be handled by this
2181    // analysis.
2182    if (!I->isBranch())
2183      return true;
2184
2185    // Handle unconditional branches.
2186    if (I->getOpcode() == X86::JMP_4) {
2187      UnCondBrIter = I;
2188
2189      if (!AllowModify) {
2190        TBB = I->getOperand(0).getMBB();
2191        continue;
2192      }
2193
2194      // If the block has any instructions after a JMP, delete them.
2195      while (llvm::next(I) != MBB.end())
2196        llvm::next(I)->eraseFromParent();
2197
2198      Cond.clear();
2199      FBB = 0;
2200
2201      // Delete the JMP if it's equivalent to a fall-through.
2202      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2203        TBB = 0;
2204        I->eraseFromParent();
2205        I = MBB.end();
2206        UnCondBrIter = MBB.end();
2207        continue;
2208      }
2209
2210      // TBB is used to indicate the unconditional destination.
2211      TBB = I->getOperand(0).getMBB();
2212      continue;
2213    }
2214
2215    // Handle conditional branches.
2216    X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2217    if (BranchCode == X86::COND_INVALID)
2218      return true;  // Can't handle indirect branch.
2219
2220    // Working from the bottom, handle the first conditional branch.
2221    if (Cond.empty()) {
2222      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2223      if (AllowModify && UnCondBrIter != MBB.end() &&
2224          MBB.isLayoutSuccessor(TargetBB)) {
2225        // If we can modify the code and it ends in something like:
2226        //
2227        //     jCC L1
2228        //     jmp L2
2229        //   L1:
2230        //     ...
2231        //   L2:
2232        //
2233        // Then we can change this to:
2234        //
2235        //     jnCC L2
2236        //   L1:
2237        //     ...
2238        //   L2:
2239        //
2240        // Which is a bit more efficient.
2241        // We conditionally jump to the fall-through block.
2242        BranchCode = GetOppositeBranchCondition(BranchCode);
2243        unsigned JNCC = GetCondBranchFromCond(BranchCode);
2244        MachineBasicBlock::iterator OldInst = I;
2245
2246        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2247          .addMBB(UnCondBrIter->getOperand(0).getMBB());
2248        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2249          .addMBB(TargetBB);
2250
2251        OldInst->eraseFromParent();
2252        UnCondBrIter->eraseFromParent();
2253
2254        // Restart the analysis.
2255        UnCondBrIter = MBB.end();
2256        I = MBB.end();
2257        continue;
2258      }
2259
2260      FBB = TBB;
2261      TBB = I->getOperand(0).getMBB();
2262      Cond.push_back(MachineOperand::CreateImm(BranchCode));
2263      continue;
2264    }
2265
2266    // Handle subsequent conditional branches. Only handle the case where all
2267    // conditional branches branch to the same destination and their condition
2268    // opcodes fit one of the special multi-branch idioms.
2269    assert(Cond.size() == 1);
2270    assert(TBB);
2271
2272    // Only handle the case where all conditional branches branch to the same
2273    // destination.
2274    if (TBB != I->getOperand(0).getMBB())
2275      return true;
2276
2277    // If the conditions are the same, we can leave them alone.
2278    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2279    if (OldBranchCode == BranchCode)
2280      continue;
2281
2282    // If they differ, see if they fit one of the known patterns. Theoretically,
2283    // we could handle more patterns here, but we shouldn't expect to see them
2284    // if instruction selection has done a reasonable job.
2285    if ((OldBranchCode == X86::COND_NP &&
2286         BranchCode == X86::COND_E) ||
2287        (OldBranchCode == X86::COND_E &&
2288         BranchCode == X86::COND_NP))
2289      BranchCode = X86::COND_NP_OR_E;
2290    else if ((OldBranchCode == X86::COND_P &&
2291              BranchCode == X86::COND_NE) ||
2292             (OldBranchCode == X86::COND_NE &&
2293              BranchCode == X86::COND_P))
2294      BranchCode = X86::COND_NE_OR_P;
2295    else
2296      return true;
2297
2298    // Update the MachineOperand.
2299    Cond[0].setImm(BranchCode);
2300  }
2301
2302  return false;
2303}
2304
2305unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2306  MachineBasicBlock::iterator I = MBB.end();
2307  unsigned Count = 0;
2308
2309  while (I != MBB.begin()) {
2310    --I;
2311    if (I->isDebugValue())
2312      continue;
2313    if (I->getOpcode() != X86::JMP_4 &&
2314        GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2315      break;
2316    // Remove the branch.
2317    I->eraseFromParent();
2318    I = MBB.end();
2319    ++Count;
2320  }
2321
2322  return Count;
2323}
2324
2325unsigned
2326X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2327                           MachineBasicBlock *FBB,
2328                           const SmallVectorImpl<MachineOperand> &Cond,
2329                           DebugLoc DL) const {
2330  // Shouldn't be a fall through.
2331  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2332  assert((Cond.size() == 1 || Cond.size() == 0) &&
2333         "X86 branch conditions have one component!");
2334
2335  if (Cond.empty()) {
2336    // Unconditional branch?
2337    assert(!FBB && "Unconditional branch with multiple successors!");
2338    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2339    return 1;
2340  }
2341
2342  // Conditional branch.
2343  unsigned Count = 0;
2344  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2345  switch (CC) {
2346  case X86::COND_NP_OR_E:
2347    // Synthesize NP_OR_E with two branches.
2348    BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2349    ++Count;
2350    BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2351    ++Count;
2352    break;
2353  case X86::COND_NE_OR_P:
2354    // Synthesize NE_OR_P with two branches.
2355    BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2356    ++Count;
2357    BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2358    ++Count;
2359    break;
2360  default: {
2361    unsigned Opc = GetCondBranchFromCond(CC);
2362    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2363    ++Count;
2364  }
2365  }
2366  if (FBB) {
2367    // Two-way Conditional branch. Insert the second branch.
2368    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2369    ++Count;
2370  }
2371  return Count;
2372}
2373
2374/// isHReg - Test if the given register is a physical h register.
2375static bool isHReg(unsigned Reg) {
2376  return X86::GR8_ABCD_HRegClass.contains(Reg);
2377}
2378
2379// Try and copy between VR128/VR64 and GR64 registers.
2380static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2381                                        bool HasAVX) {
2382  // SrcReg(VR128) -> DestReg(GR64)
2383  // SrcReg(VR64)  -> DestReg(GR64)
2384  // SrcReg(GR64)  -> DestReg(VR128)
2385  // SrcReg(GR64)  -> DestReg(VR64)
2386
2387  if (X86::GR64RegClass.contains(DestReg)) {
2388    if (X86::VR128RegClass.contains(SrcReg)) {
2389      // Copy from a VR128 register to a GR64 register.
2390      return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2391    } else if (X86::VR64RegClass.contains(SrcReg)) {
2392      // Copy from a VR64 register to a GR64 register.
2393      return X86::MOVSDto64rr;
2394    }
2395  } else if (X86::GR64RegClass.contains(SrcReg)) {
2396    // Copy from a GR64 register to a VR128 register.
2397    if (X86::VR128RegClass.contains(DestReg))
2398      return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2399    // Copy from a GR64 register to a VR64 register.
2400    else if (X86::VR64RegClass.contains(DestReg))
2401      return X86::MOV64toSDrr;
2402  }
2403
2404  // SrcReg(FR32) -> DestReg(GR32)
2405  // SrcReg(GR32) -> DestReg(FR32)
2406
2407  if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2408      // Copy from a FR32 register to a GR32 register.
2409      return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2410
2411  if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2412      // Copy from a GR32 register to a FR32 register.
2413      return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2414
2415  return 0;
2416}
2417
2418void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2419                               MachineBasicBlock::iterator MI, DebugLoc DL,
2420                               unsigned DestReg, unsigned SrcReg,
2421                               bool KillSrc) const {
2422  // First deal with the normal symmetric copies.
2423  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2424  unsigned Opc = 0;
2425  if (X86::GR64RegClass.contains(DestReg, SrcReg))
2426    Opc = X86::MOV64rr;
2427  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2428    Opc = X86::MOV32rr;
2429  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2430    Opc = X86::MOV16rr;
2431  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2432    // Copying to or from a physical H register on x86-64 requires a NOREX
2433    // move.  Otherwise use a normal move.
2434    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2435        TM.getSubtarget<X86Subtarget>().is64Bit()) {
2436      Opc = X86::MOV8rr_NOREX;
2437      // Both operands must be encodable without an REX prefix.
2438      assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2439             "8-bit H register can not be copied outside GR8_NOREX");
2440    } else
2441      Opc = X86::MOV8rr;
2442  } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2443    Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2444  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2445    Opc = X86::VMOVAPSYrr;
2446  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2447    Opc = X86::MMX_MOVQ64rr;
2448  else
2449    Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2450
2451  if (Opc) {
2452    BuildMI(MBB, MI, DL, get(Opc), DestReg)
2453      .addReg(SrcReg, getKillRegState(KillSrc));
2454    return;
2455  }
2456
2457  // Moving EFLAGS to / from another register requires a push and a pop.
2458  if (SrcReg == X86::EFLAGS) {
2459    if (X86::GR64RegClass.contains(DestReg)) {
2460      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2461      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2462      return;
2463    } else if (X86::GR32RegClass.contains(DestReg)) {
2464      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2465      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2466      return;
2467    }
2468  }
2469  if (DestReg == X86::EFLAGS) {
2470    if (X86::GR64RegClass.contains(SrcReg)) {
2471      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2472        .addReg(SrcReg, getKillRegState(KillSrc));
2473      BuildMI(MBB, MI, DL, get(X86::POPF64));
2474      return;
2475    } else if (X86::GR32RegClass.contains(SrcReg)) {
2476      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2477        .addReg(SrcReg, getKillRegState(KillSrc));
2478      BuildMI(MBB, MI, DL, get(X86::POPF32));
2479      return;
2480    }
2481  }
2482
2483  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2484               << " to " << RI.getName(DestReg) << '\n');
2485  llvm_unreachable("Cannot emit physreg copy instruction");
2486}
2487
2488static unsigned getLoadStoreRegOpcode(unsigned Reg,
2489                                      const TargetRegisterClass *RC,
2490                                      bool isStackAligned,
2491                                      const TargetMachine &TM,
2492                                      bool load) {
2493  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2494  switch (RC->getSize()) {
2495  default:
2496    llvm_unreachable("Unknown spill size");
2497  case 1:
2498    assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2499    if (TM.getSubtarget<X86Subtarget>().is64Bit())
2500      // Copying to or from a physical H register on x86-64 requires a NOREX
2501      // move.  Otherwise use a normal move.
2502      if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2503        return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2504    return load ? X86::MOV8rm : X86::MOV8mr;
2505  case 2:
2506    assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2507    return load ? X86::MOV16rm : X86::MOV16mr;
2508  case 4:
2509    if (X86::GR32RegClass.hasSubClassEq(RC))
2510      return load ? X86::MOV32rm : X86::MOV32mr;
2511    if (X86::FR32RegClass.hasSubClassEq(RC))
2512      return load ?
2513        (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2514        (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2515    if (X86::RFP32RegClass.hasSubClassEq(RC))
2516      return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2517    llvm_unreachable("Unknown 4-byte regclass");
2518  case 8:
2519    if (X86::GR64RegClass.hasSubClassEq(RC))
2520      return load ? X86::MOV64rm : X86::MOV64mr;
2521    if (X86::FR64RegClass.hasSubClassEq(RC))
2522      return load ?
2523        (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2524        (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2525    if (X86::VR64RegClass.hasSubClassEq(RC))
2526      return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2527    if (X86::RFP64RegClass.hasSubClassEq(RC))
2528      return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2529    llvm_unreachable("Unknown 8-byte regclass");
2530  case 10:
2531    assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2532    return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2533  case 16: {
2534    assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2535    // If stack is realigned we can use aligned stores.
2536    if (isStackAligned)
2537      return load ?
2538        (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2539        (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2540    else
2541      return load ?
2542        (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2543        (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2544  }
2545  case 32:
2546    assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2547    // If stack is realigned we can use aligned stores.
2548    if (isStackAligned)
2549      return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2550    else
2551      return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2552  }
2553}
2554
2555static unsigned getStoreRegOpcode(unsigned SrcReg,
2556                                  const TargetRegisterClass *RC,
2557                                  bool isStackAligned,
2558                                  TargetMachine &TM) {
2559  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2560}
2561
2562
2563static unsigned getLoadRegOpcode(unsigned DestReg,
2564                                 const TargetRegisterClass *RC,
2565                                 bool isStackAligned,
2566                                 const TargetMachine &TM) {
2567  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2568}
2569
2570void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2571                                       MachineBasicBlock::iterator MI,
2572                                       unsigned SrcReg, bool isKill, int FrameIdx,
2573                                       const TargetRegisterClass *RC,
2574                                       const TargetRegisterInfo *TRI) const {
2575  const MachineFunction &MF = *MBB.getParent();
2576  assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2577         "Stack slot too small for store");
2578  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2579  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2580    RI.canRealignStack(MF);
2581  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2582  DebugLoc DL = MBB.findDebugLoc(MI);
2583  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2584    .addReg(SrcReg, getKillRegState(isKill));
2585}
2586
2587void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2588                                  bool isKill,
2589                                  SmallVectorImpl<MachineOperand> &Addr,
2590                                  const TargetRegisterClass *RC,
2591                                  MachineInstr::mmo_iterator MMOBegin,
2592                                  MachineInstr::mmo_iterator MMOEnd,
2593                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
2594  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2595  bool isAligned = MMOBegin != MMOEnd &&
2596                   (*MMOBegin)->getAlignment() >= Alignment;
2597  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2598  DebugLoc DL;
2599  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2600  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2601    MIB.addOperand(Addr[i]);
2602  MIB.addReg(SrcReg, getKillRegState(isKill));
2603  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2604  NewMIs.push_back(MIB);
2605}
2606
2607
2608void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2609                                        MachineBasicBlock::iterator MI,
2610                                        unsigned DestReg, int FrameIdx,
2611                                        const TargetRegisterClass *RC,
2612                                        const TargetRegisterInfo *TRI) const {
2613  const MachineFunction &MF = *MBB.getParent();
2614  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2615  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2616    RI.canRealignStack(MF);
2617  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2618  DebugLoc DL = MBB.findDebugLoc(MI);
2619  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2620}
2621
2622void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2623                                 SmallVectorImpl<MachineOperand> &Addr,
2624                                 const TargetRegisterClass *RC,
2625                                 MachineInstr::mmo_iterator MMOBegin,
2626                                 MachineInstr::mmo_iterator MMOEnd,
2627                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2628  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2629  bool isAligned = MMOBegin != MMOEnd &&
2630                   (*MMOBegin)->getAlignment() >= Alignment;
2631  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2632  DebugLoc DL;
2633  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2634  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2635    MIB.addOperand(Addr[i]);
2636  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2637  NewMIs.push_back(MIB);
2638}
2639
2640/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2641/// instruction with two undef reads of the register being defined.  This is
2642/// used for mapping:
2643///   %xmm4 = V_SET0
2644/// to:
2645///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2646///
2647static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2648  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2649  unsigned Reg = MI->getOperand(0).getReg();
2650  MI->setDesc(Desc);
2651
2652  // MachineInstr::addOperand() will insert explicit operands before any
2653  // implicit operands.
2654  MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2655                         .addReg(Reg, RegState::Undef);
2656  // But we don't trust that.
2657  assert(MI->getOperand(1).getReg() == Reg &&
2658         MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2659  return true;
2660}
2661
2662bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2663  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2664  switch (MI->getOpcode()) {
2665  case X86::V_SET0:
2666  case X86::FsFLD0SS:
2667  case X86::FsFLD0SD:
2668    return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2669  case X86::TEST8ri_NOREX:
2670    MI->setDesc(get(X86::TEST8ri));
2671    return true;
2672  }
2673  return false;
2674}
2675
2676MachineInstr*
2677X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2678                                       int FrameIx, uint64_t Offset,
2679                                       const MDNode *MDPtr,
2680                                       DebugLoc DL) const {
2681  X86AddressMode AM;
2682  AM.BaseType = X86AddressMode::FrameIndexBase;
2683  AM.Base.FrameIndex = FrameIx;
2684  MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2685  addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2686  return &*MIB;
2687}
2688
2689static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2690                                     const SmallVectorImpl<MachineOperand> &MOs,
2691                                     MachineInstr *MI,
2692                                     const TargetInstrInfo &TII) {
2693  // Create the base instruction with the memory operand as the first part.
2694  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2695                                              MI->getDebugLoc(), true);
2696  MachineInstrBuilder MIB(NewMI);
2697  unsigned NumAddrOps = MOs.size();
2698  for (unsigned i = 0; i != NumAddrOps; ++i)
2699    MIB.addOperand(MOs[i]);
2700  if (NumAddrOps < 4)  // FrameIndex only
2701    addOffset(MIB, 0);
2702
2703  // Loop over the rest of the ri operands, converting them over.
2704  unsigned NumOps = MI->getDesc().getNumOperands()-2;
2705  for (unsigned i = 0; i != NumOps; ++i) {
2706    MachineOperand &MO = MI->getOperand(i+2);
2707    MIB.addOperand(MO);
2708  }
2709  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2710    MachineOperand &MO = MI->getOperand(i);
2711    MIB.addOperand(MO);
2712  }
2713  return MIB;
2714}
2715
2716static MachineInstr *FuseInst(MachineFunction &MF,
2717                              unsigned Opcode, unsigned OpNo,
2718                              const SmallVectorImpl<MachineOperand> &MOs,
2719                              MachineInstr *MI, const TargetInstrInfo &TII) {
2720  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2721                                              MI->getDebugLoc(), true);
2722  MachineInstrBuilder MIB(NewMI);
2723
2724  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2725    MachineOperand &MO = MI->getOperand(i);
2726    if (i == OpNo) {
2727      assert(MO.isReg() && "Expected to fold into reg operand!");
2728      unsigned NumAddrOps = MOs.size();
2729      for (unsigned i = 0; i != NumAddrOps; ++i)
2730        MIB.addOperand(MOs[i]);
2731      if (NumAddrOps < 4)  // FrameIndex only
2732        addOffset(MIB, 0);
2733    } else {
2734      MIB.addOperand(MO);
2735    }
2736  }
2737  return MIB;
2738}
2739
2740static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2741                                const SmallVectorImpl<MachineOperand> &MOs,
2742                                MachineInstr *MI) {
2743  MachineFunction &MF = *MI->getParent()->getParent();
2744  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2745
2746  unsigned NumAddrOps = MOs.size();
2747  for (unsigned i = 0; i != NumAddrOps; ++i)
2748    MIB.addOperand(MOs[i]);
2749  if (NumAddrOps < 4)  // FrameIndex only
2750    addOffset(MIB, 0);
2751  return MIB.addImm(0);
2752}
2753
2754MachineInstr*
2755X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2756                                    MachineInstr *MI, unsigned i,
2757                                    const SmallVectorImpl<MachineOperand> &MOs,
2758                                    unsigned Size, unsigned Align) const {
2759  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2760  bool isTwoAddrFold = false;
2761  unsigned NumOps = MI->getDesc().getNumOperands();
2762  bool isTwoAddr = NumOps > 1 &&
2763    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2764
2765  // FIXME: AsmPrinter doesn't know how to handle
2766  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2767  if (MI->getOpcode() == X86::ADD32ri &&
2768      MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2769    return NULL;
2770
2771  MachineInstr *NewMI = NULL;
2772  // Folding a memory location into the two-address part of a two-address
2773  // instruction is different than folding it other places.  It requires
2774  // replacing the *two* registers with the memory location.
2775  if (isTwoAddr && NumOps >= 2 && i < 2 &&
2776      MI->getOperand(0).isReg() &&
2777      MI->getOperand(1).isReg() &&
2778      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2779    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2780    isTwoAddrFold = true;
2781  } else if (i == 0) { // If operand 0
2782    if (MI->getOpcode() == X86::MOV64r0)
2783      NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2784    else if (MI->getOpcode() == X86::MOV32r0)
2785      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2786    else if (MI->getOpcode() == X86::MOV16r0)
2787      NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2788    else if (MI->getOpcode() == X86::MOV8r0)
2789      NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2790    if (NewMI)
2791      return NewMI;
2792
2793    OpcodeTablePtr = &RegOp2MemOpTable0;
2794  } else if (i == 1) {
2795    OpcodeTablePtr = &RegOp2MemOpTable1;
2796  } else if (i == 2) {
2797    OpcodeTablePtr = &RegOp2MemOpTable2;
2798  }
2799
2800  // If table selected...
2801  if (OpcodeTablePtr) {
2802    // Find the Opcode to fuse
2803    DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2804      OpcodeTablePtr->find(MI->getOpcode());
2805    if (I != OpcodeTablePtr->end()) {
2806      unsigned Opcode = I->second.first;
2807      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2808      if (Align < MinAlign)
2809        return NULL;
2810      bool NarrowToMOV32rm = false;
2811      if (Size) {
2812        unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2813        if (Size < RCSize) {
2814          // Check if it's safe to fold the load. If the size of the object is
2815          // narrower than the load width, then it's not.
2816          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2817            return NULL;
2818          // If this is a 64-bit load, but the spill slot is 32, then we can do
2819          // a 32-bit load which is implicitly zero-extended. This likely is due
2820          // to liveintervalanalysis remat'ing a load from stack slot.
2821          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2822            return NULL;
2823          Opcode = X86::MOV32rm;
2824          NarrowToMOV32rm = true;
2825        }
2826      }
2827
2828      if (isTwoAddrFold)
2829        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2830      else
2831        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2832
2833      if (NarrowToMOV32rm) {
2834        // If this is the special case where we use a MOV32rm to load a 32-bit
2835        // value and zero-extend the top bits. Change the destination register
2836        // to a 32-bit one.
2837        unsigned DstReg = NewMI->getOperand(0).getReg();
2838        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2839          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2840                                                   X86::sub_32bit));
2841        else
2842          NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2843      }
2844      return NewMI;
2845    }
2846  }
2847
2848  // No fusion
2849  if (PrintFailedFusing && !MI->isCopy())
2850    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2851  return NULL;
2852}
2853
2854/// hasPartialRegUpdate - Return true for all instructions that only update
2855/// the first 32 or 64-bits of the destination register and leave the rest
2856/// unmodified. This can be used to avoid folding loads if the instructions
2857/// only update part of the destination register, and the non-updated part is
2858/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2859/// instructions breaks the partial register dependency and it can improve
2860/// performance. e.g.:
2861///
2862///   movss (%rdi), %xmm0
2863///   cvtss2sd %xmm0, %xmm0
2864///
2865/// Instead of
2866///   cvtss2sd (%rdi), %xmm0
2867///
2868/// FIXME: This should be turned into a TSFlags.
2869///
2870static bool hasPartialRegUpdate(unsigned Opcode) {
2871  switch (Opcode) {
2872  case X86::CVTSI2SSrr:
2873  case X86::CVTSI2SS64rr:
2874  case X86::CVTSI2SDrr:
2875  case X86::CVTSI2SD64rr:
2876  case X86::CVTSD2SSrr:
2877  case X86::Int_CVTSD2SSrr:
2878  case X86::CVTSS2SDrr:
2879  case X86::Int_CVTSS2SDrr:
2880  case X86::RCPSSr:
2881  case X86::RCPSSr_Int:
2882  case X86::ROUNDSDr:
2883  case X86::ROUNDSDr_Int:
2884  case X86::ROUNDSSr:
2885  case X86::ROUNDSSr_Int:
2886  case X86::RSQRTSSr:
2887  case X86::RSQRTSSr_Int:
2888  case X86::SQRTSSr:
2889  case X86::SQRTSSr_Int:
2890  // AVX encoded versions
2891  case X86::VCVTSD2SSrr:
2892  case X86::Int_VCVTSD2SSrr:
2893  case X86::VCVTSS2SDrr:
2894  case X86::Int_VCVTSS2SDrr:
2895  case X86::VRCPSSr:
2896  case X86::VROUNDSDr:
2897  case X86::VROUNDSDr_Int:
2898  case X86::VROUNDSSr:
2899  case X86::VROUNDSSr_Int:
2900  case X86::VRSQRTSSr:
2901  case X86::VSQRTSSr:
2902    return true;
2903  }
2904
2905  return false;
2906}
2907
2908/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
2909/// instructions we would like before a partial register update.
2910unsigned X86InstrInfo::
2911getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
2912                             const TargetRegisterInfo *TRI) const {
2913  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
2914    return 0;
2915
2916  // If MI is marked as reading Reg, the partial register update is wanted.
2917  const MachineOperand &MO = MI->getOperand(0);
2918  unsigned Reg = MO.getReg();
2919  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2920    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
2921      return 0;
2922  } else {
2923    if (MI->readsRegister(Reg, TRI))
2924      return 0;
2925  }
2926
2927  // If any of the preceding 16 instructions are reading Reg, insert a
2928  // dependency breaking instruction.  The magic number is based on a few
2929  // Nehalem experiments.
2930  return 16;
2931}
2932
2933void X86InstrInfo::
2934breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
2935                          const TargetRegisterInfo *TRI) const {
2936  unsigned Reg = MI->getOperand(OpNum).getReg();
2937  if (X86::VR128RegClass.contains(Reg)) {
2938    // These instructions are all floating point domain, so xorps is the best
2939    // choice.
2940    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2941    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
2942    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
2943      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
2944  } else if (X86::VR256RegClass.contains(Reg)) {
2945    // Use vxorps to clear the full ymm register.
2946    // It wants to read and write the xmm sub-register.
2947    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
2948    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
2949      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
2950      .addReg(Reg, RegState::ImplicitDefine);
2951  } else
2952    return;
2953  MI->addRegisterKilled(Reg, TRI, true);
2954}
2955
2956MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2957                                                  MachineInstr *MI,
2958                                           const SmallVectorImpl<unsigned> &Ops,
2959                                                  int FrameIndex) const {
2960  // Check switch flag
2961  if (NoFusing) return NULL;
2962
2963  // Unless optimizing for size, don't fold to avoid partial
2964  // register update stalls
2965  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2966      hasPartialRegUpdate(MI->getOpcode()))
2967    return 0;
2968
2969  const MachineFrameInfo *MFI = MF.getFrameInfo();
2970  unsigned Size = MFI->getObjectSize(FrameIndex);
2971  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2972  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2973    unsigned NewOpc = 0;
2974    unsigned RCSize = 0;
2975    switch (MI->getOpcode()) {
2976    default: return NULL;
2977    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
2978    case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2979    case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2980    case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2981    }
2982    // Check if it's safe to fold the load. If the size of the object is
2983    // narrower than the load width, then it's not.
2984    if (Size < RCSize)
2985      return NULL;
2986    // Change to CMPXXri r, 0 first.
2987    MI->setDesc(get(NewOpc));
2988    MI->getOperand(1).ChangeToImmediate(0);
2989  } else if (Ops.size() != 1)
2990    return NULL;
2991
2992  SmallVector<MachineOperand,4> MOs;
2993  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2994  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2995}
2996
2997MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2998                                                  MachineInstr *MI,
2999                                           const SmallVectorImpl<unsigned> &Ops,
3000                                                  MachineInstr *LoadMI) const {
3001  // Check switch flag
3002  if (NoFusing) return NULL;
3003
3004  // Unless optimizing for size, don't fold to avoid partial
3005  // register update stalls
3006  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3007      hasPartialRegUpdate(MI->getOpcode()))
3008    return 0;
3009
3010  // Determine the alignment of the load.
3011  unsigned Alignment = 0;
3012  if (LoadMI->hasOneMemOperand())
3013    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
3014  else
3015    switch (LoadMI->getOpcode()) {
3016    case X86::AVX_SET0PSY:
3017    case X86::AVX_SET0PDY:
3018    case X86::AVX2_SETALLONES:
3019    case X86::AVX2_SET0:
3020      Alignment = 32;
3021      break;
3022    case X86::V_SET0:
3023    case X86::V_SETALLONES:
3024    case X86::AVX_SETALLONES:
3025      Alignment = 16;
3026      break;
3027    case X86::FsFLD0SD:
3028      Alignment = 8;
3029      break;
3030    case X86::FsFLD0SS:
3031      Alignment = 4;
3032      break;
3033    default:
3034      return 0;
3035    }
3036  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3037    unsigned NewOpc = 0;
3038    switch (MI->getOpcode()) {
3039    default: return NULL;
3040    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
3041    case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3042    case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3043    case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3044    }
3045    // Change to CMPXXri r, 0 first.
3046    MI->setDesc(get(NewOpc));
3047    MI->getOperand(1).ChangeToImmediate(0);
3048  } else if (Ops.size() != 1)
3049    return NULL;
3050
3051  // Make sure the subregisters match.
3052  // Otherwise we risk changing the size of the load.
3053  if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3054    return NULL;
3055
3056  SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3057  switch (LoadMI->getOpcode()) {
3058  case X86::V_SET0:
3059  case X86::V_SETALLONES:
3060  case X86::AVX_SET0PSY:
3061  case X86::AVX_SET0PDY:
3062  case X86::AVX_SETALLONES:
3063  case X86::AVX2_SETALLONES:
3064  case X86::AVX2_SET0:
3065  case X86::FsFLD0SD:
3066  case X86::FsFLD0SS: {
3067    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
3068    // Create a constant-pool entry and operands to load from it.
3069
3070    // Medium and large mode can't fold loads this way.
3071    if (TM.getCodeModel() != CodeModel::Small &&
3072        TM.getCodeModel() != CodeModel::Kernel)
3073      return NULL;
3074
3075    // x86-32 PIC requires a PIC base register for constant pools.
3076    unsigned PICBase = 0;
3077    if (TM.getRelocationModel() == Reloc::PIC_) {
3078      if (TM.getSubtarget<X86Subtarget>().is64Bit())
3079        PICBase = X86::RIP;
3080      else
3081        // FIXME: PICBase = getGlobalBaseReg(&MF);
3082        // This doesn't work for several reasons.
3083        // 1. GlobalBaseReg may have been spilled.
3084        // 2. It may not be live at MI.
3085        return NULL;
3086    }
3087
3088    // Create a constant-pool entry.
3089    MachineConstantPool &MCP = *MF.getConstantPool();
3090    Type *Ty;
3091    unsigned Opc = LoadMI->getOpcode();
3092    if (Opc == X86::FsFLD0SS)
3093      Ty = Type::getFloatTy(MF.getFunction()->getContext());
3094    else if (Opc == X86::FsFLD0SD)
3095      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
3096    else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3097      Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
3098    else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
3099      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
3100    else
3101      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
3102
3103    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3104                      Opc == X86::AVX2_SETALLONES);
3105    const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3106                                    Constant::getNullValue(Ty);
3107    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
3108
3109    // Create operands to load from the constant pool entry.
3110    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3111    MOs.push_back(MachineOperand::CreateImm(1));
3112    MOs.push_back(MachineOperand::CreateReg(0, false));
3113    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
3114    MOs.push_back(MachineOperand::CreateReg(0, false));
3115    break;
3116  }
3117  default: {
3118    // Folding a normal load. Just copy the load's address operands.
3119    unsigned NumOps = LoadMI->getDesc().getNumOperands();
3120    for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3121      MOs.push_back(LoadMI->getOperand(i));
3122    break;
3123  }
3124  }
3125  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3126}
3127
3128
3129bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3130                                  const SmallVectorImpl<unsigned> &Ops) const {
3131  // Check switch flag
3132  if (NoFusing) return 0;
3133
3134  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3135    switch (MI->getOpcode()) {
3136    default: return false;
3137    case X86::TEST8rr:
3138    case X86::TEST16rr:
3139    case X86::TEST32rr:
3140    case X86::TEST64rr:
3141      return true;
3142    case X86::ADD32ri:
3143      // FIXME: AsmPrinter doesn't know how to handle
3144      // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3145      if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3146        return false;
3147      break;
3148    }
3149  }
3150
3151  if (Ops.size() != 1)
3152    return false;
3153
3154  unsigned OpNum = Ops[0];
3155  unsigned Opc = MI->getOpcode();
3156  unsigned NumOps = MI->getDesc().getNumOperands();
3157  bool isTwoAddr = NumOps > 1 &&
3158    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3159
3160  // Folding a memory location into the two-address part of a two-address
3161  // instruction is different than folding it other places.  It requires
3162  // replacing the *two* registers with the memory location.
3163  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3164  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3165    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3166  } else if (OpNum == 0) { // If operand 0
3167    switch (Opc) {
3168    case X86::MOV8r0:
3169    case X86::MOV16r0:
3170    case X86::MOV32r0:
3171    case X86::MOV64r0: return true;
3172    default: break;
3173    }
3174    OpcodeTablePtr = &RegOp2MemOpTable0;
3175  } else if (OpNum == 1) {
3176    OpcodeTablePtr = &RegOp2MemOpTable1;
3177  } else if (OpNum == 2) {
3178    OpcodeTablePtr = &RegOp2MemOpTable2;
3179  }
3180
3181  if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3182    return true;
3183  return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3184}
3185
3186bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3187                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3188                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
3189  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3190    MemOp2RegOpTable.find(MI->getOpcode());
3191  if (I == MemOp2RegOpTable.end())
3192    return false;
3193  unsigned Opc = I->second.first;
3194  unsigned Index = I->second.second & TB_INDEX_MASK;
3195  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3196  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3197  if (UnfoldLoad && !FoldedLoad)
3198    return false;
3199  UnfoldLoad &= FoldedLoad;
3200  if (UnfoldStore && !FoldedStore)
3201    return false;
3202  UnfoldStore &= FoldedStore;
3203
3204  const MCInstrDesc &MCID = get(Opc);
3205  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3206  if (!MI->hasOneMemOperand() &&
3207      RC == &X86::VR128RegClass &&
3208      !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3209    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3210    // conservatively assume the address is unaligned. That's bad for
3211    // performance.
3212    return false;
3213  SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3214  SmallVector<MachineOperand,2> BeforeOps;
3215  SmallVector<MachineOperand,2> AfterOps;
3216  SmallVector<MachineOperand,4> ImpOps;
3217  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3218    MachineOperand &Op = MI->getOperand(i);
3219    if (i >= Index && i < Index + X86::AddrNumOperands)
3220      AddrOps.push_back(Op);
3221    else if (Op.isReg() && Op.isImplicit())
3222      ImpOps.push_back(Op);
3223    else if (i < Index)
3224      BeforeOps.push_back(Op);
3225    else if (i > Index)
3226      AfterOps.push_back(Op);
3227  }
3228
3229  // Emit the load instruction.
3230  if (UnfoldLoad) {
3231    std::pair<MachineInstr::mmo_iterator,
3232              MachineInstr::mmo_iterator> MMOs =
3233      MF.extractLoadMemRefs(MI->memoperands_begin(),
3234                            MI->memoperands_end());
3235    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3236    if (UnfoldStore) {
3237      // Address operands cannot be marked isKill.
3238      for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3239        MachineOperand &MO = NewMIs[0]->getOperand(i);
3240        if (MO.isReg())
3241          MO.setIsKill(false);
3242      }
3243    }
3244  }
3245
3246  // Emit the data processing instruction.
3247  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3248  MachineInstrBuilder MIB(DataMI);
3249
3250  if (FoldedStore)
3251    MIB.addReg(Reg, RegState::Define);
3252  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3253    MIB.addOperand(BeforeOps[i]);
3254  if (FoldedLoad)
3255    MIB.addReg(Reg);
3256  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3257    MIB.addOperand(AfterOps[i]);
3258  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3259    MachineOperand &MO = ImpOps[i];
3260    MIB.addReg(MO.getReg(),
3261               getDefRegState(MO.isDef()) |
3262               RegState::Implicit |
3263               getKillRegState(MO.isKill()) |
3264               getDeadRegState(MO.isDead()) |
3265               getUndefRegState(MO.isUndef()));
3266  }
3267  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3268  unsigned NewOpc = 0;
3269  switch (DataMI->getOpcode()) {
3270  default: break;
3271  case X86::CMP64ri32:
3272  case X86::CMP64ri8:
3273  case X86::CMP32ri:
3274  case X86::CMP32ri8:
3275  case X86::CMP16ri:
3276  case X86::CMP16ri8:
3277  case X86::CMP8ri: {
3278    MachineOperand &MO0 = DataMI->getOperand(0);
3279    MachineOperand &MO1 = DataMI->getOperand(1);
3280    if (MO1.getImm() == 0) {
3281      switch (DataMI->getOpcode()) {
3282      default: break;
3283      case X86::CMP64ri8:
3284      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3285      case X86::CMP32ri8:
3286      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
3287      case X86::CMP16ri8:
3288      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
3289      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
3290      }
3291      DataMI->setDesc(get(NewOpc));
3292      MO1.ChangeToRegister(MO0.getReg(), false);
3293    }
3294  }
3295  }
3296  NewMIs.push_back(DataMI);
3297
3298  // Emit the store instruction.
3299  if (UnfoldStore) {
3300    const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
3301    std::pair<MachineInstr::mmo_iterator,
3302              MachineInstr::mmo_iterator> MMOs =
3303      MF.extractStoreMemRefs(MI->memoperands_begin(),
3304                             MI->memoperands_end());
3305    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3306  }
3307
3308  return true;
3309}
3310
3311bool
3312X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3313                                  SmallVectorImpl<SDNode*> &NewNodes) const {
3314  if (!N->isMachineOpcode())
3315    return false;
3316
3317  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3318    MemOp2RegOpTable.find(N->getMachineOpcode());
3319  if (I == MemOp2RegOpTable.end())
3320    return false;
3321  unsigned Opc = I->second.first;
3322  unsigned Index = I->second.second & TB_INDEX_MASK;
3323  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3324  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3325  const MCInstrDesc &MCID = get(Opc);
3326  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3327  unsigned NumDefs = MCID.NumDefs;
3328  std::vector<SDValue> AddrOps;
3329  std::vector<SDValue> BeforeOps;
3330  std::vector<SDValue> AfterOps;
3331  DebugLoc dl = N->getDebugLoc();
3332  unsigned NumOps = N->getNumOperands();
3333  for (unsigned i = 0; i != NumOps-1; ++i) {
3334    SDValue Op = N->getOperand(i);
3335    if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3336      AddrOps.push_back(Op);
3337    else if (i < Index-NumDefs)
3338      BeforeOps.push_back(Op);
3339    else if (i > Index-NumDefs)
3340      AfterOps.push_back(Op);
3341  }
3342  SDValue Chain = N->getOperand(NumOps-1);
3343  AddrOps.push_back(Chain);
3344
3345  // Emit the load instruction.
3346  SDNode *Load = 0;
3347  MachineFunction &MF = DAG.getMachineFunction();
3348  if (FoldedLoad) {
3349    EVT VT = *RC->vt_begin();
3350    std::pair<MachineInstr::mmo_iterator,
3351              MachineInstr::mmo_iterator> MMOs =
3352      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3353                            cast<MachineSDNode>(N)->memoperands_end());
3354    if (!(*MMOs.first) &&
3355        RC == &X86::VR128RegClass &&
3356        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3357      // Do not introduce a slow unaligned load.
3358      return false;
3359    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3360    bool isAligned = (*MMOs.first) &&
3361                     (*MMOs.first)->getAlignment() >= Alignment;
3362    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3363                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
3364    NewNodes.push_back(Load);
3365
3366    // Preserve memory reference information.
3367    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3368  }
3369
3370  // Emit the data processing instruction.
3371  std::vector<EVT> VTs;
3372  const TargetRegisterClass *DstRC = 0;
3373  if (MCID.getNumDefs() > 0) {
3374    DstRC = getRegClass(MCID, 0, &RI);
3375    VTs.push_back(*DstRC->vt_begin());
3376  }
3377  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3378    EVT VT = N->getValueType(i);
3379    if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3380      VTs.push_back(VT);
3381  }
3382  if (Load)
3383    BeforeOps.push_back(SDValue(Load, 0));
3384  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3385  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3386                                      BeforeOps.size());
3387  NewNodes.push_back(NewNode);
3388
3389  // Emit the store instruction.
3390  if (FoldedStore) {
3391    AddrOps.pop_back();
3392    AddrOps.push_back(SDValue(NewNode, 0));
3393    AddrOps.push_back(Chain);
3394    std::pair<MachineInstr::mmo_iterator,
3395              MachineInstr::mmo_iterator> MMOs =
3396      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3397                             cast<MachineSDNode>(N)->memoperands_end());
3398    if (!(*MMOs.first) &&
3399        RC == &X86::VR128RegClass &&
3400        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3401      // Do not introduce a slow unaligned store.
3402      return false;
3403    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3404    bool isAligned = (*MMOs.first) &&
3405                     (*MMOs.first)->getAlignment() >= Alignment;
3406    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3407                                                         isAligned, TM),
3408                                       dl, MVT::Other,
3409                                       &AddrOps[0], AddrOps.size());
3410    NewNodes.push_back(Store);
3411
3412    // Preserve memory reference information.
3413    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3414  }
3415
3416  return true;
3417}
3418
3419unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3420                                      bool UnfoldLoad, bool UnfoldStore,
3421                                      unsigned *LoadRegIndex) const {
3422  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3423    MemOp2RegOpTable.find(Opc);
3424  if (I == MemOp2RegOpTable.end())
3425    return 0;
3426  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3427  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3428  if (UnfoldLoad && !FoldedLoad)
3429    return 0;
3430  if (UnfoldStore && !FoldedStore)
3431    return 0;
3432  if (LoadRegIndex)
3433    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3434  return I->second.first;
3435}
3436
3437bool
3438X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3439                                     int64_t &Offset1, int64_t &Offset2) const {
3440  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3441    return false;
3442  unsigned Opc1 = Load1->getMachineOpcode();
3443  unsigned Opc2 = Load2->getMachineOpcode();
3444  switch (Opc1) {
3445  default: return false;
3446  case X86::MOV8rm:
3447  case X86::MOV16rm:
3448  case X86::MOV32rm:
3449  case X86::MOV64rm:
3450  case X86::LD_Fp32m:
3451  case X86::LD_Fp64m:
3452  case X86::LD_Fp80m:
3453  case X86::MOVSSrm:
3454  case X86::MOVSDrm:
3455  case X86::MMX_MOVD64rm:
3456  case X86::MMX_MOVQ64rm:
3457  case X86::FsMOVAPSrm:
3458  case X86::FsMOVAPDrm:
3459  case X86::MOVAPSrm:
3460  case X86::MOVUPSrm:
3461  case X86::MOVAPDrm:
3462  case X86::MOVDQArm:
3463  case X86::MOVDQUrm:
3464  // AVX load instructions
3465  case X86::VMOVSSrm:
3466  case X86::VMOVSDrm:
3467  case X86::FsVMOVAPSrm:
3468  case X86::FsVMOVAPDrm:
3469  case X86::VMOVAPSrm:
3470  case X86::VMOVUPSrm:
3471  case X86::VMOVAPDrm:
3472  case X86::VMOVDQArm:
3473  case X86::VMOVDQUrm:
3474  case X86::VMOVAPSYrm:
3475  case X86::VMOVUPSYrm:
3476  case X86::VMOVAPDYrm:
3477  case X86::VMOVDQAYrm:
3478  case X86::VMOVDQUYrm:
3479    break;
3480  }
3481  switch (Opc2) {
3482  default: return false;
3483  case X86::MOV8rm:
3484  case X86::MOV16rm:
3485  case X86::MOV32rm:
3486  case X86::MOV64rm:
3487  case X86::LD_Fp32m:
3488  case X86::LD_Fp64m:
3489  case X86::LD_Fp80m:
3490  case X86::MOVSSrm:
3491  case X86::MOVSDrm:
3492  case X86::MMX_MOVD64rm:
3493  case X86::MMX_MOVQ64rm:
3494  case X86::FsMOVAPSrm:
3495  case X86::FsMOVAPDrm:
3496  case X86::MOVAPSrm:
3497  case X86::MOVUPSrm:
3498  case X86::MOVAPDrm:
3499  case X86::MOVDQArm:
3500  case X86::MOVDQUrm:
3501  // AVX load instructions
3502  case X86::VMOVSSrm:
3503  case X86::VMOVSDrm:
3504  case X86::FsVMOVAPSrm:
3505  case X86::FsVMOVAPDrm:
3506  case X86::VMOVAPSrm:
3507  case X86::VMOVUPSrm:
3508  case X86::VMOVAPDrm:
3509  case X86::VMOVDQArm:
3510  case X86::VMOVDQUrm:
3511  case X86::VMOVAPSYrm:
3512  case X86::VMOVUPSYrm:
3513  case X86::VMOVAPDYrm:
3514  case X86::VMOVDQAYrm:
3515  case X86::VMOVDQUYrm:
3516    break;
3517  }
3518
3519  // Check if chain operands and base addresses match.
3520  if (Load1->getOperand(0) != Load2->getOperand(0) ||
3521      Load1->getOperand(5) != Load2->getOperand(5))
3522    return false;
3523  // Segment operands should match as well.
3524  if (Load1->getOperand(4) != Load2->getOperand(4))
3525    return false;
3526  // Scale should be 1, Index should be Reg0.
3527  if (Load1->getOperand(1) == Load2->getOperand(1) &&
3528      Load1->getOperand(2) == Load2->getOperand(2)) {
3529    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3530      return false;
3531
3532    // Now let's examine the displacements.
3533    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3534        isa<ConstantSDNode>(Load2->getOperand(3))) {
3535      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3536      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3537      return true;
3538    }
3539  }
3540  return false;
3541}
3542
3543bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3544                                           int64_t Offset1, int64_t Offset2,
3545                                           unsigned NumLoads) const {
3546  assert(Offset2 > Offset1);
3547  if ((Offset2 - Offset1) / 8 > 64)
3548    return false;
3549
3550  unsigned Opc1 = Load1->getMachineOpcode();
3551  unsigned Opc2 = Load2->getMachineOpcode();
3552  if (Opc1 != Opc2)
3553    return false;  // FIXME: overly conservative?
3554
3555  switch (Opc1) {
3556  default: break;
3557  case X86::LD_Fp32m:
3558  case X86::LD_Fp64m:
3559  case X86::LD_Fp80m:
3560  case X86::MMX_MOVD64rm:
3561  case X86::MMX_MOVQ64rm:
3562    return false;
3563  }
3564
3565  EVT VT = Load1->getValueType(0);
3566  switch (VT.getSimpleVT().SimpleTy) {
3567  default:
3568    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3569    // have 16 of them to play with.
3570    if (TM.getSubtargetImpl()->is64Bit()) {
3571      if (NumLoads >= 3)
3572        return false;
3573    } else if (NumLoads) {
3574      return false;
3575    }
3576    break;
3577  case MVT::i8:
3578  case MVT::i16:
3579  case MVT::i32:
3580  case MVT::i64:
3581  case MVT::f32:
3582  case MVT::f64:
3583    if (NumLoads)
3584      return false;
3585    break;
3586  }
3587
3588  return true;
3589}
3590
3591
3592bool X86InstrInfo::
3593ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3594  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3595  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3596  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3597    return true;
3598  Cond[0].setImm(GetOppositeBranchCondition(CC));
3599  return false;
3600}
3601
3602bool X86InstrInfo::
3603isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3604  // FIXME: Return false for x87 stack register classes for now. We can't
3605  // allow any loads of these registers before FpGet_ST0_80.
3606  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3607           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3608}
3609
3610/// getGlobalBaseReg - Return a virtual register initialized with the
3611/// the global base register value. Output instructions required to
3612/// initialize the register in the function entry block, if necessary.
3613///
3614/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3615///
3616unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3617  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3618         "X86-64 PIC uses RIP relative addressing");
3619
3620  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3621  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3622  if (GlobalBaseReg != 0)
3623    return GlobalBaseReg;
3624
3625  // Create the register. The code to initialize it is inserted
3626  // later, by the CGBR pass (below).
3627  MachineRegisterInfo &RegInfo = MF->getRegInfo();
3628  GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3629  X86FI->setGlobalBaseReg(GlobalBaseReg);
3630  return GlobalBaseReg;
3631}
3632
3633// These are the replaceable SSE instructions. Some of these have Int variants
3634// that we don't include here. We don't want to replace instructions selected
3635// by intrinsics.
3636static const uint16_t ReplaceableInstrs[][3] = {
3637  //PackedSingle     PackedDouble    PackedInt
3638  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
3639  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
3640  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
3641  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
3642  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
3643  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
3644  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
3645  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
3646  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
3647  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
3648  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
3649  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
3650  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
3651  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
3652  // AVX 128-bit support
3653  { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
3654  { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
3655  { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
3656  { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
3657  { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
3658  { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3659  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
3660  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
3661  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
3662  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
3663  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
3664  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
3665  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
3666  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
3667  // AVX 256-bit support
3668  { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
3669  { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
3670  { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
3671  { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
3672  { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
3673  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
3674};
3675
3676static const uint16_t ReplaceableInstrsAVX2[][3] = {
3677  //PackedSingle       PackedDouble       PackedInt
3678  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
3679  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
3680  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
3681  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
3682  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
3683  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
3684  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
3685  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
3686  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3687  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3688  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
3689  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
3690  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
3691  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
3692};
3693
3694// FIXME: Some shuffle and unpack instructions have equivalents in different
3695// domains, but they require a bit more work than just switching opcodes.
3696
3697static const uint16_t *lookup(unsigned opcode, unsigned domain) {
3698  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3699    if (ReplaceableInstrs[i][domain-1] == opcode)
3700      return ReplaceableInstrs[i];
3701  return 0;
3702}
3703
3704static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
3705  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3706    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3707      return ReplaceableInstrsAVX2[i];
3708  return 0;
3709}
3710
3711std::pair<uint16_t, uint16_t>
3712X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3713  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3714  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
3715  uint16_t validDomains = 0;
3716  if (domain && lookup(MI->getOpcode(), domain))
3717    validDomains = 0xe;
3718  else if (domain && lookupAVX2(MI->getOpcode(), domain))
3719    validDomains = hasAVX2 ? 0xe : 0x6;
3720  return std::make_pair(domain, validDomains);
3721}
3722
3723void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3724  assert(Domain>0 && Domain<4 && "Invalid execution domain");
3725  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3726  assert(dom && "Not an SSE instruction");
3727  const uint16_t *table = lookup(MI->getOpcode(), dom);
3728  if (!table) { // try the other table
3729    assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3730           "256-bit vector operations only available in AVX2");
3731    table = lookupAVX2(MI->getOpcode(), dom);
3732  }
3733  assert(table && "Cannot change domain");
3734  MI->setDesc(get(table[Domain-1]));
3735}
3736
3737/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3738void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3739  NopInst.setOpcode(X86::NOOP);
3740}
3741
3742bool X86InstrInfo::isHighLatencyDef(int opc) const {
3743  switch (opc) {
3744  default: return false;
3745  case X86::DIVSDrm:
3746  case X86::DIVSDrm_Int:
3747  case X86::DIVSDrr:
3748  case X86::DIVSDrr_Int:
3749  case X86::DIVSSrm:
3750  case X86::DIVSSrm_Int:
3751  case X86::DIVSSrr:
3752  case X86::DIVSSrr_Int:
3753  case X86::SQRTPDm:
3754  case X86::SQRTPDm_Int:
3755  case X86::SQRTPDr:
3756  case X86::SQRTPDr_Int:
3757  case X86::SQRTPSm:
3758  case X86::SQRTPSm_Int:
3759  case X86::SQRTPSr:
3760  case X86::SQRTPSr_Int:
3761  case X86::SQRTSDm:
3762  case X86::SQRTSDm_Int:
3763  case X86::SQRTSDr:
3764  case X86::SQRTSDr_Int:
3765  case X86::SQRTSSm:
3766  case X86::SQRTSSm_Int:
3767  case X86::SQRTSSr:
3768  case X86::SQRTSSr_Int:
3769  // AVX instructions with high latency
3770  case X86::VDIVSDrm:
3771  case X86::VDIVSDrm_Int:
3772  case X86::VDIVSDrr:
3773  case X86::VDIVSDrr_Int:
3774  case X86::VDIVSSrm:
3775  case X86::VDIVSSrm_Int:
3776  case X86::VDIVSSrr:
3777  case X86::VDIVSSrr_Int:
3778  case X86::VSQRTPDm:
3779  case X86::VSQRTPDm_Int:
3780  case X86::VSQRTPDr:
3781  case X86::VSQRTPDr_Int:
3782  case X86::VSQRTPSm:
3783  case X86::VSQRTPSm_Int:
3784  case X86::VSQRTPSr:
3785  case X86::VSQRTPSr_Int:
3786  case X86::VSQRTSDm:
3787  case X86::VSQRTSDm_Int:
3788  case X86::VSQRTSDr:
3789  case X86::VSQRTSSm:
3790  case X86::VSQRTSSm_Int:
3791  case X86::VSQRTSSr:
3792    return true;
3793  }
3794}
3795
3796bool X86InstrInfo::
3797hasHighOperandLatency(const InstrItineraryData *ItinData,
3798                      const MachineRegisterInfo *MRI,
3799                      const MachineInstr *DefMI, unsigned DefIdx,
3800                      const MachineInstr *UseMI, unsigned UseIdx) const {
3801  return isHighLatencyDef(DefMI->getOpcode());
3802}
3803
3804namespace {
3805  /// CGBR - Create Global Base Reg pass. This initializes the PIC
3806  /// global base register for x86-32.
3807  struct CGBR : public MachineFunctionPass {
3808    static char ID;
3809    CGBR() : MachineFunctionPass(ID) {}
3810
3811    virtual bool runOnMachineFunction(MachineFunction &MF) {
3812      const X86TargetMachine *TM =
3813        static_cast<const X86TargetMachine *>(&MF.getTarget());
3814
3815      assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3816             "X86-64 PIC uses RIP relative addressing");
3817
3818      // Only emit a global base reg in PIC mode.
3819      if (TM->getRelocationModel() != Reloc::PIC_)
3820        return false;
3821
3822      X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3823      unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3824
3825      // If we didn't need a GlobalBaseReg, don't insert code.
3826      if (GlobalBaseReg == 0)
3827        return false;
3828
3829      // Insert the set of GlobalBaseReg into the first MBB of the function
3830      MachineBasicBlock &FirstMBB = MF.front();
3831      MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3832      DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3833      MachineRegisterInfo &RegInfo = MF.getRegInfo();
3834      const X86InstrInfo *TII = TM->getInstrInfo();
3835
3836      unsigned PC;
3837      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3838        PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3839      else
3840        PC = GlobalBaseReg;
3841
3842      // Operand of MovePCtoStack is completely ignored by asm printer. It's
3843      // only used in JIT code emission as displacement to pc.
3844      BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3845
3846      // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3847      // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3848      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3849        // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3850        BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3851          .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3852                                        X86II::MO_GOT_ABSOLUTE_ADDRESS);
3853      }
3854
3855      return true;
3856    }
3857
3858    virtual const char *getPassName() const {
3859      return "X86 PIC Global Base Reg Initialization";
3860    }
3861
3862    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3863      AU.setPreservesCFG();
3864      MachineFunctionPass::getAnalysisUsage(AU);
3865    }
3866  };
3867}
3868
3869char CGBR::ID = 0;
3870FunctionPass*
3871llvm::createGlobalBaseRegPass() { return new CGBR(); }
3872