X86InstrFragmentsSIMD.td revision 360784
1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides pattern fragments useful for SIMD instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// MMX specific DAG Nodes. 15//===----------------------------------------------------------------------===// 16 17// Low word of MMX to GPR. 18def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 19 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 20// GPR to low word of MMX. 21def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1, 22 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>; 23 24//===----------------------------------------------------------------------===// 25// MMX Pattern Fragments 26//===----------------------------------------------------------------------===// 27 28def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>; 29 30//===----------------------------------------------------------------------===// 31// SSE specific DAG Nodes. 32//===----------------------------------------------------------------------===// 33 34def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 36 SDTCisVT<3, i8>]>; 37 38def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; 39def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; 40def X86fmins : SDNode<"X86ISD::FMINS", SDTFPBinOp>; 41def X86fmaxs : SDNode<"X86ISD::FMAXS", SDTFPBinOp>; 42 43// Commutative and Associative FMIN and FMAX. 44def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 49def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, 50 [SDNPCommutative, SDNPAssociative]>; 51def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, 52 [SDNPCommutative, SDNPAssociative]>; 53def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, 54 [SDNPCommutative, SDNPAssociative]>; 55def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>; 56def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; 57def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; 58def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>; 59def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>; 60def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>; 61def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>; 62def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; 63def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; 64def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>; 65def X86pshufb : SDNode<"X86ISD::PSHUFB", 66 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>, 67 SDTCisSameAs<0,2>]>>; 68def X86psadbw : SDNode<"X86ISD::PSADBW", 69 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 70 SDTCVecEltisVT<1, i8>, 71 SDTCisSameSizeAs<0,1>, 72 SDTCisSameAs<1,2>]>, [SDNPCommutative]>; 73def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW", 74 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 75 SDTCVecEltisVT<1, i8>, 76 SDTCisSameSizeAs<0,1>, 77 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>; 78def X86andnp : SDNode<"X86ISD::ANDNP", 79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 80 SDTCisSameAs<0,2>]>>; 81def X86multishift : SDNode<"X86ISD::MULTISHIFT", 82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 83 SDTCisSameAs<1,2>]>>; 84def X86pextrb : SDNode<"X86ISD::PEXTRB", 85 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>, 86 SDTCisPtrTy<2>]>>; 87def X86pextrw : SDNode<"X86ISD::PEXTRW", 88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>, 89 SDTCisPtrTy<2>]>>; 90def X86pinsrb : SDNode<"X86ISD::PINSRB", 91 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 92 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 93def X86pinsrw : SDNode<"X86ISD::PINSRW", 94 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, 95 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; 96def X86insertps : SDNode<"X86ISD::INSERTPS", 97 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, 98 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>; 99def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", 100 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; 101 102def X86vzld : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, 103 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 104def X86vextractst : SDNode<"X86ISD::VEXTRACT_STORE", SDTStore, 105 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 106def X86VBroadcastld : SDNode<"X86ISD::VBROADCAST_LOAD", SDTLoad, 107 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 108 109def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 110 SDTCisInt<0>, SDTCisInt<1>, 111 SDTCisOpSmallerThanOp<0, 1>]>; 112def SDTVmtrunc : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 113 SDTCisInt<0>, SDTCisInt<1>, 114 SDTCisOpSmallerThanOp<0, 1>, 115 SDTCisSameAs<0, 2>, 116 SDTCVecEltisVT<3, i1>, 117 SDTCisSameNumEltsAs<1, 3>]>; 118 119def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>; 120def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>; 121def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>; 122def X86vmtrunc : SDNode<"X86ISD::VMTRUNC", SDTVmtrunc>; 123def X86vmtruncs : SDNode<"X86ISD::VMTRUNCS", SDTVmtrunc>; 124def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>; 125 126def X86vfpext : SDNode<"X86ISD::VFPEXT", 127 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 128 SDTCVecEltisVT<1, f32>, 129 SDTCisSameSizeAs<0, 1>]>>; 130 131def X86strict_vfpext : SDNode<"X86ISD::STRICT_VFPEXT", 132 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 133 SDTCVecEltisVT<1, f32>, 134 SDTCisSameSizeAs<0, 1>]>, 135 [SDNPHasChain]>; 136 137def X86any_vfpext : PatFrags<(ops node:$src), 138 [(X86strict_vfpext node:$src), 139 (X86vfpext node:$src)]>; 140 141def X86vfpround: SDNode<"X86ISD::VFPROUND", 142 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 143 SDTCVecEltisVT<1, f64>, 144 SDTCisOpSmallerThanOp<0, 1>]>>; 145 146def X86strict_vfpround: SDNode<"X86ISD::STRICT_VFPROUND", 147 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 148 SDTCVecEltisVT<1, f64>, 149 SDTCisOpSmallerThanOp<0, 1>]>, 150 [SDNPHasChain]>; 151 152def X86any_vfpround : PatFrags<(ops node:$src), 153 [(X86strict_vfpround node:$src), 154 (X86vfpround node:$src)]>; 155 156def X86frounds : SDNode<"X86ISD::VFPROUNDS", 157 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 158 SDTCisSameAs<0, 1>, 159 SDTCVecEltisVT<2, f64>, 160 SDTCisSameSizeAs<0, 2>]>>; 161 162def X86froundsRnd: SDNode<"X86ISD::VFPROUNDS_RND", 163 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 164 SDTCisSameAs<0, 1>, 165 SDTCVecEltisVT<2, f64>, 166 SDTCisSameSizeAs<0, 2>, 167 SDTCisVT<3, i32>]>>; 168 169def X86fpexts : SDNode<"X86ISD::VFPEXTS", 170 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 171 SDTCisSameAs<0, 1>, 172 SDTCVecEltisVT<2, f32>, 173 SDTCisSameSizeAs<0, 2>]>>; 174def X86fpextsSAE : SDNode<"X86ISD::VFPEXTS_SAE", 175 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>, 176 SDTCisSameAs<0, 1>, 177 SDTCVecEltisVT<2, f32>, 178 SDTCisSameSizeAs<0, 2>]>>; 179 180def X86vmfpround: SDNode<"X86ISD::VMFPROUND", 181 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 182 SDTCVecEltisVT<1, f64>, 183 SDTCisSameSizeAs<0, 1>, 184 SDTCisSameAs<0, 2>, 185 SDTCVecEltisVT<3, i1>, 186 SDTCisSameNumEltsAs<1, 3>]>>; 187 188def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 189 SDTCisVT<2, i8>, SDTCisInt<0>]>; 190 191def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>; 192def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>; 193def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>; 194def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>; 195 196def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>; 197def X86strict_cmpp : SDNode<"X86ISD::STRICT_CMPP", SDTX86VFCMP, [SDNPHasChain]>; 198def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3), 199 [(X86strict_cmpp node:$src1, node:$src2, node:$src3), 200 (X86cmpp node:$src1, node:$src2, node:$src3)]>; 201 202def X86CmpMaskCC : 203 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>, 204 SDTCisVec<1>, SDTCisSameAs<2, 1>, 205 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>; 206def X86CmpMaskCCScalar : 207 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>, 208 SDTCisVT<3, i8>]>; 209 210def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>; 211def X86strict_cmpm : SDNode<"X86ISD::STRICT_CMPM", X86CmpMaskCC, [SDNPHasChain]>; 212def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3), 213 [(X86strict_cmpm node:$src1, node:$src2, node:$src3), 214 (X86cmpm node:$src1, node:$src2, node:$src3)]>; 215def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>; 216def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>; 217def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>; 218 219def X86phminpos: SDNode<"X86ISD::PHMINPOS", 220 SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>; 221 222def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 223 SDTCisVec<2>, SDTCisInt<0>, 224 SDTCisInt<2>]>; 225 226def X86vshl : SDNode<"X86ISD::VSHL", X86vshiftuniform>; 227def X86vsrl : SDNode<"X86ISD::VSRL", X86vshiftuniform>; 228def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>; 229 230def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 231 SDTCisSameAs<0,2>, SDTCisInt<0>]>; 232 233def X86vshlv : SDNode<"X86ISD::VSHLV", X86vshiftvariable>; 234def X86vsrlv : SDNode<"X86ISD::VSRLV", X86vshiftvariable>; 235def X86vsrav : SDNode<"X86ISD::VSRAV", X86vshiftvariable>; 236 237def X86vshli : SDNode<"X86ISD::VSHLI", X86vshiftimm>; 238def X86vsrli : SDNode<"X86ISD::VSRLI", X86vshiftimm>; 239def X86vsrai : SDNode<"X86ISD::VSRAI", X86vshiftimm>; 240 241def X86kshiftl : SDNode<"X86ISD::KSHIFTL", 242 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 243 SDTCisSameAs<0, 1>, 244 SDTCisVT<2, i8>]>>; 245def X86kshiftr : SDNode<"X86ISD::KSHIFTR", 246 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 247 SDTCisSameAs<0, 1>, 248 SDTCisVT<2, i8>]>>; 249 250def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>; 251 252def X86vrotli : SDNode<"X86ISD::VROTLI", X86vshiftimm>; 253def X86vrotri : SDNode<"X86ISD::VROTRI", X86vshiftimm>; 254 255def X86vpshl : SDNode<"X86ISD::VPSHL", X86vshiftvariable>; 256def X86vpsha : SDNode<"X86ISD::VPSHA", X86vshiftvariable>; 257 258def X86vpcom : SDNode<"X86ISD::VPCOM", 259 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 260 SDTCisSameAs<0,2>, 261 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 262def X86vpcomu : SDNode<"X86ISD::VPCOMU", 263 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 264 SDTCisSameAs<0,2>, 265 SDTCisVT<3, i8>, SDTCisInt<0>]>>; 266def X86vpermil2 : SDNode<"X86ISD::VPERMIL2", 267 SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>, 268 SDTCisSameAs<0,2>, 269 SDTCisFP<0>, SDTCisInt<3>, 270 SDTCisSameNumEltsAs<0, 3>, 271 SDTCisSameSizeAs<0,3>, 272 SDTCisVT<4, i8>]>>; 273def X86vpperm : SDNode<"X86ISD::VPPERM", 274 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, 275 SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>; 276 277def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 278 SDTCisVec<1>, 279 SDTCisSameAs<2, 1>]>; 280 281def X86mulhrs : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>; 282def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>; 283def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; 284def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>; 285def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>; 286def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>; 287 288def X86movmsk : SDNode<"X86ISD::MOVMSK", 289 SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; 290 291def X86selects : SDNode<"X86ISD::SELECTS", 292 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, 293 SDTCisSameAs<0, 2>, 294 SDTCisSameAs<2, 3>]>>; 295 296def X86pmuludq : SDNode<"X86ISD::PMULUDQ", 297 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 298 SDTCisSameAs<0,1>, 299 SDTCisSameAs<1,2>]>, 300 [SDNPCommutative]>; 301def X86pmuldq : SDNode<"X86ISD::PMULDQ", 302 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, 303 SDTCisSameAs<0,1>, 304 SDTCisSameAs<1,2>]>, 305 [SDNPCommutative]>; 306 307def X86extrqi : SDNode<"X86ISD::EXTRQI", 308 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 309 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>; 310def X86insertqi : SDNode<"X86ISD::INSERTQI", 311 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, 312 SDTCisSameAs<1,2>, SDTCisVT<3, i8>, 313 SDTCisVT<4, i8>]>>; 314 315// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get 316// translated into one of the target nodes below during lowering. 317// Note: this is a work in progress... 318def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>; 319def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 320 SDTCisSameAs<0,2>]>; 321def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 322 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>; 323 324def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, 325 SDTCisFP<0>, SDTCisInt<2>, 326 SDTCisSameNumEltsAs<0,2>, 327 SDTCisSameSizeAs<0,2>]>; 328def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>, 329 SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>; 330def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 331 SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>; 332def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>, 333 SDTCisSameAs<0,1>, 334 SDTCisSameAs<0,2>, 335 SDTCisVT<3, i32>]>; 336def SDTFPTernaryOpImm: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0,1>, 337 SDTCisSameAs<0,2>, 338 SDTCisInt<3>, 339 SDTCisSameSizeAs<0, 3>, 340 SDTCisSameNumEltsAs<0, 3>, 341 SDTCisVT<4, i32>]>; 342def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, 343 SDTCisSameAs<0,1>, 344 SDTCisVT<2, i32>]>; 345 346def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>; 347def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>, 348 SDTCisInt<0>, SDTCisInt<1>]>; 349 350def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 351 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>; 352 353def SDTTernlog : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>, 354 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, 355 SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>; 356 357def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc. 358 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>; 359 360def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc. 361 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>; 362 363def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, 364 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, 365 SDTCisFP<0>, SDTCisVT<4, i32>]>; 366 367def X86PAlignr : SDNode<"X86ISD::PALIGNR", 368 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, 369 SDTCisSameAs<0,1>, 370 SDTCisSameAs<0,2>, 371 SDTCisVT<3, i8>]>>; 372def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; 373 374def X86VShld : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>; 375def X86VShrd : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>; 376def X86VShldv : SDNode<"X86ISD::VSHLDV", 377 SDTypeProfile<1, 3, [SDTCisVec<0>, 378 SDTCisSameAs<0,1>, 379 SDTCisSameAs<0,2>, 380 SDTCisSameAs<0,3>]>>; 381def X86VShrdv : SDNode<"X86ISD::VSHRDV", 382 SDTypeProfile<1, 3, [SDTCisVec<0>, 383 SDTCisSameAs<0,1>, 384 SDTCisSameAs<0,2>, 385 SDTCisSameAs<0,3>]>>; 386 387def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; 388 389def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; 390def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; 391def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; 392 393def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>; 394def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>; 395 396def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>; 397def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; 398def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; 399 400def X86Movsd : SDNode<"X86ISD::MOVSD", 401 SDTypeProfile<1, 2, [SDTCisVT<0, v2f64>, 402 SDTCisVT<1, v2f64>, 403 SDTCisVT<2, v2f64>]>>; 404def X86Movss : SDNode<"X86ISD::MOVSS", 405 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 406 SDTCisVT<1, v4f32>, 407 SDTCisVT<2, v4f32>]>>; 408 409def X86Movlhps : SDNode<"X86ISD::MOVLHPS", 410 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 411 SDTCisVT<1, v4f32>, 412 SDTCisVT<2, v4f32>]>>; 413def X86Movhlps : SDNode<"X86ISD::MOVHLPS", 414 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>, 415 SDTCisVT<1, v4f32>, 416 SDTCisVT<2, v4f32>]>>; 417 418def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 419 SDTCisVec<1>, SDTCisInt<1>, 420 SDTCisSameSizeAs<0,1>, 421 SDTCisSameAs<1,2>, 422 SDTCisOpSmallerThanOp<0, 1>]>; 423def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>; 424def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>; 425 426def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>; 427def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>; 428 429def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW", 430 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 431 SDTCVecEltisVT<1, i8>, 432 SDTCisSameSizeAs<0,1>, 433 SDTCisSameAs<1,2>]>>; 434def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD", 435 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>, 436 SDTCVecEltisVT<1, i16>, 437 SDTCisSameSizeAs<0,1>, 438 SDTCisSameAs<1,2>]>, 439 [SDNPCommutative]>; 440 441def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>; 442def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>; 443def X86VPermv : SDNode<"X86ISD::VPERMV", 444 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>, 445 SDTCisSameNumEltsAs<0,1>, 446 SDTCisSameSizeAs<0,1>, 447 SDTCisSameAs<0,2>]>>; 448def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>; 449def X86VPermt2 : SDNode<"X86ISD::VPERMV3", 450 SDTypeProfile<1, 3, [SDTCisVec<0>, 451 SDTCisSameAs<0,1>, SDTCisInt<2>, 452 SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>, 453 SDTCisSameSizeAs<0,2>, 454 SDTCisSameAs<0,3>]>, []>; 455 456def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>; 457 458def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>; 459 460def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImm>; 461def X86VFixupimmSAE : SDNode<"X86ISD::VFIXUPIMM_SAE", SDTFPTernaryOpImm>; 462def X86VFixupimms : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImm>; 463def X86VFixupimmSAEs : SDNode<"X86ISD::VFIXUPIMMS_SAE", SDTFPTernaryOpImm>; 464def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImm>; 465def X86VRangeSAE : SDNode<"X86ISD::VRANGE_SAE", SDTFPBinOpImm>; 466def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImm>; 467def X86VReduceSAE : SDNode<"X86ISD::VREDUCE_SAE", SDTFPUnaryOpImm>; 468def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImm>; 469def X86strict_VRndScale : SDNode<"X86ISD::STRICT_VRNDSCALE", SDTFPUnaryOpImm, 470 [SDNPHasChain]>; 471def X86any_VRndScale : PatFrags<(ops node:$src1, node:$src2), 472 [(X86strict_VRndScale node:$src1, node:$src2), 473 (X86VRndScale node:$src1, node:$src2)]>; 474 475def X86VRndScaleSAE: SDNode<"X86ISD::VRNDSCALE_SAE", SDTFPUnaryOpImm>; 476def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImm>; 477def X86VGetMantSAE : SDNode<"X86ISD::VGETMANT_SAE", SDTFPUnaryOpImm>; 478def X86Vfpclass : SDNode<"X86ISD::VFPCLASS", 479 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>, 480 SDTCisFP<1>, 481 SDTCisSameNumEltsAs<0,1>, 482 SDTCisVT<2, i32>]>, []>; 483def X86Vfpclasss : SDNode<"X86ISD::VFPCLASSS", 484 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>, 485 SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>; 486 487def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST", 488 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 489 SDTCisSubVecOfVec<1, 0>]>, []>; 490 491def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>; 492def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>; 493 494def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>; 495def X86Blendv : SDNode<"X86ISD::BLENDV", 496 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>, 497 SDTCisSameAs<0, 2>, 498 SDTCisSameAs<2, 3>, 499 SDTCisSameNumEltsAs<0, 1>, 500 SDTCisSameSizeAs<0, 1>]>>; 501 502def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>; 503 504def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>; 505def X86fadds : SDNode<"X86ISD::FADDS", SDTFPBinOp>; 506def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>; 507def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>; 508def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>; 509def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>; 510def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>; 511def X86fmuls : SDNode<"X86ISD::FMULS", SDTFPBinOp>; 512def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>; 513def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>; 514def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>; 515def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>; 516def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>; 517def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>; 518def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>; 519def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>; 520def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOp>; 521def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND", SDTFPBinOpRound>; 522def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOp>; 523def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND", SDTFPBinOpRound>; 524def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>; 525def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>; 526def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>; 527def X86fgetexp : SDNode<"X86ISD::FGETEXP", SDTFPUnaryOp>; 528def X86fgetexpSAE : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>; 529def X86fgetexps : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>; 530def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>; 531 532def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; 533def X86strict_Fmadd : SDNode<"ISD::STRICT_FMA", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; 534def X86any_Fmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3), 535 [(X86strict_Fmadd node:$src1, node:$src2, node:$src3), 536 (X86Fmadd node:$src1, node:$src2, node:$src3)]>; 537def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; 538def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 539def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>; 540def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFPTernaryOp, [SDNPCommutative]>; 541def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFPTernaryOp, [SDNPCommutative]>; 542 543def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound, [SDNPCommutative]>; 544def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound, [SDNPCommutative]>; 545def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 546def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutative]>; 547def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>; 548def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>; 549 550def X86vp2intersect : SDNode<"X86ISD::VP2INTERSECT", 551 SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 552 SDTCisVec<1>, SDTCisSameAs<1, 2>]>>; 553 554def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>, 555 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 556def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>; 557def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>; 558 559def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>; 560def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>; 561 562// VNNI 563def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, 564 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>; 565def X86Vpdpbusd : SDNode<"X86ISD::VPDPBUSD", SDTVnni>; 566def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>; 567def X86Vpdpwssd : SDNode<"X86ISD::VPDPWSSD", SDTVnni>; 568def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>; 569 570def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOp>; 571def X86rsqrt28SAE: SDNode<"X86ISD::RSQRT28_SAE", SDTFPUnaryOp>; 572def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOp>; 573def X86rcp28SAE : SDNode<"X86ISD::RCP28_SAE", SDTFPUnaryOp>; 574def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOp>; 575def X86exp2SAE : SDNode<"X86ISD::EXP2_SAE", SDTFPUnaryOp>; 576 577def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>; 578def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>; 579def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOp>; 580def X86rsqrt28SAEs : SDNode<"X86ISD::RSQRT28S_SAE", SDTFPBinOp>; 581def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOp>; 582def X86rcp28SAEs : SDNode<"X86ISD::RCP28S_SAE", SDTFPBinOp>; 583def X86Ranges : SDNode<"X86ISD::VRANGES", SDTFPBinOpImm>; 584def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>; 585def X86Reduces : SDNode<"X86ISD::VREDUCES", SDTFPBinOpImm>; 586def X86GetMants : SDNode<"X86ISD::VGETMANTS", SDTFPBinOpImm>; 587def X86RangesSAE : SDNode<"X86ISD::VRANGES_SAE", SDTFPBinOpImm>; 588def X86RndScalesSAE : SDNode<"X86ISD::VRNDSCALES_SAE", SDTFPBinOpImm>; 589def X86ReducesSAE : SDNode<"X86ISD::VREDUCES_SAE", SDTFPBinOpImm>; 590def X86GetMantsSAE : SDNode<"X86ISD::VGETMANTS_SAE", SDTFPBinOpImm>; 591 592def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3, 593 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 594 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 595 SDTCisSameNumEltsAs<0, 3>]>, []>; 596def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3, 597 [SDTCisSameAs<0, 1>, SDTCisVec<1>, 598 SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 599 SDTCisSameNumEltsAs<0, 3>]>, []>; 600 601// vpshufbitqmb 602def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB", 603 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 604 SDTCisSameAs<1,2>, 605 SDTCVecEltisVT<0,i1>, 606 SDTCisSameNumEltsAs<0,1>]>>; 607 608def SDTintToFP: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 609 SDTCisSameAs<0,1>, SDTCisInt<2>]>; 610def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 611 SDTCisSameAs<0,1>, SDTCisInt<2>, 612 SDTCisVT<3, i32>]>; 613 614def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 615 SDTCisInt<0>, SDTCisFP<1>]>; 616def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 617 SDTCisInt<0>, SDTCisFP<1>, 618 SDTCisVT<2, i32>]>; 619def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>, 620 SDTCisVec<1>]>; 621def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>, 622 SDTCisVec<1>, SDTCisVT<2, i32>]>; 623 624def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>, 625 SDTCisFP<0>, SDTCisInt<1>]>; 626def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 627 SDTCisFP<0>, SDTCisInt<1>, 628 SDTCisVT<2, i32>]>; 629 630// Scalar 631def X86SintToFp : SDNode<"X86ISD::SCALAR_SINT_TO_FP", SDTintToFP>; 632def X86SintToFpRnd : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND", SDTintToFPRound>; 633def X86UintToFp : SDNode<"X86ISD::SCALAR_UINT_TO_FP", SDTintToFP>; 634def X86UintToFpRnd : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND", SDTintToFPRound>; 635 636def X86cvtts2Int : SDNode<"X86ISD::CVTTS2SI", SDTSFloatToInt>; 637def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI", SDTSFloatToInt>; 638def X86cvtts2IntSAE : SDNode<"X86ISD::CVTTS2SI_SAE", SDTSFloatToInt>; 639def X86cvtts2UIntSAE : SDNode<"X86ISD::CVTTS2UI_SAE", SDTSFloatToInt>; 640 641def X86cvts2si : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>; 642def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>; 643def X86cvts2siRnd : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>; 644def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>; 645 646// Vector with rounding mode 647 648// cvtt fp-to-int staff 649def X86cvttp2siSAE : SDNode<"X86ISD::CVTTP2SI_SAE", SDTFloatToInt>; 650def X86cvttp2uiSAE : SDNode<"X86ISD::CVTTP2UI_SAE", SDTFloatToInt>; 651 652def X86VSintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTVintToFPRound>; 653def X86VUintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTVintToFPRound>; 654 655// cvt fp-to-int staff 656def X86cvtp2IntRnd : SDNode<"X86ISD::CVTP2SI_RND", SDTFloatToIntRnd>; 657def X86cvtp2UIntRnd : SDNode<"X86ISD::CVTP2UI_RND", SDTFloatToIntRnd>; 658 659// Vector without rounding mode 660 661// cvtt fp-to-int staff 662def X86cvttp2si : SDNode<"X86ISD::CVTTP2SI", SDTFloatToInt>; 663def X86cvttp2ui : SDNode<"X86ISD::CVTTP2UI", SDTFloatToInt>; 664def X86strict_cvttp2si : SDNode<"X86ISD::STRICT_CVTTP2SI", SDTFloatToInt, [SDNPHasChain]>; 665def X86strict_cvttp2ui : SDNode<"X86ISD::STRICT_CVTTP2UI", SDTFloatToInt, [SDNPHasChain]>; 666def X86any_cvttp2si : PatFrags<(ops node:$src), 667 [(X86strict_cvttp2si node:$src), 668 (X86cvttp2si node:$src)]>; 669def X86any_cvttp2ui : PatFrags<(ops node:$src), 670 [(X86strict_cvttp2ui node:$src), 671 (X86cvttp2ui node:$src)]>; 672 673def X86VSintToFP : SDNode<"X86ISD::CVTSI2P", SDTVintToFP>; 674def X86VUintToFP : SDNode<"X86ISD::CVTUI2P", SDTVintToFP>; 675def X86strict_VSintToFP : SDNode<"X86ISD::STRICT_CVTSI2P", SDTVintToFP, [SDNPHasChain]>; 676def X86strict_VUintToFP : SDNode<"X86ISD::STRICT_CVTUI2P", SDTVintToFP, [SDNPHasChain]>; 677def X86any_VSintToFP : PatFrags<(ops node:$src), 678 [(X86strict_VSintToFP node:$src), 679 (X86VSintToFP node:$src)]>; 680def X86any_VUintToFP : PatFrags<(ops node:$src), 681 [(X86strict_VUintToFP node:$src), 682 (X86VUintToFP node:$src)]>; 683 684 685// cvt int-to-fp staff 686def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>; 687def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>; 688 689 690// Masked versions of above 691def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 692 SDTCisFP<0>, SDTCisInt<1>, 693 SDTCisSameSizeAs<0, 1>, 694 SDTCisSameAs<0, 2>, 695 SDTCVecEltisVT<3, i1>, 696 SDTCisSameNumEltsAs<1, 3>]>; 697def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 698 SDTCisInt<0>, SDTCisFP<1>, 699 SDTCisSameSizeAs<0, 1>, 700 SDTCisSameAs<0, 2>, 701 SDTCVecEltisVT<3, i1>, 702 SDTCisSameNumEltsAs<1, 3>]>; 703 704def X86VMSintToFP : SDNode<"X86ISD::MCVTSI2P", SDTMVintToFP>; 705def X86VMUintToFP : SDNode<"X86ISD::MCVTUI2P", SDTMVintToFP>; 706 707def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>; 708def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>; 709def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>; 710def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>; 711 712 713def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", 714 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 715 SDTCVecEltisVT<1, i16>]> >; 716 717def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", 718 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, 719 SDTCVecEltisVT<1, i16>]> >; 720 721def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", 722 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, 723 SDTCVecEltisVT<1, f32>, 724 SDTCisVT<2, i32>]> >; 725def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH", 726 SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>, 727 SDTCVecEltisVT<1, f32>, 728 SDTCisVT<2, i32>, 729 SDTCisSameAs<0, 3>, 730 SDTCVecEltisVT<4, i1>, 731 SDTCisSameNumEltsAs<1, 4>]> >; 732def X86vfpextSAE : SDNode<"X86ISD::VFPEXT_SAE", 733 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>, 734 SDTCVecEltisVT<1, f32>, 735 SDTCisOpSmallerThanOp<1, 0>]>>; 736def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND", 737 SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>, 738 SDTCVecEltisVT<1, f64>, 739 SDTCisOpSmallerThanOp<0, 1>, 740 SDTCisVT<2, i32>]>>; 741 742// cvt fp to bfloat16 743def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16", 744 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 745 SDTCisSameAs<1,2>]>>; 746def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16", 747 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>, 748 SDTCVecEltisVT<1, f32>, 749 SDTCisSameAs<0, 2>, 750 SDTCVecEltisVT<3, i1>, 751 SDTCisSameNumEltsAs<1, 3>]>>; 752def X86cvtneps2bf16 : SDNode<"X86ISD::CVTNEPS2BF16", 753 SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>, 754 SDTCVecEltisVT<1, f32>]>>; 755def X86dpbf16ps : SDNode<"X86ISD::DPBF16PS", 756 SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>, 757 SDTCisSameAs<0,1>, 758 SDTCVecEltisVT<2, i32>, 759 SDTCisSameAs<2,3>]>>; 760 761// galois field arithmetic 762def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>; 763def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>; 764def X86GF2P8mulb : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>; 765 766def SDTX86MaskedStore: SDTypeProfile<0, 3, [ // masked store 767 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2> 768]>; 769 770//===----------------------------------------------------------------------===// 771// SSE Complex Patterns 772//===----------------------------------------------------------------------===// 773 774// These are 'extloads' from a scalar to the low element of a vector, zeroing 775// the top elements. These are used for the SSE 'ss' and 'sd' instruction 776// forms. 777def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [], 778 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 779 SDNPWantRoot, SDNPWantParent]>; 780def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [], 781 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, 782 SDNPWantRoot, SDNPWantParent]>; 783 784def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 785def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 786 787//===----------------------------------------------------------------------===// 788// SSE pattern fragments 789//===----------------------------------------------------------------------===// 790 791// 128-bit load pattern fragments 792def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; 793def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; 794def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; 795def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; 796def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>; 797def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>; 798 799// 256-bit load pattern fragments 800def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; 801def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; 802def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; 803def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; 804def loadv16i16 : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>; 805def loadv32i8 : PatFrag<(ops node:$ptr), (v32i8 (load node:$ptr))>; 806 807// 512-bit load pattern fragments 808def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>; 809def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>; 810def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>; 811def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>; 812def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>; 813def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>; 814 815// 128-/256-/512-bit extload pattern fragments 816def extloadv2f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 817def extloadv4f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 818def extloadv8f32 : PatFrag<(ops node:$ptr), (extloadvf32 node:$ptr)>; 819 820// Like 'store', but always requires vector size alignment. 821def alignedstore : PatFrag<(ops node:$val, node:$ptr), 822 (store node:$val, node:$ptr), [{ 823 auto *St = cast<StoreSDNode>(N); 824 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 825}]>; 826 827// Like 'load', but always requires vector size alignment. 828def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 829 auto *Ld = cast<LoadSDNode>(N); 830 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 831}]>; 832 833// 128-bit aligned load pattern fragments 834// NOTE: all 128-bit integer vector loads are promoted to v2i64 835def alignedloadv4f32 : PatFrag<(ops node:$ptr), 836 (v4f32 (alignedload node:$ptr))>; 837def alignedloadv2f64 : PatFrag<(ops node:$ptr), 838 (v2f64 (alignedload node:$ptr))>; 839def alignedloadv2i64 : PatFrag<(ops node:$ptr), 840 (v2i64 (alignedload node:$ptr))>; 841def alignedloadv4i32 : PatFrag<(ops node:$ptr), 842 (v4i32 (alignedload node:$ptr))>; 843def alignedloadv8i16 : PatFrag<(ops node:$ptr), 844 (v8i16 (alignedload node:$ptr))>; 845def alignedloadv16i8 : PatFrag<(ops node:$ptr), 846 (v16i8 (alignedload node:$ptr))>; 847 848// 256-bit aligned load pattern fragments 849// NOTE: all 256-bit integer vector loads are promoted to v4i64 850def alignedloadv8f32 : PatFrag<(ops node:$ptr), 851 (v8f32 (alignedload node:$ptr))>; 852def alignedloadv4f64 : PatFrag<(ops node:$ptr), 853 (v4f64 (alignedload node:$ptr))>; 854def alignedloadv4i64 : PatFrag<(ops node:$ptr), 855 (v4i64 (alignedload node:$ptr))>; 856def alignedloadv8i32 : PatFrag<(ops node:$ptr), 857 (v8i32 (alignedload node:$ptr))>; 858def alignedloadv16i16 : PatFrag<(ops node:$ptr), 859 (v16i16 (alignedload node:$ptr))>; 860def alignedloadv32i8 : PatFrag<(ops node:$ptr), 861 (v32i8 (alignedload node:$ptr))>; 862 863// 512-bit aligned load pattern fragments 864def alignedloadv16f32 : PatFrag<(ops node:$ptr), 865 (v16f32 (alignedload node:$ptr))>; 866def alignedloadv8f64 : PatFrag<(ops node:$ptr), 867 (v8f64 (alignedload node:$ptr))>; 868def alignedloadv8i64 : PatFrag<(ops node:$ptr), 869 (v8i64 (alignedload node:$ptr))>; 870def alignedloadv16i32 : PatFrag<(ops node:$ptr), 871 (v16i32 (alignedload node:$ptr))>; 872def alignedloadv32i16 : PatFrag<(ops node:$ptr), 873 (v32i16 (alignedload node:$ptr))>; 874def alignedloadv64i8 : PatFrag<(ops node:$ptr), 875 (v64i8 (alignedload node:$ptr))>; 876 877// Like 'load', but uses special alignment checks suitable for use in 878// memory operands in most SSE instructions, which are required to 879// be naturally aligned on some targets but not on others. If the subtarget 880// allows unaligned accesses, match any load, though this may require 881// setting a feature bit in the processor (on startup, for example). 882// Opteron 10h and later implement such a feature. 883def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 884 auto *Ld = cast<LoadSDNode>(N); 885 return Subtarget->hasSSEUnalignedMem() || 886 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 887}]>; 888 889// 128-bit memop pattern fragments 890// NOTE: all 128-bit integer vector loads are promoted to v2i64 891def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; 892def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; 893def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; 894def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; 895def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>; 896def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; 897 898def X86masked_gather : SDNode<"X86ISD::MGATHER", 899 SDTypeProfile<2, 3, [SDTCisVec<0>, 900 SDTCisVec<1>, SDTCisInt<1>, 901 SDTCisSameAs<0, 2>, 902 SDTCisSameAs<1, 3>, 903 SDTCisPtrTy<4>]>, 904 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 905 906def X86masked_scatter : SDNode<"X86ISD::MSCATTER", 907 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>, 908 SDTCisSameAs<0, 2>, 909 SDTCVecEltisVT<0, i1>, 910 SDTCisPtrTy<3>]>, 911 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 912 913def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 914 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 915 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 916 return Mgt->getIndex().getValueType() == MVT::v4i32; 917}]>; 918 919def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 920 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 921 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 922 return Mgt->getIndex().getValueType() == MVT::v8i32; 923}]>; 924 925def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 926 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 927 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 928 return Mgt->getIndex().getValueType() == MVT::v2i64; 929}]>; 930def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 931 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 932 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 933 return Mgt->getIndex().getValueType() == MVT::v4i64; 934}]>; 935def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 936 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 937 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 938 return Mgt->getIndex().getValueType() == MVT::v8i64; 939}]>; 940def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 941 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{ 942 X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N); 943 return Mgt->getIndex().getValueType() == MVT::v16i32; 944}]>; 945 946def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 947 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 948 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 949 return Sc->getIndex().getValueType() == MVT::v2i64; 950}]>; 951 952def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 953 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 954 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 955 return Sc->getIndex().getValueType() == MVT::v4i32; 956}]>; 957 958def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 959 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 960 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 961 return Sc->getIndex().getValueType() == MVT::v4i64; 962}]>; 963 964def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 965 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 966 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 967 return Sc->getIndex().getValueType() == MVT::v8i32; 968}]>; 969 970def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 971 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 972 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 973 return Sc->getIndex().getValueType() == MVT::v8i64; 974}]>; 975def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 976 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{ 977 X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N); 978 return Sc->getIndex().getValueType() == MVT::v16i32; 979}]>; 980 981// 128-bit bitconvert pattern fragments 982def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; 983def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; 984def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; 985def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; 986def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; 987def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; 988 989// 256-bit bitconvert pattern fragments 990def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>; 991def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>; 992def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>; 993def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>; 994def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>; 995def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>; 996 997// 512-bit bitconvert pattern fragments 998def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>; 999def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>; 1000def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>; 1001def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>; 1002def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>; 1003def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>; 1004 1005def X86vzload32 : PatFrag<(ops node:$src), 1006 (X86vzld node:$src), [{ 1007 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 1008}]>; 1009 1010def X86vzload64 : PatFrag<(ops node:$src), 1011 (X86vzld node:$src), [{ 1012 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 1013}]>; 1014 1015def X86vextractstore64 : PatFrag<(ops node:$val, node:$ptr), 1016 (X86vextractst node:$val, node:$ptr), [{ 1017 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 1018}]>; 1019 1020def X86VBroadcastld8 : PatFrag<(ops node:$src), 1021 (X86VBroadcastld node:$src), [{ 1022 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 1; 1023}]>; 1024 1025def X86VBroadcastld16 : PatFrag<(ops node:$src), 1026 (X86VBroadcastld node:$src), [{ 1027 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 2; 1028}]>; 1029 1030def X86VBroadcastld32 : PatFrag<(ops node:$src), 1031 (X86VBroadcastld node:$src), [{ 1032 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 4; 1033}]>; 1034 1035def X86VBroadcastld64 : PatFrag<(ops node:$src), 1036 (X86VBroadcastld node:$src), [{ 1037 return cast<MemIntrinsicSDNode>(N)->getMemoryVT().getStoreSize() == 8; 1038}]>; 1039 1040 1041def fp32imm0 : PatLeaf<(f32 fpimm), [{ 1042 return N->isExactlyValue(+0.0); 1043}]>; 1044 1045def fp64imm0 : PatLeaf<(f64 fpimm), [{ 1046 return N->isExactlyValue(+0.0); 1047}]>; 1048 1049def fp128imm0 : PatLeaf<(f128 fpimm), [{ 1050 return N->isExactlyValue(+0.0); 1051}]>; 1052 1053// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index 1054// to VEXTRACTF128/VEXTRACTI128 imm. 1055def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{ 1056 return getExtractVEXTRACTImmediate(N, 128, SDLoc(N)); 1057}]>; 1058 1059// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to 1060// VINSERTF128/VINSERTI128 imm. 1061def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{ 1062 return getInsertVINSERTImmediate(N, 128, SDLoc(N)); 1063}]>; 1064 1065// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index 1066// to VEXTRACTF64x4 imm. 1067def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{ 1068 return getExtractVEXTRACTImmediate(N, 256, SDLoc(N)); 1069}]>; 1070 1071// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to 1072// VINSERTF64x4 imm. 1073def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{ 1074 return getInsertVINSERTImmediate(N, 256, SDLoc(N)); 1075}]>; 1076 1077def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index), 1078 (extract_subvector node:$bigvec, 1079 node:$index), [{ 1080 // Index 0 can be handled via extract_subreg. 1081 return !isNullConstant(N->getOperand(1)); 1082}], EXTRACT_get_vextract128_imm>; 1083 1084def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1085 node:$index), 1086 (insert_subvector node:$bigvec, node:$smallvec, 1087 node:$index), [{}], 1088 INSERT_get_vinsert128_imm>; 1089 1090def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index), 1091 (extract_subvector node:$bigvec, 1092 node:$index), [{ 1093 // Index 0 can be handled via extract_subreg. 1094 return !isNullConstant(N->getOperand(1)); 1095}], EXTRACT_get_vextract256_imm>; 1096 1097def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec, 1098 node:$index), 1099 (insert_subvector node:$bigvec, node:$smallvec, 1100 node:$index), [{}], 1101 INSERT_get_vinsert256_imm>; 1102 1103def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1104 (masked_ld node:$src1, undef, node:$src2, node:$src3), [{ 1105 return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() && 1106 cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD && 1107 cast<MaskedLoadSDNode>(N)->isUnindexed(); 1108}]>; 1109 1110def masked_load_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1111 (masked_load node:$src1, node:$src2, node:$src3), [{ 1112 // Use the node type to determine the size the alignment needs to match. 1113 // We can't use memory VT because type widening changes the node VT, but 1114 // not the memory VT. 1115 auto *Ld = cast<MaskedLoadSDNode>(N); 1116 return Ld->getAlignment() >= Ld->getValueType(0).getStoreSize(); 1117}]>; 1118 1119def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1120 (masked_ld node:$src1, undef, node:$src2, node:$src3), [{ 1121 return cast<MaskedLoadSDNode>(N)->isExpandingLoad() && 1122 cast<MaskedLoadSDNode>(N)->isUnindexed(); 1123}]>; 1124 1125// Masked store fragments. 1126// X86mstore can't be implemented in core DAG files because some targets 1127// do not support vector types (llvm-tblgen will fail). 1128def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1129 (masked_st node:$src1, node:$src2, undef, node:$src3), [{ 1130 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 1131 !cast<MaskedStoreSDNode>(N)->isCompressingStore() && 1132 cast<MaskedStoreSDNode>(N)->isUnindexed(); 1133}]>; 1134 1135def masked_store_aligned : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1136 (masked_store node:$src1, node:$src2, node:$src3), [{ 1137 // Use the node type to determine the size the alignment needs to match. 1138 // We can't use memory VT because type widening changes the node VT, but 1139 // not the memory VT. 1140 auto *St = cast<MaskedStoreSDNode>(N); 1141 return St->getAlignment() >= St->getOperand(1).getValueType().getStoreSize(); 1142}]>; 1143 1144def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1145 (masked_st node:$src1, node:$src2, undef, node:$src3), [{ 1146 return cast<MaskedStoreSDNode>(N)->isCompressingStore() && 1147 cast<MaskedStoreSDNode>(N)->isUnindexed(); 1148}]>; 1149 1150// masked truncstore fragments 1151// X86mtruncstore can't be implemented in core DAG files because some targets 1152// doesn't support vector type ( llvm-tblgen will fail) 1153def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1154 (masked_st node:$src1, node:$src2, undef, node:$src3), [{ 1155 return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && 1156 cast<MaskedStoreSDNode>(N)->isUnindexed(); 1157}]>; 1158def masked_truncstorevi8 : 1159 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1160 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1161 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1162}]>; 1163def masked_truncstorevi16 : 1164 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1165 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1166 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1167}]>; 1168def masked_truncstorevi32 : 1169 PatFrag<(ops node:$src1, node:$src2, node:$src3), 1170 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{ 1171 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1172}]>; 1173 1174def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES", SDTStore, 1175 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1176 1177def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS", SDTStore, 1178 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1179 1180def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES", SDTX86MaskedStore, 1181 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1182 1183def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS", SDTX86MaskedStore, 1184 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 1185 1186def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr), 1187 (X86TruncSStore node:$val, node:$ptr), [{ 1188 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1189}]>; 1190 1191def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr), 1192 (X86TruncUSStore node:$val, node:$ptr), [{ 1193 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1194}]>; 1195 1196def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr), 1197 (X86TruncSStore node:$val, node:$ptr), [{ 1198 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1199}]>; 1200 1201def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr), 1202 (X86TruncUSStore node:$val, node:$ptr), [{ 1203 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1204}]>; 1205 1206def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr), 1207 (X86TruncSStore node:$val, node:$ptr), [{ 1208 return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1209}]>; 1210 1211def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr), 1212 (X86TruncUSStore node:$val, node:$ptr), [{ 1213 return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1214}]>; 1215 1216def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1217 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1218 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1219}]>; 1220 1221def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1222 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1223 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 1224}]>; 1225 1226def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1227 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1228 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1229}]>; 1230 1231def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1232 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1233 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 1234}]>; 1235 1236def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1237 (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{ 1238 return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1239}]>; 1240 1241def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3), 1242 (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{ 1243 return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 1244}]>; 1245