1234353Sdim//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2234353Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed// 9193323Sed// This file describes the X86 x87 FPU instruction set, defining the 10193323Sed// instructions, and properties of the instructions which are needed for code 11193323Sed// generation, machine code emission, and analysis. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed//===----------------------------------------------------------------------===// 16193323Sed// FPStack specific DAG Nodes. 17193323Sed//===----------------------------------------------------------------------===// 18193323Sed 19353358Sdimdef SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 20353358Sdim SDTCisPtrTy<1>]>; 21353358Sdimdef SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 22353358Sdim SDTCisPtrTy<1>]>; 23353358Sdimdef SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 24353358Sdimdef SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 25239462Sdimdef SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 26193323Sed 27193323Seddef SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 28193323Sed 29193323Seddef X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 30218893Sdim [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 31193323Seddef X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 32360784Sdim [SDNPHasChain, SDNPOptInGlue, SDNPMayStore, 33218893Sdim SDNPMemOperand]>; 34193323Seddef X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 35218893Sdim [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 36193323Seddef X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 37218893Sdim [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 38218893Sdim SDNPMemOperand]>; 39353358Sdimdef X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 40360784Sdim [SDNPHasChain, SDNPOptInGlue, SDNPMayStore, 41353358Sdim SDNPMemOperand]>; 42239462Sdimdef X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 43353358Sdimdef X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 44353358Sdim [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 45193323Seddef X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 46218893Sdim [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 47218893Sdim SDNPMemOperand]>; 48193323Sed 49353358Sdimdef X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 50353358Sdim (X86fst node:$val, node:$ptr), [{ 51353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 52353358Sdim}]>; 53353358Sdimdef X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 54353358Sdim (X86fst node:$val, node:$ptr), [{ 55353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 56353358Sdim}]>; 57353358Sdimdef X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 58353358Sdim (X86fst node:$val, node:$ptr), [{ 59353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 60353358Sdim}]>; 61353358Sdim 62353358Sdimdef X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 63353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 64353358Sdim}]>; 65353358Sdimdef X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 66353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 67353358Sdim}]>; 68353358Sdimdef X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 69353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 70353358Sdim}]>; 71353358Sdim 72353358Sdimdef X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 73353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 74353358Sdim}]>; 75353358Sdimdef X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 76353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 77353358Sdim}]>; 78353358Sdimdef X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 79353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 80353358Sdim}]>; 81353358Sdim 82353358Sdimdef X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{ 83353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 84353358Sdim}]>; 85353358Sdim 86353358Sdimdef X86fist64 : PatFrag<(ops node:$val, node:$ptr), 87353358Sdim (X86fist node:$val, node:$ptr), [{ 88353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 89353358Sdim}]>; 90353358Sdim 91353358Sdimdef X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 92353358Sdim (X86fp_to_mem node:$val, node:$ptr), [{ 93353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 94353358Sdim}]>; 95353358Sdimdef X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 96353358Sdim (X86fp_to_mem node:$val, node:$ptr), [{ 97353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 98353358Sdim}]>; 99353358Sdimdef X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 100353358Sdim (X86fp_to_mem node:$val, node:$ptr), [{ 101353358Sdim return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 102353358Sdim}]>; 103353358Sdim 104193323Sed//===----------------------------------------------------------------------===// 105193323Sed// FPStack pattern fragments 106193323Sed//===----------------------------------------------------------------------===// 107193323Sed 108327952Sdimdef fpimm0 : FPImmLeaf<fAny, [{ 109327952Sdim return Imm.isExactlyValue(+0.0); 110193323Sed}]>; 111193323Sed 112327952Sdimdef fpimmneg0 : FPImmLeaf<fAny, [{ 113327952Sdim return Imm.isExactlyValue(-0.0); 114193323Sed}]>; 115193323Sed 116327952Sdimdef fpimm1 : FPImmLeaf<fAny, [{ 117327952Sdim return Imm.isExactlyValue(+1.0); 118193323Sed}]>; 119193323Sed 120327952Sdimdef fpimmneg1 : FPImmLeaf<fAny, [{ 121327952Sdim return Imm.isExactlyValue(-1.0); 122193323Sed}]>; 123193323Sed 124327952Sdim// Some 'special' instructions - expanded after instruction selection. 125353358Sdim// Clobbers EFLAGS due to OR instruction used internally. 126353358Sdim// FIXME: Can we model this in SelectionDAG? 127353358Sdimlet usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in { 128218893Sdim def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 129193323Sed [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 130218893Sdim def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 131193323Sed [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 132218893Sdim def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 133193323Sed [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 134218893Sdim def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 135193323Sed [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 136218893Sdim def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 137193323Sed [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 138218893Sdim def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 139193323Sed [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 140218893Sdim def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 141193323Sed [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 142218893Sdim def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 143193323Sed [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 144218893Sdim def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 145193323Sed [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 146193323Sed} 147193323Sed 148193323Sed// All FP Stack operations are represented with four instructions here. The 149193323Sed// first three instructions, generated by the instruction selector, use "RFP32" 150193323Sed// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 151280031Sdim// 64-bit or 80-bit floating point values. These sizes apply to the values, 152193323Sed// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 153193323Sed// copied to each other without losing information. These instructions are all 154193323Sed// pseudo instructions and use the "_Fp" suffix. 155193323Sed// In some cases there are additional variants with a mixture of different 156193323Sed// register sizes. 157193323Sed// The second instruction is defined with FPI, which is the actual instruction 158193323Sed// emitted by the assembler. These use "RST" registers, although frequently 159193323Sed// the actual register(s) used are implicit. These are always 80 bits. 160280031Sdim// The FP stackifier pass converts one to the other after register allocation 161193323Sed// occurs. 162193323Sed// 163193323Sed// Note that the FpI instruction should have instruction selection info (e.g. 164193323Sed// a pattern) and the FPI instruction should have emission info (e.g. opcode 165193323Sed// encoding and asm printing info). 166193323Sed 167212904Sdim// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 168193323Sed// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 169193323Sed// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 170193323Sed// f80 instructions cannot use SSE and use neither of these. 171341825Sdimclass FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 172341825Sdim FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 173341825Sdimclass FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 174341825Sdim FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 175193323Sed 176193323Sed// Factoring for arithmetic. 177193323Sedmulticlass FPBinary_rr<SDNode OpNode> { 178193323Sed// Register op register -> register 179193323Sed// These are separated out because they have no reversed form. 180193323Seddef _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 181193323Sed [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 182193323Seddef _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 183193323Sed [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 184193323Seddef _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 185193323Sed [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 186193323Sed} 187193323Sed// The FopST0 series are not included here because of the irregularities 188193323Sed// in where the 'r' goes in assembly output. 189193323Sed// These instructions cannot address 80-bit memory. 190296417Sdimmulticlass FPBinary<SDNode OpNode, Format fp, string asmstring, 191296417Sdim bit Forward = 1> { 192193323Sed// ST(0) = ST(0) + [mem] 193280031Sdimdef _Fp32m : FpIf32<(outs RFP32:$dst), 194201360Srdivacky (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 195296417Sdim [!if(Forward, 196296417Sdim (set RFP32:$dst, 197296417Sdim (OpNode RFP32:$src1, (loadf32 addr:$src2))), 198296417Sdim (set RFP32:$dst, 199296417Sdim (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>; 200280031Sdimdef _Fp64m : FpIf64<(outs RFP64:$dst), 201201360Srdivacky (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 202296417Sdim [!if(Forward, 203296417Sdim (set RFP64:$dst, 204296417Sdim (OpNode RFP64:$src1, (loadf64 addr:$src2))), 205296417Sdim (set RFP64:$dst, 206296417Sdim (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>; 207280031Sdimdef _Fp64m32: FpIf64<(outs RFP64:$dst), 208201360Srdivacky (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 209296417Sdim [!if(Forward, 210296417Sdim (set RFP64:$dst, 211296417Sdim (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))), 212296417Sdim (set RFP64:$dst, 213296417Sdim (OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>; 214280031Sdimdef _Fp80m32: FpI_<(outs RFP80:$dst), 215201360Srdivacky (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 216296417Sdim [!if(Forward, 217296417Sdim (set RFP80:$dst, 218296417Sdim (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))), 219296417Sdim (set RFP80:$dst, 220296417Sdim (OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>; 221280031Sdimdef _Fp80m64: FpI_<(outs RFP80:$dst), 222201360Srdivacky (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 223296417Sdim [!if(Forward, 224296417Sdim (set RFP80:$dst, 225296417Sdim (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))), 226296417Sdim (set RFP80:$dst, 227296417Sdim (OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>; 228353358Sdimlet mayLoad = 1 in 229280031Sdimdef _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 230296417Sdim !strconcat("f", asmstring, "{s}\t$src")>; 231353358Sdimlet mayLoad = 1 in 232280031Sdimdef _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 233296417Sdim !strconcat("f", asmstring, "{l}\t$src")>; 234193323Sed// ST(0) = ST(0) + [memint] 235280031Sdimdef _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 236201360Srdivacky OneArgFPRW, 237296417Sdim [!if(Forward, 238296417Sdim (set RFP32:$dst, 239353358Sdim (OpNode RFP32:$src1, (X86fild16 addr:$src2))), 240296417Sdim (set RFP32:$dst, 241353358Sdim (OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>; 242280031Sdimdef _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 243201360Srdivacky OneArgFPRW, 244296417Sdim [!if(Forward, 245296417Sdim (set RFP32:$dst, 246353358Sdim (OpNode RFP32:$src1, (X86fild32 addr:$src2))), 247296417Sdim (set RFP32:$dst, 248353358Sdim (OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>; 249280031Sdimdef _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 250201360Srdivacky OneArgFPRW, 251296417Sdim [!if(Forward, 252296417Sdim (set RFP64:$dst, 253353358Sdim (OpNode RFP64:$src1, (X86fild16 addr:$src2))), 254296417Sdim (set RFP64:$dst, 255353358Sdim (OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>; 256280031Sdimdef _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 257201360Srdivacky OneArgFPRW, 258296417Sdim [!if(Forward, 259296417Sdim (set RFP64:$dst, 260353358Sdim (OpNode RFP64:$src1, (X86fild32 addr:$src2))), 261296417Sdim (set RFP64:$dst, 262353358Sdim (OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>; 263280031Sdimdef _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 264296417Sdim OneArgFPRW, 265296417Sdim [!if(Forward, 266296417Sdim (set RFP80:$dst, 267353358Sdim (OpNode RFP80:$src1, (X86fild16 addr:$src2))), 268296417Sdim (set RFP80:$dst, 269353358Sdim (OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>; 270280031Sdimdef _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 271296417Sdim OneArgFPRW, 272296417Sdim [!if(Forward, 273296417Sdim (set RFP80:$dst, 274353358Sdim (OpNode RFP80:$src1, (X86fild32 addr:$src2))), 275296417Sdim (set RFP80:$dst, 276353358Sdim (OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>; 277353358Sdimlet mayLoad = 1 in 278280031Sdimdef _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 279296417Sdim !strconcat("fi", asmstring, "{s}\t$src")>; 280353358Sdimlet mayLoad = 1 in 281280031Sdimdef _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 282296417Sdim !strconcat("fi", asmstring, "{l}\t$src")>; 283193323Sed} 284193323Sed 285360784Sdimlet Uses = [FPCW], mayRaiseFPException = 1 in { 286276479Sdim// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling 287276479Sdim// resources. 288327952Sdimlet hasNoSchedulingInfo = 1 in { 289360784Sdimdefm ADD : FPBinary_rr<any_fadd>; 290360784Sdimdefm SUB : FPBinary_rr<any_fsub>; 291360784Sdimdefm MUL : FPBinary_rr<any_fmul>; 292360784Sdimdefm DIV : FPBinary_rr<any_fdiv>; 293327952Sdim} 294327952Sdim 295276479Sdim// Sets the scheduling resources for the actual NAME#_F<size>m defintions. 296276479Sdimlet SchedRW = [WriteFAddLd] in { 297360784Sdimdefm ADD : FPBinary<any_fadd, MRM0m, "add">; 298360784Sdimdefm SUB : FPBinary<any_fsub, MRM4m, "sub">; 299360784Sdimdefm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>; 300276479Sdim} 301327952Sdim 302276479Sdimlet SchedRW = [WriteFMulLd] in { 303360784Sdimdefm MUL : FPBinary<any_fmul, MRM1m, "mul">; 304276479Sdim} 305327952Sdim 306276479Sdimlet SchedRW = [WriteFDivLd] in { 307360784Sdimdefm DIV : FPBinary<any_fdiv, MRM6m, "div">; 308360784Sdimdefm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>; 309239462Sdim} 310360784Sdim} // Uses = [FPCW], mayRaiseFPException = 1 311193323Sed 312276479Sdimclass FPST0rInst<Format fp, string asm> 313344779Sdim : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>; 314276479Sdimclass FPrST0Inst<Format fp, string asm> 315344779Sdim : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>; 316276479Sdimclass FPrST0PInst<Format fp, string asm> 317344779Sdim : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>; 318193323Sed 319193323Sed// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 320193323Sed// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 321193323Sed// we have to put some 'r's in and take them out of weird places. 322360784Sdimlet SchedRW = [WriteFAdd], Uses = [FPCW], mayRaiseFPException = 1 in { 323344779Sdimdef ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">; 324344779Sdimdef ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">; 325344779Sdimdef ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">; 326344779Sdimdef SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">; 327344779Sdimdef SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">; 328344779Sdimdef SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">; 329344779Sdimdef SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">; 330344779Sdimdef SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">; 331344779Sdimdef SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">; 332341825Sdim} // SchedRW 333360784Sdimlet SchedRW = [WriteFCom], Uses = [FPCW], mayRaiseFPException = 1 in { 334327952Sdimdef COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; 335327952Sdimdef COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; 336276479Sdim} // SchedRW 337360784Sdimlet SchedRW = [WriteFMul], Uses = [FPCW], mayRaiseFPException = 1 in { 338344779Sdimdef MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">; 339344779Sdimdef MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">; 340344779Sdimdef MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">; 341276479Sdim} // SchedRW 342360784Sdimlet SchedRW = [WriteFDiv], Uses = [FPCW], mayRaiseFPException = 1 in { 343344779Sdimdef DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">; 344344779Sdimdef DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">; 345344779Sdimdef DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">; 346344779Sdimdef DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">; 347344779Sdimdef DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">; 348344779Sdimdef DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">; 349276479Sdim} // SchedRW 350193323Sed 351193323Sed// Unary operations. 352341825Sdimmulticlass FPUnary<SDNode OpNode, Format fp, string asmstring> { 353193323Seddef _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 354341825Sdim [(set RFP32:$dst, (OpNode RFP32:$src))]>; 355193323Seddef _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 356341825Sdim [(set RFP64:$dst, (OpNode RFP64:$src))]>; 357193323Seddef _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 358341825Sdim [(set RFP80:$dst, (OpNode RFP80:$src))]>; 359341825Sdimdef _F : FPI<0xD9, fp, (outs), (ins), asmstring>; 360193323Sed} 361193323Sed 362341825Sdimlet SchedRW = [WriteFSign] in { 363341825Sdimdefm CHS : FPUnary<fneg, MRM_E0, "fchs">; 364341825Sdimdefm ABS : FPUnary<fabs, MRM_E1, "fabs">; 365276479Sdim} 366193323Sed 367360784Sdimlet Uses = [FPCW], mayRaiseFPException = 1 in { 368341825Sdimlet SchedRW = [WriteFSqrt80] in 369360784Sdimdefm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">; 370327952Sdim 371341825Sdimlet SchedRW = [WriteFCom] in { 372280031Sdimlet hasSideEffects = 0 in { 373193323Seddef TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 374193323Seddef TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 375193323Seddef TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 376327952Sdim} // hasSideEffects 377327952Sdim 378341825Sdimdef TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; 379327952Sdim} // SchedRW 380360784Sdim} // Uses = [FPCW], mayRaiseFPException = 1 381193323Sed 382198090Srdivacky// Versions of FP instructions that take a single memory operand. Added for the 383198090Srdivacky// disassembler; remove as they are included with patterns elsewhere. 384360784Sdimlet SchedRW = [WriteFComLd], Uses = [FPCW], mayRaiseFPException = 1 in { 385207618Srdivackydef FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 386207618Srdivackydef FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 387198090Srdivacky 388327952Sdimdef FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 389327952Sdimdef FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 390198090Srdivacky 391327952Sdimdef FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 392327952Sdimdef FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 393327952Sdim 394198090Srdivackydef FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 395198090Srdivackydef FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 396327952Sdim} // SchedRW 397198090Srdivacky 398327952Sdimlet SchedRW = [WriteMicrocoded] in { 399360784Sdimlet Defs = [FPSW, FPCW] in { 400327952Sdimdef FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 401360784Sdimdef FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">; 402360784Sdim} 403360784Sdim 404360784Sdimlet Defs = [FPSW, FPCW], Uses = [FPSW, FPCW] in { 405327952Sdimdef FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">; 406360784Sdimdef FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">; 407360784Sdim} 408198090Srdivacky 409360784Sdimlet Uses = [FPSW] in 410309124Sdimdef FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">; 411198090Srdivacky 412296417Sdimdef FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">; 413360784Sdimlet Uses = [FPCW] ,mayRaiseFPException = 1 in 414309124Sdimdef FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">; 415327952Sdim} // SchedRW 416198090Srdivacky 417193323Sed// Floating point cmovs. 418341825Sdimclass FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 419341825Sdim FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 420341825Sdimclass FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 421341825Sdim FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 422205218Srdivacky 423193323Sedmulticlass FPCMov<PatLeaf cc> { 424205218Srdivacky def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 425193323Sed CondMovFP, 426193323Sed [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 427341825Sdim cc, EFLAGS))]>; 428205218Srdivacky def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 429193323Sed CondMovFP, 430193323Sed [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 431341825Sdim cc, EFLAGS))]>; 432193323Sed def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 433193323Sed CondMovFP, 434193323Sed [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 435341825Sdim cc, EFLAGS))]>, 436205218Srdivacky Requires<[HasCMov]>; 437193323Sed} 438205218Srdivacky 439341825Sdimlet SchedRW = [WriteFCMOV] in { 440210299Sedlet Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 441193323Seddefm CMOVB : FPCMov<X86_COND_B>; 442193323Seddefm CMOVBE : FPCMov<X86_COND_BE>; 443193323Seddefm CMOVE : FPCMov<X86_COND_E>; 444193323Seddefm CMOVP : FPCMov<X86_COND_P>; 445193323Seddefm CMOVNB : FPCMov<X86_COND_AE>; 446193323Seddefm CMOVNBE: FPCMov<X86_COND_A>; 447193323Seddefm CMOVNE : FPCMov<X86_COND_NE>; 448193323Seddefm CMOVNP : FPCMov<X86_COND_NP>; 449210299Sed} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 450193323Sed 451205218Srdivackylet Predicates = [HasCMov] in { 452193323Sed// These are not factored because there's no clean way to pass DA/DB. 453344779Sdimdef CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op), 454344779Sdim "fcmovb\t{$op, %st|st, $op}">; 455344779Sdimdef CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op), 456344779Sdim "fcmovbe\t{$op, %st|st, $op}">; 457344779Sdimdef CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op), 458344779Sdim "fcmove\t{$op, %st|st, $op}">; 459344779Sdimdef CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op), 460344779Sdim "fcmovu\t{$op, %st|st, $op}">; 461344779Sdimdef CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op), 462344779Sdim "fcmovnb\t{$op, %st|st, $op}">; 463344779Sdimdef CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op), 464344779Sdim "fcmovnbe\t{$op, %st|st, $op}">; 465344779Sdimdef CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op), 466344779Sdim "fcmovne\t{$op, %st|st, $op}">; 467344779Sdimdef CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op), 468344779Sdim "fcmovnu\t{$op, %st|st, $op}">; 469205218Srdivacky} // Predicates = [HasCMov] 470327952Sdim} // SchedRW 471193323Sed 472360784Sdimlet mayRaiseFPException = 1 in { 473193323Sed// Floating point loads & stores. 474353358Sdimlet SchedRW = [WriteLoad], Uses = [FPCW] in { 475193323Sedlet canFoldAsLoad = 1 in { 476193323Seddef LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 477193323Sed [(set RFP32:$dst, (loadf32 addr:$src))]>; 478353358Sdimdef LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 479193323Sed [(set RFP64:$dst, (loadf64 addr:$src))]>; 480193323Seddef LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 481193323Sed [(set RFP80:$dst, (loadf80 addr:$src))]>; 482327952Sdim} // canFoldAsLoad 483193323Seddef LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 484193323Sed [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 485193323Seddef LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 486193323Sed [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 487193323Seddef LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 488193323Sed [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 489360784Sdimlet mayRaiseFPException = 0 in { 490193323Seddef ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 491353358Sdim [(set RFP32:$dst, (X86fild16 addr:$src))]>; 492193323Seddef ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 493353358Sdim [(set RFP32:$dst, (X86fild32 addr:$src))]>; 494193323Seddef ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 495353358Sdim [(set RFP32:$dst, (X86fild64 addr:$src))]>; 496193323Seddef ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 497353358Sdim [(set RFP64:$dst, (X86fild16 addr:$src))]>; 498193323Seddef ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 499353358Sdim [(set RFP64:$dst, (X86fild32 addr:$src))]>; 500193323Seddef ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 501353358Sdim [(set RFP64:$dst, (X86fild64 addr:$src))]>; 502193323Seddef ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 503353358Sdim [(set RFP80:$dst, (X86fild16 addr:$src))]>; 504193323Seddef ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 505353358Sdim [(set RFP80:$dst, (X86fild32 addr:$src))]>; 506193323Seddef ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 507353358Sdim [(set RFP80:$dst, (X86fild64 addr:$src))]>; 508360784Sdim} // mayRaiseFPException = 0 509327952Sdim} // SchedRW 510193323Sed 511343916Sdimlet SchedRW = [WriteStore], Uses = [FPCW] in { 512193323Seddef ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 513193323Sed [(store RFP32:$src, addr:$op)]>; 514193323Seddef ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 515193323Sed [(truncstoref32 RFP64:$src, addr:$op)]>; 516193323Seddef ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 517193323Sed [(store RFP64:$src, addr:$op)]>; 518193323Seddef ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 519193323Sed [(truncstoref32 RFP80:$src, addr:$op)]>; 520193323Seddef ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 521193323Sed [(truncstoref64 RFP80:$src, addr:$op)]>; 522193323Sed// FST does not support 80-bit memory target; FSTP must be used. 523193323Sed 524280031Sdimlet mayStore = 1, hasSideEffects = 0 in { 525193323Seddef ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 526193323Seddef ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 527193323Seddef ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 528193323Seddef ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 529193323Seddef ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 530327952Sdim} // mayStore 531327952Sdim 532193323Seddef ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 533193323Sed [(store RFP80:$src, addr:$op)]>; 534327952Sdim 535280031Sdimlet mayStore = 1, hasSideEffects = 0 in { 536193323Seddef IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 537193323Seddef IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 538193323Seddef IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 539193323Seddef IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 540193323Seddef IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 541193323Seddef IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 542193323Seddef IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 543193323Seddef IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 544193323Seddef IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 545327952Sdim} // mayStore 546343916Sdim} // SchedRW, Uses = [FPCW] 547193323Sed 548353358Sdimlet mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in { 549341825Sdimdef LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">; 550341825Sdimdef LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">; 551341825Sdimdef LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">; 552360784Sdimlet mayRaiseFPException = 0 in { 553341825Sdimdef ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">; 554341825Sdimdef ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">; 555341825Sdimdef ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">; 556193323Sed} 557360784Sdim} 558343916Sdimlet mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 559341825Sdimdef ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">; 560341825Sdimdef ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">; 561341825Sdimdef ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">; 562341825Sdimdef ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">; 563341825Sdimdef ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">; 564341825Sdimdef IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">; 565341825Sdimdef IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">; 566341825Sdimdef IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">; 567341825Sdimdef IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">; 568341825Sdimdef IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">; 569193323Sed} 570193323Sed 571193323Sed// FISTTP requires SSE3 even though it's a FPStack op. 572343916Sdimlet Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in { 573193323Seddef ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 574234353Sdim [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 575193323Seddef ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 576234353Sdim [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 577193323Seddef ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 578234353Sdim [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 579193323Seddef ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 580234353Sdim [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 581193323Seddef ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 582234353Sdim [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 583193323Seddef ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 584234353Sdim [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 585193323Seddef ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 586234353Sdim [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 587193323Seddef ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 588234353Sdim [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 589193323Seddef ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 590234353Sdim [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 591234353Sdim} // Predicates = [HasSSE3] 592193323Sed 593343916Sdimlet mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in { 594341825Sdimdef ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">; 595341825Sdimdef ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">; 596341825Sdimdef ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">; 597193323Sed} 598193323Sed 599193323Sed// FP Stack manipulation instructions. 600353358Sdimlet SchedRW = [WriteMove], Uses = [FPCW] in { 601344779Sdimdef LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">; 602344779Sdimdef ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">; 603344779Sdimdef ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">; 604344779Sdimdef XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">; 605249423Sdim} 606193323Sed 607193323Sed// Floating point constant loads. 608353358Sdimlet SchedRW = [WriteZero], Uses = [FPCW] in { 609193323Seddef LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 610193323Sed [(set RFP32:$dst, fpimm0)]>; 611193323Seddef LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 612193323Sed [(set RFP32:$dst, fpimm1)]>; 613193323Seddef LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 614193323Sed [(set RFP64:$dst, fpimm0)]>; 615193323Seddef LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 616193323Sed [(set RFP64:$dst, fpimm1)]>; 617193323Seddef LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 618193323Sed [(set RFP80:$dst, fpimm0)]>; 619193323Seddef LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 620193323Sed [(set RFP80:$dst, fpimm1)]>; 621193323Sed} 622193323Sed 623353358Sdimlet SchedRW = [WriteFLD0], Uses = [FPCW] in 624341825Sdimdef LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">; 625193323Sed 626353358Sdimlet SchedRW = [WriteFLD1], Uses = [FPCW] in 627341825Sdimdef LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">; 628341825Sdim 629360784Sdimlet SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW] in { 630341825Sdimdef FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>; 631341825Sdimdef FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>; 632341825Sdimdef FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>; 633341825Sdimdef FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>; 634341825Sdimdef FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>; 635341825Sdim} // SchedRW 636341825Sdim 637193323Sed// Floating point compares. 638343916Sdimlet SchedRW = [WriteFCom], Uses = [FPCW] in { 639193323Seddef UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 640360784Sdim [(set FPSW, (trunc (X86any_fcmp RFP32:$lhs, RFP32:$rhs)))]>; 641193323Seddef UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 642360784Sdim [(set FPSW, (trunc (X86any_fcmp RFP64:$lhs, RFP64:$rhs)))]>; 643193323Seddef UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 644360784Sdim [(set FPSW, (trunc (X86any_fcmp RFP80:$lhs, RFP80:$rhs)))]>; 645360784Sdimdef COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 646360784Sdim [(set FPSW, (trunc (X86strict_fcmps RFP32:$lhs, RFP32:$rhs)))]>; 647360784Sdimdef COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 648360784Sdim [(set FPSW, (trunc (X86strict_fcmps RFP64:$lhs, RFP64:$rhs)))]>; 649360784Sdimdef COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 650360784Sdim [(set FPSW, (trunc (X86strict_fcmps RFP80:$lhs, RFP80:$rhs)))]>; 651249423Sdim} // SchedRW 652360784Sdim} // mayRaiseFPException = 1 653239462Sdim 654360784Sdimlet SchedRW = [WriteFCom], mayRaiseFPException = 1 in { 655205407Srdivacky// CC = ST(0) cmp ST(i) 656360784Sdimlet Defs = [EFLAGS, FPCW], Uses = [FPCW] in { 657343916Sdimdef UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 658360784Sdim [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>, 659343916Sdim Requires<[FPStackf32, HasCMov]>; 660343916Sdimdef UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 661360784Sdim [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>, 662343916Sdim Requires<[FPStackf64, HasCMov]>; 663193323Seddef UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 664360784Sdim [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>, 665343916Sdim Requires<[HasCMov]>; 666360784Sdimdef COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 667360784Sdim [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>, 668360784Sdim Requires<[FPStackf32, HasCMov]>; 669360784Sdimdef COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 670360784Sdim [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>, 671360784Sdim Requires<[FPStackf64, HasCMov]>; 672360784Sdimdef COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 673360784Sdim [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>, 674360784Sdim Requires<[HasCMov]>; 675193323Sed} 676193323Sed 677360784Sdimlet Uses = [ST0, FPCW] in { 678276479Sdimdef UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) 679344779Sdim (outs), (ins RSTi:$reg), "fucom\t$reg">; 680276479Sdimdef UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop 681344779Sdim (outs), (ins RSTi:$reg), "fucomp\t$reg">; 682276479Sdimdef UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop 683341825Sdim (outs), (ins), "fucompp">; 684239462Sdim} 685193323Sed 686343916Sdimlet Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in { 687276479Sdimdef UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) 688344779Sdim (outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">; 689276479Sdimdef UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop 690344779Sdim (outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">; 691193323Sed 692344779Sdimdef COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg), 693344779Sdim "fcomi\t{$reg, %st|st, $reg}">; 694344779Sdimdef COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg), 695344779Sdim "fcompi\t{$reg, %st|st, $reg}">; 696239462Sdim} 697249423Sdim} // SchedRW 698201360Srdivacky 699193323Sed// Floating point flag ops. 700249423Sdimlet SchedRW = [WriteALU] in { 701360784Sdimlet Defs = [AX, FPSW], Uses = [FPSW] in 702276479Sdimdef FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags 703261991Sdim (outs), (ins), "fnstsw\t{%ax|ax}", 704341825Sdim [(set AX, (X86fp_stsw FPSW))]>; 705343916Sdimlet Defs = [FPSW], Uses = [FPCW] in 706193323Seddef FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 707193323Sed (outs), (ins i16mem:$dst), "fnstcw\t$dst", 708341825Sdim [(X86fp_cwd_get16 addr:$dst)]>; 709249423Sdim} // SchedRW 710343916Sdimlet Defs = [FPSW,FPCW], mayLoad = 1 in 711193323Seddef FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 712341825Sdim (outs), (ins i16mem:$dst), "fldcw\t$dst", []>, 713249423Sdim Sched<[WriteLoad]>; 714193323Sed 715218893Sdim// FPU control instructions 716249423Sdimlet SchedRW = [WriteMicrocoded] in { 717344779Sdimdef FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">; 718344779Sdimdef FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">; 719321369Sdim 720360784Sdimlet Defs = [FPSW, FPCW] in 721360784Sdimdef FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>; 722201360Srdivacky// Clear exceptions 723360784Sdimlet Defs = [FPSW] in 724341825Sdimdef FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>; 725249423Sdim} // SchedRW 726201360Srdivacky 727341825Sdim// Operand-less floating-point instructions for the disassembler. 728360784Sdimlet Defs = [FPSW] in 729341825Sdimdef FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>; 730341825Sdim 731249423Sdimlet SchedRW = [WriteMicrocoded] in { 732327952Sdimlet Defs = [FPSW] in { 733341825Sdimdef WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>; 734341825Sdimdef FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>; 735360784Sdimdef FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>; 736360784Sdimdef FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>; 737360784Sdimlet Uses = [FPCW], mayRaiseFPException = 1 in { 738341825Sdimdef F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>; 739341825Sdimdef FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>; 740341825Sdimdef FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>; 741341825Sdimdef FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>; 742341825Sdimdef FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>; 743341825Sdimdef FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>; 744341825Sdimdef FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>; 745341825Sdimdef FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>; 746360784Sdimdef FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>; 747360784Sdimdef FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>; 748341825Sdimdef FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>; 749341825Sdimdef FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>; 750341825Sdimdef FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>; 751341825Sdimdef FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>; 752360784Sdim} // Uses = [FPCW], mayRaiseFPException = 1 753327952Sdim} // Defs = [FPSW] 754201360Srdivacky 755360784Sdimlet Uses = [FPSW, FPCW] in { 756341825Sdimdef FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 757341825Sdim "fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB, 758327952Sdim Requires<[HasFXSR]>; 759341825Sdimdef FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst), 760341825Sdim "fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>, 761341825Sdim TB, Requires<[HasFXSR, In64BitMode]>; 762360784Sdim} // Uses = [FPSW, FPCW] 763360784Sdim 764360784Sdimlet Defs = [FPSW, FPCW] in { 765341825Sdimdef FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src), 766341825Sdim "fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>, 767327952Sdim TB, Requires<[HasFXSR]>; 768341825Sdimdef FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src), 769341825Sdim "fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>, 770341825Sdim TB, Requires<[HasFXSR, In64BitMode]>; 771360784Sdim} // Defs = [FPSW, FPCW] 772249423Sdim} // SchedRW 773201360Srdivacky 774193323Sed//===----------------------------------------------------------------------===// 775193323Sed// Non-Instruction Patterns 776193323Sed//===----------------------------------------------------------------------===// 777193323Sed 778193323Sed// Required for RET of f32 / f64 / f80 values. 779353358Sdimdef : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>; 780360784Sdimdef : Pat<(X86fldf32 addr:$src), (LD_Fp32m64 addr:$src)>; 781353358Sdimdef : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>; 782360784Sdimdef : Pat<(X86fldf32 addr:$src), (LD_Fp32m80 addr:$src)>; 783360784Sdimdef : Pat<(X86fldf64 addr:$src), (LD_Fp64m80 addr:$src)>; 784353358Sdimdef : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>; 785193323Sed 786193323Sed// Required for CALL which return f32 / f64 / f80 values. 787353358Sdimdef : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>; 788353358Sdimdef : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>; 789353358Sdimdef : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>; 790353358Sdimdef : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>; 791353358Sdimdef : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>; 792353358Sdimdef : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>; 793193323Sed 794193323Sed// Floating point constant -0.0 and -1.0 795193323Seddef : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 796193323Seddef : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 797193323Seddef : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 798193323Seddef : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 799193323Seddef : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 800193323Seddef : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 801193323Sed 802193323Sed// Used to conv. i64 to f64 since there isn't a SSE version. 803353358Sdimdef : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>; 804193323Sed 805353358Sdim// Used to conv. between f80 and i64 for i64 atomic loads. 806353358Sdimdef : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>; 807353358Sdimdef : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>; 808353358Sdim 809193323Sed// FP extensions map onto simple pseudo-value conversions if they are to/from 810193323Sed// the FP stack. 811360784Sdimdef : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 812193323Sed Requires<[FPStackf32]>; 813360784Sdimdef : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 814193323Sed Requires<[FPStackf32]>; 815360784Sdimdef : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 816193323Sed Requires<[FPStackf64]>; 817193323Sed 818193323Sed// FP truncations map onto simple pseudo-value conversions if they are to/from 819193323Sed// the FP stack. We have validated that only value-preserving truncations make 820193323Sed// it through isel. 821360784Sdimdef : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 822193323Sed Requires<[FPStackf32]>; 823360784Sdimdef : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 824193323Sed Requires<[FPStackf32]>; 825360784Sdimdef : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 826193323Sed Requires<[FPStackf64]>; 827