X86InstrControl.td revision 309124
12340Sbde//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 250476Speter// 31638Srgrimes// The LLVM Compiler Infrastructure 42340Sbde// 578347Sobrien// This file is distributed under the University of Illinois Open Source 61638Srgrimes// License. See LICENSE.TXT for details. 7209024Simp// 8209024Simp//===----------------------------------------------------------------------===// 9209024Simp// 10215149Sdim// This file describes the X86 jump, return, call, and related instructions. 11215149Sdim// 12215149Sdim//===----------------------------------------------------------------------===// 13215149Sdim 14215149Sdim//===----------------------------------------------------------------------===// 15209024Simp// Control Flow Instructions. 16239272Sgonzo// 17209024Simp 18209024Simp// Return instructions. 19241298Smarcel// 20241298Smarcel// The X86retflag return instructions are variadic because we may add ST0 and 21241298Smarcel// ST1 arguments when returning values on the x87 stack. 22241298Smarcellet isTerminator = 1, isReturn = 1, isBarrier = 1, 2319343Ssteve hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 2419343Ssteve def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), 2519343Ssteve "ret{l}", [], IIC_RET>, OpSize32, 2619343Ssteve Requires<[Not64BitMode]>; 2719343Ssteve def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), 2819343Ssteve "ret{q}", [], IIC_RET>, OpSize32, 2919343Ssteve Requires<[In64BitMode]>; 3019343Ssteve def RETW : I <0xC3, RawFrm, (outs), (ins), 3119343Ssteve "ret{w}", 3219343Ssteve [], IIC_RET>, OpSize16; 3319343Ssteve def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 3419343Ssteve "ret{l}\t$amt", 35117173Sru [], IIC_RET_IMM>, OpSize32, 3619343Ssteve Requires<[Not64BitMode]>; 371638Srgrimes def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 382340Sbde "ret{q}\t$amt", 3919343Ssteve [], IIC_RET_IMM>, OpSize32, 4019343Ssteve Requires<[In64BitMode]>; 4119343Ssteve def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 42270484Sdes "ret{w}\t$amt", 4319343Ssteve [], IIC_RET_IMM>, OpSize16; 442340Sbde def LRETL : I <0xCB, RawFrm, (outs), (ins), 45270484Sdes "{l}ret{l|f}", [], IIC_RET>, OpSize32; 46270484Sdes def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 47270484Sdes "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>; 481638Srgrimes def LRETW : I <0xCB, RawFrm, (outs), (ins), 492340Sbde "{l}ret{w|f}", [], IIC_RET>, OpSize16; 502340Sbde def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 51217100Skib "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32; 521638Srgrimes def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 5319343Ssteve "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>; 5419343Ssteve def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 55125445Sbde "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16; 5619343Ssteve 572340Sbde // The machine return from interrupt instruction, but sometimes we need to 58209024Simp // perform a post-epilogue stack adjustment. Codegen emits the pseudo form 59177865Sobrien // which expands to include an SP adjustment if necessary. 60173375Scognet def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, 61177865Sobrien OpSize16; 6219343Ssteve def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], 63173850Sjb IIC_IRET>, OpSize32; 64173850Sjb def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", [], 65173375Scognet IIC_IRET>, Requires<[In64BitMode]>; 66173850Sjb let isCodeGenOnly = 1 in 67202807Ssepotvin def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; 681638Srgrimes def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; 69179184Sjb} 70179184Sjb 71179184Sjb// Unconditional branches. 72179184Sjblet isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 73179184Sjb def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 74212422Srpaulo "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; 75179184Sjb let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 76179184Sjb def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), 77179184Sjb "jmp\t$dst", [], IIC_JMP_REL>, OpSize16; 78206082Snetchild def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), 79206082Snetchild "jmp\t$dst", [], IIC_JMP_REL>, OpSize32; 80206082Snetchild } 81179184Sjb} 82179184Sjb 832419Spaul// Conditional Branches. 84204024Smarcellet isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { 85202807Ssepotvin multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 861638Srgrimes def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, 872340Sbde [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>; 881638Srgrimes let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 89125119Sru def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm, 902340Sbde [], IIC_Jcc>, OpSize16, TB; 912340Sbde def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm, 922340Sbde [], IIC_Jcc>, TB, OpSize32; 932340Sbde } 942340Sbde } 952340Sbde} 962340Sbde 972340Sbdedefm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; 982340Sbdedefm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>; 992340Sbdedefm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; 1001638Srgrimesdefm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; 101251748Ssjgdefm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; 102251748Ssjgdefm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; 103251748Ssjgdefm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; 104133369Shartidefm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; 105251748Ssjgdefm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; 106251748Ssjgdefm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; 107251748Ssjgdefm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; 108251748Ssjgdefm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; 109133369Shartidefm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; 110133369Shartidefm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; 111133369Shartidefm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; 112133369Shartidefm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; 11319343Ssteve 11419343Ssteve// jcx/jecx/jrcx instructions. 11519343Sstevelet isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { 11619343Ssteve // These are the 32-bit versions of this instruction for the asmparser. In 1172340Sbde // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 1182340Sbde // jecxz. 11919343Ssteve let Uses = [CX] in 1202340Sbde def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 1211638Srgrimes "jcxz\t$dst", [], IIC_JCXZ>, AdSize16, 1225257Sache Requires<[Not64BitMode]>; 1235257Sache let Uses = [ECX] in 1242340Sbde def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 1252340Sbde "jecxz\t$dst", [], IIC_JCXZ>, AdSize32; 1261638Srgrimes 1272340Sbde let Uses = [RCX] in 1282340Sbde def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 1291638Srgrimes "jrcxz\t$dst", [], IIC_JCXZ>, AdSize64, 1302340Sbde Requires<[In64BitMode]>; 13192813Sru} 13292491Smarkm 13392491Smarkm// Indirect branches 134120485Smarkmlet isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 13592491Smarkm def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", 1361638Srgrimes [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>, 1372340Sbde OpSize16, Sched<[WriteJump]>; 1381638Srgrimes def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", 139234575Simp [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>, 140234575Simp Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>; 141234575Simp 14236054Sbde def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 14336054Sbde [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>, 14436054Sbde OpSize32, Sched<[WriteJump]>; 145244236Semaste def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 146244236Semaste [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, 147294064Ssmh Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>; 148294064Ssmh 1492340Sbde def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 1502340Sbde [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>, 1511638Srgrimes Sched<[WriteJump]>; 1522340Sbde def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 1532340Sbde [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, 154244366Semaste Requires<[In64BitMode]>, Sched<[WriteJumpLd]>; 1551638Srgrimes 1562340Sbde let Predicates = [Not64BitMode] in { 1572340Sbde def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 1582340Sbde (ins i16imm:$off, i16imm:$seg), 15919343Ssteve "ljmp{w}\t$seg, $off", [], 16019343Ssteve IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>; 16119343Ssteve def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 1622340Sbde (ins i32imm:$off, i16imm:$seg), 16319343Ssteve "ljmp{l}\t$seg, $off", [], 1642340Sbde IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>; 16519343Ssteve } 166129163Sbde def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), 16719343Ssteve "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, 16819343Ssteve Sched<[WriteJump]>; 16919343Ssteve 17019343Ssteve def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), 17119343Ssteve "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16, 17219343Ssteve Sched<[WriteJumpLd]>; 17319343Ssteve def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), 17411613Sbde "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32, 17519481Salex Sched<[WriteJumpLd]>; 176228137Sfjoe} 17719343Ssteve 17819343Ssteve 17919481Salex// Loop instructions 180228137Sfjoelet SchedRW = [WriteJump] in { 18119343Sstevedef LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>; 18219343Sstevedef LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>; 183211243Swilldef LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>; 18419343Ssteve} 18519343Ssteve 18619343Ssteve//===----------------------------------------------------------------------===// 18719343Ssteve// Call Instructions... 18819343Ssteve// 18919481Salexlet isCall = 1 in 190228137Sfjoe // All calls clobber the non-callee saved registers. ESP is marked as 19119343Ssteve // a use to prevent stack-pointer assignments that appear immediately 19219343Ssteve // before calls from potentially appearing dead. Uses for argument 19319481Salex // registers are added manually. 194228137Sfjoe let Uses = [ESP] in { 19519343Ssteve def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 19619343Ssteve (outs), (ins i32imm_pcrel:$dst), 19719481Salex "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32, 19819481Salex Requires<[Not64BitMode]>, Sched<[WriteJump]>; 19939208Sobrien let hasSideEffects = 0 in 20019343Ssteve def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 201228137Sfjoe (outs), (ins i16imm_pcrel:$dst), 20219343Ssteve "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16, 20319343Ssteve Sched<[WriteJump]>; 20419481Salex def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), 20519481Salex "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>, 20639208Sobrien OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 20719343Ssteve def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), 208228137Sfjoe "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))], 20919343Ssteve IIC_CALL_MEM>, OpSize16, 21019343Ssteve Requires<[Not64BitMode,FavorMemIndirectCall]>, 21119481Salex Sched<[WriteJumpLd]>; 21219343Ssteve def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 21319343Ssteve "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, 21419343Ssteve OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 21519481Salex def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 21619343Ssteve "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], 21719343Ssteve IIC_CALL_MEM>, OpSize32, 21819343Ssteve Requires<[Not64BitMode,FavorMemIndirectCall]>, 21919481Salex Sched<[WriteJumpLd]>; 22019481Salex 22139208Sobrien let Predicates = [Not64BitMode] in { 22219343Ssteve def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 22319343Ssteve (ins i16imm:$off, i16imm:$seg), 22419481Salex "lcall{w}\t$seg, $off", [], 22519481Salex IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>; 22639208Sobrien def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 22719343Ssteve (ins i32imm:$off, i16imm:$seg), 22819343Ssteve "lcall{l}\t$seg, $off", [], 22919343Ssteve IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>; 23019343Ssteve } 23119343Ssteve 23211613Sbde def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), 233211243Swill "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16, 23411613Sbde Sched<[WriteJumpLd]>; 23511613Sbde def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), 236103713Smarkm "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32, 237103713Smarkm Sched<[WriteJumpLd]>; 238103713Smarkm } 239103713Smarkm 240103713Smarkm 241103713Smarkm// Tail call stuff. 242103713Smarkm 243103713Smarkmlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 24477817Sobrien isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 24577817Sobrien let Uses = [ESP] in { 246228137Sfjoe def TCRETURNdi : PseudoI<(outs), 24777817Sobrien (ins i32imm_pcrel:$dst, i32imm:$offset), []>; 2481638Srgrimes def TCRETURNri : PseudoI<(outs), 249280329Sdim (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 250228137Sfjoe let mayLoad = 1 in 2511638Srgrimes def TCRETURNmi : PseudoI<(outs), 25277817Sobrien (ins i32mem_TC:$dst, i32imm:$offset), []>; 25377817Sobrien 25477817Sobrien // FIXME: The should be pseudo instructions that are lowered when going to 25536673Sdt // mcinst. 256280329Sdim def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 2571844Swollman (ins i32imm_pcrel:$dst), 25836054Sbde "jmp\t$dst", 259280329Sdim [], IIC_JMP_REL>; 260228137Sfjoe def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 26136054Sbde "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead. 2621638Srgrimes let mayLoad = 1 in 263280329Sdim def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), 264228137Sfjoe "jmp{l}\t{*}$dst", [], IIC_JMP_MEM>; 2651638Srgrimes} 26677818Sobrien 26777818Sobrien 26877818Sobrien//===----------------------------------------------------------------------===// 26977818Sobrien// Call Instructions... 2701638Srgrimes// 271280329Sdim 2721638Srgrimes// RSP is marked as a use to prevent stack-pointer assignments that appear 2733292Srgrimes// immediately before calls from potentially appearing dead. Uses for argument 274280329Sdim// registers are added manually. 275228137Sfjoelet isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in { 2763292Srgrimes // NOTE: this pattern doesn't match "X86call imm", because we do not know 277117173Sru // that the offset between an arbitrary immediate and the call will fit in 278280329Sdim // the 32-bit pcrel field that we have. 279280329Sdim def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 280228137Sfjoe (outs), (ins i64i32imm_pcrel:$dst), 281117173Sru "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32, 282117173Sru Requires<[In64BitMode]>; 2831638Srgrimes def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 284228137Sfjoe "call{q}\t{*}$dst", [(X86call GR64:$dst)], 2851638Srgrimes IIC_CALL_RI>, 28616068Sphk Requires<[In64BitMode]>; 2871638Srgrimes def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 28816068Sphk "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], 28916068Sphk IIC_CALL_MEM>, 29039208Sobrien Requires<[In64BitMode,FavorMemIndirectCall]>; 291228137Sfjoe 2921638Srgrimes def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), 2931638Srgrimes "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; 29415959Sphk} 29515959Sphk 29639208Sobrienlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 297228137Sfjoe isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1, 2981638Srgrimes SchedRW = [WriteJump] in { 29921582Ssteve def TCRETURNdi64 : PseudoI<(outs), 3001638Srgrimes (ins i64i32imm_pcrel:$dst, i32imm:$offset), 30121582Ssteve []>; 30221582Ssteve def TCRETURNri64 : PseudoI<(outs), 3031638Srgrimes (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>; 3041638Srgrimes let mayLoad = 1 in 30515959Sphk def TCRETURNmi64 : PseudoI<(outs), 3061638Srgrimes (ins i64mem_TC:$dst, i32imm:$offset), []>; 3071638Srgrimes 30811613Sbde def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), 309228137Sfjoe "jmp\t$dst", [], IIC_JMP_REL>; 3101638Srgrimes def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 3111638Srgrimes "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 31211613Sbde 3131638Srgrimes let mayLoad = 1 in 31439208Sobrien def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 315228137Sfjoe "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 3161638Srgrimes 31716068Sphk // Win64 wants jumps leaving the function to have a REX_W prefix. 3181638Srgrimes let hasREX_WPrefix = 1 in { 31916068Sphk def TAILJMPd64_REX : Ii32PCRel<0xE9, RawFrm, (outs), 32016068Sphk (ins i64i32imm_pcrel:$dst), 32139208Sobrien "rex64 jmp\t$dst", [], IIC_JMP_REL>; 322228137Sfjoe def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 3231638Srgrimes "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 3241638Srgrimes 32515959Sphk let mayLoad = 1 in 32615959Sphk def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 32739208Sobrien "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; 328228137Sfjoe } 3291844Swollman} 330129163Sbde