X86ISelDAGToDAG.cpp revision 251662
1//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a DAG pattern matching instruction selector for X86, 11// converting from a legalized dag to a X86 dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-isel" 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86RegisterInfo.h" 20#include "X86Subtarget.h" 21#include "X86TargetMachine.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/SelectionDAGISel.h" 28#include "llvm/IR/Instructions.h" 29#include "llvm/IR/Intrinsics.h" 30#include "llvm/IR/Type.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37using namespace llvm; 38 39STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); 40 41//===----------------------------------------------------------------------===// 42// Pattern Matcher Implementation 43//===----------------------------------------------------------------------===// 44 45namespace { 46 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses 47 /// SDValue's instead of register numbers for the leaves of the matched 48 /// tree. 49 struct X86ISelAddressMode { 50 enum { 51 RegBase, 52 FrameIndexBase 53 } BaseType; 54 55 // This is really a union, discriminated by BaseType! 56 SDValue Base_Reg; 57 int Base_FrameIndex; 58 59 unsigned Scale; 60 SDValue IndexReg; 61 int32_t Disp; 62 SDValue Segment; 63 const GlobalValue *GV; 64 const Constant *CP; 65 const BlockAddress *BlockAddr; 66 const char *ES; 67 int JT; 68 unsigned Align; // CP alignment. 69 unsigned char SymbolFlags; // X86II::MO_* 70 71 X86ISelAddressMode() 72 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), 73 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0), 74 SymbolFlags(X86II::MO_NO_FLAG) { 75 } 76 77 bool hasSymbolicDisplacement() const { 78 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0; 79 } 80 81 bool hasBaseOrIndexReg() const { 82 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; 83 } 84 85 /// isRIPRelative - Return true if this addressing mode is already RIP 86 /// relative. 87 bool isRIPRelative() const { 88 if (BaseType != RegBase) return false; 89 if (RegisterSDNode *RegNode = 90 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) 91 return RegNode->getReg() == X86::RIP; 92 return false; 93 } 94 95 void setBaseReg(SDValue Reg) { 96 BaseType = RegBase; 97 Base_Reg = Reg; 98 } 99 100#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 101 void dump() { 102 dbgs() << "X86ISelAddressMode " << this << '\n'; 103 dbgs() << "Base_Reg "; 104 if (Base_Reg.getNode() != 0) 105 Base_Reg.getNode()->dump(); 106 else 107 dbgs() << "nul"; 108 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n' 109 << " Scale" << Scale << '\n' 110 << "IndexReg "; 111 if (IndexReg.getNode() != 0) 112 IndexReg.getNode()->dump(); 113 else 114 dbgs() << "nul"; 115 dbgs() << " Disp " << Disp << '\n' 116 << "GV "; 117 if (GV) 118 GV->dump(); 119 else 120 dbgs() << "nul"; 121 dbgs() << " CP "; 122 if (CP) 123 CP->dump(); 124 else 125 dbgs() << "nul"; 126 dbgs() << '\n' 127 << "ES "; 128 if (ES) 129 dbgs() << ES; 130 else 131 dbgs() << "nul"; 132 dbgs() << " JT" << JT << " Align" << Align << '\n'; 133 } 134#endif 135 }; 136} 137 138namespace { 139 //===--------------------------------------------------------------------===// 140 /// ISel - X86 specific code to select X86 machine instructions for 141 /// SelectionDAG operations. 142 /// 143 class X86DAGToDAGISel : public SelectionDAGISel { 144 /// X86Lowering - This object fully describes how to lower LLVM code to an 145 /// X86-specific SelectionDAG. 146 const X86TargetLowering &X86Lowering; 147 148 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 149 /// make the right decision when generating code for different targets. 150 const X86Subtarget *Subtarget; 151 152 /// OptForSize - If true, selector should try to optimize for code size 153 /// instead of performance. 154 bool OptForSize; 155 156 public: 157 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) 158 : SelectionDAGISel(tm, OptLevel), 159 X86Lowering(*tm.getTargetLowering()), 160 Subtarget(&tm.getSubtarget<X86Subtarget>()), 161 OptForSize(false) {} 162 163 virtual const char *getPassName() const { 164 return "X86 DAG->DAG Instruction Selection"; 165 } 166 167 virtual void EmitFunctionEntryCode(); 168 169 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 170 171 virtual void PreprocessISelDAG(); 172 173 inline bool immSext8(SDNode *N) const { 174 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue()); 175 } 176 177 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit 178 // sign extended field. 179 inline bool i64immSExt32(SDNode *N) const { 180 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue(); 181 return (int64_t)v == (int32_t)v; 182 } 183 184// Include the pieces autogenerated from the target description. 185#include "X86GenDAGISel.inc" 186 187 private: 188 SDNode *Select(SDNode *N); 189 SDNode *SelectGather(SDNode *N, unsigned Opc); 190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 191 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT); 192 193 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM); 194 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM); 195 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 196 bool MatchAddress(SDValue N, X86ISelAddressMode &AM); 197 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 198 unsigned Depth); 199 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 200 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, 201 SDValue &Scale, SDValue &Index, SDValue &Disp, 202 SDValue &Segment); 203 bool SelectLEAAddr(SDValue N, SDValue &Base, 204 SDValue &Scale, SDValue &Index, SDValue &Disp, 205 SDValue &Segment); 206 bool SelectTLSADDRAddr(SDValue N, SDValue &Base, 207 SDValue &Scale, SDValue &Index, SDValue &Disp, 208 SDValue &Segment); 209 bool SelectScalarSSELoad(SDNode *Root, SDValue N, 210 SDValue &Base, SDValue &Scale, 211 SDValue &Index, SDValue &Disp, 212 SDValue &Segment, 213 SDValue &NodeWithChain); 214 215 bool TryFoldLoad(SDNode *P, SDValue N, 216 SDValue &Base, SDValue &Scale, 217 SDValue &Index, SDValue &Disp, 218 SDValue &Segment); 219 220 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 221 /// inline asm expressions. 222 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 223 char ConstraintCode, 224 std::vector<SDValue> &OutOps); 225 226 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); 227 228 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 229 SDValue &Scale, SDValue &Index, 230 SDValue &Disp, SDValue &Segment) { 231 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 232 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) : 233 AM.Base_Reg; 234 Scale = getI8Imm(AM.Scale); 235 Index = AM.IndexReg; 236 // These are 32-bit even in 64-bit mode since RIP relative offset 237 // is 32-bit. 238 if (AM.GV) 239 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(), 240 MVT::i32, AM.Disp, 241 AM.SymbolFlags); 242 else if (AM.CP) 243 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, 244 AM.Align, AM.Disp, AM.SymbolFlags); 245 else if (AM.ES) { 246 assert(!AM.Disp && "Non-zero displacement is ignored with ES."); 247 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags); 248 } else if (AM.JT != -1) { 249 assert(!AM.Disp && "Non-zero displacement is ignored with JT."); 250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags); 251 } else if (AM.BlockAddr) 252 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp, 253 AM.SymbolFlags); 254 else 255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); 256 257 if (AM.Segment.getNode()) 258 Segment = AM.Segment; 259 else 260 Segment = CurDAG->getRegister(0, MVT::i32); 261 } 262 263 /// getI8Imm - Return a target constant with the specified value, of type 264 /// i8. 265 inline SDValue getI8Imm(unsigned Imm) { 266 return CurDAG->getTargetConstant(Imm, MVT::i8); 267 } 268 269 /// getI32Imm - Return a target constant with the specified value, of type 270 /// i32. 271 inline SDValue getI32Imm(unsigned Imm) { 272 return CurDAG->getTargetConstant(Imm, MVT::i32); 273 } 274 275 /// getGlobalBaseReg - Return an SDNode that returns the value of 276 /// the global base register. Output instructions required to 277 /// initialize the global base register, if necessary. 278 /// 279 SDNode *getGlobalBaseReg(); 280 281 /// getTargetMachine - Return a reference to the TargetMachine, casted 282 /// to the target-specific type. 283 const X86TargetMachine &getTargetMachine() const { 284 return static_cast<const X86TargetMachine &>(TM); 285 } 286 287 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 288 /// to the target-specific type. 289 const X86InstrInfo *getInstrInfo() const { 290 return getTargetMachine().getInstrInfo(); 291 } 292 }; 293} 294 295 296bool 297X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { 298 if (OptLevel == CodeGenOpt::None) return false; 299 300 if (!N.hasOneUse()) 301 return false; 302 303 if (N.getOpcode() != ISD::LOAD) 304 return true; 305 306 // If N is a load, do additional profitability checks. 307 if (U == Root) { 308 switch (U->getOpcode()) { 309 default: break; 310 case X86ISD::ADD: 311 case X86ISD::SUB: 312 case X86ISD::AND: 313 case X86ISD::XOR: 314 case X86ISD::OR: 315 case ISD::ADD: 316 case ISD::ADDC: 317 case ISD::ADDE: 318 case ISD::AND: 319 case ISD::OR: 320 case ISD::XOR: { 321 SDValue Op1 = U->getOperand(1); 322 323 // If the other operand is a 8-bit immediate we should fold the immediate 324 // instead. This reduces code size. 325 // e.g. 326 // movl 4(%esp), %eax 327 // addl $4, %eax 328 // vs. 329 // movl $4, %eax 330 // addl 4(%esp), %eax 331 // The former is 2 bytes shorter. In case where the increment is 1, then 332 // the saving can be 4 bytes (by using incl %eax). 333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1)) 334 if (Imm->getAPIntValue().isSignedIntN(8)) 335 return false; 336 337 // If the other operand is a TLS address, we should fold it instead. 338 // This produces 339 // movl %gs:0, %eax 340 // leal i@NTPOFF(%eax), %eax 341 // instead of 342 // movl $i@NTPOFF, %eax 343 // addl %gs:0, %eax 344 // if the block also has an access to a second TLS address this will save 345 // a load. 346 // FIXME: This is probably also true for non TLS addresses. 347 if (Op1.getOpcode() == X86ISD::Wrapper) { 348 SDValue Val = Op1.getOperand(0); 349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress) 350 return false; 351 } 352 } 353 } 354 } 355 356 return true; 357} 358 359/// MoveBelowCallOrigChain - Replace the original chain operand of the call with 360/// load's chain operand and move load below the call's chain operand. 361static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load, 362 SDValue Call, SDValue OrigChain) { 363 SmallVector<SDValue, 8> Ops; 364 SDValue Chain = OrigChain.getOperand(0); 365 if (Chain.getNode() == Load.getNode()) 366 Ops.push_back(Load.getOperand(0)); 367 else { 368 assert(Chain.getOpcode() == ISD::TokenFactor && 369 "Unexpected chain operand"); 370 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) 371 if (Chain.getOperand(i).getNode() == Load.getNode()) 372 Ops.push_back(Load.getOperand(0)); 373 else 374 Ops.push_back(Chain.getOperand(i)); 375 SDValue NewChain = 376 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), 377 MVT::Other, &Ops[0], Ops.size()); 378 Ops.clear(); 379 Ops.push_back(NewChain); 380 } 381 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i) 382 Ops.push_back(OrigChain.getOperand(i)); 383 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size()); 384 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0), 385 Load.getOperand(1), Load.getOperand(2)); 386 387 unsigned NumOps = Call.getNode()->getNumOperands(); 388 Ops.clear(); 389 Ops.push_back(SDValue(Load.getNode(), 1)); 390 for (unsigned i = 1, e = NumOps; i != e; ++i) 391 Ops.push_back(Call.getOperand(i)); 392 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps); 393} 394 395/// isCalleeLoad - Return true if call address is a load and it can be 396/// moved below CALLSEQ_START and the chains leading up to the call. 397/// Return the CALLSEQ_START by reference as a second output. 398/// In the case of a tail call, there isn't a callseq node between the call 399/// chain and the load. 400static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) { 401 // The transformation is somewhat dangerous if the call's chain was glued to 402 // the call. After MoveBelowOrigChain the load is moved between the call and 403 // the chain, this can create a cycle if the load is not folded. So it is 404 // *really* important that we are sure the load will be folded. 405 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse()) 406 return false; 407 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode()); 408 if (!LD || 409 LD->isVolatile() || 410 LD->getAddressingMode() != ISD::UNINDEXED || 411 LD->getExtensionType() != ISD::NON_EXTLOAD) 412 return false; 413 414 // Now let's find the callseq_start. 415 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) { 416 if (!Chain.hasOneUse()) 417 return false; 418 Chain = Chain.getOperand(0); 419 } 420 421 if (!Chain.getNumOperands()) 422 return false; 423 // Since we are not checking for AA here, conservatively abort if the chain 424 // writes to memory. It's not safe to move the callee (a load) across a store. 425 if (isa<MemSDNode>(Chain.getNode()) && 426 cast<MemSDNode>(Chain.getNode())->writeMem()) 427 return false; 428 if (Chain.getOperand(0).getNode() == Callee.getNode()) 429 return true; 430 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor && 431 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) && 432 Callee.getValue(1).hasOneUse()) 433 return true; 434 return false; 435} 436 437void X86DAGToDAGISel::PreprocessISelDAG() { 438 // OptForSize is used in pattern predicates that isel is matching. 439 OptForSize = MF->getFunction()->getAttributes(). 440 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize); 441 442 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 443 E = CurDAG->allnodes_end(); I != E; ) { 444 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues. 445 446 if (OptLevel != CodeGenOpt::None && 447 // Only does this when target favors doesn't favor register indirect 448 // call. 449 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) || 450 (N->getOpcode() == X86ISD::TC_RETURN && 451 // Only does this if load can be folded into TC_RETURN. 452 (Subtarget->is64Bit() || 453 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) { 454 /// Also try moving call address load from outside callseq_start to just 455 /// before the call to allow it to be folded. 456 /// 457 /// [Load chain] 458 /// ^ 459 /// | 460 /// [Load] 461 /// ^ ^ 462 /// | | 463 /// / \-- 464 /// / | 465 ///[CALLSEQ_START] | 466 /// ^ | 467 /// | | 468 /// [LOAD/C2Reg] | 469 /// | | 470 /// \ / 471 /// \ / 472 /// [CALL] 473 bool HasCallSeq = N->getOpcode() == X86ISD::CALL; 474 SDValue Chain = N->getOperand(0); 475 SDValue Load = N->getOperand(1); 476 if (!isCalleeLoad(Load, Chain, HasCallSeq)) 477 continue; 478 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain); 479 ++NumLoadMoved; 480 continue; 481 } 482 483 // Lower fpround and fpextend nodes that target the FP stack to be store and 484 // load to the stack. This is a gross hack. We would like to simply mark 485 // these as being illegal, but when we do that, legalize produces these when 486 // it expands calls, then expands these in the same legalize pass. We would 487 // like dag combine to be able to hack on these between the call expansion 488 // and the node legalization. As such this pass basically does "really 489 // late" legalization of these inline with the X86 isel pass. 490 // FIXME: This should only happen when not compiled with -O0. 491 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) 492 continue; 493 494 EVT SrcVT = N->getOperand(0).getValueType(); 495 EVT DstVT = N->getValueType(0); 496 497 // If any of the sources are vectors, no fp stack involved. 498 if (SrcVT.isVector() || DstVT.isVector()) 499 continue; 500 501 // If the source and destination are SSE registers, then this is a legal 502 // conversion that should not be lowered. 503 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); 504 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); 505 if (SrcIsSSE && DstIsSSE) 506 continue; 507 508 if (!SrcIsSSE && !DstIsSSE) { 509 // If this is an FPStack extension, it is a noop. 510 if (N->getOpcode() == ISD::FP_EXTEND) 511 continue; 512 // If this is a value-preserving FPStack truncation, it is a noop. 513 if (N->getConstantOperandVal(1)) 514 continue; 515 } 516 517 // Here we could have an FP stack truncation or an FPStack <-> SSE convert. 518 // FPStack has extload and truncstore. SSE can fold direct loads into other 519 // operations. Based on this, decide what we want to do. 520 EVT MemVT; 521 if (N->getOpcode() == ISD::FP_ROUND) 522 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 523 else 524 MemVT = SrcIsSSE ? SrcVT : DstVT; 525 526 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); 527 DebugLoc dl = N->getDebugLoc(); 528 529 // FIXME: optimize the case where the src/dest is a load or store? 530 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, 531 N->getOperand(0), 532 MemTmp, MachinePointerInfo(), MemVT, 533 false, false, 0); 534 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, 535 MachinePointerInfo(), 536 MemVT, false, false, 0); 537 538 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the 539 // extload we created. This will cause general havok on the dag because 540 // anything below the conversion could be folded into other existing nodes. 541 // To avoid invalidating 'I', back it up to the convert node. 542 --I; 543 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 544 545 // Now that we did that, the node is dead. Increment the iterator to the 546 // next node to process, then delete N. 547 ++I; 548 CurDAG->DeleteNode(N); 549 } 550} 551 552 553/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in 554/// the main function. 555void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, 556 MachineFrameInfo *MFI) { 557 const TargetInstrInfo *TII = TM.getInstrInfo(); 558 if (Subtarget->isTargetCygMing()) { 559 unsigned CallOp = 560 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 561 BuildMI(BB, DebugLoc(), 562 TII->get(CallOp)).addExternalSymbol("__main"); 563 } 564} 565 566void X86DAGToDAGISel::EmitFunctionEntryCode() { 567 // If this is main, emit special code for main. 568 if (const Function *Fn = MF->getFunction()) 569 if (Fn->hasExternalLinkage() && Fn->getName() == "main") 570 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo()); 571} 572 573static bool isDispSafeForFrameIndex(int64_t Val) { 574 // On 64-bit platforms, we can run into an issue where a frame index 575 // includes a displacement that, when added to the explicit displacement, 576 // will overflow the displacement field. Assuming that the frame index 577 // displacement fits into a 31-bit integer (which is only slightly more 578 // aggressive than the current fundamental assumption that it fits into 579 // a 32-bit integer), a 31-bit disp should always be safe. 580 return isInt<31>(Val); 581} 582 583bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset, 584 X86ISelAddressMode &AM) { 585 int64_t Val = AM.Disp + Offset; 586 CodeModel::Model M = TM.getCodeModel(); 587 if (Subtarget->is64Bit()) { 588 if (!X86::isOffsetSuitableForCodeModel(Val, M, 589 AM.hasSymbolicDisplacement())) 590 return true; 591 // In addition to the checks required for a register base, check that 592 // we do not try to use an unsafe Disp with a frame index. 593 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase && 594 !isDispSafeForFrameIndex(Val)) 595 return true; 596 } 597 AM.Disp = Val; 598 return false; 599 600} 601 602bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){ 603 SDValue Address = N->getOperand(1); 604 605 // load gs:0 -> GS segment register. 606 // load fs:0 -> FS segment register. 607 // 608 // This optimization is valid because the GNU TLS model defines that 609 // gs:0 (or fs:0 on X86-64) contains its own address. 610 // For more information see http://people.redhat.com/drepper/tls.pdf 611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address)) 612 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 && 613 Subtarget->isTargetLinux()) 614 switch (N->getPointerInfo().getAddrSpace()) { 615 case 256: 616 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 617 return false; 618 case 257: 619 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 620 return false; 621 } 622 623 return true; 624} 625 626/// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes 627/// into an addressing mode. These wrap things that will resolve down into a 628/// symbol reference. If no match is possible, this returns true, otherwise it 629/// returns false. 630bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { 631 // If the addressing mode already has a symbol as the displacement, we can 632 // never match another symbol. 633 if (AM.hasSymbolicDisplacement()) 634 return true; 635 636 SDValue N0 = N.getOperand(0); 637 CodeModel::Model M = TM.getCodeModel(); 638 639 // Handle X86-64 rip-relative addresses. We check this before checking direct 640 // folding because RIP is preferable to non-RIP accesses. 641 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP && 642 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so 643 // they cannot be folded into immediate fields. 644 // FIXME: This can be improved for kernel and other models? 645 (M == CodeModel::Small || M == CodeModel::Kernel)) { 646 // Base and index reg must be 0 in order to use %rip as base. 647 if (AM.hasBaseOrIndexReg()) 648 return true; 649 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 650 X86ISelAddressMode Backup = AM; 651 AM.GV = G->getGlobal(); 652 AM.SymbolFlags = G->getTargetFlags(); 653 if (FoldOffsetIntoAddress(G->getOffset(), AM)) { 654 AM = Backup; 655 return true; 656 } 657 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 658 X86ISelAddressMode Backup = AM; 659 AM.CP = CP->getConstVal(); 660 AM.Align = CP->getAlignment(); 661 AM.SymbolFlags = CP->getTargetFlags(); 662 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) { 663 AM = Backup; 664 return true; 665 } 666 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 667 AM.ES = S->getSymbol(); 668 AM.SymbolFlags = S->getTargetFlags(); 669 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 670 AM.JT = J->getIndex(); 671 AM.SymbolFlags = J->getTargetFlags(); 672 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) { 673 X86ISelAddressMode Backup = AM; 674 AM.BlockAddr = BA->getBlockAddress(); 675 AM.SymbolFlags = BA->getTargetFlags(); 676 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) { 677 AM = Backup; 678 return true; 679 } 680 } else 681 llvm_unreachable("Unhandled symbol reference node."); 682 683 if (N.getOpcode() == X86ISD::WrapperRIP) 684 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); 685 return false; 686 } 687 688 // Handle the case when globals fit in our immediate field: This is true for 689 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit 690 // mode, this only applies to a non-RIP-relative computation. 691 if (!Subtarget->is64Bit() || 692 M == CodeModel::Small || M == CodeModel::Kernel) { 693 assert(N.getOpcode() != X86ISD::WrapperRIP && 694 "RIP-relative addressing already handled"); 695 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 696 AM.GV = G->getGlobal(); 697 AM.Disp += G->getOffset(); 698 AM.SymbolFlags = G->getTargetFlags(); 699 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 700 AM.CP = CP->getConstVal(); 701 AM.Align = CP->getAlignment(); 702 AM.Disp += CP->getOffset(); 703 AM.SymbolFlags = CP->getTargetFlags(); 704 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 705 AM.ES = S->getSymbol(); 706 AM.SymbolFlags = S->getTargetFlags(); 707 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 708 AM.JT = J->getIndex(); 709 AM.SymbolFlags = J->getTargetFlags(); 710 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) { 711 AM.BlockAddr = BA->getBlockAddress(); 712 AM.Disp += BA->getOffset(); 713 AM.SymbolFlags = BA->getTargetFlags(); 714 } else 715 llvm_unreachable("Unhandled symbol reference node."); 716 return false; 717 } 718 719 return true; 720} 721 722/// MatchAddress - Add the specified node to the specified addressing mode, 723/// returning true if it cannot be done. This just pattern matches for the 724/// addressing mode. 725bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) { 726 if (MatchAddressRecursively(N, AM, 0)) 727 return true; 728 729 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has 730 // a smaller encoding and avoids a scaled-index. 731 if (AM.Scale == 2 && 732 AM.BaseType == X86ISelAddressMode::RegBase && 733 AM.Base_Reg.getNode() == 0) { 734 AM.Base_Reg = AM.IndexReg; 735 AM.Scale = 1; 736 } 737 738 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode, 739 // because it has a smaller encoding. 740 // TODO: Which other code models can use this? 741 if (TM.getCodeModel() == CodeModel::Small && 742 Subtarget->is64Bit() && 743 AM.Scale == 1 && 744 AM.BaseType == X86ISelAddressMode::RegBase && 745 AM.Base_Reg.getNode() == 0 && 746 AM.IndexReg.getNode() == 0 && 747 AM.SymbolFlags == X86II::MO_NO_FLAG && 748 AM.hasSymbolicDisplacement()) 749 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); 750 751 return false; 752} 753 754// Insert a node into the DAG at least before the Pos node's position. This 755// will reposition the node as needed, and will assign it a node ID that is <= 756// the Pos node's ID. Note that this does *not* preserve the uniqueness of node 757// IDs! The selection DAG must no longer depend on their uniqueness when this 758// is used. 759static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) { 760 if (N.getNode()->getNodeId() == -1 || 761 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) { 762 DAG.RepositionNode(Pos.getNode(), N.getNode()); 763 N.getNode()->setNodeId(Pos.getNode()->getNodeId()); 764 } 765} 766 767// Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This 768// allows us to convert the shift and and into an h-register extract and 769// a scaled index. Returns false if the simplification is performed. 770static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N, 771 uint64_t Mask, 772 SDValue Shift, SDValue X, 773 X86ISelAddressMode &AM) { 774 if (Shift.getOpcode() != ISD::SRL || 775 !isa<ConstantSDNode>(Shift.getOperand(1)) || 776 !Shift.hasOneUse()) 777 return true; 778 779 int ScaleLog = 8 - Shift.getConstantOperandVal(1); 780 if (ScaleLog <= 0 || ScaleLog >= 4 || 781 Mask != (0xffu << ScaleLog)) 782 return true; 783 784 EVT VT = N.getValueType(); 785 DebugLoc DL = N.getDebugLoc(); 786 SDValue Eight = DAG.getConstant(8, MVT::i8); 787 SDValue NewMask = DAG.getConstant(0xff, VT); 788 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); 789 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); 790 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8); 791 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount); 792 793 // Insert the new nodes into the topological ordering. We must do this in 794 // a valid topological ordering as nothing is going to go back and re-sort 795 // these nodes. We continually insert before 'N' in sequence as this is 796 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no 797 // hierarchy left to express. 798 InsertDAGNode(DAG, N, Eight); 799 InsertDAGNode(DAG, N, Srl); 800 InsertDAGNode(DAG, N, NewMask); 801 InsertDAGNode(DAG, N, And); 802 InsertDAGNode(DAG, N, ShlCount); 803 InsertDAGNode(DAG, N, Shl); 804 DAG.ReplaceAllUsesWith(N, Shl); 805 AM.IndexReg = And; 806 AM.Scale = (1 << ScaleLog); 807 return false; 808} 809 810// Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this 811// allows us to fold the shift into this addressing mode. Returns false if the 812// transform succeeded. 813static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N, 814 uint64_t Mask, 815 SDValue Shift, SDValue X, 816 X86ISelAddressMode &AM) { 817 if (Shift.getOpcode() != ISD::SHL || 818 !isa<ConstantSDNode>(Shift.getOperand(1))) 819 return true; 820 821 // Not likely to be profitable if either the AND or SHIFT node has more 822 // than one use (unless all uses are for address computation). Besides, 823 // isel mechanism requires their node ids to be reused. 824 if (!N.hasOneUse() || !Shift.hasOneUse()) 825 return true; 826 827 // Verify that the shift amount is something we can fold. 828 unsigned ShiftAmt = Shift.getConstantOperandVal(1); 829 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) 830 return true; 831 832 EVT VT = N.getValueType(); 833 DebugLoc DL = N.getDebugLoc(); 834 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT); 835 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask); 836 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); 837 838 // Insert the new nodes into the topological ordering. We must do this in 839 // a valid topological ordering as nothing is going to go back and re-sort 840 // these nodes. We continually insert before 'N' in sequence as this is 841 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no 842 // hierarchy left to express. 843 InsertDAGNode(DAG, N, NewMask); 844 InsertDAGNode(DAG, N, NewAnd); 845 InsertDAGNode(DAG, N, NewShift); 846 DAG.ReplaceAllUsesWith(N, NewShift); 847 848 AM.Scale = 1 << ShiftAmt; 849 AM.IndexReg = NewAnd; 850 return false; 851} 852 853// Implement some heroics to detect shifts of masked values where the mask can 854// be replaced by extending the shift and undoing that in the addressing mode 855// scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and 856// (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in 857// the addressing mode. This results in code such as: 858// 859// int f(short *y, int *lookup_table) { 860// ... 861// return *y + lookup_table[*y >> 11]; 862// } 863// 864// Turning into: 865// movzwl (%rdi), %eax 866// movl %eax, %ecx 867// shrl $11, %ecx 868// addl (%rsi,%rcx,4), %eax 869// 870// Instead of: 871// movzwl (%rdi), %eax 872// movl %eax, %ecx 873// shrl $9, %ecx 874// andl $124, %rcx 875// addl (%rsi,%rcx), %eax 876// 877// Note that this function assumes the mask is provided as a mask *after* the 878// value is shifted. The input chain may or may not match that, but computing 879// such a mask is trivial. 880static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N, 881 uint64_t Mask, 882 SDValue Shift, SDValue X, 883 X86ISelAddressMode &AM) { 884 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || 885 !isa<ConstantSDNode>(Shift.getOperand(1))) 886 return true; 887 888 unsigned ShiftAmt = Shift.getConstantOperandVal(1); 889 unsigned MaskLZ = CountLeadingZeros_64(Mask); 890 unsigned MaskTZ = CountTrailingZeros_64(Mask); 891 892 // The amount of shift we're trying to fit into the addressing mode is taken 893 // from the trailing zeros of the mask. 894 unsigned AMShiftAmt = MaskTZ; 895 896 // There is nothing we can do here unless the mask is removing some bits. 897 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits. 898 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true; 899 900 // We also need to ensure that mask is a continuous run of bits. 901 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true; 902 903 // Scale the leading zero count down based on the actual size of the value. 904 // Also scale it down based on the size of the shift. 905 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt; 906 907 // The final check is to ensure that any masked out high bits of X are 908 // already known to be zero. Otherwise, the mask has a semantic impact 909 // other than masking out a couple of low bits. Unfortunately, because of 910 // the mask, zero extensions will be removed from operands in some cases. 911 // This code works extra hard to look through extensions because we can 912 // replace them with zero extensions cheaply if necessary. 913 bool ReplacingAnyExtend = false; 914 if (X.getOpcode() == ISD::ANY_EXTEND) { 915 unsigned ExtendBits = 916 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits(); 917 // Assume that we'll replace the any-extend with a zero-extend, and 918 // narrow the search to the extended value. 919 X = X.getOperand(0); 920 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits; 921 ReplacingAnyExtend = true; 922 } 923 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(), 924 MaskLZ); 925 APInt KnownZero, KnownOne; 926 DAG.ComputeMaskedBits(X, KnownZero, KnownOne); 927 if (MaskedHighBits != KnownZero) return true; 928 929 // We've identified a pattern that can be transformed into a single shift 930 // and an addressing mode. Make it so. 931 EVT VT = N.getValueType(); 932 if (ReplacingAnyExtend) { 933 assert(X.getValueType() != VT); 934 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND. 935 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X); 936 InsertDAGNode(DAG, N, NewX); 937 X = NewX; 938 } 939 DebugLoc DL = N.getDebugLoc(); 940 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8); 941 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); 942 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8); 943 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); 944 945 // Insert the new nodes into the topological ordering. We must do this in 946 // a valid topological ordering as nothing is going to go back and re-sort 947 // these nodes. We continually insert before 'N' in sequence as this is 948 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no 949 // hierarchy left to express. 950 InsertDAGNode(DAG, N, NewSRLAmt); 951 InsertDAGNode(DAG, N, NewSRL); 952 InsertDAGNode(DAG, N, NewSHLAmt); 953 InsertDAGNode(DAG, N, NewSHL); 954 DAG.ReplaceAllUsesWith(N, NewSHL); 955 956 AM.Scale = 1 << AMShiftAmt; 957 AM.IndexReg = NewSRL; 958 return false; 959} 960 961bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 962 unsigned Depth) { 963 DebugLoc dl = N.getDebugLoc(); 964 DEBUG({ 965 dbgs() << "MatchAddress: "; 966 AM.dump(); 967 }); 968 // Limit recursion. 969 if (Depth > 5) 970 return MatchAddressBase(N, AM); 971 972 // If this is already a %rip relative address, we can only merge immediates 973 // into it. Instead of handling this in every case, we handle it here. 974 // RIP relative addressing: %rip + 32-bit displacement! 975 if (AM.isRIPRelative()) { 976 // FIXME: JumpTable and ExternalSymbol address currently don't like 977 // displacements. It isn't very important, but this should be fixed for 978 // consistency. 979 if (!AM.ES && AM.JT != -1) return true; 980 981 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) 982 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM)) 983 return false; 984 return true; 985 } 986 987 switch (N.getOpcode()) { 988 default: break; 989 case ISD::Constant: { 990 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 991 if (!FoldOffsetIntoAddress(Val, AM)) 992 return false; 993 break; 994 } 995 996 case X86ISD::Wrapper: 997 case X86ISD::WrapperRIP: 998 if (!MatchWrapper(N, AM)) 999 return false; 1000 break; 1001 1002 case ISD::LOAD: 1003 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM)) 1004 return false; 1005 break; 1006 1007 case ISD::FrameIndex: 1008 if (AM.BaseType == X86ISelAddressMode::RegBase && 1009 AM.Base_Reg.getNode() == 0 && 1010 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) { 1011 AM.BaseType = X86ISelAddressMode::FrameIndexBase; 1012 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 1013 return false; 1014 } 1015 break; 1016 1017 case ISD::SHL: 1018 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) 1019 break; 1020 1021 if (ConstantSDNode 1022 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) { 1023 unsigned Val = CN->getZExtValue(); 1024 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so 1025 // that the base operand remains free for further matching. If 1026 // the base doesn't end up getting used, a post-processing step 1027 // in MatchAddress turns (,x,2) into (x,x), which is cheaper. 1028 if (Val == 1 || Val == 2 || Val == 3) { 1029 AM.Scale = 1 << Val; 1030 SDValue ShVal = N.getNode()->getOperand(0); 1031 1032 // Okay, we know that we have a scale by now. However, if the scaled 1033 // value is an add of something and a constant, we can fold the 1034 // constant into the disp field here. 1035 if (CurDAG->isBaseWithConstantOffset(ShVal)) { 1036 AM.IndexReg = ShVal.getNode()->getOperand(0); 1037 ConstantSDNode *AddVal = 1038 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1)); 1039 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val; 1040 if (!FoldOffsetIntoAddress(Disp, AM)) 1041 return false; 1042 } 1043 1044 AM.IndexReg = ShVal; 1045 return false; 1046 } 1047 } 1048 break; 1049 1050 case ISD::SRL: { 1051 // Scale must not be used already. 1052 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break; 1053 1054 SDValue And = N.getOperand(0); 1055 if (And.getOpcode() != ISD::AND) break; 1056 SDValue X = And.getOperand(0); 1057 1058 // We only handle up to 64-bit values here as those are what matter for 1059 // addressing mode optimizations. 1060 if (X.getValueSizeInBits() > 64) break; 1061 1062 // The mask used for the transform is expected to be post-shift, but we 1063 // found the shift first so just apply the shift to the mask before passing 1064 // it down. 1065 if (!isa<ConstantSDNode>(N.getOperand(1)) || 1066 !isa<ConstantSDNode>(And.getOperand(1))) 1067 break; 1068 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1); 1069 1070 // Try to fold the mask and shift into the scale, and return false if we 1071 // succeed. 1072 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM)) 1073 return false; 1074 break; 1075 } 1076 1077 case ISD::SMUL_LOHI: 1078 case ISD::UMUL_LOHI: 1079 // A mul_lohi where we need the low part can be folded as a plain multiply. 1080 if (N.getResNo() != 0) break; 1081 // FALL THROUGH 1082 case ISD::MUL: 1083 case X86ISD::MUL_IMM: 1084 // X*[3,5,9] -> X+X*[2,4,8] 1085 if (AM.BaseType == X86ISelAddressMode::RegBase && 1086 AM.Base_Reg.getNode() == 0 && 1087 AM.IndexReg.getNode() == 0) { 1088 if (ConstantSDNode 1089 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) 1090 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 || 1091 CN->getZExtValue() == 9) { 1092 AM.Scale = unsigned(CN->getZExtValue())-1; 1093 1094 SDValue MulVal = N.getNode()->getOperand(0); 1095 SDValue Reg; 1096 1097 // Okay, we know that we have a scale by now. However, if the scaled 1098 // value is an add of something and a constant, we can fold the 1099 // constant into the disp field here. 1100 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && 1101 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) { 1102 Reg = MulVal.getNode()->getOperand(0); 1103 ConstantSDNode *AddVal = 1104 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1)); 1105 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue(); 1106 if (FoldOffsetIntoAddress(Disp, AM)) 1107 Reg = N.getNode()->getOperand(0); 1108 } else { 1109 Reg = N.getNode()->getOperand(0); 1110 } 1111 1112 AM.IndexReg = AM.Base_Reg = Reg; 1113 return false; 1114 } 1115 } 1116 break; 1117 1118 case ISD::SUB: { 1119 // Given A-B, if A can be completely folded into the address and 1120 // the index field with the index field unused, use -B as the index. 1121 // This is a win if a has multiple parts that can be folded into 1122 // the address. Also, this saves a mov if the base register has 1123 // other uses, since it avoids a two-address sub instruction, however 1124 // it costs an additional mov if the index register has other uses. 1125 1126 // Add an artificial use to this node so that we can keep track of 1127 // it if it gets CSE'd with a different node. 1128 HandleSDNode Handle(N); 1129 1130 // Test if the LHS of the sub can be folded. 1131 X86ISelAddressMode Backup = AM; 1132 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) { 1133 AM = Backup; 1134 break; 1135 } 1136 // Test if the index field is free for use. 1137 if (AM.IndexReg.getNode() || AM.isRIPRelative()) { 1138 AM = Backup; 1139 break; 1140 } 1141 1142 int Cost = 0; 1143 SDValue RHS = Handle.getValue().getNode()->getOperand(1); 1144 // If the RHS involves a register with multiple uses, this 1145 // transformation incurs an extra mov, due to the neg instruction 1146 // clobbering its operand. 1147 if (!RHS.getNode()->hasOneUse() || 1148 RHS.getNode()->getOpcode() == ISD::CopyFromReg || 1149 RHS.getNode()->getOpcode() == ISD::TRUNCATE || 1150 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || 1151 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && 1152 RHS.getNode()->getOperand(0).getValueType() == MVT::i32)) 1153 ++Cost; 1154 // If the base is a register with multiple uses, this 1155 // transformation may save a mov. 1156 if ((AM.BaseType == X86ISelAddressMode::RegBase && 1157 AM.Base_Reg.getNode() && 1158 !AM.Base_Reg.getNode()->hasOneUse()) || 1159 AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1160 --Cost; 1161 // If the folded LHS was interesting, this transformation saves 1162 // address arithmetic. 1163 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) + 1164 ((AM.Disp != 0) && (Backup.Disp == 0)) + 1165 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2) 1166 --Cost; 1167 // If it doesn't look like it may be an overall win, don't do it. 1168 if (Cost >= 0) { 1169 AM = Backup; 1170 break; 1171 } 1172 1173 // Ok, the transformation is legal and appears profitable. Go for it. 1174 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 1175 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 1176 AM.IndexReg = Neg; 1177 AM.Scale = 1; 1178 1179 // Insert the new nodes into the topological ordering. 1180 InsertDAGNode(*CurDAG, N, Zero); 1181 InsertDAGNode(*CurDAG, N, Neg); 1182 return false; 1183 } 1184 1185 case ISD::ADD: { 1186 // Add an artificial use to this node so that we can keep track of 1187 // it if it gets CSE'd with a different node. 1188 HandleSDNode Handle(N); 1189 1190 X86ISelAddressMode Backup = AM; 1191 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 1192 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)) 1193 return false; 1194 AM = Backup; 1195 1196 // Try again after commuting the operands. 1197 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&& 1198 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1)) 1199 return false; 1200 AM = Backup; 1201 1202 // If we couldn't fold both operands into the address at the same time, 1203 // see if we can just put each operand into a register and fold at least 1204 // the add. 1205 if (AM.BaseType == X86ISelAddressMode::RegBase && 1206 !AM.Base_Reg.getNode() && 1207 !AM.IndexReg.getNode()) { 1208 N = Handle.getValue(); 1209 AM.Base_Reg = N.getOperand(0); 1210 AM.IndexReg = N.getOperand(1); 1211 AM.Scale = 1; 1212 return false; 1213 } 1214 N = Handle.getValue(); 1215 break; 1216 } 1217 1218 case ISD::OR: 1219 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 1220 if (CurDAG->isBaseWithConstantOffset(N)) { 1221 X86ISelAddressMode Backup = AM; 1222 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1)); 1223 1224 // Start with the LHS as an addr mode. 1225 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 1226 !FoldOffsetIntoAddress(CN->getSExtValue(), AM)) 1227 return false; 1228 AM = Backup; 1229 } 1230 break; 1231 1232 case ISD::AND: { 1233 // Perform some heroic transforms on an and of a constant-count shift 1234 // with a constant to enable use of the scaled offset field. 1235 1236 // Scale must not be used already. 1237 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break; 1238 1239 SDValue Shift = N.getOperand(0); 1240 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break; 1241 SDValue X = Shift.getOperand(0); 1242 1243 // We only handle up to 64-bit values here as those are what matter for 1244 // addressing mode optimizations. 1245 if (X.getValueSizeInBits() > 64) break; 1246 1247 if (!isa<ConstantSDNode>(N.getOperand(1))) 1248 break; 1249 uint64_t Mask = N.getConstantOperandVal(1); 1250 1251 // Try to fold the mask and shift into an extract and scale. 1252 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM)) 1253 return false; 1254 1255 // Try to fold the mask and shift directly into the scale. 1256 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM)) 1257 return false; 1258 1259 // Try to swap the mask and shift to place shifts which can be done as 1260 // a scale on the outside of the mask. 1261 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM)) 1262 return false; 1263 break; 1264 } 1265 } 1266 1267 return MatchAddressBase(N, AM); 1268} 1269 1270/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 1271/// specified addressing mode without any further recursion. 1272bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) { 1273 // Is the base register already occupied? 1274 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) { 1275 // If so, check to see if the scale index register is set. 1276 if (AM.IndexReg.getNode() == 0) { 1277 AM.IndexReg = N; 1278 AM.Scale = 1; 1279 return false; 1280 } 1281 1282 // Otherwise, we cannot select it. 1283 return true; 1284 } 1285 1286 // Default, generate it as a register. 1287 AM.BaseType = X86ISelAddressMode::RegBase; 1288 AM.Base_Reg = N; 1289 return false; 1290} 1291 1292/// SelectAddr - returns true if it is able pattern match an addressing mode. 1293/// It returns the operands which make up the maximal addressing mode it can 1294/// match by reference. 1295/// 1296/// Parent is the parent node of the addr operand that is being matched. It 1297/// is always a load, store, atomic node, or null. It is only null when 1298/// checking memory operands for inline asm nodes. 1299bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, 1300 SDValue &Scale, SDValue &Index, 1301 SDValue &Disp, SDValue &Segment) { 1302 X86ISelAddressMode AM; 1303 1304 if (Parent && 1305 // This list of opcodes are all the nodes that have an "addr:$ptr" operand 1306 // that are not a MemSDNode, and thus don't have proper addrspace info. 1307 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme 1308 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores 1309 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme 1310 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp 1311 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp 1312 unsigned AddrSpace = 1313 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace(); 1314 // AddrSpace 256 -> GS, 257 -> FS. 1315 if (AddrSpace == 256) 1316 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 1317 if (AddrSpace == 257) 1318 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 1319 } 1320 1321 if (MatchAddress(N, AM)) 1322 return false; 1323 1324 EVT VT = N.getValueType(); 1325 if (AM.BaseType == X86ISelAddressMode::RegBase) { 1326 if (!AM.Base_Reg.getNode()) 1327 AM.Base_Reg = CurDAG->getRegister(0, VT); 1328 } 1329 1330 if (!AM.IndexReg.getNode()) 1331 AM.IndexReg = CurDAG->getRegister(0, VT); 1332 1333 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1334 return true; 1335} 1336 1337/// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to 1338/// match a load whose top elements are either undef or zeros. The load flavor 1339/// is derived from the type of N, which is either v4f32 or v2f64. 1340/// 1341/// We also return: 1342/// PatternChainNode: this is the matched node that has a chain input and 1343/// output. 1344bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root, 1345 SDValue N, SDValue &Base, 1346 SDValue &Scale, SDValue &Index, 1347 SDValue &Disp, SDValue &Segment, 1348 SDValue &PatternNodeWithChain) { 1349 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { 1350 PatternNodeWithChain = N.getOperand(0); 1351 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) && 1352 PatternNodeWithChain.hasOneUse() && 1353 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && 1354 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) { 1355 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain); 1356 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1357 return false; 1358 return true; 1359 } 1360 } 1361 1362 // Also handle the case where we explicitly require zeros in the top 1363 // elements. This is a vector shuffle from the zero vector. 1364 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() && 1365 // Check to see if the top elements are all zeros (or bitcast of zeros). 1366 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 1367 N.getOperand(0).getNode()->hasOneUse() && 1368 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) && 1369 N.getOperand(0).getOperand(0).hasOneUse() && 1370 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && 1371 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) { 1372 // Okay, this is a zero extending load. Fold it. 1373 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0)); 1374 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1375 return false; 1376 PatternNodeWithChain = SDValue(LD, 0); 1377 return true; 1378 } 1379 return false; 1380} 1381 1382 1383/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing 1384/// mode it matches can be cost effectively emitted as an LEA instruction. 1385bool X86DAGToDAGISel::SelectLEAAddr(SDValue N, 1386 SDValue &Base, SDValue &Scale, 1387 SDValue &Index, SDValue &Disp, 1388 SDValue &Segment) { 1389 X86ISelAddressMode AM; 1390 1391 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support 1392 // segments. 1393 SDValue Copy = AM.Segment; 1394 SDValue T = CurDAG->getRegister(0, MVT::i32); 1395 AM.Segment = T; 1396 if (MatchAddress(N, AM)) 1397 return false; 1398 assert (T == AM.Segment); 1399 AM.Segment = Copy; 1400 1401 EVT VT = N.getValueType(); 1402 unsigned Complexity = 0; 1403 if (AM.BaseType == X86ISelAddressMode::RegBase) 1404 if (AM.Base_Reg.getNode()) 1405 Complexity = 1; 1406 else 1407 AM.Base_Reg = CurDAG->getRegister(0, VT); 1408 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1409 Complexity = 4; 1410 1411 if (AM.IndexReg.getNode()) 1412 Complexity++; 1413 else 1414 AM.IndexReg = CurDAG->getRegister(0, VT); 1415 1416 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with 1417 // a simple shift. 1418 if (AM.Scale > 1) 1419 Complexity++; 1420 1421 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA 1422 // to a LEA. This is determined with some expermentation but is by no means 1423 // optimal (especially for code size consideration). LEA is nice because of 1424 // its three-address nature. Tweak the cost function again when we can run 1425 // convertToThreeAddress() at register allocation time. 1426 if (AM.hasSymbolicDisplacement()) { 1427 // For X86-64, we should always use lea to materialize RIP relative 1428 // addresses. 1429 if (Subtarget->is64Bit()) 1430 Complexity = 4; 1431 else 1432 Complexity += 2; 1433 } 1434 1435 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode())) 1436 Complexity++; 1437 1438 // If it isn't worth using an LEA, reject it. 1439 if (Complexity <= 2) 1440 return false; 1441 1442 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1443 return true; 1444} 1445 1446/// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes. 1447bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base, 1448 SDValue &Scale, SDValue &Index, 1449 SDValue &Disp, SDValue &Segment) { 1450 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress); 1451 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 1452 1453 X86ISelAddressMode AM; 1454 AM.GV = GA->getGlobal(); 1455 AM.Disp += GA->getOffset(); 1456 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType()); 1457 AM.SymbolFlags = GA->getTargetFlags(); 1458 1459 if (N.getValueType() == MVT::i32) { 1460 AM.Scale = 1; 1461 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32); 1462 } else { 1463 AM.IndexReg = CurDAG->getRegister(0, MVT::i64); 1464 } 1465 1466 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1467 return true; 1468} 1469 1470 1471bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, 1472 SDValue &Base, SDValue &Scale, 1473 SDValue &Index, SDValue &Disp, 1474 SDValue &Segment) { 1475 if (!ISD::isNON_EXTLoad(N.getNode()) || 1476 !IsProfitableToFold(N, P, P) || 1477 !IsLegalToFold(N, P, P, OptLevel)) 1478 return false; 1479 1480 return SelectAddr(N.getNode(), 1481 N.getOperand(1), Base, Scale, Index, Disp, Segment); 1482} 1483 1484/// getGlobalBaseReg - Return an SDNode that returns the value of 1485/// the global base register. Output instructions required to 1486/// initialize the global base register, if necessary. 1487/// 1488SDNode *X86DAGToDAGISel::getGlobalBaseReg() { 1489 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF); 1490 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 1491} 1492 1493SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { 1494 SDValue Chain = Node->getOperand(0); 1495 SDValue In1 = Node->getOperand(1); 1496 SDValue In2L = Node->getOperand(2); 1497 SDValue In2H = Node->getOperand(3); 1498 1499 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1500 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1501 return NULL; 1502 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1503 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1504 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; 1505 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 1506 MVT::i32, MVT::i32, MVT::Other, Ops); 1507 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1); 1508 return ResNode; 1509} 1510 1511/// Atomic opcode table 1512/// 1513enum AtomicOpc { 1514 ADD, 1515 SUB, 1516 INC, 1517 DEC, 1518 OR, 1519 AND, 1520 XOR, 1521 AtomicOpcEnd 1522}; 1523 1524enum AtomicSz { 1525 ConstantI8, 1526 I8, 1527 SextConstantI16, 1528 ConstantI16, 1529 I16, 1530 SextConstantI32, 1531 ConstantI32, 1532 I32, 1533 SextConstantI64, 1534 ConstantI64, 1535 I64, 1536 AtomicSzEnd 1537}; 1538 1539static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = { 1540 { 1541 X86::LOCK_ADD8mi, 1542 X86::LOCK_ADD8mr, 1543 X86::LOCK_ADD16mi8, 1544 X86::LOCK_ADD16mi, 1545 X86::LOCK_ADD16mr, 1546 X86::LOCK_ADD32mi8, 1547 X86::LOCK_ADD32mi, 1548 X86::LOCK_ADD32mr, 1549 X86::LOCK_ADD64mi8, 1550 X86::LOCK_ADD64mi32, 1551 X86::LOCK_ADD64mr, 1552 }, 1553 { 1554 X86::LOCK_SUB8mi, 1555 X86::LOCK_SUB8mr, 1556 X86::LOCK_SUB16mi8, 1557 X86::LOCK_SUB16mi, 1558 X86::LOCK_SUB16mr, 1559 X86::LOCK_SUB32mi8, 1560 X86::LOCK_SUB32mi, 1561 X86::LOCK_SUB32mr, 1562 X86::LOCK_SUB64mi8, 1563 X86::LOCK_SUB64mi32, 1564 X86::LOCK_SUB64mr, 1565 }, 1566 { 1567 0, 1568 X86::LOCK_INC8m, 1569 0, 1570 0, 1571 X86::LOCK_INC16m, 1572 0, 1573 0, 1574 X86::LOCK_INC32m, 1575 0, 1576 0, 1577 X86::LOCK_INC64m, 1578 }, 1579 { 1580 0, 1581 X86::LOCK_DEC8m, 1582 0, 1583 0, 1584 X86::LOCK_DEC16m, 1585 0, 1586 0, 1587 X86::LOCK_DEC32m, 1588 0, 1589 0, 1590 X86::LOCK_DEC64m, 1591 }, 1592 { 1593 X86::LOCK_OR8mi, 1594 X86::LOCK_OR8mr, 1595 X86::LOCK_OR16mi8, 1596 X86::LOCK_OR16mi, 1597 X86::LOCK_OR16mr, 1598 X86::LOCK_OR32mi8, 1599 X86::LOCK_OR32mi, 1600 X86::LOCK_OR32mr, 1601 X86::LOCK_OR64mi8, 1602 X86::LOCK_OR64mi32, 1603 X86::LOCK_OR64mr, 1604 }, 1605 { 1606 X86::LOCK_AND8mi, 1607 X86::LOCK_AND8mr, 1608 X86::LOCK_AND16mi8, 1609 X86::LOCK_AND16mi, 1610 X86::LOCK_AND16mr, 1611 X86::LOCK_AND32mi8, 1612 X86::LOCK_AND32mi, 1613 X86::LOCK_AND32mr, 1614 X86::LOCK_AND64mi8, 1615 X86::LOCK_AND64mi32, 1616 X86::LOCK_AND64mr, 1617 }, 1618 { 1619 X86::LOCK_XOR8mi, 1620 X86::LOCK_XOR8mr, 1621 X86::LOCK_XOR16mi8, 1622 X86::LOCK_XOR16mi, 1623 X86::LOCK_XOR16mr, 1624 X86::LOCK_XOR32mi8, 1625 X86::LOCK_XOR32mi, 1626 X86::LOCK_XOR32mr, 1627 X86::LOCK_XOR64mi8, 1628 X86::LOCK_XOR64mi32, 1629 X86::LOCK_XOR64mr, 1630 } 1631}; 1632 1633// Return the target constant operand for atomic-load-op and do simple 1634// translations, such as from atomic-load-add to lock-sub. The return value is 1635// one of the following 3 cases: 1636// + target-constant, the operand could be supported as a target constant. 1637// + empty, the operand is not needed any more with the new op selected. 1638// + non-empty, otherwise. 1639static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG, 1640 DebugLoc dl, 1641 enum AtomicOpc &Op, EVT NVT, 1642 SDValue Val) { 1643 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) { 1644 int64_t CNVal = CN->getSExtValue(); 1645 // Quit if not 32-bit imm. 1646 if ((int32_t)CNVal != CNVal) 1647 return Val; 1648 // For atomic-load-add, we could do some optimizations. 1649 if (Op == ADD) { 1650 // Translate to INC/DEC if ADD by 1 or -1. 1651 if ((CNVal == 1) || (CNVal == -1)) { 1652 Op = (CNVal == 1) ? INC : DEC; 1653 // No more constant operand after being translated into INC/DEC. 1654 return SDValue(); 1655 } 1656 // Translate to SUB if ADD by negative value. 1657 if (CNVal < 0) { 1658 Op = SUB; 1659 CNVal = -CNVal; 1660 } 1661 } 1662 return CurDAG->getTargetConstant(CNVal, NVT); 1663 } 1664 1665 // If the value operand is single-used, try to optimize it. 1666 if (Op == ADD && Val.hasOneUse()) { 1667 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x). 1668 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) { 1669 Op = SUB; 1670 return Val.getOperand(1); 1671 } 1672 // A special case for i16, which needs truncating as, in most cases, it's 1673 // promoted to i32. We will translate 1674 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x)) 1675 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 && 1676 Val.getOperand(0).getOpcode() == ISD::SUB && 1677 X86::isZeroNode(Val.getOperand(0).getOperand(0))) { 1678 Op = SUB; 1679 Val = Val.getOperand(0); 1680 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT, 1681 Val.getOperand(1)); 1682 } 1683 } 1684 1685 return Val; 1686} 1687 1688SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) { 1689 if (Node->hasAnyUseOfValue(0)) 1690 return 0; 1691 1692 DebugLoc dl = Node->getDebugLoc(); 1693 1694 // Optimize common patterns for __sync_or_and_fetch and similar arith 1695 // operations where the result is not used. This allows us to use the "lock" 1696 // version of the arithmetic instruction. 1697 SDValue Chain = Node->getOperand(0); 1698 SDValue Ptr = Node->getOperand(1); 1699 SDValue Val = Node->getOperand(2); 1700 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1701 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1702 return 0; 1703 1704 // Which index into the table. 1705 enum AtomicOpc Op; 1706 switch (Node->getOpcode()) { 1707 default: 1708 return 0; 1709 case ISD::ATOMIC_LOAD_OR: 1710 Op = OR; 1711 break; 1712 case ISD::ATOMIC_LOAD_AND: 1713 Op = AND; 1714 break; 1715 case ISD::ATOMIC_LOAD_XOR: 1716 Op = XOR; 1717 break; 1718 case ISD::ATOMIC_LOAD_ADD: 1719 Op = ADD; 1720 break; 1721 } 1722 1723 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val); 1724 bool isUnOp = !Val.getNode(); 1725 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant); 1726 1727 unsigned Opc = 0; 1728 switch (NVT.getSimpleVT().SimpleTy) { 1729 default: return 0; 1730 case MVT::i8: 1731 if (isCN) 1732 Opc = AtomicOpcTbl[Op][ConstantI8]; 1733 else 1734 Opc = AtomicOpcTbl[Op][I8]; 1735 break; 1736 case MVT::i16: 1737 if (isCN) { 1738 if (immSext8(Val.getNode())) 1739 Opc = AtomicOpcTbl[Op][SextConstantI16]; 1740 else 1741 Opc = AtomicOpcTbl[Op][ConstantI16]; 1742 } else 1743 Opc = AtomicOpcTbl[Op][I16]; 1744 break; 1745 case MVT::i32: 1746 if (isCN) { 1747 if (immSext8(Val.getNode())) 1748 Opc = AtomicOpcTbl[Op][SextConstantI32]; 1749 else 1750 Opc = AtomicOpcTbl[Op][ConstantI32]; 1751 } else 1752 Opc = AtomicOpcTbl[Op][I32]; 1753 break; 1754 case MVT::i64: 1755 Opc = AtomicOpcTbl[Op][I64]; 1756 if (isCN) { 1757 if (immSext8(Val.getNode())) 1758 Opc = AtomicOpcTbl[Op][SextConstantI64]; 1759 else if (i64immSExt32(Val.getNode())) 1760 Opc = AtomicOpcTbl[Op][ConstantI64]; 1761 } 1762 break; 1763 } 1764 1765 assert(Opc != 0 && "Invalid arith lock transform!"); 1766 1767 SDValue Ret; 1768 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1769 dl, NVT), 0); 1770 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1771 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1772 if (isUnOp) { 1773 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; 1774 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0); 1775 } else { 1776 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; 1777 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0); 1778 } 1779 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1780 SDValue RetVals[] = { Undef, Ret }; 1781 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1782} 1783 1784/// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has 1785/// any uses which require the SF or OF bits to be accurate. 1786static bool HasNoSignedComparisonUses(SDNode *N) { 1787 // Examine each user of the node. 1788 for (SDNode::use_iterator UI = N->use_begin(), 1789 UE = N->use_end(); UI != UE; ++UI) { 1790 // Only examine CopyToReg uses. 1791 if (UI->getOpcode() != ISD::CopyToReg) 1792 return false; 1793 // Only examine CopyToReg uses that copy to EFLAGS. 1794 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() != 1795 X86::EFLAGS) 1796 return false; 1797 // Examine each user of the CopyToReg use. 1798 for (SDNode::use_iterator FlagUI = UI->use_begin(), 1799 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) { 1800 // Only examine the Flag result. 1801 if (FlagUI.getUse().getResNo() != 1) continue; 1802 // Anything unusual: assume conservatively. 1803 if (!FlagUI->isMachineOpcode()) return false; 1804 // Examine the opcode of the user. 1805 switch (FlagUI->getMachineOpcode()) { 1806 // These comparisons don't treat the most significant bit specially. 1807 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr: 1808 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr: 1809 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm: 1810 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm: 1811 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4: 1812 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4: 1813 case X86::CMOVA16rr: case X86::CMOVA16rm: 1814 case X86::CMOVA32rr: case X86::CMOVA32rm: 1815 case X86::CMOVA64rr: case X86::CMOVA64rm: 1816 case X86::CMOVAE16rr: case X86::CMOVAE16rm: 1817 case X86::CMOVAE32rr: case X86::CMOVAE32rm: 1818 case X86::CMOVAE64rr: case X86::CMOVAE64rm: 1819 case X86::CMOVB16rr: case X86::CMOVB16rm: 1820 case X86::CMOVB32rr: case X86::CMOVB32rm: 1821 case X86::CMOVB64rr: case X86::CMOVB64rm: 1822 case X86::CMOVBE16rr: case X86::CMOVBE16rm: 1823 case X86::CMOVBE32rr: case X86::CMOVBE32rm: 1824 case X86::CMOVBE64rr: case X86::CMOVBE64rm: 1825 case X86::CMOVE16rr: case X86::CMOVE16rm: 1826 case X86::CMOVE32rr: case X86::CMOVE32rm: 1827 case X86::CMOVE64rr: case X86::CMOVE64rm: 1828 case X86::CMOVNE16rr: case X86::CMOVNE16rm: 1829 case X86::CMOVNE32rr: case X86::CMOVNE32rm: 1830 case X86::CMOVNE64rr: case X86::CMOVNE64rm: 1831 case X86::CMOVNP16rr: case X86::CMOVNP16rm: 1832 case X86::CMOVNP32rr: case X86::CMOVNP32rm: 1833 case X86::CMOVNP64rr: case X86::CMOVNP64rm: 1834 case X86::CMOVP16rr: case X86::CMOVP16rm: 1835 case X86::CMOVP32rr: case X86::CMOVP32rm: 1836 case X86::CMOVP64rr: case X86::CMOVP64rm: 1837 continue; 1838 // Anything else: assume conservatively. 1839 default: return false; 1840 } 1841 } 1842 } 1843 return true; 1844} 1845 1846/// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode 1847/// is suitable for doing the {load; increment or decrement; store} to modify 1848/// transformation. 1849static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc, 1850 SDValue StoredVal, SelectionDAG *CurDAG, 1851 LoadSDNode* &LoadNode, SDValue &InputChain) { 1852 1853 // is the value stored the result of a DEC or INC? 1854 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false; 1855 1856 // is the stored value result 0 of the load? 1857 if (StoredVal.getResNo() != 0) return false; 1858 1859 // are there other uses of the loaded value than the inc or dec? 1860 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false; 1861 1862 // is the store non-extending and non-indexed? 1863 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal()) 1864 return false; 1865 1866 SDValue Load = StoredVal->getOperand(0); 1867 // Is the stored value a non-extending and non-indexed load? 1868 if (!ISD::isNormalLoad(Load.getNode())) return false; 1869 1870 // Return LoadNode by reference. 1871 LoadNode = cast<LoadSDNode>(Load); 1872 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8) 1873 EVT LdVT = LoadNode->getMemoryVT(); 1874 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 && 1875 LdVT != MVT::i8) 1876 return false; 1877 1878 // Is store the only read of the loaded value? 1879 if (!Load.hasOneUse()) 1880 return false; 1881 1882 // Is the address of the store the same as the load? 1883 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || 1884 LoadNode->getOffset() != StoreNode->getOffset()) 1885 return false; 1886 1887 // Check if the chain is produced by the load or is a TokenFactor with 1888 // the load output chain as an operand. Return InputChain by reference. 1889 SDValue Chain = StoreNode->getChain(); 1890 1891 bool ChainCheck = false; 1892 if (Chain == Load.getValue(1)) { 1893 ChainCheck = true; 1894 InputChain = LoadNode->getChain(); 1895 } else if (Chain.getOpcode() == ISD::TokenFactor) { 1896 SmallVector<SDValue, 4> ChainOps; 1897 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) { 1898 SDValue Op = Chain.getOperand(i); 1899 if (Op == Load.getValue(1)) { 1900 ChainCheck = true; 1901 continue; 1902 } 1903 1904 // Make sure using Op as part of the chain would not cause a cycle here. 1905 // In theory, we could check whether the chain node is a predecessor of 1906 // the load. But that can be very expensive. Instead visit the uses and 1907 // make sure they all have smaller node id than the load. 1908 int LoadId = LoadNode->getNodeId(); 1909 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 1910 UE = UI->use_end(); UI != UE; ++UI) { 1911 if (UI.getUse().getResNo() != 0) 1912 continue; 1913 if (UI->getNodeId() > LoadId) 1914 return false; 1915 } 1916 1917 ChainOps.push_back(Op); 1918 } 1919 1920 if (ChainCheck) 1921 // Make a new TokenFactor with all the other input chains except 1922 // for the load. 1923 InputChain = CurDAG->getNode(ISD::TokenFactor, Chain.getDebugLoc(), 1924 MVT::Other, &ChainOps[0], ChainOps.size()); 1925 } 1926 if (!ChainCheck) 1927 return false; 1928 1929 return true; 1930} 1931 1932/// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory 1933/// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC. 1934static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) { 1935 if (Opc == X86ISD::DEC) { 1936 if (LdVT == MVT::i64) return X86::DEC64m; 1937 if (LdVT == MVT::i32) return X86::DEC32m; 1938 if (LdVT == MVT::i16) return X86::DEC16m; 1939 if (LdVT == MVT::i8) return X86::DEC8m; 1940 } else { 1941 assert(Opc == X86ISD::INC && "unrecognized opcode"); 1942 if (LdVT == MVT::i64) return X86::INC64m; 1943 if (LdVT == MVT::i32) return X86::INC32m; 1944 if (LdVT == MVT::i16) return X86::INC16m; 1945 if (LdVT == MVT::i8) return X86::INC8m; 1946 } 1947 llvm_unreachable("unrecognized size for LdVT"); 1948} 1949 1950/// SelectGather - Customized ISel for GATHER operations. 1951/// 1952SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) { 1953 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale 1954 SDValue Chain = Node->getOperand(0); 1955 SDValue VSrc = Node->getOperand(2); 1956 SDValue Base = Node->getOperand(3); 1957 SDValue VIdx = Node->getOperand(4); 1958 SDValue VMask = Node->getOperand(5); 1959 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6)); 1960 if (!Scale) 1961 return 0; 1962 1963 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(), 1964 MVT::Other); 1965 1966 // Memory Operands: Base, Scale, Index, Disp, Segment 1967 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32); 1968 SDValue Segment = CurDAG->getRegister(0, MVT::i32); 1969 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx, 1970 Disp, Segment, VMask, Chain}; 1971 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), VTs, Ops); 1972 // Node has 2 outputs: VDst and MVT::Other. 1973 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other. 1974 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other 1975 // of ResNode. 1976 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0)); 1977 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2)); 1978 return ResNode; 1979} 1980 1981SDNode *X86DAGToDAGISel::Select(SDNode *Node) { 1982 EVT NVT = Node->getValueType(0); 1983 unsigned Opc, MOpc; 1984 unsigned Opcode = Node->getOpcode(); 1985 DebugLoc dl = Node->getDebugLoc(); 1986 1987 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n'); 1988 1989 if (Node->isMachineOpcode()) { 1990 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); 1991 return NULL; // Already selected. 1992 } 1993 1994 switch (Opcode) { 1995 default: break; 1996 case ISD::INTRINSIC_W_CHAIN: { 1997 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 1998 switch (IntNo) { 1999 default: break; 2000 case Intrinsic::x86_avx2_gather_d_pd: 2001 case Intrinsic::x86_avx2_gather_d_pd_256: 2002 case Intrinsic::x86_avx2_gather_q_pd: 2003 case Intrinsic::x86_avx2_gather_q_pd_256: 2004 case Intrinsic::x86_avx2_gather_d_ps: 2005 case Intrinsic::x86_avx2_gather_d_ps_256: 2006 case Intrinsic::x86_avx2_gather_q_ps: 2007 case Intrinsic::x86_avx2_gather_q_ps_256: 2008 case Intrinsic::x86_avx2_gather_d_q: 2009 case Intrinsic::x86_avx2_gather_d_q_256: 2010 case Intrinsic::x86_avx2_gather_q_q: 2011 case Intrinsic::x86_avx2_gather_q_q_256: 2012 case Intrinsic::x86_avx2_gather_d_d: 2013 case Intrinsic::x86_avx2_gather_d_d_256: 2014 case Intrinsic::x86_avx2_gather_q_d: 2015 case Intrinsic::x86_avx2_gather_q_d_256: { 2016 unsigned Opc; 2017 switch (IntNo) { 2018 default: llvm_unreachable("Impossible intrinsic"); 2019 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break; 2020 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break; 2021 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break; 2022 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break; 2023 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break; 2024 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break; 2025 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break; 2026 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break; 2027 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break; 2028 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break; 2029 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break; 2030 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break; 2031 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break; 2032 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break; 2033 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break; 2034 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break; 2035 } 2036 SDNode *RetVal = SelectGather(Node, Opc); 2037 if (RetVal) 2038 // We already called ReplaceUses inside SelectGather. 2039 return NULL; 2040 break; 2041 } 2042 } 2043 break; 2044 } 2045 case X86ISD::GlobalBaseReg: 2046 return getGlobalBaseReg(); 2047 2048 2049 case X86ISD::ATOMOR64_DAG: 2050 case X86ISD::ATOMXOR64_DAG: 2051 case X86ISD::ATOMADD64_DAG: 2052 case X86ISD::ATOMSUB64_DAG: 2053 case X86ISD::ATOMNAND64_DAG: 2054 case X86ISD::ATOMAND64_DAG: 2055 case X86ISD::ATOMMAX64_DAG: 2056 case X86ISD::ATOMMIN64_DAG: 2057 case X86ISD::ATOMUMAX64_DAG: 2058 case X86ISD::ATOMUMIN64_DAG: 2059 case X86ISD::ATOMSWAP64_DAG: { 2060 unsigned Opc; 2061 switch (Opcode) { 2062 default: llvm_unreachable("Impossible opcode"); 2063 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break; 2064 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break; 2065 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break; 2066 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break; 2067 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break; 2068 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break; 2069 case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break; 2070 case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break; 2071 case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break; 2072 case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break; 2073 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break; 2074 } 2075 SDNode *RetVal = SelectAtomic64(Node, Opc); 2076 if (RetVal) 2077 return RetVal; 2078 break; 2079 } 2080 2081 case ISD::ATOMIC_LOAD_XOR: 2082 case ISD::ATOMIC_LOAD_AND: 2083 case ISD::ATOMIC_LOAD_OR: 2084 case ISD::ATOMIC_LOAD_ADD: { 2085 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT); 2086 if (RetVal) 2087 return RetVal; 2088 break; 2089 } 2090 case ISD::AND: 2091 case ISD::OR: 2092 case ISD::XOR: { 2093 // For operations of the form (x << C1) op C2, check if we can use a smaller 2094 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1. 2095 SDValue N0 = Node->getOperand(0); 2096 SDValue N1 = Node->getOperand(1); 2097 2098 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse()) 2099 break; 2100 2101 // i8 is unshrinkable, i16 should be promoted to i32. 2102 if (NVT != MVT::i32 && NVT != MVT::i64) 2103 break; 2104 2105 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1); 2106 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 2107 if (!Cst || !ShlCst) 2108 break; 2109 2110 int64_t Val = Cst->getSExtValue(); 2111 uint64_t ShlVal = ShlCst->getZExtValue(); 2112 2113 // Make sure that we don't change the operation by removing bits. 2114 // This only matters for OR and XOR, AND is unaffected. 2115 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1; 2116 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0) 2117 break; 2118 2119 unsigned ShlOp, Op; 2120 EVT CstVT = NVT; 2121 2122 // Check the minimum bitwidth for the new constant. 2123 // TODO: AND32ri is the same as AND64ri32 with zext imm. 2124 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr 2125 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32. 2126 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal)) 2127 CstVT = MVT::i8; 2128 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal)) 2129 CstVT = MVT::i32; 2130 2131 // Bail if there is no smaller encoding. 2132 if (NVT == CstVT) 2133 break; 2134 2135 switch (NVT.getSimpleVT().SimpleTy) { 2136 default: llvm_unreachable("Unsupported VT!"); 2137 case MVT::i32: 2138 assert(CstVT == MVT::i8); 2139 ShlOp = X86::SHL32ri; 2140 2141 switch (Opcode) { 2142 default: llvm_unreachable("Impossible opcode"); 2143 case ISD::AND: Op = X86::AND32ri8; break; 2144 case ISD::OR: Op = X86::OR32ri8; break; 2145 case ISD::XOR: Op = X86::XOR32ri8; break; 2146 } 2147 break; 2148 case MVT::i64: 2149 assert(CstVT == MVT::i8 || CstVT == MVT::i32); 2150 ShlOp = X86::SHL64ri; 2151 2152 switch (Opcode) { 2153 default: llvm_unreachable("Impossible opcode"); 2154 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break; 2155 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break; 2156 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break; 2157 } 2158 break; 2159 } 2160 2161 // Emit the smaller op and the shift. 2162 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT); 2163 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst); 2164 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0), 2165 getI8Imm(ShlVal)); 2166 } 2167 case X86ISD::UMUL: { 2168 SDValue N0 = Node->getOperand(0); 2169 SDValue N1 = Node->getOperand(1); 2170 2171 unsigned LoReg; 2172 switch (NVT.getSimpleVT().SimpleTy) { 2173 default: llvm_unreachable("Unsupported VT!"); 2174 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; 2175 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; 2176 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; 2177 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; 2178 } 2179 2180 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 2181 N0, SDValue()).getValue(1); 2182 2183 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32); 2184 SDValue Ops[] = {N1, InFlag}; 2185 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops); 2186 2187 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0)); 2188 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1)); 2189 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2)); 2190 return NULL; 2191 } 2192 2193 case ISD::SMUL_LOHI: 2194 case ISD::UMUL_LOHI: { 2195 SDValue N0 = Node->getOperand(0); 2196 SDValue N1 = Node->getOperand(1); 2197 2198 bool isSigned = Opcode == ISD::SMUL_LOHI; 2199 bool hasBMI2 = Subtarget->hasBMI2(); 2200 if (!isSigned) { 2201 switch (NVT.getSimpleVT().SimpleTy) { 2202 default: llvm_unreachable("Unsupported VT!"); 2203 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; 2204 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; 2205 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r; 2206 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break; 2207 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r; 2208 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break; 2209 } 2210 } else { 2211 switch (NVT.getSimpleVT().SimpleTy) { 2212 default: llvm_unreachable("Unsupported VT!"); 2213 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; 2214 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; 2215 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; 2216 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; 2217 } 2218 } 2219 2220 unsigned SrcReg, LoReg, HiReg; 2221 switch (Opc) { 2222 default: llvm_unreachable("Unknown MUL opcode!"); 2223 case X86::IMUL8r: 2224 case X86::MUL8r: 2225 SrcReg = LoReg = X86::AL; HiReg = X86::AH; 2226 break; 2227 case X86::IMUL16r: 2228 case X86::MUL16r: 2229 SrcReg = LoReg = X86::AX; HiReg = X86::DX; 2230 break; 2231 case X86::IMUL32r: 2232 case X86::MUL32r: 2233 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; 2234 break; 2235 case X86::IMUL64r: 2236 case X86::MUL64r: 2237 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; 2238 break; 2239 case X86::MULX32rr: 2240 SrcReg = X86::EDX; LoReg = HiReg = 0; 2241 break; 2242 case X86::MULX64rr: 2243 SrcReg = X86::RDX; LoReg = HiReg = 0; 2244 break; 2245 } 2246 2247 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 2248 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2249 // Multiply is commmutative. 2250 if (!foldedLoad) { 2251 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2252 if (foldedLoad) 2253 std::swap(N0, N1); 2254 } 2255 2256 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg, 2257 N0, SDValue()).getValue(1); 2258 SDValue ResHi, ResLo; 2259 2260 if (foldedLoad) { 2261 SDValue Chain; 2262 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 2263 InFlag }; 2264 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) { 2265 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue); 2266 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops); 2267 ResHi = SDValue(CNode, 0); 2268 ResLo = SDValue(CNode, 1); 2269 Chain = SDValue(CNode, 2); 2270 InFlag = SDValue(CNode, 3); 2271 } else { 2272 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue); 2273 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops); 2274 Chain = SDValue(CNode, 0); 2275 InFlag = SDValue(CNode, 1); 2276 } 2277 2278 // Update the chain. 2279 ReplaceUses(N1.getValue(1), Chain); 2280 } else { 2281 SDValue Ops[] = { N1, InFlag }; 2282 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) { 2283 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue); 2284 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops); 2285 ResHi = SDValue(CNode, 0); 2286 ResLo = SDValue(CNode, 1); 2287 InFlag = SDValue(CNode, 2); 2288 } else { 2289 SDVTList VTs = CurDAG->getVTList(MVT::Glue); 2290 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops); 2291 InFlag = SDValue(CNode, 0); 2292 } 2293 } 2294 2295 // Prevent use of AH in a REX instruction by referencing AX instead. 2296 if (HiReg == X86::AH && Subtarget->is64Bit() && 2297 !SDValue(Node, 1).use_empty()) { 2298 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2299 X86::AX, MVT::i16, InFlag); 2300 InFlag = Result.getValue(2); 2301 // Get the low part if needed. Don't use getCopyFromReg for aliasing 2302 // registers. 2303 if (!SDValue(Node, 0).use_empty()) 2304 ReplaceUses(SDValue(Node, 1), 2305 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2306 2307 // Shift AX down 8 bits. 2308 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 2309 Result, 2310 CurDAG->getTargetConstant(8, MVT::i8)), 0); 2311 // Then truncate it down to i8. 2312 ReplaceUses(SDValue(Node, 1), 2313 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2314 } 2315 // Copy the low half of the result, if it is needed. 2316 if (!SDValue(Node, 0).use_empty()) { 2317 if (ResLo.getNode() == 0) { 2318 assert(LoReg && "Register for low half is not defined!"); 2319 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT, 2320 InFlag); 2321 InFlag = ResLo.getValue(2); 2322 } 2323 ReplaceUses(SDValue(Node, 0), ResLo); 2324 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n'); 2325 } 2326 // Copy the high half of the result, if it is needed. 2327 if (!SDValue(Node, 1).use_empty()) { 2328 if (ResHi.getNode() == 0) { 2329 assert(HiReg && "Register for high half is not defined!"); 2330 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, 2331 InFlag); 2332 InFlag = ResHi.getValue(2); 2333 } 2334 ReplaceUses(SDValue(Node, 1), ResHi); 2335 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n'); 2336 } 2337 2338 // Propagate ordering to the last node, for now. 2339 CurDAG->AssignOrdering(InFlag.getNode(), CurDAG->GetOrdering(Node)); 2340 2341 return NULL; 2342 } 2343 2344 case ISD::SDIVREM: 2345 case ISD::UDIVREM: { 2346 SDValue N0 = Node->getOperand(0); 2347 SDValue N1 = Node->getOperand(1); 2348 2349 bool isSigned = Opcode == ISD::SDIVREM; 2350 if (!isSigned) { 2351 switch (NVT.getSimpleVT().SimpleTy) { 2352 default: llvm_unreachable("Unsupported VT!"); 2353 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; 2354 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; 2355 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; 2356 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; 2357 } 2358 } else { 2359 switch (NVT.getSimpleVT().SimpleTy) { 2360 default: llvm_unreachable("Unsupported VT!"); 2361 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; 2362 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; 2363 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; 2364 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; 2365 } 2366 } 2367 2368 unsigned LoReg, HiReg, ClrReg; 2369 unsigned ClrOpcode, SExtOpcode; 2370 switch (NVT.getSimpleVT().SimpleTy) { 2371 default: llvm_unreachable("Unsupported VT!"); 2372 case MVT::i8: 2373 LoReg = X86::AL; ClrReg = HiReg = X86::AH; 2374 ClrOpcode = 0; 2375 SExtOpcode = X86::CBW; 2376 break; 2377 case MVT::i16: 2378 LoReg = X86::AX; HiReg = X86::DX; 2379 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX; 2380 SExtOpcode = X86::CWD; 2381 break; 2382 case MVT::i32: 2383 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; 2384 ClrOpcode = X86::MOV32r0; 2385 SExtOpcode = X86::CDQ; 2386 break; 2387 case MVT::i64: 2388 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; 2389 ClrOpcode = X86::MOV64r0; 2390 SExtOpcode = X86::CQO; 2391 break; 2392 } 2393 2394 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 2395 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2396 bool signBitIsZero = CurDAG->SignBitIsZero(N0); 2397 2398 SDValue InFlag; 2399 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) { 2400 // Special case for div8, just use a move with zero extension to AX to 2401 // clear the upper 8 bits (AH). 2402 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; 2403 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 2404 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; 2405 Move = 2406 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32, 2407 MVT::Other, Ops), 0); 2408 Chain = Move.getValue(1); 2409 ReplaceUses(N0.getValue(1), Chain); 2410 } else { 2411 Move = 2412 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0); 2413 Chain = CurDAG->getEntryNode(); 2414 } 2415 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue()); 2416 InFlag = Chain.getValue(1); 2417 } else { 2418 InFlag = 2419 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, 2420 LoReg, N0, SDValue()).getValue(1); 2421 if (isSigned && !signBitIsZero) { 2422 // Sign extend the low part into the high part. 2423 InFlag = 2424 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0); 2425 } else { 2426 // Zero out the high part, effectively zero extending the input. 2427 SDValue ClrNode = 2428 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0); 2429 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg, 2430 ClrNode, InFlag).getValue(1); 2431 } 2432 } 2433 2434 if (foldedLoad) { 2435 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 2436 InFlag }; 2437 SDNode *CNode = 2438 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops); 2439 InFlag = SDValue(CNode, 1); 2440 // Update the chain. 2441 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 2442 } else { 2443 InFlag = 2444 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0); 2445 } 2446 2447 // Prevent use of AH in a REX instruction by referencing AX instead. 2448 // Shift it down 8 bits. 2449 if (HiReg == X86::AH && Subtarget->is64Bit() && 2450 !SDValue(Node, 1).use_empty()) { 2451 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2452 X86::AX, MVT::i16, InFlag); 2453 InFlag = Result.getValue(2); 2454 2455 // If we also need AL (the quotient), get it by extracting a subreg from 2456 // Result. The fast register allocator does not like multiple CopyFromReg 2457 // nodes using aliasing registers. 2458 if (!SDValue(Node, 0).use_empty()) 2459 ReplaceUses(SDValue(Node, 0), 2460 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2461 2462 // Shift AX right by 8 bits instead of using AH. 2463 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 2464 Result, 2465 CurDAG->getTargetConstant(8, MVT::i8)), 2466 0); 2467 ReplaceUses(SDValue(Node, 1), 2468 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2469 } 2470 // Copy the division (low) result, if it is needed. 2471 if (!SDValue(Node, 0).use_empty()) { 2472 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2473 LoReg, NVT, InFlag); 2474 InFlag = Result.getValue(2); 2475 ReplaceUses(SDValue(Node, 0), Result); 2476 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2477 } 2478 // Copy the remainder (high) result, if it is needed. 2479 if (!SDValue(Node, 1).use_empty()) { 2480 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2481 HiReg, NVT, InFlag); 2482 InFlag = Result.getValue(2); 2483 ReplaceUses(SDValue(Node, 1), Result); 2484 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2485 } 2486 return NULL; 2487 } 2488 2489 case X86ISD::CMP: 2490 case X86ISD::SUB: { 2491 // Sometimes a SUB is used to perform comparison. 2492 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0)) 2493 // This node is not a CMP. 2494 break; 2495 SDValue N0 = Node->getOperand(0); 2496 SDValue N1 = Node->getOperand(1); 2497 2498 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to 2499 // use a smaller encoding. 2500 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && 2501 HasNoSignedComparisonUses(Node)) 2502 // Look past the truncate if CMP is the only use of it. 2503 N0 = N0.getOperand(0); 2504 if ((N0.getNode()->getOpcode() == ISD::AND || 2505 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) && 2506 N0.getNode()->hasOneUse() && 2507 N0.getValueType() != MVT::i8 && 2508 X86::isZeroNode(N1)) { 2509 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1)); 2510 if (!C) break; 2511 2512 // For example, convert "testl %eax, $8" to "testb %al, $8" 2513 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 && 2514 (!(C->getZExtValue() & 0x80) || 2515 HasNoSignedComparisonUses(Node))) { 2516 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8); 2517 SDValue Reg = N0.getNode()->getOperand(0); 2518 2519 // On x86-32, only the ABCD registers have 8-bit subregisters. 2520 if (!Subtarget->is64Bit()) { 2521 const TargetRegisterClass *TRC; 2522 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2523 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2524 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2525 default: llvm_unreachable("Unsupported TEST operand type!"); 2526 } 2527 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2528 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2529 Reg.getValueType(), Reg, RC), 0); 2530 } 2531 2532 // Extract the l-register. 2533 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, 2534 MVT::i8, Reg); 2535 2536 // Emit a testb. 2537 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, 2538 Subreg, Imm); 2539 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has 2540 // one, do not call ReplaceAllUsesWith. 2541 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)), 2542 SDValue(NewNode, 0)); 2543 return NULL; 2544 } 2545 2546 // For example, "testl %eax, $2048" to "testb %ah, $8". 2547 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 && 2548 (!(C->getZExtValue() & 0x8000) || 2549 HasNoSignedComparisonUses(Node))) { 2550 // Shift the immediate right by 8 bits. 2551 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8, 2552 MVT::i8); 2553 SDValue Reg = N0.getNode()->getOperand(0); 2554 2555 // Put the value in an ABCD register. 2556 const TargetRegisterClass *TRC; 2557 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2558 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; 2559 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2560 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2561 default: llvm_unreachable("Unsupported TEST operand type!"); 2562 } 2563 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2564 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2565 Reg.getValueType(), Reg, RC), 0); 2566 2567 // Extract the h-register. 2568 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, 2569 MVT::i8, Reg); 2570 2571 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only 2572 // target GR8_NOREX registers, so make sure the register class is 2573 // forced. 2574 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, 2575 MVT::i32, Subreg, ShiftedImm); 2576 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has 2577 // one, do not call ReplaceAllUsesWith. 2578 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)), 2579 SDValue(NewNode, 0)); 2580 return NULL; 2581 } 2582 2583 // For example, "testl %eax, $32776" to "testw %ax, $32776". 2584 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 && 2585 N0.getValueType() != MVT::i16 && 2586 (!(C->getZExtValue() & 0x8000) || 2587 HasNoSignedComparisonUses(Node))) { 2588 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16); 2589 SDValue Reg = N0.getNode()->getOperand(0); 2590 2591 // Extract the 16-bit subregister. 2592 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, 2593 MVT::i16, Reg); 2594 2595 // Emit a testw. 2596 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, 2597 Subreg, Imm); 2598 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has 2599 // one, do not call ReplaceAllUsesWith. 2600 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)), 2601 SDValue(NewNode, 0)); 2602 return NULL; 2603 } 2604 2605 // For example, "testq %rax, $268468232" to "testl %eax, $268468232". 2606 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 && 2607 N0.getValueType() == MVT::i64 && 2608 (!(C->getZExtValue() & 0x80000000) || 2609 HasNoSignedComparisonUses(Node))) { 2610 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32); 2611 SDValue Reg = N0.getNode()->getOperand(0); 2612 2613 // Extract the 32-bit subregister. 2614 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, 2615 MVT::i32, Reg); 2616 2617 // Emit a testl. 2618 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, 2619 Subreg, Imm); 2620 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has 2621 // one, do not call ReplaceAllUsesWith. 2622 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)), 2623 SDValue(NewNode, 0)); 2624 return NULL; 2625 } 2626 } 2627 break; 2628 } 2629 case ISD::STORE: { 2630 // Change a chain of {load; incr or dec; store} of the same value into 2631 // a simple increment or decrement through memory of that value, if the 2632 // uses of the modified value and its address are suitable. 2633 // The DEC64m tablegen pattern is currently not able to match the case where 2634 // the EFLAGS on the original DEC are used. (This also applies to 2635 // {INC,DEC}X{64,32,16,8}.) 2636 // We'll need to improve tablegen to allow flags to be transferred from a 2637 // node in the pattern to the result node. probably with a new keyword 2638 // for example, we have this 2639 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", 2640 // [(store (add (loadi64 addr:$dst), -1), addr:$dst), 2641 // (implicit EFLAGS)]>; 2642 // but maybe need something like this 2643 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", 2644 // [(store (add (loadi64 addr:$dst), -1), addr:$dst), 2645 // (transferrable EFLAGS)]>; 2646 2647 StoreSDNode *StoreNode = cast<StoreSDNode>(Node); 2648 SDValue StoredVal = StoreNode->getOperand(1); 2649 unsigned Opc = StoredVal->getOpcode(); 2650 2651 LoadSDNode *LoadNode = 0; 2652 SDValue InputChain; 2653 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG, 2654 LoadNode, InputChain)) 2655 break; 2656 2657 SDValue Base, Scale, Index, Disp, Segment; 2658 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(), 2659 Base, Scale, Index, Disp, Segment)) 2660 break; 2661 2662 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2); 2663 MemOp[0] = StoreNode->getMemOperand(); 2664 MemOp[1] = LoadNode->getMemOperand(); 2665 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain }; 2666 EVT LdVT = LoadNode->getMemoryVT(); 2667 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc); 2668 MachineSDNode *Result = CurDAG->getMachineNode(newOpc, 2669 Node->getDebugLoc(), 2670 MVT::i32, MVT::Other, Ops); 2671 Result->setMemRefs(MemOp, MemOp + 2); 2672 2673 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1)); 2674 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0)); 2675 2676 return Result; 2677 } 2678 } 2679 2680 SDNode *ResNode = SelectCode(Node); 2681 2682 DEBUG(dbgs() << "=> "; 2683 if (ResNode == NULL || ResNode == Node) 2684 Node->dump(CurDAG); 2685 else 2686 ResNode->dump(CurDAG); 2687 dbgs() << '\n'); 2688 2689 return ResNode; 2690} 2691 2692bool X86DAGToDAGISel:: 2693SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2694 std::vector<SDValue> &OutOps) { 2695 SDValue Op0, Op1, Op2, Op3, Op4; 2696 switch (ConstraintCode) { 2697 case 'o': // offsetable ?? 2698 case 'v': // not offsetable ?? 2699 default: return true; 2700 case 'm': // memory 2701 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) 2702 return true; 2703 break; 2704 } 2705 2706 OutOps.push_back(Op0); 2707 OutOps.push_back(Op1); 2708 OutOps.push_back(Op2); 2709 OutOps.push_back(Op3); 2710 OutOps.push_back(Op4); 2711 return false; 2712} 2713 2714/// createX86ISelDag - This pass converts a legalized DAG into a 2715/// X86-specific DAG, ready for instruction scheduling. 2716/// 2717FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, 2718 CodeGenOpt::Level OptLevel) { 2719 return new X86DAGToDAGISel(TM, OptLevel); 2720} 2721