X86FixupLEAs.cpp revision 321369
1251607Sdim//===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim// 10276479Sdim// This file defines the pass that finds instructions that can be 11276479Sdim// re-written as LEA instructions in order to reduce pipeline delays. 12296417Sdim// When optimizing for size it replaces suitable LEAs with INC or DEC. 13251607Sdim// 14251607Sdim//===----------------------------------------------------------------------===// 15251607Sdim 16251607Sdim#include "X86.h" 17251607Sdim#include "X86InstrInfo.h" 18251607Sdim#include "X86Subtarget.h" 19251607Sdim#include "llvm/ADT/Statistic.h" 20251607Sdim#include "llvm/CodeGen/LiveVariables.h" 21251607Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 22251607Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 23251607Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 24251607Sdim#include "llvm/CodeGen/Passes.h" 25251607Sdim#include "llvm/Support/Debug.h" 26251607Sdim#include "llvm/Support/raw_ostream.h" 27251607Sdim#include "llvm/Target/TargetInstrInfo.h" 28251607Sdimusing namespace llvm; 29251607Sdim 30321369Sdimnamespace llvm { 31321369Sdimvoid initializeFixupLEAPassPass(PassRegistry &); 32321369Sdim} 33276479Sdim 34321369Sdim#define FIXUPLEA_DESC "X86 LEA Fixup" 35321369Sdim#define FIXUPLEA_NAME "x86-fixup-LEAs" 36321369Sdim 37321369Sdim#define DEBUG_TYPE FIXUPLEA_NAME 38321369Sdim 39251607SdimSTATISTIC(NumLEAs, "Number of LEA instructions created"); 40251607Sdim 41251607Sdimnamespace { 42276479Sdimclass FixupLEAPass : public MachineFunctionPass { 43276479Sdim enum RegUsageState { RU_NotUsed, RU_Write, RU_Read }; 44321369Sdim 45276479Sdim /// \brief Loop over all of the instructions in the basic block 46276479Sdim /// replacing applicable instructions with LEA instructions, 47276479Sdim /// where appropriate. 48276479Sdim bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI); 49251607Sdim 50251607Sdim 51276479Sdim /// \brief Given a machine register, look for the instruction 52276479Sdim /// which writes it in the current basic block. If found, 53276479Sdim /// try to replace it with an equivalent LEA instruction. 54288943Sdim /// If replacement succeeds, then also process the newly created 55276479Sdim /// instruction. 56276479Sdim void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I, 57276479Sdim MachineFunction::iterator MFI); 58251607Sdim 59276479Sdim /// \brief Given a memory access or LEA instruction 60276479Sdim /// whose address mode uses a base and/or index register, look for 61276479Sdim /// an opportunity to replace the instruction which sets the base or index 62276479Sdim /// register with an equivalent LEA instruction. 63276479Sdim void processInstruction(MachineBasicBlock::iterator &I, 64276479Sdim MachineFunction::iterator MFI); 65251607Sdim 66276479Sdim /// \brief Given a LEA instruction which is unprofitable 67276479Sdim /// on Silvermont try to replace it with an equivalent ADD instruction 68276479Sdim void processInstructionForSLM(MachineBasicBlock::iterator &I, 69276479Sdim MachineFunction::iterator MFI); 70251607Sdim 71321369Sdim 72321369Sdim /// \brief Given a LEA instruction which is unprofitable 73321369Sdim /// on SNB+ try to replace it with other instructions. 74321369Sdim /// According to Intel's Optimization Reference Manual: 75321369Sdim /// " For LEA instructions with three source operands and some specific 76321369Sdim /// situations, instruction latency has increased to 3 cycles, and must 77321369Sdim /// dispatch via port 1: 78321369Sdim /// - LEA that has all three source operands: base, index, and offset 79321369Sdim /// - LEA that uses base and index registers where the base is EBP, RBP, 80321369Sdim /// or R13 81321369Sdim /// - LEA that uses RIP relative addressing mode 82321369Sdim /// - LEA that uses 16-bit addressing mode " 83321369Sdim /// This function currently handles the first 2 cases only. 84321369Sdim MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI, 85321369Sdim MachineFunction::iterator MFI); 86321369Sdim 87296417Sdim /// \brief Look for LEAs that add 1 to reg or subtract 1 from reg 88296417Sdim /// and convert them to INC or DEC respectively. 89296417Sdim bool fixupIncDec(MachineBasicBlock::iterator &I, 90296417Sdim MachineFunction::iterator MFI) const; 91296417Sdim 92276479Sdim /// \brief Determine if an instruction references a machine register 93276479Sdim /// and, if so, whether it reads or writes the register. 94276479Sdim RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I); 95251607Sdim 96276479Sdim /// \brief Step backwards through a basic block, looking 97276479Sdim /// for an instruction which writes a register within 98276479Sdim /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles. 99276479Sdim MachineBasicBlock::iterator searchBackwards(MachineOperand &p, 100276479Sdim MachineBasicBlock::iterator &I, 101276479Sdim MachineFunction::iterator MFI); 102251607Sdim 103276479Sdim /// \brief if an instruction can be converted to an 104276479Sdim /// equivalent LEA, insert the new instruction into the basic block 105276479Sdim /// and return a pointer to it. Otherwise, return zero. 106276479Sdim MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI, 107276479Sdim MachineBasicBlock::iterator &MBBI) const; 108251607Sdim 109276479Sdimpublic: 110321369Sdim static char ID; 111251607Sdim 112321369Sdim StringRef getPassName() const override { return FIXUPLEA_DESC; } 113321369Sdim 114321369Sdim FixupLEAPass() : MachineFunctionPass(ID) { 115321369Sdim initializeFixupLEAPassPass(*PassRegistry::getPassRegistry()); 116321369Sdim } 117321369Sdim 118276479Sdim /// \brief Loop over all of the basic blocks, 119276479Sdim /// replacing instructions by equivalent LEA instructions 120276479Sdim /// if needed and when possible. 121276479Sdim bool runOnMachineFunction(MachineFunction &MF) override; 122251607Sdim 123309124Sdim // This pass runs after regalloc and doesn't support VReg operands. 124309124Sdim MachineFunctionProperties getRequiredProperties() const override { 125309124Sdim return MachineFunctionProperties().set( 126314564Sdim MachineFunctionProperties::Property::NoVRegs); 127309124Sdim } 128309124Sdim 129276479Sdimprivate: 130276479Sdim MachineFunction *MF; 131276479Sdim const X86InstrInfo *TII; // Machine instruction info. 132296417Sdim bool OptIncDec; 133296417Sdim bool OptLEA; 134276479Sdim}; 135251607Sdim} 136251607Sdim 137321369Sdimchar FixupLEAPass::ID = 0; 138321369Sdim 139321369SdimINITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false) 140321369Sdim 141251607SdimMachineInstr * 142251607SdimFixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI, 143251607Sdim MachineBasicBlock::iterator &MBBI) const { 144309124Sdim MachineInstr &MI = *MBBI; 145309124Sdim switch (MI.getOpcode()) { 146276479Sdim case X86::MOV32rr: 147251607Sdim case X86::MOV64rr: { 148309124Sdim const MachineOperand &Src = MI.getOperand(1); 149309124Sdim const MachineOperand &Dest = MI.getOperand(0); 150309124Sdim MachineInstr *NewMI = 151309124Sdim BuildMI(*MF, MI.getDebugLoc(), 152309124Sdim TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r 153309124Sdim : X86::LEA64r)) 154321369Sdim .add(Dest) 155321369Sdim .add(Src) 156309124Sdim .addImm(1) 157309124Sdim .addReg(0) 158309124Sdim .addImm(0) 159309124Sdim .addReg(0); 160276479Sdim MFI->insert(MBBI, NewMI); // Insert the new inst 161251607Sdim return NewMI; 162251607Sdim } 163251607Sdim case X86::ADD64ri32: 164251607Sdim case X86::ADD64ri8: 165251607Sdim case X86::ADD64ri32_DB: 166251607Sdim case X86::ADD64ri8_DB: 167251607Sdim case X86::ADD32ri: 168251607Sdim case X86::ADD32ri8: 169251607Sdim case X86::ADD32ri_DB: 170251607Sdim case X86::ADD32ri8_DB: 171251607Sdim case X86::ADD16ri: 172251607Sdim case X86::ADD16ri8: 173251607Sdim case X86::ADD16ri_DB: 174251607Sdim case X86::ADD16ri8_DB: 175309124Sdim if (!MI.getOperand(2).isImm()) { 176251607Sdim // convertToThreeAddress will call getImm() 177251607Sdim // which requires isImm() to be true 178276479Sdim return nullptr; 179251607Sdim } 180255978Sdim break; 181255978Sdim case X86::ADD16rr: 182255978Sdim case X86::ADD16rr_DB: 183309124Sdim if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) { 184255978Sdim // if src1 != src2, then convertToThreeAddress will 185255978Sdim // need to create a Virtual register, which we cannot do 186255978Sdim // after register allocation. 187276479Sdim return nullptr; 188255978Sdim } 189251607Sdim } 190309124Sdim return TII->convertToThreeAddress(MFI, MI, nullptr); 191251607Sdim} 192251607Sdim 193276479SdimFunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); } 194251607Sdim 195251607Sdimbool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) { 196309124Sdim if (skipFunction(*Func.getFunction())) 197309124Sdim return false; 198309124Sdim 199251607Sdim MF = &Func; 200288943Sdim const X86Subtarget &ST = Func.getSubtarget<X86Subtarget>(); 201296417Sdim OptIncDec = !ST.slowIncDec() || Func.getFunction()->optForMinSize(); 202321369Sdim OptLEA = ST.LEAusesAG() || ST.slowLEA() || ST.slow3OpsLEA(); 203296417Sdim 204296417Sdim if (!OptLEA && !OptIncDec) 205276479Sdim return false; 206251607Sdim 207288943Sdim TII = ST.getInstrInfo(); 208276479Sdim 209251607Sdim DEBUG(dbgs() << "Start X86FixupLEAs\n";); 210251607Sdim // Process all basic blocks. 211251607Sdim for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I) 212251607Sdim processBasicBlock(Func, I); 213251607Sdim DEBUG(dbgs() << "End X86FixupLEAs\n";); 214251607Sdim 215251607Sdim return true; 216251607Sdim} 217251607Sdim 218276479SdimFixupLEAPass::RegUsageState 219276479SdimFixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) { 220251607Sdim RegUsageState RegUsage = RU_NotUsed; 221309124Sdim MachineInstr &MI = *I; 222251607Sdim 223309124Sdim for (unsigned int i = 0; i < MI.getNumOperands(); ++i) { 224309124Sdim MachineOperand &opnd = MI.getOperand(i); 225276479Sdim if (opnd.isReg() && opnd.getReg() == p.getReg()) { 226251607Sdim if (opnd.isDef()) 227251607Sdim return RU_Write; 228251607Sdim RegUsage = RU_Read; 229251607Sdim } 230251607Sdim } 231251607Sdim return RegUsage; 232251607Sdim} 233251607Sdim 234251607Sdim/// getPreviousInstr - Given a reference to an instruction in a basic 235251607Sdim/// block, return a reference to the previous instruction in the block, 236251607Sdim/// wrapping around to the last instruction of the block if the block 237251607Sdim/// branches to itself. 238276479Sdimstatic inline bool getPreviousInstr(MachineBasicBlock::iterator &I, 239251607Sdim MachineFunction::iterator MFI) { 240251607Sdim if (I == MFI->begin()) { 241296417Sdim if (MFI->isPredecessor(&*MFI)) { 242251607Sdim I = --MFI->end(); 243251607Sdim return true; 244276479Sdim } else 245251607Sdim return false; 246251607Sdim } 247251607Sdim --I; 248251607Sdim return true; 249251607Sdim} 250251607Sdim 251276479SdimMachineBasicBlock::iterator 252276479SdimFixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I, 253276479Sdim MachineFunction::iterator MFI) { 254251607Sdim int InstrDistance = 1; 255251607Sdim MachineBasicBlock::iterator CurInst; 256251607Sdim static const int INSTR_DISTANCE_THRESHOLD = 5; 257251607Sdim 258251607Sdim CurInst = I; 259251607Sdim bool Found; 260251607Sdim Found = getPreviousInstr(CurInst, MFI); 261276479Sdim while (Found && I != CurInst) { 262251607Sdim if (CurInst->isCall() || CurInst->isInlineAsm()) 263251607Sdim break; 264251607Sdim if (InstrDistance > INSTR_DISTANCE_THRESHOLD) 265251607Sdim break; // too far back to make a difference 266276479Sdim if (usesRegister(p, CurInst) == RU_Write) { 267251607Sdim return CurInst; 268251607Sdim } 269280031Sdim InstrDistance += TII->getInstrLatency( 270309124Sdim MF->getSubtarget().getInstrItineraryData(), *CurInst); 271251607Sdim Found = getPreviousInstr(CurInst, MFI); 272251607Sdim } 273309124Sdim return MachineBasicBlock::iterator(); 274251607Sdim} 275251607Sdim 276321369Sdimstatic inline bool isLEA(const int Opcode) { 277321369Sdim return Opcode == X86::LEA16r || Opcode == X86::LEA32r || 278321369Sdim Opcode == X86::LEA64r || Opcode == X86::LEA64_32r; 279296417Sdim} 280296417Sdim 281321369Sdimstatic inline bool isInefficientLEAReg(unsigned int Reg) { 282321369Sdim return Reg == X86::EBP || Reg == X86::RBP || Reg == X86::R13; 283321369Sdim} 284321369Sdim 285321369Sdimstatic inline bool isRegOperand(const MachineOperand &Op) { 286321369Sdim return Op.isReg() && Op.getReg() != X86::NoRegister; 287321369Sdim} 288321369Sdim/// hasIneffecientLEARegs - LEA that uses base and index registers 289321369Sdim/// where the base is EBP, RBP, or R13 290321369Sdimstatic inline bool hasInefficientLEABaseReg(const MachineOperand &Base, 291321369Sdim const MachineOperand &Index) { 292321369Sdim return Base.isReg() && isInefficientLEAReg(Base.getReg()) && 293321369Sdim isRegOperand(Index); 294321369Sdim} 295321369Sdim 296321369Sdimstatic inline bool hasLEAOffset(const MachineOperand &Offset) { 297321369Sdim return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal(); 298321369Sdim} 299321369Sdim 300321369Sdim// LEA instruction that has all three operands: offset, base and index 301321369Sdimstatic inline bool isThreeOperandsLEA(const MachineOperand &Base, 302321369Sdim const MachineOperand &Index, 303321369Sdim const MachineOperand &Offset) { 304321369Sdim return isRegOperand(Base) && isRegOperand(Index) && hasLEAOffset(Offset); 305321369Sdim} 306321369Sdim 307321369Sdimstatic inline int getADDrrFromLEA(int LEAOpcode) { 308321369Sdim switch (LEAOpcode) { 309321369Sdim default: 310321369Sdim llvm_unreachable("Unexpected LEA instruction"); 311321369Sdim case X86::LEA16r: 312321369Sdim return X86::ADD16rr; 313321369Sdim case X86::LEA32r: 314321369Sdim return X86::ADD32rr; 315321369Sdim case X86::LEA64_32r: 316321369Sdim case X86::LEA64r: 317321369Sdim return X86::ADD64rr; 318321369Sdim } 319321369Sdim} 320321369Sdim 321321369Sdimstatic inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) { 322321369Sdim bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm()); 323321369Sdim switch (LEAOpcode) { 324321369Sdim default: 325321369Sdim llvm_unreachable("Unexpected LEA instruction"); 326321369Sdim case X86::LEA16r: 327321369Sdim return IsInt8 ? X86::ADD16ri8 : X86::ADD16ri; 328321369Sdim case X86::LEA32r: 329321369Sdim case X86::LEA64_32r: 330321369Sdim return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri; 331321369Sdim case X86::LEA64r: 332321369Sdim return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32; 333321369Sdim } 334321369Sdim} 335321369Sdim 336296417Sdim/// isLEASimpleIncOrDec - Does this LEA have one these forms: 337296417Sdim/// lea %reg, 1(%reg) 338296417Sdim/// lea %reg, -1(%reg) 339309124Sdimstatic inline bool isLEASimpleIncOrDec(MachineInstr &LEA) { 340309124Sdim unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg(); 341309124Sdim unsigned DstReg = LEA.getOperand(0).getReg(); 342296417Sdim unsigned AddrDispOp = 1 + X86::AddrDisp; 343296417Sdim return SrcReg == DstReg && 344309124Sdim LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && 345309124Sdim LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 && 346309124Sdim LEA.getOperand(AddrDispOp).isImm() && 347309124Sdim (LEA.getOperand(AddrDispOp).getImm() == 1 || 348309124Sdim LEA.getOperand(AddrDispOp).getImm() == -1); 349296417Sdim} 350296417Sdim 351296417Sdimbool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I, 352296417Sdim MachineFunction::iterator MFI) const { 353309124Sdim MachineInstr &MI = *I; 354309124Sdim int Opcode = MI.getOpcode(); 355296417Sdim if (!isLEA(Opcode)) 356296417Sdim return false; 357296417Sdim 358296417Sdim if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) { 359296417Sdim int NewOpcode; 360309124Sdim bool isINC = MI.getOperand(4).getImm() == 1; 361296417Sdim switch (Opcode) { 362296417Sdim case X86::LEA16r: 363296417Sdim NewOpcode = isINC ? X86::INC16r : X86::DEC16r; 364296417Sdim break; 365296417Sdim case X86::LEA32r: 366296417Sdim case X86::LEA64_32r: 367296417Sdim NewOpcode = isINC ? X86::INC32r : X86::DEC32r; 368296417Sdim break; 369296417Sdim case X86::LEA64r: 370296417Sdim NewOpcode = isINC ? X86::INC64r : X86::DEC64r; 371296417Sdim break; 372296417Sdim } 373296417Sdim 374296417Sdim MachineInstr *NewMI = 375309124Sdim BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode)) 376321369Sdim .add(MI.getOperand(0)) 377321369Sdim .add(MI.getOperand(1)); 378296417Sdim MFI->erase(I); 379296417Sdim I = static_cast<MachineBasicBlock::iterator>(NewMI); 380296417Sdim return true; 381296417Sdim } 382296417Sdim return false; 383296417Sdim} 384296417Sdim 385276479Sdimvoid FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I, 386251607Sdim MachineFunction::iterator MFI) { 387251607Sdim // Process a load, store, or LEA instruction. 388309124Sdim MachineInstr &MI = *I; 389309124Sdim const MCInstrDesc &Desc = MI.getDesc(); 390309124Sdim int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags); 391251607Sdim if (AddrOffset >= 0) { 392251607Sdim AddrOffset += X86II::getOperandBias(Desc); 393309124Sdim MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); 394251607Sdim if (p.isReg() && p.getReg() != X86::ESP) { 395251607Sdim seekLEAFixup(p, I, MFI); 396251607Sdim } 397309124Sdim MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg); 398251607Sdim if (q.isReg() && q.getReg() != X86::ESP) { 399251607Sdim seekLEAFixup(q, I, MFI); 400251607Sdim } 401251607Sdim } 402251607Sdim} 403251607Sdim 404276479Sdimvoid FixupLEAPass::seekLEAFixup(MachineOperand &p, 405276479Sdim MachineBasicBlock::iterator &I, 406251607Sdim MachineFunction::iterator MFI) { 407251607Sdim MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI); 408309124Sdim if (MBI != MachineBasicBlock::iterator()) { 409276479Sdim MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI); 410251607Sdim if (NewMI) { 411251607Sdim ++NumLEAs; 412276479Sdim DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump();); 413251607Sdim // now to replace with an equivalent LEA... 414276479Sdim DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump();); 415251607Sdim MFI->erase(MBI); 416251607Sdim MachineBasicBlock::iterator J = 417276479Sdim static_cast<MachineBasicBlock::iterator>(NewMI); 418251607Sdim processInstruction(J, MFI); 419251607Sdim } 420251607Sdim } 421251607Sdim} 422251607Sdim 423276479Sdimvoid FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I, 424276479Sdim MachineFunction::iterator MFI) { 425309124Sdim MachineInstr &MI = *I; 426321369Sdim const int Opcode = MI.getOpcode(); 427321369Sdim if (!isLEA(Opcode)) 428276479Sdim return; 429309124Sdim if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() || 430276479Sdim !TII->isSafeToClobberEFLAGS(*MFI, I)) 431276479Sdim return; 432309124Sdim const unsigned DstR = MI.getOperand(0).getReg(); 433309124Sdim const unsigned SrcR1 = MI.getOperand(1).getReg(); 434309124Sdim const unsigned SrcR2 = MI.getOperand(3).getReg(); 435276479Sdim if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) 436276479Sdim return; 437309124Sdim if (MI.getOperand(2).getImm() > 1) 438276479Sdim return; 439276479Sdim DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump();); 440276479Sdim DEBUG(dbgs() << "FixLEA: Replaced by: ";); 441276479Sdim MachineInstr *NewMI = nullptr; 442276479Sdim // Make ADD instruction for two registers writing to LEA's destination 443276479Sdim if (SrcR1 != 0 && SrcR2 != 0) { 444321369Sdim const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode)); 445321369Sdim const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1); 446321369Sdim NewMI = 447321369Sdim BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src); 448276479Sdim DEBUG(NewMI->dump();); 449276479Sdim } 450276479Sdim // Make ADD instruction for immediate 451309124Sdim if (MI.getOperand(4).getImm() != 0) { 452321369Sdim const MCInstrDesc &ADDri = 453321369Sdim TII->get(getADDriFromLEA(Opcode, MI.getOperand(4))); 454309124Sdim const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); 455321369Sdim NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR) 456321369Sdim .add(SrcR) 457309124Sdim .addImm(MI.getOperand(4).getImm()); 458276479Sdim DEBUG(NewMI->dump();); 459276479Sdim } 460276479Sdim if (NewMI) { 461276479Sdim MFI->erase(I); 462321369Sdim I = NewMI; 463276479Sdim } 464276479Sdim} 465276479Sdim 466321369SdimMachineInstr * 467321369SdimFixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI, 468321369Sdim MachineFunction::iterator MFI) { 469321369Sdim 470321369Sdim const int LEAOpcode = MI.getOpcode(); 471321369Sdim if (!isLEA(LEAOpcode)) 472321369Sdim return nullptr; 473321369Sdim 474321369Sdim const MachineOperand &Dst = MI.getOperand(0); 475321369Sdim const MachineOperand &Base = MI.getOperand(1); 476321369Sdim const MachineOperand &Scale = MI.getOperand(2); 477321369Sdim const MachineOperand &Index = MI.getOperand(3); 478321369Sdim const MachineOperand &Offset = MI.getOperand(4); 479321369Sdim const MachineOperand &Segment = MI.getOperand(5); 480321369Sdim 481321369Sdim if (!(isThreeOperandsLEA(Base, Index, Offset) || 482321369Sdim hasInefficientLEABaseReg(Base, Index)) || 483321369Sdim !TII->isSafeToClobberEFLAGS(*MFI, MI) || 484321369Sdim Segment.getReg() != X86::NoRegister) 485321369Sdim return nullptr; 486321369Sdim 487321369Sdim unsigned int DstR = Dst.getReg(); 488321369Sdim unsigned int BaseR = Base.getReg(); 489321369Sdim unsigned int IndexR = Index.getReg(); 490321369Sdim unsigned SSDstR = 491321369Sdim (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR; 492321369Sdim bool IsScale1 = Scale.getImm() == 1; 493321369Sdim bool IsInefficientBase = isInefficientLEAReg(BaseR); 494321369Sdim bool IsInefficientIndex = isInefficientLEAReg(IndexR); 495321369Sdim 496321369Sdim // Skip these cases since it takes more than 2 instructions 497321369Sdim // to replace the LEA instruction. 498321369Sdim if (IsInefficientBase && SSDstR == BaseR && !IsScale1) 499321369Sdim return nullptr; 500321369Sdim if (LEAOpcode == X86::LEA64_32r && IsInefficientBase && 501321369Sdim (IsInefficientIndex || !IsScale1)) 502321369Sdim return nullptr; 503321369Sdim 504321369Sdim const DebugLoc DL = MI.getDebugLoc(); 505321369Sdim const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode)); 506321369Sdim const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset)); 507321369Sdim 508321369Sdim DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump();); 509321369Sdim DEBUG(dbgs() << "FixLEA: Replaced by: ";); 510321369Sdim 511321369Sdim // First try to replace LEA with one or two (for the 3-op LEA case) 512321369Sdim // add instructions: 513321369Sdim // 1.lea (%base,%index,1), %base => add %index,%base 514321369Sdim // 2.lea (%base,%index,1), %index => add %base,%index 515321369Sdim if (IsScale1 && (DstR == BaseR || DstR == IndexR)) { 516321369Sdim const MachineOperand &Src = DstR == BaseR ? Index : Base; 517321369Sdim MachineInstr *NewMI = 518321369Sdim BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Src); 519321369Sdim DEBUG(NewMI->dump();); 520321369Sdim // Create ADD instruction for the Offset in case of 3-Ops LEA. 521321369Sdim if (hasLEAOffset(Offset)) { 522321369Sdim NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); 523321369Sdim DEBUG(NewMI->dump();); 524321369Sdim } 525321369Sdim return NewMI; 526321369Sdim } 527321369Sdim // If the base is inefficient try switching the index and base operands, 528321369Sdim // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction: 529321369Sdim // lea offset(%base,%index,scale),%dst => 530321369Sdim // lea (%base,%index,scale); add offset,%dst 531321369Sdim if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) { 532321369Sdim MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode)) 533321369Sdim .add(Dst) 534321369Sdim .add(IsInefficientBase ? Index : Base) 535321369Sdim .add(Scale) 536321369Sdim .add(IsInefficientBase ? Base : Index) 537321369Sdim .addImm(0) 538321369Sdim .add(Segment); 539321369Sdim DEBUG(NewMI->dump();); 540321369Sdim // Create ADD instruction for the Offset in case of 3-Ops LEA. 541321369Sdim if (hasLEAOffset(Offset)) { 542321369Sdim NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); 543321369Sdim DEBUG(NewMI->dump();); 544321369Sdim } 545321369Sdim return NewMI; 546321369Sdim } 547321369Sdim // Handle the rest of the cases with inefficient base register: 548321369Sdim assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!"); 549321369Sdim assert(IsInefficientBase && "efficient base should be handled already!"); 550321369Sdim 551321369Sdim // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst 552321369Sdim if (IsScale1 && !hasLEAOffset(Offset)) { 553321369Sdim TII->copyPhysReg(*MFI, MI, DL, DstR, BaseR, Base.isKill()); 554321369Sdim DEBUG(MI.getPrevNode()->dump();); 555321369Sdim 556321369Sdim MachineInstr *NewMI = 557321369Sdim BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Index); 558321369Sdim DEBUG(NewMI->dump();); 559321369Sdim return NewMI; 560321369Sdim } 561321369Sdim // lea offset(%base,%index,scale), %dst => 562321369Sdim // lea offset( ,%index,scale), %dst; add %base,%dst 563321369Sdim MachineInstr *NewMI = BuildMI(*MFI, MI, DL, TII->get(LEAOpcode)) 564321369Sdim .add(Dst) 565321369Sdim .addReg(0) 566321369Sdim .add(Scale) 567321369Sdim .add(Index) 568321369Sdim .add(Offset) 569321369Sdim .add(Segment); 570321369Sdim DEBUG(NewMI->dump();); 571321369Sdim 572321369Sdim NewMI = BuildMI(*MFI, MI, DL, ADDrr, DstR).addReg(DstR).add(Base); 573321369Sdim DEBUG(NewMI->dump();); 574321369Sdim return NewMI; 575321369Sdim} 576321369Sdim 577251607Sdimbool FixupLEAPass::processBasicBlock(MachineFunction &MF, 578251607Sdim MachineFunction::iterator MFI) { 579251607Sdim 580276479Sdim for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) { 581296417Sdim if (OptIncDec) 582296417Sdim if (fixupIncDec(I, MFI)) 583296417Sdim continue; 584296417Sdim 585296417Sdim if (OptLEA) { 586296417Sdim if (MF.getSubtarget<X86Subtarget>().isSLM()) 587296417Sdim processInstructionForSLM(I, MFI); 588321369Sdim 589321369Sdim else { 590321369Sdim if (MF.getSubtarget<X86Subtarget>().slow3OpsLEA()) { 591321369Sdim if (auto *NewMI = processInstrForSlow3OpLEA(*I, MFI)) { 592321369Sdim MFI->erase(I); 593321369Sdim I = NewMI; 594321369Sdim } 595321369Sdim } else 596321369Sdim processInstruction(I, MFI); 597321369Sdim } 598296417Sdim } 599276479Sdim } 600251607Sdim return false; 601251607Sdim} 602