X86MCCodeEmitter.cpp revision 296417
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the X86MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MCTargetDesc/X86MCTargetDesc.h" 15#include "MCTargetDesc/X86BaseInfo.h" 16#include "MCTargetDesc/X86FixupKinds.h" 17#include "llvm/MC/MCCodeEmitter.h" 18#include "llvm/MC/MCContext.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCSymbol.h" 25#include "llvm/Support/raw_ostream.h" 26 27using namespace llvm; 28 29#define DEBUG_TYPE "mccodeemitter" 30 31namespace { 32class X86MCCodeEmitter : public MCCodeEmitter { 33 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete; 34 void operator=(const X86MCCodeEmitter &) = delete; 35 const MCInstrInfo &MCII; 36 MCContext &Ctx; 37public: 38 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 39 : MCII(mcii), Ctx(ctx) { 40 } 41 42 ~X86MCCodeEmitter() override {} 43 44 bool is64BitMode(const MCSubtargetInfo &STI) const { 45 return STI.getFeatureBits()[X86::Mode64Bit]; 46 } 47 48 bool is32BitMode(const MCSubtargetInfo &STI) const { 49 return STI.getFeatureBits()[X86::Mode32Bit]; 50 } 51 52 bool is16BitMode(const MCSubtargetInfo &STI) const { 53 return STI.getFeatureBits()[X86::Mode16Bit]; 54 } 55 56 /// Is16BitMemOperand - Return true if the specified instruction has 57 /// a 16-bit memory operand. Op specifies the operand # of the memoperand. 58 bool Is16BitMemOperand(const MCInst &MI, unsigned Op, 59 const MCSubtargetInfo &STI) const { 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 63 64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && 65 Disp.isImm() && Disp.getImm() < 0x10000) 66 return true; 67 if ((BaseReg.getReg() != 0 && 68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 69 (IndexReg.getReg() != 0 && 70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 71 return true; 72 return false; 73 } 74 75 unsigned GetX86RegNum(const MCOperand &MO) const { 76 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 77 } 78 79 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 80 // 0-7 and the difference between the 2 groups is given by the REX prefix. 81 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 82 // in 1's complement form, example: 83 // 84 // ModRM field => XMM9 => 1 85 // VEX.VVVV => XMM9 => ~9 86 // 87 // See table 4-35 of Intel AVX Programming Reference for details. 88 unsigned char getVEXRegisterEncoding(const MCInst &MI, 89 unsigned OpNum) const { 90 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 92 if (X86II::isX86_64ExtendedReg(SrcReg)) 93 SrcRegNum |= 8; 94 95 // The registers represented through VEX_VVVV should 96 // be encoded in 1's complement form. 97 return (~SrcRegNum) & 0xf; 98 } 99 100 unsigned char getWriteMaskRegisterEncoding(const MCInst &MI, 101 unsigned OpNum) const { 102 assert(X86::K0 != MI.getOperand(OpNum).getReg() && 103 "Invalid mask register as write-mask!"); 104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum)); 105 return MaskRegNum; 106 } 107 108 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 109 OS << (char)C; 110 ++CurByte; 111 } 112 113 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 114 raw_ostream &OS) const { 115 // Output the constant in little endian byte order. 116 for (unsigned i = 0; i != Size; ++i) { 117 EmitByte(Val & 255, CurByte, OS); 118 Val >>= 8; 119 } 120 } 121 122 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 123 unsigned ImmSize, MCFixupKind FixupKind, 124 unsigned &CurByte, raw_ostream &OS, 125 SmallVectorImpl<MCFixup> &Fixups, 126 int ImmOffset = 0) const; 127 128 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 129 unsigned RM) { 130 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 131 return RM | (RegOpcode << 3) | (Mod << 6); 132 } 133 134 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 135 unsigned &CurByte, raw_ostream &OS) const { 136 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 137 } 138 139 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 140 unsigned &CurByte, raw_ostream &OS) const { 141 // SIB byte is in the same format as the ModRMByte. 142 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 143 } 144 145 146 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 147 unsigned RegOpcodeField, 148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 149 SmallVectorImpl<MCFixup> &Fixups, 150 const MCSubtargetInfo &STI) const; 151 152 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 153 SmallVectorImpl<MCFixup> &Fixups, 154 const MCSubtargetInfo &STI) const override; 155 156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 157 const MCInst &MI, const MCInstrDesc &Desc, 158 raw_ostream &OS) const; 159 160 void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand, 161 const MCInst &MI, raw_ostream &OS) const; 162 163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 164 const MCInst &MI, const MCInstrDesc &Desc, 165 const MCSubtargetInfo &STI, 166 raw_ostream &OS) const; 167}; 168 169} // end anonymous namespace 170 171MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 172 const MCRegisterInfo &MRI, 173 MCContext &Ctx) { 174 return new X86MCCodeEmitter(MCII, Ctx); 175} 176 177/// isDisp8 - Return true if this signed displacement fits in a 8-bit 178/// sign-extended field. 179static bool isDisp8(int Value) { 180 return Value == (signed char)Value; 181} 182 183/// isCDisp8 - Return true if this signed displacement fits in a 8-bit 184/// compressed dispacement field. 185static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { 186 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && 187 "Compressed 8-bit displacement is only valid for EVEX inst."); 188 189 unsigned CD8_Scale = 190 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; 191 if (CD8_Scale == 0) { 192 CValue = Value; 193 return isDisp8(Value); 194 } 195 196 unsigned Mask = CD8_Scale - 1; 197 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size."); 198 if (Value & Mask) // Unaligned offset 199 return false; 200 Value /= (int)CD8_Scale; 201 bool Ret = (Value == (signed char)Value); 202 203 if (Ret) 204 CValue = Value; 205 return Ret; 206} 207 208/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 209/// in an instruction with the specified TSFlags. 210static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 211 unsigned Size = X86II::getSizeOfImm(TSFlags); 212 bool isPCRel = X86II::isImmPCRel(TSFlags); 213 214 if (X86II::isImmSigned(TSFlags)) { 215 switch (Size) { 216 default: llvm_unreachable("Unsupported signed fixup size!"); 217 case 4: return MCFixupKind(X86::reloc_signed_4byte); 218 } 219 } 220 return MCFixup::getKindForSize(Size, isPCRel); 221} 222 223/// Is32BitMemOperand - Return true if the specified instruction has 224/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 225static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 228 229 if ((BaseReg.getReg() != 0 && 230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 231 (IndexReg.getReg() != 0 && 232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 233 return true; 234 return false; 235} 236 237/// Is64BitMemOperand - Return true if the specified instruction has 238/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 239#ifndef NDEBUG 240static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 242 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 243 244 if ((BaseReg.getReg() != 0 && 245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 246 (IndexReg.getReg() != 0 && 247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 248 return true; 249 return false; 250} 251#endif 252 253/// StartsWithGlobalOffsetTable - Check if this expression starts with 254/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 255/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 256/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 257/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 258/// of a binary expression. 259enum GlobalOffsetTableExprKind { 260 GOT_None, 261 GOT_Normal, 262 GOT_SymDiff 263}; 264static GlobalOffsetTableExprKind 265StartsWithGlobalOffsetTable(const MCExpr *Expr) { 266 const MCExpr *RHS = nullptr; 267 if (Expr->getKind() == MCExpr::Binary) { 268 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 269 Expr = BE->getLHS(); 270 RHS = BE->getRHS(); 271 } 272 273 if (Expr->getKind() != MCExpr::SymbolRef) 274 return GOT_None; 275 276 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 277 const MCSymbol &S = Ref->getSymbol(); 278 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 279 return GOT_None; 280 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 281 return GOT_SymDiff; 282 return GOT_Normal; 283} 284 285static bool HasSecRelSymbolRef(const MCExpr *Expr) { 286 if (Expr->getKind() == MCExpr::SymbolRef) { 287 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 288 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 289 } 290 return false; 291} 292 293void X86MCCodeEmitter:: 294EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 295 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 296 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 297 const MCExpr *Expr = nullptr; 298 if (DispOp.isImm()) { 299 // If this is a simple integer displacement that doesn't require a 300 // relocation, emit it now. 301 if (FixupKind != FK_PCRel_1 && 302 FixupKind != FK_PCRel_2 && 303 FixupKind != FK_PCRel_4) { 304 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 305 return; 306 } 307 Expr = MCConstantExpr::create(DispOp.getImm(), Ctx); 308 } else { 309 Expr = DispOp.getExpr(); 310 } 311 312 // If we have an immoffset, add it to the expression. 313 if ((FixupKind == FK_Data_4 || 314 FixupKind == FK_Data_8 || 315 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 316 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 317 if (Kind != GOT_None) { 318 assert(ImmOffset == 0); 319 320 if (Size == 8) { 321 FixupKind = MCFixupKind(X86::reloc_global_offset_table8); 322 } else { 323 assert(Size == 4); 324 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 325 } 326 327 if (Kind == GOT_Normal) 328 ImmOffset = CurByte; 329 } else if (Expr->getKind() == MCExpr::SymbolRef) { 330 if (HasSecRelSymbolRef(Expr)) { 331 FixupKind = MCFixupKind(FK_SecRel_4); 332 } 333 } else if (Expr->getKind() == MCExpr::Binary) { 334 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr); 335 if (HasSecRelSymbolRef(Bin->getLHS()) 336 || HasSecRelSymbolRef(Bin->getRHS())) { 337 FixupKind = MCFixupKind(FK_SecRel_4); 338 } 339 } 340 } 341 342 // If the fixup is pc-relative, we need to bias the value to be relative to 343 // the start of the field, not the end of the field. 344 if (FixupKind == FK_PCRel_4 || 345 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 346 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 347 ImmOffset -= 4; 348 if (FixupKind == FK_PCRel_2) 349 ImmOffset -= 2; 350 if (FixupKind == FK_PCRel_1) 351 ImmOffset -= 1; 352 353 if (ImmOffset) 354 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx), 355 Ctx); 356 357 // Emit a symbolic constant as a fixup and 4 zeros. 358 Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc)); 359 EmitConstant(0, Size, CurByte, OS); 360} 361 362void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 363 unsigned RegOpcodeField, 364 uint64_t TSFlags, unsigned &CurByte, 365 raw_ostream &OS, 366 SmallVectorImpl<MCFixup> &Fixups, 367 const MCSubtargetInfo &STI) const{ 368 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 369 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 370 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 371 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 372 unsigned BaseReg = Base.getReg(); 373 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; 374 375 // Handle %rip relative addressing. 376 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 377 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode"); 378 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 379 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 380 381 unsigned FixupKind = X86::reloc_riprel_4byte; 382 383 // movq loads are handled with a special relocation form which allows the 384 // linker to eliminate some loads for GOT references which end up in the 385 // same linkage unit. 386 if (MI.getOpcode() == X86::MOV64rm) 387 FixupKind = X86::reloc_riprel_4byte_movq_load; 388 389 // rip-relative addressing is actually relative to the *next* instruction. 390 // Since an immediate can follow the mod/rm byte for an instruction, this 391 // means that we need to bias the immediate field of the instruction with 392 // the size of the immediate field. If we have this case, add it into the 393 // expression to emit. 394 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 395 396 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 397 CurByte, OS, Fixups, -ImmSize); 398 return; 399 } 400 401 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 402 403 // 16-bit addressing forms of the ModR/M byte have a different encoding for 404 // the R/M field and are far more limited in which registers can be used. 405 if (Is16BitMemOperand(MI, Op, STI)) { 406 if (BaseReg) { 407 // For 32-bit addressing, the row and column values in Table 2-2 are 408 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with 409 // some special cases. And GetX86RegNum reflects that numbering. 410 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A, 411 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only 412 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order, 413 // while values 0-3 indicate the allowed combinations (base+index) of 414 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI. 415 // 416 // R16Table[] is a lookup from the normal RegNo, to the row values from 417 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed. 418 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 }; 419 unsigned RMfield = R16Table[BaseRegNo]; 420 421 assert(RMfield && "invalid 16-bit base register"); 422 423 if (IndexReg.getReg()) { 424 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)]; 425 426 assert(IndexReg16 && "invalid 16-bit index register"); 427 // We must have one of SI/DI (4,5), and one of BP/BX (6,7). 428 assert(((IndexReg16 ^ RMfield) & 2) && 429 "invalid 16-bit base/index register combination"); 430 assert(Scale.getImm() == 1 && 431 "invalid scale for 16-bit memory reference"); 432 433 // Allow base/index to appear in either order (although GAS doesn't). 434 if (IndexReg16 & 2) 435 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); 436 else 437 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); 438 } 439 440 if (Disp.isImm() && isDisp8(Disp.getImm())) { 441 if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 442 // There is no displacement; just the register. 443 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS); 444 return; 445 } 446 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded. 447 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); 448 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 449 return; 450 } 451 // This is the [REG]+disp16 case. 452 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS); 453 } else { 454 // There is no BaseReg; this is the plain [disp16] case. 455 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS); 456 } 457 458 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases. 459 EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups); 460 return; 461 } 462 463 // Determine whether a SIB byte is needed. 464 // If no BaseReg, issue a RIP relative instruction only if the MCE can 465 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 466 // 2-7) and absolute references. 467 468 if (// The SIB byte must be used if there is an index register. 469 IndexReg.getReg() == 0 && 470 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 471 // encode to an R/M value of 4, which indicates that a SIB byte is 472 // present. 473 BaseRegNo != N86::ESP && 474 // If there is no base register and we're in 64-bit mode, we need a SIB 475 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 476 (!is64BitMode(STI) || BaseReg != 0)) { 477 478 if (BaseReg == 0) { // [disp32] in X86-32 mode 479 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 480 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 481 return; 482 } 483 484 // If the base is not EBP/ESP and there is no displacement, use simple 485 // indirect register encoding, this handles addresses like [EAX]. The 486 // encoding for [EBP] with no displacement means [disp32] so we handle it 487 // by emitting a displacement of 0 below. 488 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 489 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 490 return; 491 } 492 493 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 494 if (Disp.isImm()) { 495 if (!HasEVEX && isDisp8(Disp.getImm())) { 496 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 497 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 498 return; 499 } 500 // Try EVEX compressed 8-bit displacement first; if failed, fall back to 501 // 32-bit displacement. 502 int CDisp8 = 0; 503 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 504 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 505 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 506 CDisp8 - Disp.getImm()); 507 return; 508 } 509 } 510 511 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 512 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 513 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 514 CurByte, OS, Fixups); 515 return; 516 } 517 518 // We need a SIB byte, so start by outputting the ModR/M byte first 519 assert(IndexReg.getReg() != X86::ESP && 520 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 521 522 bool ForceDisp32 = false; 523 bool ForceDisp8 = false; 524 int CDisp8 = 0; 525 int ImmOffset = 0; 526 if (BaseReg == 0) { 527 // If there is no base register, we emit the special case SIB byte with 528 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 529 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 530 ForceDisp32 = true; 531 } else if (!Disp.isImm()) { 532 // Emit the normal disp32 encoding. 533 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 534 ForceDisp32 = true; 535 } else if (Disp.getImm() == 0 && 536 // Base reg can't be anything that ends up with '5' as the base 537 // reg, it is the magic [*] nomenclature that indicates no base. 538 BaseRegNo != N86::EBP) { 539 // Emit no displacement ModR/M byte 540 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 541 } else if (!HasEVEX && isDisp8(Disp.getImm())) { 542 // Emit the disp8 encoding. 543 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 544 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 545 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 546 // Emit the disp8 encoding. 547 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 548 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 549 ImmOffset = CDisp8 - Disp.getImm(); 550 } else { 551 // Emit the normal disp32 encoding. 552 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 553 } 554 555 // Calculate what the SS field value should be... 556 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 557 unsigned SS = SSTable[Scale.getImm()]; 558 559 if (BaseReg == 0) { 560 // Handle the SIB byte for the case where there is no base, see Intel 561 // Manual 2A, table 2-7. The displacement has already been output. 562 unsigned IndexRegNo; 563 if (IndexReg.getReg()) 564 IndexRegNo = GetX86RegNum(IndexReg); 565 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 566 IndexRegNo = 4; 567 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 568 } else { 569 unsigned IndexRegNo; 570 if (IndexReg.getReg()) 571 IndexRegNo = GetX86RegNum(IndexReg); 572 else 573 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 574 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 575 } 576 577 // Do we need to output a displacement? 578 if (ForceDisp8) 579 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset); 580 else if (ForceDisp32 || Disp.getImm() != 0) 581 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 582 CurByte, OS, Fixups); 583} 584 585/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 586/// called VEX. 587void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 588 int MemOperand, const MCInst &MI, 589 const MCInstrDesc &Desc, 590 raw_ostream &OS) const { 591 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX."); 592 593 uint64_t Encoding = TSFlags & X86II::EncodingMask; 594 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 595 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 596 bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3; 597 bool HasMemOp4 = TSFlags & X86II::MemOp4; 598 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 599 600 // VEX_R: opcode externsion equivalent to REX.R in 601 // 1's complement (inverted) form 602 // 603 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 604 // 0: Same as REX_R=1 (64 bit mode only) 605 // 606 unsigned char VEX_R = 0x1; 607 unsigned char EVEX_R2 = 0x1; 608 609 // VEX_X: equivalent to REX.X, only used when a 610 // register is used for index in SIB Byte. 611 // 612 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 613 // 0: Same as REX.X=1 (64-bit mode only) 614 unsigned char VEX_X = 0x1; 615 616 // VEX_B: 617 // 618 // 1: Same as REX_B=0 (ignored in 32-bit mode) 619 // 0: Same as REX_B=1 (64 bit mode only) 620 // 621 unsigned char VEX_B = 0x1; 622 623 // VEX_W: opcode specific (use like REX.W, or used for 624 // opcode extension, or ignored, depending on the opcode byte) 625 unsigned char VEX_W = 0; 626 627 // VEX_5M (VEX m-mmmmm field): 628 // 629 // 0b00000: Reserved for future use 630 // 0b00001: implied 0F leading opcode 631 // 0b00010: implied 0F 38 leading opcode bytes 632 // 0b00011: implied 0F 3A leading opcode bytes 633 // 0b00100-0b11111: Reserved for future use 634 // 0b01000: XOP map select - 08h instructions with imm byte 635 // 0b01001: XOP map select - 09h instructions with no imm byte 636 // 0b01010: XOP map select - 0Ah instructions with imm dword 637 unsigned char VEX_5M = 0; 638 639 // VEX_4V (VEX vvvv field): a register specifier 640 // (in 1's complement form) or 1111 if unused. 641 unsigned char VEX_4V = 0xf; 642 unsigned char EVEX_V2 = 0x1; 643 644 // VEX_L (Vector Length): 645 // 646 // 0: scalar or 128-bit vector 647 // 1: 256-bit vector 648 // 649 unsigned char VEX_L = 0; 650 unsigned char EVEX_L2 = 0; 651 652 // VEX_PP: opcode extension providing equivalent 653 // functionality of a SIMD prefix 654 // 655 // 0b00: None 656 // 0b01: 66 657 // 0b10: F3 658 // 0b11: F2 659 // 660 unsigned char VEX_PP = 0; 661 662 // EVEX_U 663 unsigned char EVEX_U = 1; // Always '1' so far 664 665 // EVEX_z 666 unsigned char EVEX_z = 0; 667 668 // EVEX_b 669 unsigned char EVEX_b = 0; 670 671 // EVEX_rc 672 unsigned char EVEX_rc = 0; 673 674 // EVEX_aaa 675 unsigned char EVEX_aaa = 0; 676 677 bool EncodeRC = false; 678 679 if (TSFlags & X86II::VEX_W) 680 VEX_W = 1; 681 682 if (TSFlags & X86II::VEX_L) 683 VEX_L = 1; 684 if (TSFlags & X86II::EVEX_L2) 685 EVEX_L2 = 1; 686 687 if (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) 688 EVEX_z = 1; 689 690 if ((TSFlags & X86II::EVEX_B)) 691 EVEX_b = 1; 692 693 switch (TSFlags & X86II::OpPrefixMask) { 694 default: break; // VEX_PP already correct 695 case X86II::PD: VEX_PP = 0x1; break; // 66 696 case X86II::XS: VEX_PP = 0x2; break; // F3 697 case X86II::XD: VEX_PP = 0x3; break; // F2 698 } 699 700 switch (TSFlags & X86II::OpMapMask) { 701 default: llvm_unreachable("Invalid prefix!"); 702 case X86II::TB: VEX_5M = 0x1; break; // 0F 703 case X86II::T8: VEX_5M = 0x2; break; // 0F 38 704 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A 705 case X86II::XOP8: VEX_5M = 0x8; break; 706 case X86II::XOP9: VEX_5M = 0x9; break; 707 case X86II::XOPA: VEX_5M = 0xA; break; 708 } 709 710 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 711 unsigned NumOps = Desc.getNumOperands(); 712 unsigned CurOp = X86II::getOperandBias(Desc); 713 714 switch (TSFlags & X86II::FormMask) { 715 default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!"); 716 case X86II::RawFrm: 717 break; 718 case X86II::MRMDestMem: { 719 // MRMDestMem instructions forms: 720 // MemAddr, src1(ModR/M) 721 // MemAddr, src1(VEX_4V), src2(ModR/M) 722 // MemAddr, src1(ModR/M), imm8 723 // 724 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 725 X86::AddrBaseReg).getReg())) 726 VEX_B = 0x0; 727 if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand + 728 X86::AddrIndexReg).getReg())) 729 VEX_X = 0x0; 730 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand + 731 X86::AddrIndexReg).getReg())) 732 EVEX_V2 = 0x0; 733 734 CurOp += X86::AddrNumOperands; 735 736 if (HasEVEX_K) 737 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 738 739 if (HasVEX_4V) { 740 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 741 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 742 EVEX_V2 = 0x0; 743 CurOp++; 744 } 745 746 const MCOperand &MO = MI.getOperand(CurOp); 747 if (MO.isReg()) { 748 if (X86II::isX86_64ExtendedReg(MO.getReg())) 749 VEX_R = 0x0; 750 if (X86II::is32ExtendedReg(MO.getReg())) 751 EVEX_R2 = 0x0; 752 } 753 break; 754 } 755 case X86II::MRMSrcMem: 756 // MRMSrcMem instructions forms: 757 // src1(ModR/M), MemAddr 758 // src1(ModR/M), src2(VEX_4V), MemAddr 759 // src1(ModR/M), MemAddr, imm8 760 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 761 // 762 // FMA4: 763 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 764 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 765 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 766 VEX_R = 0x0; 767 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 768 EVEX_R2 = 0x0; 769 CurOp++; 770 771 if (HasEVEX_K) 772 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 773 774 if (HasVEX_4V) { 775 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 776 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 777 EVEX_V2 = 0x0; 778 CurOp++; 779 } 780 781 if (X86II::isX86_64ExtendedReg( 782 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 783 VEX_B = 0x0; 784 if (X86II::isX86_64ExtendedReg( 785 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 786 VEX_X = 0x0; 787 if (X86II::is32ExtendedReg(MI.getOperand(MemOperand + 788 X86::AddrIndexReg).getReg())) 789 EVEX_V2 = 0x0; 790 791 if (HasVEX_4VOp3) 792 // Instruction format for 4VOp3: 793 // src1(ModR/M), MemAddr, src3(VEX_4V) 794 // CurOp points to start of the MemoryOperand, 795 // it skips TIED_TO operands if exist, then increments past src1. 796 // CurOp + X86::AddrNumOperands will point to src3. 797 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 798 break; 799 case X86II::MRM0m: case X86II::MRM1m: 800 case X86II::MRM2m: case X86II::MRM3m: 801 case X86II::MRM4m: case X86II::MRM5m: 802 case X86II::MRM6m: case X86II::MRM7m: { 803 // MRM[0-9]m instructions forms: 804 // MemAddr 805 // src1(VEX_4V), MemAddr 806 if (HasVEX_4V) { 807 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 808 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 809 EVEX_V2 = 0x0; 810 CurOp++; 811 } 812 813 if (HasEVEX_K) 814 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 815 816 if (X86II::isX86_64ExtendedReg( 817 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 818 VEX_B = 0x0; 819 if (X86II::isX86_64ExtendedReg( 820 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 821 VEX_X = 0x0; 822 break; 823 } 824 case X86II::MRMSrcReg: 825 // MRMSrcReg instructions forms: 826 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 827 // dst(ModR/M), src1(ModR/M) 828 // dst(ModR/M), src1(ModR/M), imm8 829 // 830 // FMA4: 831 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 832 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 833 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 834 VEX_R = 0x0; 835 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 836 EVEX_R2 = 0x0; 837 CurOp++; 838 839 if (HasEVEX_K) 840 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 841 842 if (HasVEX_4V) { 843 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 844 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 845 EVEX_V2 = 0x0; 846 CurOp++; 847 } 848 849 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 850 CurOp++; 851 852 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 853 VEX_B = 0x0; 854 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 855 VEX_X = 0x0; 856 CurOp++; 857 if (HasVEX_4VOp3) 858 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 859 if (EVEX_b) { 860 if (HasEVEX_RC) { 861 unsigned RcOperand = NumOps-1; 862 assert(RcOperand >= CurOp); 863 EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3; 864 } 865 EncodeRC = true; 866 } 867 break; 868 case X86II::MRMDestReg: 869 // MRMDestReg instructions forms: 870 // dst(ModR/M), src(ModR/M) 871 // dst(ModR/M), src(ModR/M), imm8 872 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 873 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 874 VEX_B = 0x0; 875 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 876 VEX_X = 0x0; 877 CurOp++; 878 879 if (HasEVEX_K) 880 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 881 882 if (HasVEX_4V) { 883 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 884 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 885 EVEX_V2 = 0x0; 886 CurOp++; 887 } 888 889 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 890 VEX_R = 0x0; 891 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 892 EVEX_R2 = 0x0; 893 if (EVEX_b) 894 EncodeRC = true; 895 break; 896 case X86II::MRM0r: case X86II::MRM1r: 897 case X86II::MRM2r: case X86II::MRM3r: 898 case X86II::MRM4r: case X86II::MRM5r: 899 case X86II::MRM6r: case X86II::MRM7r: 900 // MRM0r-MRM7r instructions forms: 901 // dst(VEX_4V), src(ModR/M), imm8 902 if (HasVEX_4V) { 903 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 904 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 905 EVEX_V2 = 0x0; 906 CurOp++; 907 } 908 if (HasEVEX_K) 909 EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); 910 911 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 912 VEX_B = 0x0; 913 if (X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) 914 VEX_X = 0x0; 915 break; 916 } 917 918 if (Encoding == X86II::VEX || Encoding == X86II::XOP) { 919 // VEX opcode prefix can have 2 or 3 bytes 920 // 921 // 3 bytes: 922 // +-----+ +--------------+ +-------------------+ 923 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 924 // +-----+ +--------------+ +-------------------+ 925 // 2 bytes: 926 // +-----+ +-------------------+ 927 // | C5h | | R | vvvv | L | pp | 928 // +-----+ +-------------------+ 929 // 930 // XOP uses a similar prefix: 931 // +-----+ +--------------+ +-------------------+ 932 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp | 933 // +-----+ +--------------+ +-------------------+ 934 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 935 936 // Can we use the 2 byte VEX prefix? 937 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { 938 EmitByte(0xC5, CurByte, OS); 939 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 940 return; 941 } 942 943 // 3 byte VEX prefix 944 EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS); 945 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 946 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 947 } else { 948 assert(Encoding == X86II::EVEX && "unknown encoding!"); 949 // EVEX opcode prefix can have 4 bytes 950 // 951 // +-----+ +--------------+ +-------------------+ +------------------------+ 952 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 953 // +-----+ +--------------+ +-------------------+ +------------------------+ 954 assert((VEX_5M & 0x3) == VEX_5M 955 && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 956 957 VEX_5M &= 0x3; 958 959 EmitByte(0x62, CurByte, OS); 960 EmitByte((VEX_R << 7) | 961 (VEX_X << 6) | 962 (VEX_B << 5) | 963 (EVEX_R2 << 4) | 964 VEX_5M, CurByte, OS); 965 EmitByte((VEX_W << 7) | 966 (VEX_4V << 3) | 967 (EVEX_U << 2) | 968 VEX_PP, CurByte, OS); 969 if (EncodeRC) 970 EmitByte((EVEX_z << 7) | 971 (EVEX_rc << 5) | 972 (EVEX_b << 4) | 973 (EVEX_V2 << 3) | 974 EVEX_aaa, CurByte, OS); 975 else 976 EmitByte((EVEX_z << 7) | 977 (EVEX_L2 << 6) | 978 (VEX_L << 5) | 979 (EVEX_b << 4) | 980 (EVEX_V2 << 3) | 981 EVEX_aaa, CurByte, OS); 982 } 983} 984 985/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 986/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 987/// size, and 3) use of X86-64 extended registers. 988static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 989 const MCInstrDesc &Desc) { 990 unsigned REX = 0; 991 bool UsesHighByteReg = false; 992 993 if (TSFlags & X86II::REX_W) 994 REX |= 1 << 3; // set REX.W 995 996 if (MI.getNumOperands() == 0) return REX; 997 998 unsigned NumOps = MI.getNumOperands(); 999 // FIXME: MCInst should explicitize the two-addrness. 1000 bool isTwoAddr = NumOps > 1 && 1001 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 1002 1003 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 1004 unsigned i = isTwoAddr ? 1 : 0; 1005 for (; i != NumOps; ++i) { 1006 const MCOperand &MO = MI.getOperand(i); 1007 if (!MO.isReg()) continue; 1008 unsigned Reg = MO.getReg(); 1009 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) 1010 UsesHighByteReg = true; 1011 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 1012 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 1013 // that returns non-zero. 1014 REX |= 0x40; // REX fixed encoding prefix 1015 break; 1016 } 1017 1018 switch (TSFlags & X86II::FormMask) { 1019 case X86II::MRMSrcReg: 1020 if (MI.getOperand(0).isReg() && 1021 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1022 REX |= 1 << 2; // set REX.R 1023 i = isTwoAddr ? 2 : 1; 1024 for (; i != NumOps; ++i) { 1025 const MCOperand &MO = MI.getOperand(i); 1026 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 1027 REX |= 1 << 0; // set REX.B 1028 } 1029 break; 1030 case X86II::MRMSrcMem: { 1031 if (MI.getOperand(0).isReg() && 1032 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1033 REX |= 1 << 2; // set REX.R 1034 unsigned Bit = 0; 1035 i = isTwoAddr ? 2 : 1; 1036 for (; i != NumOps; ++i) { 1037 const MCOperand &MO = MI.getOperand(i); 1038 if (MO.isReg()) { 1039 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1040 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 1041 Bit++; 1042 } 1043 } 1044 break; 1045 } 1046 case X86II::MRMXm: 1047 case X86II::MRM0m: case X86II::MRM1m: 1048 case X86II::MRM2m: case X86II::MRM3m: 1049 case X86II::MRM4m: case X86II::MRM5m: 1050 case X86II::MRM6m: case X86II::MRM7m: 1051 case X86II::MRMDestMem: { 1052 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 1053 i = isTwoAddr ? 1 : 0; 1054 if (NumOps > e && MI.getOperand(e).isReg() && 1055 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 1056 REX |= 1 << 2; // set REX.R 1057 unsigned Bit = 0; 1058 for (; i != e; ++i) { 1059 const MCOperand &MO = MI.getOperand(i); 1060 if (MO.isReg()) { 1061 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1062 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 1063 Bit++; 1064 } 1065 } 1066 break; 1067 } 1068 default: 1069 if (MI.getOperand(0).isReg() && 1070 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1071 REX |= 1 << 0; // set REX.B 1072 i = isTwoAddr ? 2 : 1; 1073 for (unsigned e = NumOps; i != e; ++i) { 1074 const MCOperand &MO = MI.getOperand(i); 1075 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 1076 REX |= 1 << 2; // set REX.R 1077 } 1078 break; 1079 } 1080 if (REX && UsesHighByteReg) 1081 report_fatal_error("Cannot encode high byte register in REX-prefixed instruction"); 1082 1083 return REX; 1084} 1085 1086/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 1087void X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte, 1088 unsigned SegOperand, 1089 const MCInst &MI, 1090 raw_ostream &OS) const { 1091 // Check for explicit segment override on memory operand. 1092 switch (MI.getOperand(SegOperand).getReg()) { 1093 default: llvm_unreachable("Unknown segment register!"); 1094 case 0: break; 1095 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 1096 case X86::SS: EmitByte(0x36, CurByte, OS); break; 1097 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 1098 case X86::ES: EmitByte(0x26, CurByte, OS); break; 1099 case X86::FS: EmitByte(0x64, CurByte, OS); break; 1100 case X86::GS: EmitByte(0x65, CurByte, OS); break; 1101 } 1102} 1103 1104/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 1105/// 1106/// MemOperand is the operand # of the start of a memory operand if present. If 1107/// Not present, it is -1. 1108void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1109 int MemOperand, const MCInst &MI, 1110 const MCInstrDesc &Desc, 1111 const MCSubtargetInfo &STI, 1112 raw_ostream &OS) const { 1113 1114 // Emit the operand size opcode prefix as needed. 1115 if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32 1116 : X86II::OpSize16)) 1117 EmitByte(0x66, CurByte, OS); 1118 1119 // Emit the LOCK opcode prefix. 1120 if (TSFlags & X86II::LOCK) 1121 EmitByte(0xF0, CurByte, OS); 1122 1123 switch (TSFlags & X86II::OpPrefixMask) { 1124 case X86II::PD: // 66 1125 EmitByte(0x66, CurByte, OS); 1126 break; 1127 case X86II::XS: // F3 1128 EmitByte(0xF3, CurByte, OS); 1129 break; 1130 case X86II::XD: // F2 1131 EmitByte(0xF2, CurByte, OS); 1132 break; 1133 } 1134 1135 // Handle REX prefix. 1136 // FIXME: Can this come before F2 etc to simplify emission? 1137 if (is64BitMode(STI)) { 1138 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 1139 EmitByte(0x40 | REX, CurByte, OS); 1140 } 1141 1142 // 0x0F escape code must be emitted just before the opcode. 1143 switch (TSFlags & X86II::OpMapMask) { 1144 case X86II::TB: // Two-byte opcode map 1145 case X86II::T8: // 0F 38 1146 case X86II::TA: // 0F 3A 1147 EmitByte(0x0F, CurByte, OS); 1148 break; 1149 } 1150 1151 switch (TSFlags & X86II::OpMapMask) { 1152 case X86II::T8: // 0F 38 1153 EmitByte(0x38, CurByte, OS); 1154 break; 1155 case X86II::TA: // 0F 3A 1156 EmitByte(0x3A, CurByte, OS); 1157 break; 1158 } 1159} 1160 1161void X86MCCodeEmitter:: 1162encodeInstruction(const MCInst &MI, raw_ostream &OS, 1163 SmallVectorImpl<MCFixup> &Fixups, 1164 const MCSubtargetInfo &STI) const { 1165 unsigned Opcode = MI.getOpcode(); 1166 const MCInstrDesc &Desc = MCII.get(Opcode); 1167 uint64_t TSFlags = Desc.TSFlags; 1168 1169 // Pseudo instructions don't get encoded. 1170 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1171 return; 1172 1173 unsigned NumOps = Desc.getNumOperands(); 1174 unsigned CurOp = X86II::getOperandBias(Desc); 1175 1176 // Keep track of the current byte being emitted. 1177 unsigned CurByte = 0; 1178 1179 // Encoding type for this instruction. 1180 uint64_t Encoding = TSFlags & X86II::EncodingMask; 1181 1182 // It uses the VEX.VVVV field? 1183 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1184 bool HasVEX_4VOp3 = TSFlags & X86II::VEX_4VOp3; 1185 bool HasMemOp4 = TSFlags & X86II::MemOp4; 1186 const unsigned MemOp4_I8IMMOperand = 2; 1187 1188 // It uses the EVEX.aaa field? 1189 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1190 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 1191 1192 // Determine where the memory operand starts, if present. 1193 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1194 if (MemoryOperand != -1) MemoryOperand += CurOp; 1195 1196 // Emit segment override opcode prefix as needed. 1197 if (MemoryOperand >= 0) 1198 EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg, 1199 MI, OS); 1200 1201 // Emit the repeat opcode prefix as needed. 1202 if (TSFlags & X86II::REP) 1203 EmitByte(0xF3, CurByte, OS); 1204 1205 // Emit the address size opcode prefix as needed. 1206 bool need_address_override; 1207 uint64_t AdSize = TSFlags & X86II::AdSizeMask; 1208 if ((is16BitMode(STI) && AdSize == X86II::AdSize32) || 1209 (is32BitMode(STI) && AdSize == X86II::AdSize16) || 1210 (is64BitMode(STI) && AdSize == X86II::AdSize32)) { 1211 need_address_override = true; 1212 } else if (MemoryOperand < 0) { 1213 need_address_override = false; 1214 } else if (is64BitMode(STI)) { 1215 assert(!Is16BitMemOperand(MI, MemoryOperand, STI)); 1216 need_address_override = Is32BitMemOperand(MI, MemoryOperand); 1217 } else if (is32BitMode(STI)) { 1218 assert(!Is64BitMemOperand(MI, MemoryOperand)); 1219 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI); 1220 } else { 1221 assert(is16BitMode(STI)); 1222 assert(!Is64BitMemOperand(MI, MemoryOperand)); 1223 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI); 1224 } 1225 1226 if (need_address_override) 1227 EmitByte(0x67, CurByte, OS); 1228 1229 if (Encoding == 0) 1230 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS); 1231 else 1232 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1233 1234 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1235 1236 if (TSFlags & X86II::Has3DNow0F0FOpcode) 1237 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1238 1239 unsigned SrcRegNum = 0; 1240 switch (TSFlags & X86II::FormMask) { 1241 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1242 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1243 case X86II::Pseudo: 1244 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1245 case X86II::RawFrmDstSrc: { 1246 unsigned siReg = MI.getOperand(1).getReg(); 1247 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 1248 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 1249 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 1250 "SI and DI register sizes do not match"); 1251 // Emit segment override opcode prefix as needed (not for %ds). 1252 if (MI.getOperand(2).getReg() != X86::DS) 1253 EmitSegmentOverridePrefix(CurByte, 2, MI, OS); 1254 // Emit AdSize prefix as needed. 1255 if ((!is32BitMode(STI) && siReg == X86::ESI) || 1256 (is32BitMode(STI) && siReg == X86::SI)) 1257 EmitByte(0x67, CurByte, OS); 1258 CurOp += 3; // Consume operands. 1259 EmitByte(BaseOpcode, CurByte, OS); 1260 break; 1261 } 1262 case X86II::RawFrmSrc: { 1263 unsigned siReg = MI.getOperand(0).getReg(); 1264 // Emit segment override opcode prefix as needed (not for %ds). 1265 if (MI.getOperand(1).getReg() != X86::DS) 1266 EmitSegmentOverridePrefix(CurByte, 1, MI, OS); 1267 // Emit AdSize prefix as needed. 1268 if ((!is32BitMode(STI) && siReg == X86::ESI) || 1269 (is32BitMode(STI) && siReg == X86::SI)) 1270 EmitByte(0x67, CurByte, OS); 1271 CurOp += 2; // Consume operands. 1272 EmitByte(BaseOpcode, CurByte, OS); 1273 break; 1274 } 1275 case X86II::RawFrmDst: { 1276 unsigned siReg = MI.getOperand(0).getReg(); 1277 // Emit AdSize prefix as needed. 1278 if ((!is32BitMode(STI) && siReg == X86::EDI) || 1279 (is32BitMode(STI) && siReg == X86::DI)) 1280 EmitByte(0x67, CurByte, OS); 1281 ++CurOp; // Consume operand. 1282 EmitByte(BaseOpcode, CurByte, OS); 1283 break; 1284 } 1285 case X86II::RawFrm: 1286 EmitByte(BaseOpcode, CurByte, OS); 1287 break; 1288 case X86II::RawFrmMemOffs: 1289 // Emit segment override opcode prefix as needed. 1290 EmitSegmentOverridePrefix(CurByte, 1, MI, OS); 1291 EmitByte(BaseOpcode, CurByte, OS); 1292 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1293 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1294 CurByte, OS, Fixups); 1295 ++CurOp; // skip segment operand 1296 break; 1297 case X86II::RawFrmImm8: 1298 EmitByte(BaseOpcode, CurByte, OS); 1299 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1300 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1301 CurByte, OS, Fixups); 1302 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1303 OS, Fixups); 1304 break; 1305 case X86II::RawFrmImm16: 1306 EmitByte(BaseOpcode, CurByte, OS); 1307 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1308 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1309 CurByte, OS, Fixups); 1310 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1311 OS, Fixups); 1312 break; 1313 1314 case X86II::AddRegFrm: 1315 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1316 break; 1317 1318 case X86II::MRMDestReg: 1319 EmitByte(BaseOpcode, CurByte, OS); 1320 SrcRegNum = CurOp + 1; 1321 1322 if (HasEVEX_K) // Skip writemask 1323 SrcRegNum++; 1324 1325 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1326 ++SrcRegNum; 1327 1328 EmitRegModRMByte(MI.getOperand(CurOp), 1329 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1330 CurOp = SrcRegNum + 1; 1331 break; 1332 1333 case X86II::MRMDestMem: 1334 EmitByte(BaseOpcode, CurByte, OS); 1335 SrcRegNum = CurOp + X86::AddrNumOperands; 1336 1337 if (HasEVEX_K) // Skip writemask 1338 SrcRegNum++; 1339 1340 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1341 ++SrcRegNum; 1342 1343 EmitMemModRMByte(MI, CurOp, 1344 GetX86RegNum(MI.getOperand(SrcRegNum)), 1345 TSFlags, CurByte, OS, Fixups, STI); 1346 CurOp = SrcRegNum + 1; 1347 break; 1348 1349 case X86II::MRMSrcReg: 1350 EmitByte(BaseOpcode, CurByte, OS); 1351 SrcRegNum = CurOp + 1; 1352 1353 if (HasEVEX_K) // Skip writemask 1354 SrcRegNum++; 1355 1356 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1357 ++SrcRegNum; 1358 1359 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1360 ++SrcRegNum; 1361 1362 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1363 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1364 1365 // 2 operands skipped with HasMemOp4, compensate accordingly 1366 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1367 if (HasVEX_4VOp3) 1368 ++CurOp; 1369 // do not count the rounding control operand 1370 if (HasEVEX_RC) 1371 NumOps--; 1372 break; 1373 1374 case X86II::MRMSrcMem: { 1375 int AddrOperands = X86::AddrNumOperands; 1376 unsigned FirstMemOp = CurOp+1; 1377 1378 if (HasEVEX_K) { // Skip writemask 1379 ++AddrOperands; 1380 ++FirstMemOp; 1381 } 1382 1383 if (HasVEX_4V) { 1384 ++AddrOperands; 1385 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1386 } 1387 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1388 ++FirstMemOp; 1389 1390 EmitByte(BaseOpcode, CurByte, OS); 1391 1392 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1393 TSFlags, CurByte, OS, Fixups, STI); 1394 CurOp += AddrOperands + 1; 1395 if (HasVEX_4VOp3) 1396 ++CurOp; 1397 break; 1398 } 1399 1400 case X86II::MRMXr: 1401 case X86II::MRM0r: case X86II::MRM1r: 1402 case X86II::MRM2r: case X86II::MRM3r: 1403 case X86II::MRM4r: case X86II::MRM5r: 1404 case X86II::MRM6r: case X86II::MRM7r: { 1405 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1406 ++CurOp; 1407 if (HasEVEX_K) // Skip writemask 1408 ++CurOp; 1409 EmitByte(BaseOpcode, CurByte, OS); 1410 uint64_t Form = TSFlags & X86II::FormMask; 1411 EmitRegModRMByte(MI.getOperand(CurOp++), 1412 (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, 1413 CurByte, OS); 1414 break; 1415 } 1416 1417 case X86II::MRMXm: 1418 case X86II::MRM0m: case X86II::MRM1m: 1419 case X86II::MRM2m: case X86II::MRM3m: 1420 case X86II::MRM4m: case X86II::MRM5m: 1421 case X86II::MRM6m: case X86II::MRM7m: { 1422 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1423 ++CurOp; 1424 if (HasEVEX_K) // Skip writemask 1425 ++CurOp; 1426 EmitByte(BaseOpcode, CurByte, OS); 1427 uint64_t Form = TSFlags & X86II::FormMask; 1428 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m, 1429 TSFlags, CurByte, OS, Fixups, STI); 1430 CurOp += X86::AddrNumOperands; 1431 break; 1432 } 1433 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1434 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 1435 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 1436 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1437 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 1438 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 1439 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 1440 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 1441 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 1442 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 1443 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 1444 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 1445 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 1446 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 1447 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1448 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 1449 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 1450 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 1451 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 1452 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 1453 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 1454 case X86II::MRM_FF: 1455 EmitByte(BaseOpcode, CurByte, OS); 1456 1457 uint64_t Form = TSFlags & X86II::FormMask; 1458 EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS); 1459 break; 1460 } 1461 1462 // If there is a remaining operand, it must be a trailing immediate. Emit it 1463 // according to the right size for the instruction. Some instructions 1464 // (SSE4a extrq and insertq) have two trailing immediates. 1465 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1466 // The last source register of a 4 operand instruction in AVX is encoded 1467 // in bits[7:4] of a immediate byte. 1468 if (TSFlags & X86II::VEX_I8IMM) { 1469 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1470 : CurOp); 1471 ++CurOp; 1472 unsigned RegNum = GetX86RegNum(MO) << 4; 1473 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1474 RegNum |= 1 << 7; 1475 // If there is an additional 5th operand it must be an immediate, which 1476 // is encoded in bits[3:0] 1477 if (CurOp != NumOps) { 1478 const MCOperand &MIMM = MI.getOperand(CurOp++); 1479 if (MIMM.isImm()) { 1480 unsigned Val = MIMM.getImm(); 1481 assert(Val < 16 && "Immediate operand value out of range"); 1482 RegNum |= Val; 1483 } 1484 } 1485 EmitImmediate(MCOperand::createImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1486 CurByte, OS, Fixups); 1487 } else { 1488 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1489 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1490 CurByte, OS, Fixups); 1491 } 1492 } 1493 1494 if (TSFlags & X86II::Has3DNow0F0FOpcode) 1495 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1496 1497#ifndef NDEBUG 1498 // FIXME: Verify. 1499 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1500 errs() << "Cannot encode all operands of: "; 1501 MI.dump(); 1502 errs() << '\n'; 1503 abort(); 1504 } 1505#endif 1506} 1507