X86MCCodeEmitter.cpp revision 251662
1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the X86MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/X86MCTargetDesc.h" 16#include "MCTargetDesc/X86BaseInfo.h" 17#include "MCTargetDesc/X86FixupKinds.h" 18#include "llvm/MC/MCCodeEmitter.h" 19#include "llvm/MC/MCContext.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCInst.h" 22#include "llvm/MC/MCInstrInfo.h" 23#include "llvm/MC/MCRegisterInfo.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MCSymbol.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30namespace { 31class X86MCCodeEmitter : public MCCodeEmitter { 32 X86MCCodeEmitter(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 33 void operator=(const X86MCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 const MCInstrInfo &MCII; 35 const MCSubtargetInfo &STI; 36 MCContext &Ctx; 37public: 38 X86MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 39 MCContext &ctx) 40 : MCII(mcii), STI(sti), Ctx(ctx) { 41 } 42 43 ~X86MCCodeEmitter() {} 44 45 bool is64BitMode() const { 46 // FIXME: Can tablegen auto-generate this? 47 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; 48 } 49 50 bool is32BitMode() const { 51 // FIXME: Can tablegen auto-generate this? 52 return (STI.getFeatureBits() & X86::Mode64Bit) == 0; 53 } 54 55 unsigned GetX86RegNum(const MCOperand &MO) const { 56 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7; 57 } 58 59 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 60 // 0-7 and the difference between the 2 groups is given by the REX prefix. 61 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded 62 // in 1's complement form, example: 63 // 64 // ModRM field => XMM9 => 1 65 // VEX.VVVV => XMM9 => ~9 66 // 67 // See table 4-35 of Intel AVX Programming Reference for details. 68 unsigned char getVEXRegisterEncoding(const MCInst &MI, 69 unsigned OpNum) const { 70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); 71 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); 72 if (X86II::isX86_64ExtendedReg(SrcReg)) 73 SrcRegNum |= 8; 74 75 // The registers represented through VEX_VVVV should 76 // be encoded in 1's complement form. 77 return (~SrcRegNum) & 0xf; 78 } 79 80 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const { 81 OS << (char)C; 82 ++CurByte; 83 } 84 85 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 86 raw_ostream &OS) const { 87 // Output the constant in little endian byte order. 88 for (unsigned i = 0; i != Size; ++i) { 89 EmitByte(Val & 255, CurByte, OS); 90 Val >>= 8; 91 } 92 } 93 94 void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 95 unsigned ImmSize, MCFixupKind FixupKind, 96 unsigned &CurByte, raw_ostream &OS, 97 SmallVectorImpl<MCFixup> &Fixups, 98 int ImmOffset = 0) const; 99 100 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 101 unsigned RM) { 102 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 103 return RM | (RegOpcode << 3) | (Mod << 6); 104 } 105 106 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 107 unsigned &CurByte, raw_ostream &OS) const { 108 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 109 } 110 111 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 112 unsigned &CurByte, raw_ostream &OS) const { 113 // SIB byte is in the same format as the ModRMByte. 114 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 115 } 116 117 118 void EmitMemModRMByte(const MCInst &MI, unsigned Op, 119 unsigned RegOpcodeField, 120 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS, 121 SmallVectorImpl<MCFixup> &Fixups) const; 122 123 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 124 SmallVectorImpl<MCFixup> &Fixups) const; 125 126 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 127 const MCInst &MI, const MCInstrDesc &Desc, 128 raw_ostream &OS) const; 129 130 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, 131 int MemOperand, const MCInst &MI, 132 raw_ostream &OS) const; 133 134 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 135 const MCInst &MI, const MCInstrDesc &Desc, 136 raw_ostream &OS) const; 137}; 138 139} // end anonymous namespace 140 141 142MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 143 const MCRegisterInfo &MRI, 144 const MCSubtargetInfo &STI, 145 MCContext &Ctx) { 146 return new X86MCCodeEmitter(MCII, STI, Ctx); 147} 148 149/// isDisp8 - Return true if this signed displacement fits in a 8-bit 150/// sign-extended field. 151static bool isDisp8(int Value) { 152 return Value == (signed char)Value; 153} 154 155/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 156/// in an instruction with the specified TSFlags. 157static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 158 unsigned Size = X86II::getSizeOfImm(TSFlags); 159 bool isPCRel = X86II::isImmPCRel(TSFlags); 160 161 return MCFixup::getKindForSize(Size, isPCRel); 162} 163 164/// Is32BitMemOperand - Return true if the specified instruction has 165/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 166static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 168 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 169 170 if ((BaseReg.getReg() != 0 && 171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 172 (IndexReg.getReg() != 0 && 173 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 174 return true; 175 return false; 176} 177 178/// Is64BitMemOperand - Return true if the specified instruction has 179/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 180#ifndef NDEBUG 181static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 183 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 184 185 if ((BaseReg.getReg() != 0 && 186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 187 (IndexReg.getReg() != 0 && 188 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 189 return true; 190 return false; 191} 192#endif 193 194/// Is16BitMemOperand - Return true if the specified instruction has 195/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 196static bool Is16BitMemOperand(const MCInst &MI, unsigned Op) { 197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 198 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 199 200 if ((BaseReg.getReg() != 0 && 201 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 202 (IndexReg.getReg() != 0 && 203 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 204 return true; 205 return false; 206} 207 208/// StartsWithGlobalOffsetTable - Check if this expression starts with 209/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 210/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 211/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 212/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 213/// of a binary expression. 214enum GlobalOffsetTableExprKind { 215 GOT_None, 216 GOT_Normal, 217 GOT_SymDiff 218}; 219static GlobalOffsetTableExprKind 220StartsWithGlobalOffsetTable(const MCExpr *Expr) { 221 const MCExpr *RHS = 0; 222 if (Expr->getKind() == MCExpr::Binary) { 223 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 224 Expr = BE->getLHS(); 225 RHS = BE->getRHS(); 226 } 227 228 if (Expr->getKind() != MCExpr::SymbolRef) 229 return GOT_None; 230 231 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 232 const MCSymbol &S = Ref->getSymbol(); 233 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 234 return GOT_None; 235 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 236 return GOT_SymDiff; 237 return GOT_Normal; 238} 239 240static bool HasSecRelSymbolRef(const MCExpr *Expr) { 241 if (Expr->getKind() == MCExpr::SymbolRef) { 242 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 243 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 244 } 245 return false; 246} 247 248void X86MCCodeEmitter:: 249EmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 250 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 251 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 252 const MCExpr *Expr = NULL; 253 if (DispOp.isImm()) { 254 // If this is a simple integer displacement that doesn't require a 255 // relocation, emit it now. 256 if (FixupKind != FK_PCRel_1 && 257 FixupKind != FK_PCRel_2 && 258 FixupKind != FK_PCRel_4) { 259 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 260 return; 261 } 262 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx); 263 } else { 264 Expr = DispOp.getExpr(); 265 } 266 267 // If we have an immoffset, add it to the expression. 268 if ((FixupKind == FK_Data_4 || 269 FixupKind == FK_Data_8 || 270 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 271 GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 272 if (Kind != GOT_None) { 273 assert(ImmOffset == 0); 274 275 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 276 if (Kind == GOT_Normal) 277 ImmOffset = CurByte; 278 } else if (Expr->getKind() == MCExpr::SymbolRef) { 279 if (HasSecRelSymbolRef(Expr)) { 280 FixupKind = MCFixupKind(FK_SecRel_4); 281 } 282 } else if (Expr->getKind() == MCExpr::Binary) { 283 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr); 284 if (HasSecRelSymbolRef(Bin->getLHS()) 285 || HasSecRelSymbolRef(Bin->getRHS())) { 286 FixupKind = MCFixupKind(FK_SecRel_4); 287 } 288 } 289 } 290 291 // If the fixup is pc-relative, we need to bias the value to be relative to 292 // the start of the field, not the end of the field. 293 if (FixupKind == FK_PCRel_4 || 294 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 295 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load)) 296 ImmOffset -= 4; 297 if (FixupKind == FK_PCRel_2) 298 ImmOffset -= 2; 299 if (FixupKind == FK_PCRel_1) 300 ImmOffset -= 1; 301 302 if (ImmOffset) 303 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx), 304 Ctx); 305 306 // Emit a symbolic constant as a fixup and 4 zeros. 307 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind, Loc)); 308 EmitConstant(0, Size, CurByte, OS); 309} 310 311void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, 312 unsigned RegOpcodeField, 313 uint64_t TSFlags, unsigned &CurByte, 314 raw_ostream &OS, 315 SmallVectorImpl<MCFixup> &Fixups) const{ 316 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 317 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 318 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 319 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 320 unsigned BaseReg = Base.getReg(); 321 322 // Handle %rip relative addressing. 323 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 324 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode"); 325 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 326 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 327 328 unsigned FixupKind = X86::reloc_riprel_4byte; 329 330 // movq loads are handled with a special relocation form which allows the 331 // linker to eliminate some loads for GOT references which end up in the 332 // same linkage unit. 333 if (MI.getOpcode() == X86::MOV64rm) 334 FixupKind = X86::reloc_riprel_4byte_movq_load; 335 336 // rip-relative addressing is actually relative to the *next* instruction. 337 // Since an immediate can follow the mod/rm byte for an instruction, this 338 // means that we need to bias the immediate field of the instruction with 339 // the size of the immediate field. If we have this case, add it into the 340 // expression to emit. 341 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; 342 343 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 344 CurByte, OS, Fixups, -ImmSize); 345 return; 346 } 347 348 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 349 350 // Determine whether a SIB byte is needed. 351 // If no BaseReg, issue a RIP relative instruction only if the MCE can 352 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 353 // 2-7) and absolute references. 354 355 if (// The SIB byte must be used if there is an index register. 356 IndexReg.getReg() == 0 && 357 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 358 // encode to an R/M value of 4, which indicates that a SIB byte is 359 // present. 360 BaseRegNo != N86::ESP && 361 // If there is no base register and we're in 64-bit mode, we need a SIB 362 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 363 (!is64BitMode() || BaseReg != 0)) { 364 365 if (BaseReg == 0) { // [disp32] in X86-32 mode 366 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 367 EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 368 return; 369 } 370 371 // If the base is not EBP/ESP and there is no displacement, use simple 372 // indirect register encoding, this handles addresses like [EAX]. The 373 // encoding for [EBP] with no displacement means [disp32] so we handle it 374 // by emitting a displacement of 0 below. 375 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 376 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 377 return; 378 } 379 380 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 381 if (Disp.isImm() && isDisp8(Disp.getImm())) { 382 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 383 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 384 return; 385 } 386 387 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 388 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 389 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS, 390 Fixups); 391 return; 392 } 393 394 // We need a SIB byte, so start by outputting the ModR/M byte first 395 assert(IndexReg.getReg() != X86::ESP && 396 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 397 398 bool ForceDisp32 = false; 399 bool ForceDisp8 = false; 400 if (BaseReg == 0) { 401 // If there is no base register, we emit the special case SIB byte with 402 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 403 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 404 ForceDisp32 = true; 405 } else if (!Disp.isImm()) { 406 // Emit the normal disp32 encoding. 407 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 408 ForceDisp32 = true; 409 } else if (Disp.getImm() == 0 && 410 // Base reg can't be anything that ends up with '5' as the base 411 // reg, it is the magic [*] nomenclature that indicates no base. 412 BaseRegNo != N86::EBP) { 413 // Emit no displacement ModR/M byte 414 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 415 } else if (isDisp8(Disp.getImm())) { 416 // Emit the disp8 encoding. 417 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 418 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 419 } else { 420 // Emit the normal disp32 encoding. 421 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 422 } 423 424 // Calculate what the SS field value should be... 425 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 426 unsigned SS = SSTable[Scale.getImm()]; 427 428 if (BaseReg == 0) { 429 // Handle the SIB byte for the case where there is no base, see Intel 430 // Manual 2A, table 2-7. The displacement has already been output. 431 unsigned IndexRegNo; 432 if (IndexReg.getReg()) 433 IndexRegNo = GetX86RegNum(IndexReg); 434 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 435 IndexRegNo = 4; 436 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 437 } else { 438 unsigned IndexRegNo; 439 if (IndexReg.getReg()) 440 IndexRegNo = GetX86RegNum(IndexReg); 441 else 442 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 443 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 444 } 445 446 // Do we need to output a displacement? 447 if (ForceDisp8) 448 EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 449 else if (ForceDisp32 || Disp.getImm() != 0) 450 EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 451 CurByte, OS, Fixups); 452} 453 454/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 455/// called VEX. 456void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 457 int MemOperand, const MCInst &MI, 458 const MCInstrDesc &Desc, 459 raw_ostream &OS) const { 460 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 461 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 462 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 463 464 // VEX_R: opcode externsion equivalent to REX.R in 465 // 1's complement (inverted) form 466 // 467 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 468 // 0: Same as REX_R=1 (64 bit mode only) 469 // 470 unsigned char VEX_R = 0x1; 471 472 // VEX_X: equivalent to REX.X, only used when a 473 // register is used for index in SIB Byte. 474 // 475 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 476 // 0: Same as REX.X=1 (64-bit mode only) 477 unsigned char VEX_X = 0x1; 478 479 // VEX_B: 480 // 481 // 1: Same as REX_B=0 (ignored in 32-bit mode) 482 // 0: Same as REX_B=1 (64 bit mode only) 483 // 484 unsigned char VEX_B = 0x1; 485 486 // VEX_W: opcode specific (use like REX.W, or used for 487 // opcode extension, or ignored, depending on the opcode byte) 488 unsigned char VEX_W = 0; 489 490 // XOP: Use XOP prefix byte 0x8f instead of VEX. 491 unsigned char XOP = 0; 492 493 // VEX_5M (VEX m-mmmmm field): 494 // 495 // 0b00000: Reserved for future use 496 // 0b00001: implied 0F leading opcode 497 // 0b00010: implied 0F 38 leading opcode bytes 498 // 0b00011: implied 0F 3A leading opcode bytes 499 // 0b00100-0b11111: Reserved for future use 500 // 0b01000: XOP map select - 08h instructions with imm byte 501 // 0b10001: XOP map select - 09h instructions with no imm byte 502 unsigned char VEX_5M = 0x1; 503 504 // VEX_4V (VEX vvvv field): a register specifier 505 // (in 1's complement form) or 1111 if unused. 506 unsigned char VEX_4V = 0xf; 507 508 // VEX_L (Vector Length): 509 // 510 // 0: scalar or 128-bit vector 511 // 1: 256-bit vector 512 // 513 unsigned char VEX_L = 0; 514 515 // VEX_PP: opcode extension providing equivalent 516 // functionality of a SIMD prefix 517 // 518 // 0b00: None 519 // 0b01: 66 520 // 0b10: F3 521 // 0b11: F2 522 // 523 unsigned char VEX_PP = 0; 524 525 // Encode the operand size opcode prefix as needed. 526 if (TSFlags & X86II::OpSize) 527 VEX_PP = 0x01; 528 529 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 530 VEX_W = 1; 531 532 if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 533 XOP = 1; 534 535 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 536 VEX_L = 1; 537 538 switch (TSFlags & X86II::Op0Mask) { 539 default: llvm_unreachable("Invalid prefix!"); 540 case X86II::T8: // 0F 38 541 VEX_5M = 0x2; 542 break; 543 case X86II::TA: // 0F 3A 544 VEX_5M = 0x3; 545 break; 546 case X86II::T8XS: // F3 0F 38 547 VEX_PP = 0x2; 548 VEX_5M = 0x2; 549 break; 550 case X86II::T8XD: // F2 0F 38 551 VEX_PP = 0x3; 552 VEX_5M = 0x2; 553 break; 554 case X86II::TAXD: // F2 0F 3A 555 VEX_PP = 0x3; 556 VEX_5M = 0x3; 557 break; 558 case X86II::XS: // F3 0F 559 VEX_PP = 0x2; 560 break; 561 case X86II::XD: // F2 0F 562 VEX_PP = 0x3; 563 break; 564 case X86II::XOP8: 565 VEX_5M = 0x8; 566 break; 567 case X86II::XOP9: 568 VEX_5M = 0x9; 569 break; 570 case X86II::A6: // Bypass: Not used by VEX 571 case X86II::A7: // Bypass: Not used by VEX 572 case X86II::TB: // Bypass: Not used by VEX 573 case 0: 574 break; // No prefix! 575 } 576 577 578 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 579 unsigned NumOps = Desc.getNumOperands(); 580 unsigned CurOp = 0; 581 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 582 ++CurOp; 583 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) { 584 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 585 // Special case for GATHER with 2 TIED_TO operands 586 // Skip the first 2 operands: dst, mask_wb 587 CurOp += 2; 588 } 589 590 switch (TSFlags & X86II::FormMask) { 591 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 592 case X86II::MRMDestMem: { 593 // MRMDestMem instructions forms: 594 // MemAddr, src1(ModR/M) 595 // MemAddr, src1(VEX_4V), src2(ModR/M) 596 // MemAddr, src1(ModR/M), imm8 597 // 598 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg())) 599 VEX_B = 0x0; 600 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) 601 VEX_X = 0x0; 602 603 CurOp = X86::AddrNumOperands; 604 if (HasVEX_4V) 605 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 606 607 const MCOperand &MO = MI.getOperand(CurOp); 608 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 609 VEX_R = 0x0; 610 break; 611 } 612 case X86II::MRMSrcMem: 613 // MRMSrcMem instructions forms: 614 // src1(ModR/M), MemAddr 615 // src1(ModR/M), src2(VEX_4V), MemAddr 616 // src1(ModR/M), MemAddr, imm8 617 // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 618 // 619 // FMA4: 620 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 621 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 622 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp++).getReg())) 623 VEX_R = 0x0; 624 625 if (HasVEX_4V) 626 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 627 628 if (X86II::isX86_64ExtendedReg( 629 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 630 VEX_B = 0x0; 631 if (X86II::isX86_64ExtendedReg( 632 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 633 VEX_X = 0x0; 634 635 if (HasVEX_4VOp3) 636 // Instruction format for 4VOp3: 637 // src1(ModR/M), MemAddr, src3(VEX_4V) 638 // CurOp points to start of the MemoryOperand, 639 // it skips TIED_TO operands if exist, then increments past src1. 640 // CurOp + X86::AddrNumOperands will point to src3. 641 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); 642 break; 643 case X86II::MRM0m: case X86II::MRM1m: 644 case X86II::MRM2m: case X86II::MRM3m: 645 case X86II::MRM4m: case X86II::MRM5m: 646 case X86II::MRM6m: case X86II::MRM7m: { 647 // MRM[0-9]m instructions forms: 648 // MemAddr 649 // src1(VEX_4V), MemAddr 650 if (HasVEX_4V) 651 VEX_4V = getVEXRegisterEncoding(MI, 0); 652 653 if (X86II::isX86_64ExtendedReg( 654 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 655 VEX_B = 0x0; 656 if (X86II::isX86_64ExtendedReg( 657 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 658 VEX_X = 0x0; 659 break; 660 } 661 case X86II::MRMSrcReg: 662 // MRMSrcReg instructions forms: 663 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 664 // dst(ModR/M), src1(ModR/M) 665 // dst(ModR/M), src1(ModR/M), imm8 666 // 667 // FMA4: 668 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 669 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 670 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 671 VEX_R = 0x0; 672 CurOp++; 673 674 if (HasVEX_4V) 675 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 676 677 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 678 CurOp++; 679 680 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 681 VEX_B = 0x0; 682 CurOp++; 683 if (HasVEX_4VOp3) 684 VEX_4V = getVEXRegisterEncoding(MI, CurOp); 685 break; 686 case X86II::MRMDestReg: 687 // MRMDestReg instructions forms: 688 // dst(ModR/M), src(ModR/M) 689 // dst(ModR/M), src(ModR/M), imm8 690 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 691 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 692 VEX_B = 0x0; 693 CurOp++; 694 695 if (HasVEX_4V) 696 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 697 698 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 699 VEX_R = 0x0; 700 break; 701 case X86II::MRM0r: case X86II::MRM1r: 702 case X86II::MRM2r: case X86II::MRM3r: 703 case X86II::MRM4r: case X86II::MRM5r: 704 case X86II::MRM6r: case X86II::MRM7r: 705 // MRM0r-MRM7r instructions forms: 706 // dst(VEX_4V), src(ModR/M), imm8 707 VEX_4V = getVEXRegisterEncoding(MI, 0); 708 if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 709 VEX_B = 0x0; 710 break; 711 default: // RawFrm 712 break; 713 } 714 715 // Emit segment override opcode prefix as needed. 716 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 717 718 // VEX opcode prefix can have 2 or 3 bytes 719 // 720 // 3 bytes: 721 // +-----+ +--------------+ +-------------------+ 722 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 723 // +-----+ +--------------+ +-------------------+ 724 // 2 bytes: 725 // +-----+ +-------------------+ 726 // | C5h | | R | vvvv | L | pp | 727 // +-----+ +-------------------+ 728 // 729 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 730 731 if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 732 EmitByte(0xC5, CurByte, OS); 733 EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 734 return; 735 } 736 737 // 3 byte VEX prefix 738 EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS); 739 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 740 EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 741} 742 743/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 744/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 745/// size, and 3) use of X86-64 extended registers. 746static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 747 const MCInstrDesc &Desc) { 748 unsigned REX = 0; 749 if (TSFlags & X86II::REX_W) 750 REX |= 1 << 3; // set REX.W 751 752 if (MI.getNumOperands() == 0) return REX; 753 754 unsigned NumOps = MI.getNumOperands(); 755 // FIXME: MCInst should explicitize the two-addrness. 756 bool isTwoAddr = NumOps > 1 && 757 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 758 759 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 760 unsigned i = isTwoAddr ? 1 : 0; 761 for (; i != NumOps; ++i) { 762 const MCOperand &MO = MI.getOperand(i); 763 if (!MO.isReg()) continue; 764 unsigned Reg = MO.getReg(); 765 if (!X86II::isX86_64NonExtLowByteReg(Reg)) continue; 766 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 767 // that returns non-zero. 768 REX |= 0x40; // REX fixed encoding prefix 769 break; 770 } 771 772 switch (TSFlags & X86II::FormMask) { 773 case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!"); 774 case X86II::MRMSrcReg: 775 if (MI.getOperand(0).isReg() && 776 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 777 REX |= 1 << 2; // set REX.R 778 i = isTwoAddr ? 2 : 1; 779 for (; i != NumOps; ++i) { 780 const MCOperand &MO = MI.getOperand(i); 781 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 782 REX |= 1 << 0; // set REX.B 783 } 784 break; 785 case X86II::MRMSrcMem: { 786 if (MI.getOperand(0).isReg() && 787 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 788 REX |= 1 << 2; // set REX.R 789 unsigned Bit = 0; 790 i = isTwoAddr ? 2 : 1; 791 for (; i != NumOps; ++i) { 792 const MCOperand &MO = MI.getOperand(i); 793 if (MO.isReg()) { 794 if (X86II::isX86_64ExtendedReg(MO.getReg())) 795 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1) 796 Bit++; 797 } 798 } 799 break; 800 } 801 case X86II::MRM0m: case X86II::MRM1m: 802 case X86II::MRM2m: case X86II::MRM3m: 803 case X86II::MRM4m: case X86II::MRM5m: 804 case X86II::MRM6m: case X86II::MRM7m: 805 case X86II::MRMDestMem: { 806 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 807 i = isTwoAddr ? 1 : 0; 808 if (NumOps > e && MI.getOperand(e).isReg() && 809 X86II::isX86_64ExtendedReg(MI.getOperand(e).getReg())) 810 REX |= 1 << 2; // set REX.R 811 unsigned Bit = 0; 812 for (; i != e; ++i) { 813 const MCOperand &MO = MI.getOperand(i); 814 if (MO.isReg()) { 815 if (X86II::isX86_64ExtendedReg(MO.getReg())) 816 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1) 817 Bit++; 818 } 819 } 820 break; 821 } 822 default: 823 if (MI.getOperand(0).isReg() && 824 X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 825 REX |= 1 << 0; // set REX.B 826 i = isTwoAddr ? 2 : 1; 827 for (unsigned e = NumOps; i != e; ++i) { 828 const MCOperand &MO = MI.getOperand(i); 829 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 830 REX |= 1 << 2; // set REX.R 831 } 832 break; 833 } 834 return REX; 835} 836 837/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 838void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, 839 unsigned &CurByte, int MemOperand, 840 const MCInst &MI, 841 raw_ostream &OS) const { 842 switch (TSFlags & X86II::SegOvrMask) { 843 default: llvm_unreachable("Invalid segment!"); 844 case 0: 845 // No segment override, check for explicit one on memory operand. 846 if (MemOperand != -1) { // If the instruction has a memory operand. 847 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 848 default: llvm_unreachable("Unknown segment register!"); 849 case 0: break; 850 case X86::CS: EmitByte(0x2E, CurByte, OS); break; 851 case X86::SS: EmitByte(0x36, CurByte, OS); break; 852 case X86::DS: EmitByte(0x3E, CurByte, OS); break; 853 case X86::ES: EmitByte(0x26, CurByte, OS); break; 854 case X86::FS: EmitByte(0x64, CurByte, OS); break; 855 case X86::GS: EmitByte(0x65, CurByte, OS); break; 856 } 857 } 858 break; 859 case X86II::FS: 860 EmitByte(0x64, CurByte, OS); 861 break; 862 case X86II::GS: 863 EmitByte(0x65, CurByte, OS); 864 break; 865 } 866} 867 868/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode. 869/// 870/// MemOperand is the operand # of the start of a memory operand if present. If 871/// Not present, it is -1. 872void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 873 int MemOperand, const MCInst &MI, 874 const MCInstrDesc &Desc, 875 raw_ostream &OS) const { 876 877 // Emit the lock opcode prefix as needed. 878 if (TSFlags & X86II::LOCK) 879 EmitByte(0xF0, CurByte, OS); 880 881 // Emit segment override opcode prefix as needed. 882 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 883 884 // Emit the repeat opcode prefix as needed. 885 if ((TSFlags & X86II::Op0Mask) == X86II::REP) 886 EmitByte(0xF3, CurByte, OS); 887 888 // Emit the address size opcode prefix as needed. 889 bool need_address_override; 890 if (TSFlags & X86II::AdSize) { 891 need_address_override = true; 892 } else if (MemOperand == -1) { 893 need_address_override = false; 894 } else if (is64BitMode()) { 895 assert(!Is16BitMemOperand(MI, MemOperand)); 896 need_address_override = Is32BitMemOperand(MI, MemOperand); 897 } else if (is32BitMode()) { 898 assert(!Is64BitMemOperand(MI, MemOperand)); 899 need_address_override = Is16BitMemOperand(MI, MemOperand); 900 } else { 901 need_address_override = false; 902 } 903 904 if (need_address_override) 905 EmitByte(0x67, CurByte, OS); 906 907 // Emit the operand size opcode prefix as needed. 908 if (TSFlags & X86II::OpSize) 909 EmitByte(0x66, CurByte, OS); 910 911 bool Need0FPrefix = false; 912 switch (TSFlags & X86II::Op0Mask) { 913 default: llvm_unreachable("Invalid prefix!"); 914 case 0: break; // No prefix! 915 case X86II::REP: break; // already handled. 916 case X86II::TB: // Two-byte opcode prefix 917 case X86II::T8: // 0F 38 918 case X86II::TA: // 0F 3A 919 case X86II::A6: // 0F A6 920 case X86II::A7: // 0F A7 921 Need0FPrefix = true; 922 break; 923 case X86II::T8XS: // F3 0F 38 924 EmitByte(0xF3, CurByte, OS); 925 Need0FPrefix = true; 926 break; 927 case X86II::T8XD: // F2 0F 38 928 EmitByte(0xF2, CurByte, OS); 929 Need0FPrefix = true; 930 break; 931 case X86II::TAXD: // F2 0F 3A 932 EmitByte(0xF2, CurByte, OS); 933 Need0FPrefix = true; 934 break; 935 case X86II::XS: // F3 0F 936 EmitByte(0xF3, CurByte, OS); 937 Need0FPrefix = true; 938 break; 939 case X86II::XD: // F2 0F 940 EmitByte(0xF2, CurByte, OS); 941 Need0FPrefix = true; 942 break; 943 case X86II::D8: EmitByte(0xD8, CurByte, OS); break; 944 case X86II::D9: EmitByte(0xD9, CurByte, OS); break; 945 case X86II::DA: EmitByte(0xDA, CurByte, OS); break; 946 case X86II::DB: EmitByte(0xDB, CurByte, OS); break; 947 case X86II::DC: EmitByte(0xDC, CurByte, OS); break; 948 case X86II::DD: EmitByte(0xDD, CurByte, OS); break; 949 case X86II::DE: EmitByte(0xDE, CurByte, OS); break; 950 case X86II::DF: EmitByte(0xDF, CurByte, OS); break; 951 } 952 953 // Handle REX prefix. 954 // FIXME: Can this come before F2 etc to simplify emission? 955 if (is64BitMode()) { 956 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc)) 957 EmitByte(0x40 | REX, CurByte, OS); 958 } 959 960 // 0x0F escape code must be emitted just before the opcode. 961 if (Need0FPrefix) 962 EmitByte(0x0F, CurByte, OS); 963 964 // FIXME: Pull this up into previous switch if REX can be moved earlier. 965 switch (TSFlags & X86II::Op0Mask) { 966 case X86II::T8XS: // F3 0F 38 967 case X86II::T8XD: // F2 0F 38 968 case X86II::T8: // 0F 38 969 EmitByte(0x38, CurByte, OS); 970 break; 971 case X86II::TAXD: // F2 0F 3A 972 case X86II::TA: // 0F 3A 973 EmitByte(0x3A, CurByte, OS); 974 break; 975 case X86II::A6: // 0F A6 976 EmitByte(0xA6, CurByte, OS); 977 break; 978 case X86II::A7: // 0F A7 979 EmitByte(0xA7, CurByte, OS); 980 break; 981 } 982} 983 984void X86MCCodeEmitter:: 985EncodeInstruction(const MCInst &MI, raw_ostream &OS, 986 SmallVectorImpl<MCFixup> &Fixups) const { 987 unsigned Opcode = MI.getOpcode(); 988 const MCInstrDesc &Desc = MCII.get(Opcode); 989 uint64_t TSFlags = Desc.TSFlags; 990 991 // Pseudo instructions don't get encoded. 992 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 993 return; 994 995 unsigned NumOps = Desc.getNumOperands(); 996 unsigned CurOp = X86II::getOperandBias(Desc); 997 998 // Keep track of the current byte being emitted. 999 unsigned CurByte = 0; 1000 1001 // Is this instruction encoded using the AVX VEX prefix? 1002 bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 1003 1004 // It uses the VEX.VVVV field? 1005 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1006 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1007 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1008 const unsigned MemOp4_I8IMMOperand = 2; 1009 1010 // Determine where the memory operand starts, if present. 1011 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1012 if (MemoryOperand != -1) MemoryOperand += CurOp; 1013 1014 if (!HasVEXPrefix) 1015 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1016 else 1017 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1018 1019 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1020 1021 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1022 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1023 1024 unsigned SrcRegNum = 0; 1025 switch (TSFlags & X86II::FormMask) { 1026 case X86II::MRMInitReg: 1027 llvm_unreachable("FIXME: Remove this form when the JIT moves to MCCodeEmitter!"); 1028 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n"; 1029 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1030 case X86II::Pseudo: 1031 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1032 case X86II::RawFrm: 1033 EmitByte(BaseOpcode, CurByte, OS); 1034 break; 1035 case X86II::RawFrmImm8: 1036 EmitByte(BaseOpcode, CurByte, OS); 1037 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1038 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1039 CurByte, OS, Fixups); 1040 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1041 OS, Fixups); 1042 break; 1043 case X86II::RawFrmImm16: 1044 EmitByte(BaseOpcode, CurByte, OS); 1045 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1046 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1047 CurByte, OS, Fixups); 1048 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1049 OS, Fixups); 1050 break; 1051 1052 case X86II::AddRegFrm: 1053 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1054 break; 1055 1056 case X86II::MRMDestReg: 1057 EmitByte(BaseOpcode, CurByte, OS); 1058 SrcRegNum = CurOp + 1; 1059 1060 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1061 ++SrcRegNum; 1062 1063 EmitRegModRMByte(MI.getOperand(CurOp), 1064 GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1065 CurOp = SrcRegNum + 1; 1066 break; 1067 1068 case X86II::MRMDestMem: 1069 EmitByte(BaseOpcode, CurByte, OS); 1070 SrcRegNum = CurOp + X86::AddrNumOperands; 1071 1072 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1073 ++SrcRegNum; 1074 1075 EmitMemModRMByte(MI, CurOp, 1076 GetX86RegNum(MI.getOperand(SrcRegNum)), 1077 TSFlags, CurByte, OS, Fixups); 1078 CurOp = SrcRegNum + 1; 1079 break; 1080 1081 case X86II::MRMSrcReg: 1082 EmitByte(BaseOpcode, CurByte, OS); 1083 SrcRegNum = CurOp + 1; 1084 1085 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1086 ++SrcRegNum; 1087 1088 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1089 ++SrcRegNum; 1090 1091 EmitRegModRMByte(MI.getOperand(SrcRegNum), 1092 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1093 1094 // 2 operands skipped with HasMemOp4, compensate accordingly 1095 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1096 if (HasVEX_4VOp3) 1097 ++CurOp; 1098 break; 1099 1100 case X86II::MRMSrcMem: { 1101 int AddrOperands = X86::AddrNumOperands; 1102 unsigned FirstMemOp = CurOp+1; 1103 if (HasVEX_4V) { 1104 ++AddrOperands; 1105 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1106 } 1107 if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1108 ++FirstMemOp; 1109 1110 EmitByte(BaseOpcode, CurByte, OS); 1111 1112 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1113 TSFlags, CurByte, OS, Fixups); 1114 CurOp += AddrOperands + 1; 1115 if (HasVEX_4VOp3) 1116 ++CurOp; 1117 break; 1118 } 1119 1120 case X86II::MRM0r: case X86II::MRM1r: 1121 case X86II::MRM2r: case X86II::MRM3r: 1122 case X86II::MRM4r: case X86II::MRM5r: 1123 case X86II::MRM6r: case X86II::MRM7r: 1124 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1125 ++CurOp; 1126 EmitByte(BaseOpcode, CurByte, OS); 1127 EmitRegModRMByte(MI.getOperand(CurOp++), 1128 (TSFlags & X86II::FormMask)-X86II::MRM0r, 1129 CurByte, OS); 1130 break; 1131 case X86II::MRM0m: case X86II::MRM1m: 1132 case X86II::MRM2m: case X86II::MRM3m: 1133 case X86II::MRM4m: case X86II::MRM5m: 1134 case X86II::MRM6m: case X86II::MRM7m: 1135 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1136 ++CurOp; 1137 EmitByte(BaseOpcode, CurByte, OS); 1138 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m, 1139 TSFlags, CurByte, OS, Fixups); 1140 CurOp += X86::AddrNumOperands; 1141 break; 1142 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3: 1143 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9: 1144 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0: 1145 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5: 1146 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9: 1147 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC: 1148 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF: 1149 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8: 1150 case X86II::MRM_F9: 1151 EmitByte(BaseOpcode, CurByte, OS); 1152 1153 unsigned char MRM; 1154 switch (TSFlags & X86II::FormMask) { 1155 default: llvm_unreachable("Invalid Form"); 1156 case X86II::MRM_C1: MRM = 0xC1; break; 1157 case X86II::MRM_C2: MRM = 0xC2; break; 1158 case X86II::MRM_C3: MRM = 0xC3; break; 1159 case X86II::MRM_C4: MRM = 0xC4; break; 1160 case X86II::MRM_C8: MRM = 0xC8; break; 1161 case X86II::MRM_C9: MRM = 0xC9; break; 1162 case X86II::MRM_CA: MRM = 0xCA; break; 1163 case X86II::MRM_CB: MRM = 0xCB; break; 1164 case X86II::MRM_D0: MRM = 0xD0; break; 1165 case X86II::MRM_D1: MRM = 0xD1; break; 1166 case X86II::MRM_D4: MRM = 0xD4; break; 1167 case X86II::MRM_D5: MRM = 0xD5; break; 1168 case X86II::MRM_D6: MRM = 0xD6; break; 1169 case X86II::MRM_D8: MRM = 0xD8; break; 1170 case X86II::MRM_D9: MRM = 0xD9; break; 1171 case X86II::MRM_DA: MRM = 0xDA; break; 1172 case X86II::MRM_DB: MRM = 0xDB; break; 1173 case X86II::MRM_DC: MRM = 0xDC; break; 1174 case X86II::MRM_DD: MRM = 0xDD; break; 1175 case X86II::MRM_DE: MRM = 0xDE; break; 1176 case X86II::MRM_DF: MRM = 0xDF; break; 1177 case X86II::MRM_E8: MRM = 0xE8; break; 1178 case X86II::MRM_F0: MRM = 0xF0; break; 1179 case X86II::MRM_F8: MRM = 0xF8; break; 1180 case X86II::MRM_F9: MRM = 0xF9; break; 1181 } 1182 EmitByte(MRM, CurByte, OS); 1183 break; 1184 } 1185 1186 // If there is a remaining operand, it must be a trailing immediate. Emit it 1187 // according to the right size for the instruction. Some instructions 1188 // (SSE4a extrq and insertq) have two trailing immediates. 1189 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1190 // The last source register of a 4 operand instruction in AVX is encoded 1191 // in bits[7:4] of a immediate byte. 1192 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1193 const MCOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1194 : CurOp); 1195 ++CurOp; 1196 unsigned RegNum = GetX86RegNum(MO) << 4; 1197 if (X86II::isX86_64ExtendedReg(MO.getReg())) 1198 RegNum |= 1 << 7; 1199 // If there is an additional 5th operand it must be an immediate, which 1200 // is encoded in bits[3:0] 1201 if (CurOp != NumOps) { 1202 const MCOperand &MIMM = MI.getOperand(CurOp++); 1203 if (MIMM.isImm()) { 1204 unsigned Val = MIMM.getImm(); 1205 assert(Val < 16 && "Immediate operand value out of range"); 1206 RegNum |= Val; 1207 } 1208 } 1209 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, 1210 CurByte, OS, Fixups); 1211 } else { 1212 unsigned FixupKind; 1213 // FIXME: Is there a better way to know that we need a signed relocation? 1214 if (MI.getOpcode() == X86::ADD64ri32 || 1215 MI.getOpcode() == X86::MOV64ri32 || 1216 MI.getOpcode() == X86::MOV64mi32 || 1217 MI.getOpcode() == X86::PUSH64i32) 1218 FixupKind = X86::reloc_signed_4byte; 1219 else 1220 FixupKind = getImmFixupKind(TSFlags); 1221 EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1222 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind), 1223 CurByte, OS, Fixups); 1224 } 1225 } 1226 1227 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode) 1228 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1229 1230#ifndef NDEBUG 1231 // FIXME: Verify. 1232 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1233 errs() << "Cannot encode all operands of: "; 1234 MI.dump(); 1235 errs() << '\n'; 1236 abort(); 1237 } 1238#endif 1239} 1240