X86MCCodeEmitter.cpp revision 329410
1234353Sdim//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim// 10226584Sdim// This file implements the X86MCCodeEmitter class. 11226584Sdim// 12226584Sdim//===----------------------------------------------------------------------===// 13226584Sdim 14226584Sdim#include "MCTargetDesc/X86BaseInfo.h" 15226584Sdim#include "MCTargetDesc/X86FixupKinds.h" 16321369Sdim#include "MCTargetDesc/X86MCTargetDesc.h" 17321369Sdim#include "llvm/ADT/SmallVector.h" 18226584Sdim#include "llvm/MC/MCCodeEmitter.h" 19243830Sdim#include "llvm/MC/MCContext.h" 20226584Sdim#include "llvm/MC/MCExpr.h" 21321369Sdim#include "llvm/MC/MCFixup.h" 22226584Sdim#include "llvm/MC/MCInst.h" 23321369Sdim#include "llvm/MC/MCInstrDesc.h" 24226584Sdim#include "llvm/MC/MCInstrInfo.h" 25226584Sdim#include "llvm/MC/MCRegisterInfo.h" 26226584Sdim#include "llvm/MC/MCSubtargetInfo.h" 27226584Sdim#include "llvm/MC/MCSymbol.h" 28321369Sdim#include "llvm/Support/ErrorHandling.h" 29226584Sdim#include "llvm/Support/raw_ostream.h" 30321369Sdim#include <cassert> 31321369Sdim#include <cstdint> 32321369Sdim#include <cstdlib> 33226584Sdim 34226584Sdimusing namespace llvm; 35226584Sdim 36276479Sdim#define DEBUG_TYPE "mccodeemitter" 37276479Sdim 38226584Sdimnamespace { 39321369Sdim 40226584Sdimclass X86MCCodeEmitter : public MCCodeEmitter { 41226584Sdim const MCInstrInfo &MCII; 42226584Sdim MCContext &Ctx; 43321369Sdim 44226584Sdimpublic: 45276479Sdim X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 46276479Sdim : MCII(mcii), Ctx(ctx) { 47226584Sdim } 48321369Sdim X86MCCodeEmitter(const X86MCCodeEmitter &) = delete; 49321369Sdim X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete; 50321369Sdim ~X86MCCodeEmitter() override = default; 51226584Sdim 52276479Sdim bool is64BitMode(const MCSubtargetInfo &STI) const { 53288943Sdim return STI.getFeatureBits()[X86::Mode64Bit]; 54226584Sdim } 55226584Sdim 56276479Sdim bool is32BitMode(const MCSubtargetInfo &STI) const { 57288943Sdim return STI.getFeatureBits()[X86::Mode32Bit]; 58234353Sdim } 59234353Sdim 60276479Sdim bool is16BitMode(const MCSubtargetInfo &STI) const { 61288943Sdim return STI.getFeatureBits()[X86::Mode16Bit]; 62276479Sdim } 63276479Sdim 64276479Sdim /// Is16BitMemOperand - Return true if the specified instruction has 65276479Sdim /// a 16-bit memory operand. Op specifies the operand # of the memoperand. 66276479Sdim bool Is16BitMemOperand(const MCInst &MI, unsigned Op, 67276479Sdim const MCSubtargetInfo &STI) const { 68276479Sdim const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 69276479Sdim const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 70276479Sdim const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 71276479Sdim 72276479Sdim if (is16BitMode(STI) && BaseReg.getReg() == 0 && 73276479Sdim Disp.isImm() && Disp.getImm() < 0x10000) 74276479Sdim return true; 75276479Sdim if ((BaseReg.getReg() != 0 && 76276479Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 77276479Sdim (IndexReg.getReg() != 0 && 78276479Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 79276479Sdim return true; 80276479Sdim return false; 81276479Sdim } 82276479Sdim 83243830Sdim unsigned GetX86RegNum(const MCOperand &MO) const { 84261991Sdim return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 85226584Sdim } 86226584Sdim 87309124Sdim unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const { 88309124Sdim return Ctx.getRegisterInfo()->getEncodingValue( 89309124Sdim MI.getOperand(OpNum).getReg()); 90226584Sdim } 91226584Sdim 92314564Sdim // Does this register require a bit to be set in REX prefix. 93314564Sdim bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const { 94309124Sdim return (getX86RegEncoding(MI, OpNum) >> 3) & 1; 95261991Sdim } 96261991Sdim 97309124Sdim void EmitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const { 98226584Sdim OS << (char)C; 99226584Sdim ++CurByte; 100226584Sdim } 101226584Sdim 102226584Sdim void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 103226584Sdim raw_ostream &OS) const { 104226584Sdim // Output the constant in little endian byte order. 105226584Sdim for (unsigned i = 0; i != Size; ++i) { 106226584Sdim EmitByte(Val & 255, CurByte, OS); 107226584Sdim Val >>= 8; 108226584Sdim } 109226584Sdim } 110226584Sdim 111234353Sdim void EmitImmediate(const MCOperand &Disp, SMLoc Loc, 112226584Sdim unsigned ImmSize, MCFixupKind FixupKind, 113226584Sdim unsigned &CurByte, raw_ostream &OS, 114226584Sdim SmallVectorImpl<MCFixup> &Fixups, 115226584Sdim int ImmOffset = 0) const; 116226584Sdim 117321369Sdim static uint8_t ModRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) { 118226584Sdim assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 119226584Sdim return RM | (RegOpcode << 3) | (Mod << 6); 120226584Sdim } 121226584Sdim 122226584Sdim void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 123226584Sdim unsigned &CurByte, raw_ostream &OS) const { 124226584Sdim EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS); 125226584Sdim } 126226584Sdim 127226584Sdim void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base, 128226584Sdim unsigned &CurByte, raw_ostream &OS) const { 129226584Sdim // SIB byte is in the same format as the ModRMByte. 130226584Sdim EmitByte(ModRMByte(SS, Index, Base), CurByte, OS); 131226584Sdim } 132226584Sdim 133309124Sdim void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, 134309124Sdim uint64_t TSFlags, bool Rex, unsigned &CurByte, 135309124Sdim raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, 136276479Sdim const MCSubtargetInfo &STI) const; 137226584Sdim 138288943Sdim void encodeInstruction(const MCInst &MI, raw_ostream &OS, 139276479Sdim SmallVectorImpl<MCFixup> &Fixups, 140276479Sdim const MCSubtargetInfo &STI) const override; 141226584Sdim 142226584Sdim void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 143226584Sdim const MCInst &MI, const MCInstrDesc &Desc, 144226584Sdim raw_ostream &OS) const; 145226584Sdim 146276479Sdim void EmitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand, 147276479Sdim const MCInst &MI, raw_ostream &OS) const; 148226584Sdim 149309124Sdim bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 150226584Sdim const MCInst &MI, const MCInstrDesc &Desc, 151309124Sdim const MCSubtargetInfo &STI, raw_ostream &OS) const; 152309124Sdim 153309124Sdim uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 154309124Sdim int MemOperand, const MCInstrDesc &Desc) const; 155226584Sdim}; 156226584Sdim 157226584Sdim} // end anonymous namespace 158226584Sdim 159226584Sdim/// isDisp8 - Return true if this signed displacement fits in a 8-bit 160226584Sdim/// sign-extended field. 161226584Sdimstatic bool isDisp8(int Value) { 162309124Sdim return Value == (int8_t)Value; 163226584Sdim} 164226584Sdim 165261991Sdim/// isCDisp8 - Return true if this signed displacement fits in a 8-bit 166261991Sdim/// compressed dispacement field. 167261991Sdimstatic bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { 168280031Sdim assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && 169261991Sdim "Compressed 8-bit displacement is only valid for EVEX inst."); 170261991Sdim 171276479Sdim unsigned CD8_Scale = 172280031Sdim (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; 173276479Sdim if (CD8_Scale == 0) { 174261991Sdim CValue = Value; 175261991Sdim return isDisp8(Value); 176261991Sdim } 177261991Sdim 178276479Sdim unsigned Mask = CD8_Scale - 1; 179276479Sdim assert((CD8_Scale & Mask) == 0 && "Invalid memory object size."); 180276479Sdim if (Value & Mask) // Unaligned offset 181261991Sdim return false; 182276479Sdim Value /= (int)CD8_Scale; 183309124Sdim bool Ret = (Value == (int8_t)Value); 184261991Sdim 185261991Sdim if (Ret) 186261991Sdim CValue = Value; 187261991Sdim return Ret; 188261991Sdim} 189261991Sdim 190226584Sdim/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate 191226584Sdim/// in an instruction with the specified TSFlags. 192226584Sdimstatic MCFixupKind getImmFixupKind(uint64_t TSFlags) { 193226584Sdim unsigned Size = X86II::getSizeOfImm(TSFlags); 194226584Sdim bool isPCRel = X86II::isImmPCRel(TSFlags); 195226584Sdim 196276479Sdim if (X86II::isImmSigned(TSFlags)) { 197276479Sdim switch (Size) { 198276479Sdim default: llvm_unreachable("Unsupported signed fixup size!"); 199276479Sdim case 4: return MCFixupKind(X86::reloc_signed_4byte); 200276479Sdim } 201276479Sdim } 202226584Sdim return MCFixup::getKindForSize(Size, isPCRel); 203226584Sdim} 204226584Sdim 205234353Sdim/// Is32BitMemOperand - Return true if the specified instruction has 206234353Sdim/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 207226584Sdimstatic bool Is32BitMemOperand(const MCInst &MI, unsigned Op) { 208226584Sdim const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 209226584Sdim const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 210226584Sdim 211226584Sdim if ((BaseReg.getReg() != 0 && 212226584Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 213226584Sdim (IndexReg.getReg() != 0 && 214226584Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 215226584Sdim return true; 216309124Sdim if (BaseReg.getReg() == X86::EIP) { 217309124Sdim assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); 218309124Sdim return true; 219309124Sdim } 220226584Sdim return false; 221226584Sdim} 222226584Sdim 223234353Sdim/// Is64BitMemOperand - Return true if the specified instruction has 224234353Sdim/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 225234353Sdim#ifndef NDEBUG 226234353Sdimstatic bool Is64BitMemOperand(const MCInst &MI, unsigned Op) { 227234353Sdim const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 228234353Sdim const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 229234353Sdim 230234353Sdim if ((BaseReg.getReg() != 0 && 231234353Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 232234353Sdim (IndexReg.getReg() != 0 && 233234353Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 234234353Sdim return true; 235234353Sdim return false; 236234353Sdim} 237234353Sdim#endif 238234353Sdim 239234353Sdim/// StartsWithGlobalOffsetTable - Check if this expression starts with 240234353Sdim/// _GLOBAL_OFFSET_TABLE_ and if it is of the form 241234353Sdim/// _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on ELF 242234353Sdim/// i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 243226584Sdim/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start 244226584Sdim/// of a binary expression. 245234353Sdimenum GlobalOffsetTableExprKind { 246234353Sdim GOT_None, 247234353Sdim GOT_Normal, 248234353Sdim GOT_SymDiff 249234353Sdim}; 250234353Sdimstatic GlobalOffsetTableExprKind 251234353SdimStartsWithGlobalOffsetTable(const MCExpr *Expr) { 252276479Sdim const MCExpr *RHS = nullptr; 253226584Sdim if (Expr->getKind() == MCExpr::Binary) { 254226584Sdim const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 255226584Sdim Expr = BE->getLHS(); 256234353Sdim RHS = BE->getRHS(); 257226584Sdim } 258226584Sdim 259226584Sdim if (Expr->getKind() != MCExpr::SymbolRef) 260234353Sdim return GOT_None; 261226584Sdim 262226584Sdim const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 263226584Sdim const MCSymbol &S = Ref->getSymbol(); 264234353Sdim if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 265234353Sdim return GOT_None; 266234353Sdim if (RHS && RHS->getKind() == MCExpr::SymbolRef) 267234353Sdim return GOT_SymDiff; 268234353Sdim return GOT_Normal; 269226584Sdim} 270226584Sdim 271251662Sdimstatic bool HasSecRelSymbolRef(const MCExpr *Expr) { 272251662Sdim if (Expr->getKind() == MCExpr::SymbolRef) { 273251662Sdim const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr); 274251662Sdim return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 275251662Sdim } 276251662Sdim return false; 277251662Sdim} 278251662Sdim 279226584Sdimvoid X86MCCodeEmitter:: 280234353SdimEmitImmediate(const MCOperand &DispOp, SMLoc Loc, unsigned Size, 281234353Sdim MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 282226584Sdim SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const { 283276479Sdim const MCExpr *Expr = nullptr; 284226584Sdim if (DispOp.isImm()) { 285226584Sdim // If this is a simple integer displacement that doesn't require a 286226584Sdim // relocation, emit it now. 287226584Sdim if (FixupKind != FK_PCRel_1 && 288226584Sdim FixupKind != FK_PCRel_2 && 289226584Sdim FixupKind != FK_PCRel_4) { 290226584Sdim EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS); 291226584Sdim return; 292226584Sdim } 293288943Sdim Expr = MCConstantExpr::create(DispOp.getImm(), Ctx); 294226584Sdim } else { 295226584Sdim Expr = DispOp.getExpr(); 296226584Sdim } 297226584Sdim 298226584Sdim // If we have an immoffset, add it to the expression. 299226584Sdim if ((FixupKind == FK_Data_4 || 300234353Sdim FixupKind == FK_Data_8 || 301234353Sdim FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 302234353Sdim GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable(Expr); 303234353Sdim if (Kind != GOT_None) { 304234353Sdim assert(ImmOffset == 0); 305226584Sdim 306276479Sdim if (Size == 8) { 307276479Sdim FixupKind = MCFixupKind(X86::reloc_global_offset_table8); 308276479Sdim } else { 309276479Sdim assert(Size == 4); 310276479Sdim FixupKind = MCFixupKind(X86::reloc_global_offset_table); 311276479Sdim } 312276479Sdim 313234353Sdim if (Kind == GOT_Normal) 314234353Sdim ImmOffset = CurByte; 315234353Sdim } else if (Expr->getKind() == MCExpr::SymbolRef) { 316251662Sdim if (HasSecRelSymbolRef(Expr)) { 317234353Sdim FixupKind = MCFixupKind(FK_SecRel_4); 318234353Sdim } 319251662Sdim } else if (Expr->getKind() == MCExpr::Binary) { 320251662Sdim const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr*>(Expr); 321251662Sdim if (HasSecRelSymbolRef(Bin->getLHS()) 322251662Sdim || HasSecRelSymbolRef(Bin->getRHS())) { 323251662Sdim FixupKind = MCFixupKind(FK_SecRel_4); 324251662Sdim } 325234353Sdim } 326226584Sdim } 327226584Sdim 328226584Sdim // If the fixup is pc-relative, we need to bias the value to be relative to 329226584Sdim // the start of the field, not the end of the field. 330226584Sdim if (FixupKind == FK_PCRel_4 || 331226584Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 332309124Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) || 333309124Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) || 334309124Sdim FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex)) 335226584Sdim ImmOffset -= 4; 336226584Sdim if (FixupKind == FK_PCRel_2) 337226584Sdim ImmOffset -= 2; 338226584Sdim if (FixupKind == FK_PCRel_1) 339226584Sdim ImmOffset -= 1; 340226584Sdim 341226584Sdim if (ImmOffset) 342288943Sdim Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx), 343226584Sdim Ctx); 344226584Sdim 345226584Sdim // Emit a symbolic constant as a fixup and 4 zeros. 346288943Sdim Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc)); 347226584Sdim EmitConstant(0, Size, CurByte, OS); 348226584Sdim} 349226584Sdim 350309124Sdimvoid X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op, 351226584Sdim unsigned RegOpcodeField, 352309124Sdim uint64_t TSFlags, bool Rex, 353309124Sdim unsigned &CurByte, raw_ostream &OS, 354276479Sdim SmallVectorImpl<MCFixup> &Fixups, 355309124Sdim const MCSubtargetInfo &STI) const { 356226584Sdim const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); 357226584Sdim const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg); 358226584Sdim const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); 359226584Sdim const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 360226584Sdim unsigned BaseReg = Base.getReg(); 361280031Sdim bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; 362226584Sdim 363226584Sdim // Handle %rip relative addressing. 364309124Sdim if (BaseReg == X86::RIP || 365309124Sdim BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode 366276479Sdim assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode"); 367226584Sdim assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 368226584Sdim EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 369226584Sdim 370309124Sdim unsigned Opcode = MI.getOpcode(); 371226584Sdim // movq loads are handled with a special relocation form which allows the 372226584Sdim // linker to eliminate some loads for GOT references which end up in the 373226584Sdim // same linkage unit. 374309124Sdim unsigned FixupKind = [=]() { 375309124Sdim switch (Opcode) { 376309124Sdim default: 377309124Sdim return X86::reloc_riprel_4byte; 378309124Sdim case X86::MOV64rm: 379309124Sdim assert(Rex); 380309124Sdim return X86::reloc_riprel_4byte_movq_load; 381309124Sdim case X86::CALL64m: 382309124Sdim case X86::JMP64m: 383327952Sdim case X86::TEST64mr: 384309124Sdim case X86::ADC64rm: 385309124Sdim case X86::ADD64rm: 386309124Sdim case X86::AND64rm: 387309124Sdim case X86::CMP64rm: 388309124Sdim case X86::OR64rm: 389309124Sdim case X86::SBB64rm: 390309124Sdim case X86::SUB64rm: 391309124Sdim case X86::XOR64rm: 392309124Sdim return Rex ? X86::reloc_riprel_4byte_relax_rex 393309124Sdim : X86::reloc_riprel_4byte_relax; 394309124Sdim } 395309124Sdim }(); 396226584Sdim 397226584Sdim // rip-relative addressing is actually relative to the *next* instruction. 398226584Sdim // Since an immediate can follow the mod/rm byte for an instruction, this 399329410Sdim // means that we need to bias the displacement field of the instruction with 400329410Sdim // the size of the immediate field. If we have this case, add it into the 401226584Sdim // expression to emit. 402329410Sdim // Note: rip-relative addressing using immediate displacement values should 403329410Sdim // not be adjusted, assuming it was the user's intent. 404329410Sdim int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags) 405329410Sdim ? X86II::getSizeOfImm(TSFlags) 406329410Sdim : 0; 407226584Sdim 408234353Sdim EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), 409226584Sdim CurByte, OS, Fixups, -ImmSize); 410226584Sdim return; 411226584Sdim } 412226584Sdim 413226584Sdim unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U; 414226584Sdim 415276479Sdim // 16-bit addressing forms of the ModR/M byte have a different encoding for 416276479Sdim // the R/M field and are far more limited in which registers can be used. 417276479Sdim if (Is16BitMemOperand(MI, Op, STI)) { 418276479Sdim if (BaseReg) { 419276479Sdim // For 32-bit addressing, the row and column values in Table 2-2 are 420276479Sdim // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with 421276479Sdim // some special cases. And GetX86RegNum reflects that numbering. 422276479Sdim // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A, 423276479Sdim // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only 424276479Sdim // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order, 425276479Sdim // while values 0-3 indicate the allowed combinations (base+index) of 426276479Sdim // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI. 427276479Sdim // 428276479Sdim // R16Table[] is a lookup from the normal RegNo, to the row values from 429276479Sdim // Table 2-1 for 16-bit addressing modes. Where zero means disallowed. 430276479Sdim static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 }; 431276479Sdim unsigned RMfield = R16Table[BaseRegNo]; 432276479Sdim 433276479Sdim assert(RMfield && "invalid 16-bit base register"); 434276479Sdim 435276479Sdim if (IndexReg.getReg()) { 436276479Sdim unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)]; 437276479Sdim 438276479Sdim assert(IndexReg16 && "invalid 16-bit index register"); 439276479Sdim // We must have one of SI/DI (4,5), and one of BP/BX (6,7). 440276479Sdim assert(((IndexReg16 ^ RMfield) & 2) && 441276479Sdim "invalid 16-bit base/index register combination"); 442276479Sdim assert(Scale.getImm() == 1 && 443276479Sdim "invalid scale for 16-bit memory reference"); 444276479Sdim 445276479Sdim // Allow base/index to appear in either order (although GAS doesn't). 446276479Sdim if (IndexReg16 & 2) 447276479Sdim RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); 448276479Sdim else 449276479Sdim RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); 450276479Sdim } 451276479Sdim 452276479Sdim if (Disp.isImm() && isDisp8(Disp.getImm())) { 453276479Sdim if (Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 454276479Sdim // There is no displacement; just the register. 455276479Sdim EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS); 456276479Sdim return; 457276479Sdim } 458276479Sdim // Use the [REG]+disp8 form, including for [BP] which cannot be encoded. 459276479Sdim EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); 460276479Sdim EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 461276479Sdim return; 462276479Sdim } 463276479Sdim // This is the [REG]+disp16 case. 464276479Sdim EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS); 465276479Sdim } else { 466276479Sdim // There is no BaseReg; this is the plain [disp16] case. 467276479Sdim EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS); 468276479Sdim } 469276479Sdim 470276479Sdim // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases. 471276479Sdim EmitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups); 472276479Sdim return; 473276479Sdim } 474276479Sdim 475226584Sdim // Determine whether a SIB byte is needed. 476226584Sdim // If no BaseReg, issue a RIP relative instruction only if the MCE can 477226584Sdim // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 478226584Sdim // 2-7) and absolute references. 479226584Sdim 480226584Sdim if (// The SIB byte must be used if there is an index register. 481226584Sdim IndexReg.getReg() == 0 && 482226584Sdim // The SIB byte must be used if the base is ESP/RSP/R12, all of which 483226584Sdim // encode to an R/M value of 4, which indicates that a SIB byte is 484226584Sdim // present. 485226584Sdim BaseRegNo != N86::ESP && 486226584Sdim // If there is no base register and we're in 64-bit mode, we need a SIB 487226584Sdim // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 488276479Sdim (!is64BitMode(STI) || BaseReg != 0)) { 489226584Sdim 490226584Sdim if (BaseReg == 0) { // [disp32] in X86-32 mode 491226584Sdim EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); 492234353Sdim EmitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 493226584Sdim return; 494226584Sdim } 495226584Sdim 496226584Sdim // If the base is not EBP/ESP and there is no displacement, use simple 497226584Sdim // indirect register encoding, this handles addresses like [EAX]. The 498226584Sdim // encoding for [EBP] with no displacement means [disp32] so we handle it 499226584Sdim // by emitting a displacement of 0 below. 500226584Sdim if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) { 501226584Sdim EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 502226584Sdim return; 503226584Sdim } 504226584Sdim 505226584Sdim // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 506261991Sdim if (Disp.isImm()) { 507261991Sdim if (!HasEVEX && isDisp8(Disp.getImm())) { 508261991Sdim EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 509261991Sdim EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 510261991Sdim return; 511261991Sdim } 512261991Sdim // Try EVEX compressed 8-bit displacement first; if failed, fall back to 513261991Sdim // 32-bit displacement. 514261991Sdim int CDisp8 = 0; 515261991Sdim if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 516261991Sdim EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 517261991Sdim EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 518261991Sdim CDisp8 - Disp.getImm()); 519261991Sdim return; 520261991Sdim } 521226584Sdim } 522226584Sdim 523226584Sdim // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 524226584Sdim EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 525309124Sdim unsigned Opcode = MI.getOpcode(); 526309124Sdim unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax 527309124Sdim : X86::reloc_signed_4byte; 528309124Sdim EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS, 529309124Sdim Fixups); 530226584Sdim return; 531226584Sdim } 532226584Sdim 533226584Sdim // We need a SIB byte, so start by outputting the ModR/M byte first 534226584Sdim assert(IndexReg.getReg() != X86::ESP && 535226584Sdim IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 536226584Sdim 537226584Sdim bool ForceDisp32 = false; 538226584Sdim bool ForceDisp8 = false; 539261991Sdim int CDisp8 = 0; 540261991Sdim int ImmOffset = 0; 541226584Sdim if (BaseReg == 0) { 542226584Sdim // If there is no base register, we emit the special case SIB byte with 543226584Sdim // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 544226584Sdim EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 545226584Sdim ForceDisp32 = true; 546226584Sdim } else if (!Disp.isImm()) { 547226584Sdim // Emit the normal disp32 encoding. 548226584Sdim EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 549226584Sdim ForceDisp32 = true; 550226584Sdim } else if (Disp.getImm() == 0 && 551226584Sdim // Base reg can't be anything that ends up with '5' as the base 552226584Sdim // reg, it is the magic [*] nomenclature that indicates no base. 553226584Sdim BaseRegNo != N86::EBP) { 554226584Sdim // Emit no displacement ModR/M byte 555226584Sdim EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS); 556261991Sdim } else if (!HasEVEX && isDisp8(Disp.getImm())) { 557226584Sdim // Emit the disp8 encoding. 558226584Sdim EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 559226584Sdim ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 560261991Sdim } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 561261991Sdim // Emit the disp8 encoding. 562261991Sdim EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS); 563261991Sdim ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 564261991Sdim ImmOffset = CDisp8 - Disp.getImm(); 565226584Sdim } else { 566226584Sdim // Emit the normal disp32 encoding. 567226584Sdim EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS); 568226584Sdim } 569226584Sdim 570226584Sdim // Calculate what the SS field value should be... 571226584Sdim static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 572226584Sdim unsigned SS = SSTable[Scale.getImm()]; 573226584Sdim 574226584Sdim if (BaseReg == 0) { 575226584Sdim // Handle the SIB byte for the case where there is no base, see Intel 576226584Sdim // Manual 2A, table 2-7. The displacement has already been output. 577226584Sdim unsigned IndexRegNo; 578226584Sdim if (IndexReg.getReg()) 579226584Sdim IndexRegNo = GetX86RegNum(IndexReg); 580226584Sdim else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 581226584Sdim IndexRegNo = 4; 582226584Sdim EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 583226584Sdim } else { 584226584Sdim unsigned IndexRegNo; 585226584Sdim if (IndexReg.getReg()) 586226584Sdim IndexRegNo = GetX86RegNum(IndexReg); 587226584Sdim else 588226584Sdim IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 589226584Sdim EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS); 590226584Sdim } 591226584Sdim 592226584Sdim // Do we need to output a displacement? 593226584Sdim if (ForceDisp8) 594261991Sdim EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset); 595226584Sdim else if (ForceDisp32 || Disp.getImm() != 0) 596234353Sdim EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 597234353Sdim CurByte, OS, Fixups); 598226584Sdim} 599226584Sdim 600226584Sdim/// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 601226584Sdim/// called VEX. 602226584Sdimvoid X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 603226584Sdim int MemOperand, const MCInst &MI, 604226584Sdim const MCInstrDesc &Desc, 605226584Sdim raw_ostream &OS) const { 606280031Sdim assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX."); 607226584Sdim 608280031Sdim uint64_t Encoding = TSFlags & X86II::EncodingMask; 609280031Sdim bool HasEVEX_K = TSFlags & X86II::EVEX_K; 610280031Sdim bool HasVEX_4V = TSFlags & X86II::VEX_4V; 611280031Sdim bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 612280031Sdim 613226584Sdim // VEX_R: opcode externsion equivalent to REX.R in 614226584Sdim // 1's complement (inverted) form 615226584Sdim // 616226584Sdim // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 617226584Sdim // 0: Same as REX_R=1 (64 bit mode only) 618226584Sdim // 619309124Sdim uint8_t VEX_R = 0x1; 620309124Sdim uint8_t EVEX_R2 = 0x1; 621226584Sdim 622226584Sdim // VEX_X: equivalent to REX.X, only used when a 623226584Sdim // register is used for index in SIB Byte. 624226584Sdim // 625226584Sdim // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 626226584Sdim // 0: Same as REX.X=1 (64-bit mode only) 627309124Sdim uint8_t VEX_X = 0x1; 628226584Sdim 629226584Sdim // VEX_B: 630226584Sdim // 631226584Sdim // 1: Same as REX_B=0 (ignored in 32-bit mode) 632226584Sdim // 0: Same as REX_B=1 (64 bit mode only) 633226584Sdim // 634309124Sdim uint8_t VEX_B = 0x1; 635226584Sdim 636226584Sdim // VEX_W: opcode specific (use like REX.W, or used for 637226584Sdim // opcode extension, or ignored, depending on the opcode byte) 638309124Sdim uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0; 639226584Sdim 640226584Sdim // VEX_5M (VEX m-mmmmm field): 641226584Sdim // 642226584Sdim // 0b00000: Reserved for future use 643226584Sdim // 0b00001: implied 0F leading opcode 644226584Sdim // 0b00010: implied 0F 38 leading opcode bytes 645226584Sdim // 0b00011: implied 0F 3A leading opcode bytes 646226584Sdim // 0b00100-0b11111: Reserved for future use 647234353Sdim // 0b01000: XOP map select - 08h instructions with imm byte 648261991Sdim // 0b01001: XOP map select - 09h instructions with no imm byte 649261991Sdim // 0b01010: XOP map select - 0Ah instructions with imm dword 650309124Sdim uint8_t VEX_5M; 651309124Sdim switch (TSFlags & X86II::OpMapMask) { 652309124Sdim default: llvm_unreachable("Invalid prefix!"); 653309124Sdim case X86II::TB: VEX_5M = 0x1; break; // 0F 654309124Sdim case X86II::T8: VEX_5M = 0x2; break; // 0F 38 655309124Sdim case X86II::TA: VEX_5M = 0x3; break; // 0F 3A 656309124Sdim case X86II::XOP8: VEX_5M = 0x8; break; 657309124Sdim case X86II::XOP9: VEX_5M = 0x9; break; 658309124Sdim case X86II::XOPA: VEX_5M = 0xA; break; 659309124Sdim } 660226584Sdim 661226584Sdim // VEX_4V (VEX vvvv field): a register specifier 662226584Sdim // (in 1's complement form) or 1111 if unused. 663309124Sdim uint8_t VEX_4V = 0xf; 664309124Sdim uint8_t EVEX_V2 = 0x1; 665226584Sdim 666309124Sdim // EVEX_L2/VEX_L (Vector Length): 667226584Sdim // 668309124Sdim // L2 L 669309124Sdim // 0 0: scalar or 128-bit vector 670309124Sdim // 0 1: 256-bit vector 671309124Sdim // 1 0: 512-bit vector 672226584Sdim // 673309124Sdim uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0; 674309124Sdim uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0; 675226584Sdim 676226584Sdim // VEX_PP: opcode extension providing equivalent 677226584Sdim // functionality of a SIMD prefix 678226584Sdim // 679226584Sdim // 0b00: None 680226584Sdim // 0b01: 66 681226584Sdim // 0b10: F3 682226584Sdim // 0b11: F2 683226584Sdim // 684309124Sdim uint8_t VEX_PP; 685309124Sdim switch (TSFlags & X86II::OpPrefixMask) { 686309124Sdim default: llvm_unreachable("Invalid op prefix!"); 687309124Sdim case X86II::PS: VEX_PP = 0x0; break; // none 688309124Sdim case X86II::PD: VEX_PP = 0x1; break; // 66 689309124Sdim case X86II::XS: VEX_PP = 0x2; break; // F3 690309124Sdim case X86II::XD: VEX_PP = 0x3; break; // F2 691309124Sdim } 692226584Sdim 693261991Sdim // EVEX_U 694309124Sdim uint8_t EVEX_U = 1; // Always '1' so far 695261991Sdim 696261991Sdim // EVEX_z 697309124Sdim uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0; 698261991Sdim 699261991Sdim // EVEX_b 700309124Sdim uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0; 701261991Sdim 702276479Sdim // EVEX_rc 703309124Sdim uint8_t EVEX_rc = 0; 704276479Sdim 705261991Sdim // EVEX_aaa 706309124Sdim uint8_t EVEX_aaa = 0; 707261991Sdim 708276479Sdim bool EncodeRC = false; 709226584Sdim 710226584Sdim // Classify VEX_B, VEX_4V, VEX_R, VEX_X 711239462Sdim unsigned NumOps = Desc.getNumOperands(); 712276479Sdim unsigned CurOp = X86II::getOperandBias(Desc); 713239462Sdim 714226584Sdim switch (TSFlags & X86II::FormMask) { 715276479Sdim default: llvm_unreachable("Unexpected form in EmitVEXOpcodePrefix!"); 716276479Sdim case X86II::RawFrm: 717276479Sdim break; 718226584Sdim case X86II::MRMDestMem: { 719226584Sdim // MRMDestMem instructions forms: 720226584Sdim // MemAddr, src1(ModR/M) 721226584Sdim // MemAddr, src1(VEX_4V), src2(ModR/M) 722226584Sdim // MemAddr, src1(ModR/M), imm8 723226584Sdim // 724309124Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 725309124Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 726309124Sdim unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 727309124Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 728309124Sdim if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 729309124Sdim EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 730226584Sdim 731261991Sdim CurOp += X86::AddrNumOperands; 732226584Sdim 733261991Sdim if (HasEVEX_K) 734309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 735261991Sdim 736261991Sdim if (HasVEX_4V) { 737309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 738309124Sdim VEX_4V = ~VRegEnc & 0xf; 739309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 740261991Sdim } 741261991Sdim 742309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 743309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 744309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 745226584Sdim break; 746226584Sdim } 747309124Sdim case X86II::MRMSrcMem: { 748226584Sdim // MRMSrcMem instructions forms: 749226584Sdim // src1(ModR/M), MemAddr 750226584Sdim // src1(ModR/M), src2(VEX_4V), MemAddr 751226584Sdim // src1(ModR/M), MemAddr, imm8 752314564Sdim // src1(ModR/M), MemAddr, src2(Imm[7:4]) 753226584Sdim // 754234353Sdim // FMA4: 755314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4]) 756309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 757309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 758309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 759226584Sdim 760261991Sdim if (HasEVEX_K) 761309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 762261991Sdim 763261991Sdim if (HasVEX_4V) { 764309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 765309124Sdim VEX_4V = ~VRegEnc & 0xf; 766309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 767261991Sdim } 768226584Sdim 769309124Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 770309124Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 771309124Sdim unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 772309124Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 773309124Sdim if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 774309124Sdim EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 775234353Sdim 776226584Sdim break; 777309124Sdim } 778314564Sdim case X86II::MRMSrcMem4VOp3: { 779314564Sdim // Instruction format for 4VOp3: 780314564Sdim // src1(ModR/M), MemAddr, src3(VEX_4V) 781314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 782314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 783314564Sdim 784314564Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 785314564Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 786314564Sdim unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 787314564Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 788314564Sdim 789314564Sdim VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; 790314564Sdim break; 791314564Sdim } 792314564Sdim case X86II::MRMSrcMemOp4: { 793314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 794314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 795314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 796314564Sdim 797314564Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 798314564Sdim VEX_4V = ~VRegEnc & 0xf; 799314564Sdim 800314564Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 801314564Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 802314564Sdim unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 803314564Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 804314564Sdim break; 805314564Sdim } 806226584Sdim case X86II::MRM0m: case X86II::MRM1m: 807226584Sdim case X86II::MRM2m: case X86II::MRM3m: 808226584Sdim case X86II::MRM4m: case X86II::MRM5m: 809234353Sdim case X86II::MRM6m: case X86II::MRM7m: { 810226584Sdim // MRM[0-9]m instructions forms: 811226584Sdim // MemAddr 812234353Sdim // src1(VEX_4V), MemAddr 813261991Sdim if (HasVEX_4V) { 814309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 815309124Sdim VEX_4V = ~VRegEnc & 0xf; 816309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 817261991Sdim } 818234353Sdim 819261991Sdim if (HasEVEX_K) 820309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 821261991Sdim 822309124Sdim unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 823309124Sdim VEX_B = ~(BaseRegEnc >> 3) & 1; 824309124Sdim unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 825309124Sdim VEX_X = ~(IndexRegEnc >> 3) & 1; 826226584Sdim break; 827234353Sdim } 828309124Sdim case X86II::MRMSrcReg: { 829226584Sdim // MRMSrcReg instructions forms: 830314564Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4]) 831226584Sdim // dst(ModR/M), src1(ModR/M) 832226584Sdim // dst(ModR/M), src1(ModR/M), imm8 833226584Sdim // 834249423Sdim // FMA4: 835314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 836309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 837309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 838309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 839226584Sdim 840261991Sdim if (HasEVEX_K) 841309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 842249423Sdim 843261991Sdim if (HasVEX_4V) { 844309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 845309124Sdim VEX_4V = ~VRegEnc & 0xf; 846309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 847261991Sdim } 848261991Sdim 849309124Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 850309124Sdim VEX_B = ~(RegEnc >> 3) & 1; 851309124Sdim VEX_X = ~(RegEnc >> 4) & 1; 852314564Sdim 853276479Sdim if (EVEX_b) { 854276479Sdim if (HasEVEX_RC) { 855276479Sdim unsigned RcOperand = NumOps-1; 856276479Sdim assert(RcOperand >= CurOp); 857276479Sdim EVEX_rc = MI.getOperand(RcOperand).getImm() & 0x3; 858276479Sdim } 859276479Sdim EncodeRC = true; 860280031Sdim } 861226584Sdim break; 862309124Sdim } 863314564Sdim case X86II::MRMSrcReg4VOp3: { 864314564Sdim // Instruction format for 4VOp3: 865314564Sdim // src1(ModR/M), src2(ModR/M), src3(VEX_4V) 866314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 867314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 868314564Sdim 869314564Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 870314564Sdim VEX_B = ~(RegEnc >> 3) & 1; 871314564Sdim 872314564Sdim VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; 873314564Sdim break; 874314564Sdim } 875314564Sdim case X86II::MRMSrcRegOp4: { 876314564Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 877314564Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 878314564Sdim VEX_R = ~(RegEnc >> 3) & 1; 879314564Sdim 880314564Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 881314564Sdim VEX_4V = ~VRegEnc & 0xf; 882314564Sdim 883314564Sdim // Skip second register source (encoded in Imm[7:4]) 884314564Sdim ++CurOp; 885314564Sdim 886314564Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 887314564Sdim VEX_B = ~(RegEnc >> 3) & 1; 888314564Sdim VEX_X = ~(RegEnc >> 4) & 1; 889314564Sdim break; 890314564Sdim } 891309124Sdim case X86II::MRMDestReg: { 892226584Sdim // MRMDestReg instructions forms: 893226584Sdim // dst(ModR/M), src(ModR/M) 894226584Sdim // dst(ModR/M), src(ModR/M), imm8 895249423Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 896309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 897309124Sdim VEX_B = ~(RegEnc >> 3) & 1; 898309124Sdim VEX_X = ~(RegEnc >> 4) & 1; 899249423Sdim 900261991Sdim if (HasEVEX_K) 901309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 902249423Sdim 903261991Sdim if (HasVEX_4V) { 904309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 905309124Sdim VEX_4V = ~VRegEnc & 0xf; 906309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 907261991Sdim } 908261991Sdim 909309124Sdim RegEnc = getX86RegEncoding(MI, CurOp++); 910309124Sdim VEX_R = ~(RegEnc >> 3) & 1; 911309124Sdim EVEX_R2 = ~(RegEnc >> 4) & 1; 912276479Sdim if (EVEX_b) 913276479Sdim EncodeRC = true; 914226584Sdim break; 915309124Sdim } 916226584Sdim case X86II::MRM0r: case X86II::MRM1r: 917226584Sdim case X86II::MRM2r: case X86II::MRM3r: 918226584Sdim case X86II::MRM4r: case X86II::MRM5r: 919309124Sdim case X86II::MRM6r: case X86II::MRM7r: { 920226584Sdim // MRM0r-MRM7r instructions forms: 921226584Sdim // dst(VEX_4V), src(ModR/M), imm8 922261991Sdim if (HasVEX_4V) { 923309124Sdim unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 924309124Sdim VEX_4V = ~VRegEnc & 0xf; 925309124Sdim EVEX_V2 = ~(VRegEnc >> 4) & 1; 926276479Sdim } 927261991Sdim if (HasEVEX_K) 928309124Sdim EVEX_aaa = getX86RegEncoding(MI, CurOp++); 929261991Sdim 930309124Sdim unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 931309124Sdim VEX_B = ~(RegEnc >> 3) & 1; 932309124Sdim VEX_X = ~(RegEnc >> 4) & 1; 933226584Sdim break; 934226584Sdim } 935309124Sdim } 936226584Sdim 937276479Sdim if (Encoding == X86II::VEX || Encoding == X86II::XOP) { 938261991Sdim // VEX opcode prefix can have 2 or 3 bytes 939261991Sdim // 940261991Sdim // 3 bytes: 941261991Sdim // +-----+ +--------------+ +-------------------+ 942261991Sdim // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 943261991Sdim // +-----+ +--------------+ +-------------------+ 944261991Sdim // 2 bytes: 945261991Sdim // +-----+ +-------------------+ 946261991Sdim // | C5h | | R | vvvv | L | pp | 947261991Sdim // +-----+ +-------------------+ 948261991Sdim // 949276479Sdim // XOP uses a similar prefix: 950276479Sdim // +-----+ +--------------+ +-------------------+ 951276479Sdim // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp | 952276479Sdim // +-----+ +--------------+ +-------------------+ 953309124Sdim uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 954226584Sdim 955276479Sdim // Can we use the 2 byte VEX prefix? 956276479Sdim if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { 957261991Sdim EmitByte(0xC5, CurByte, OS); 958261991Sdim EmitByte(LastByte | (VEX_R << 7), CurByte, OS); 959261991Sdim return; 960261991Sdim } 961261991Sdim 962261991Sdim // 3 byte VEX prefix 963276479Sdim EmitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS); 964261991Sdim EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 965261991Sdim EmitByte(LastByte | (VEX_W << 7), CurByte, OS); 966261991Sdim } else { 967276479Sdim assert(Encoding == X86II::EVEX && "unknown encoding!"); 968261991Sdim // EVEX opcode prefix can have 4 bytes 969261991Sdim // 970261991Sdim // +-----+ +--------------+ +-------------------+ +------------------------+ 971261991Sdim // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 972261991Sdim // +-----+ +--------------+ +-------------------+ +------------------------+ 973261991Sdim assert((VEX_5M & 0x3) == VEX_5M 974261991Sdim && "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 975261991Sdim 976261991Sdim EmitByte(0x62, CurByte, OS); 977261991Sdim EmitByte((VEX_R << 7) | 978261991Sdim (VEX_X << 6) | 979261991Sdim (VEX_B << 5) | 980261991Sdim (EVEX_R2 << 4) | 981261991Sdim VEX_5M, CurByte, OS); 982261991Sdim EmitByte((VEX_W << 7) | 983261991Sdim (VEX_4V << 3) | 984261991Sdim (EVEX_U << 2) | 985261991Sdim VEX_PP, CurByte, OS); 986276479Sdim if (EncodeRC) 987276479Sdim EmitByte((EVEX_z << 7) | 988309124Sdim (EVEX_rc << 5) | 989309124Sdim (EVEX_b << 4) | 990309124Sdim (EVEX_V2 << 3) | 991309124Sdim EVEX_aaa, CurByte, OS); 992276479Sdim else 993276479Sdim EmitByte((EVEX_z << 7) | 994309124Sdim (EVEX_L2 << 6) | 995309124Sdim (VEX_L << 5) | 996309124Sdim (EVEX_b << 4) | 997309124Sdim (EVEX_V2 << 3) | 998309124Sdim EVEX_aaa, CurByte, OS); 999226584Sdim } 1000226584Sdim} 1001226584Sdim 1002226584Sdim/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64 1003226584Sdim/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 1004226584Sdim/// size, and 3) use of X86-64 extended registers. 1005309124Sdimuint8_t X86MCCodeEmitter::DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, 1006309124Sdim int MemOperand, 1007309124Sdim const MCInstrDesc &Desc) const { 1008309124Sdim uint8_t REX = 0; 1009296417Sdim bool UsesHighByteReg = false; 1010296417Sdim 1011226584Sdim if (TSFlags & X86II::REX_W) 1012226584Sdim REX |= 1 << 3; // set REX.W 1013226584Sdim 1014226584Sdim if (MI.getNumOperands() == 0) return REX; 1015226584Sdim 1016226584Sdim unsigned NumOps = MI.getNumOperands(); 1017309124Sdim unsigned CurOp = X86II::getOperandBias(Desc); 1018226584Sdim 1019226584Sdim // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 1020309124Sdim for (unsigned i = CurOp; i != NumOps; ++i) { 1021226584Sdim const MCOperand &MO = MI.getOperand(i); 1022226584Sdim if (!MO.isReg()) continue; 1023226584Sdim unsigned Reg = MO.getReg(); 1024296417Sdim if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) 1025296417Sdim UsesHighByteReg = true; 1026314564Sdim if (X86II::isX86_64NonExtLowByteReg(Reg)) 1027314564Sdim // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything 1028314564Sdim // that returns non-zero. 1029314564Sdim REX |= 0x40; // REX fixed encoding prefix 1030226584Sdim } 1031226584Sdim 1032226584Sdim switch (TSFlags & X86II::FormMask) { 1033309124Sdim case X86II::AddRegFrm: 1034314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1035309124Sdim break; 1036226584Sdim case X86II::MRMSrcReg: 1037314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1038314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1039226584Sdim break; 1040226584Sdim case X86II::MRMSrcMem: { 1041314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1042314564Sdim REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B 1043314564Sdim REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X 1044309124Sdim CurOp += X86::AddrNumOperands; 1045226584Sdim break; 1046226584Sdim } 1047309124Sdim case X86II::MRMDestReg: 1048314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1049314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1050309124Sdim break; 1051309124Sdim case X86II::MRMDestMem: 1052314564Sdim REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B 1053314564Sdim REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X 1054309124Sdim CurOp += X86::AddrNumOperands; 1055314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1056309124Sdim break; 1057276479Sdim case X86II::MRMXm: 1058226584Sdim case X86II::MRM0m: case X86II::MRM1m: 1059226584Sdim case X86II::MRM2m: case X86II::MRM3m: 1060226584Sdim case X86II::MRM4m: case X86II::MRM5m: 1061226584Sdim case X86II::MRM6m: case X86II::MRM7m: 1062314564Sdim REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B 1063314564Sdim REX |= isREXExtendedReg(MI, MemOperand+X86::AddrIndexReg) << 1; // REX.X 1064226584Sdim break; 1065309124Sdim case X86II::MRMXr: 1066309124Sdim case X86II::MRM0r: case X86II::MRM1r: 1067309124Sdim case X86II::MRM2r: case X86II::MRM3r: 1068309124Sdim case X86II::MRM4r: case X86II::MRM5r: 1069309124Sdim case X86II::MRM6r: case X86II::MRM7r: 1070314564Sdim REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1071226584Sdim break; 1072226584Sdim } 1073296417Sdim if (REX && UsesHighByteReg) 1074296417Sdim report_fatal_error("Cannot encode high byte register in REX-prefixed instruction"); 1075296417Sdim 1076226584Sdim return REX; 1077226584Sdim} 1078226584Sdim 1079226584Sdim/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 1080276479Sdimvoid X86MCCodeEmitter::EmitSegmentOverridePrefix(unsigned &CurByte, 1081276479Sdim unsigned SegOperand, 1082276479Sdim const MCInst &MI, 1083276479Sdim raw_ostream &OS) const { 1084276479Sdim // Check for explicit segment override on memory operand. 1085276479Sdim switch (MI.getOperand(SegOperand).getReg()) { 1086276479Sdim default: llvm_unreachable("Unknown segment register!"); 1087276479Sdim case 0: break; 1088276479Sdim case X86::CS: EmitByte(0x2E, CurByte, OS); break; 1089276479Sdim case X86::SS: EmitByte(0x36, CurByte, OS); break; 1090276479Sdim case X86::DS: EmitByte(0x3E, CurByte, OS); break; 1091276479Sdim case X86::ES: EmitByte(0x26, CurByte, OS); break; 1092276479Sdim case X86::FS: EmitByte(0x64, CurByte, OS); break; 1093276479Sdim case X86::GS: EmitByte(0x65, CurByte, OS); break; 1094226584Sdim } 1095226584Sdim} 1096226584Sdim 1097309124Sdim/// Emit all instruction prefixes prior to the opcode. 1098226584Sdim/// 1099226584Sdim/// MemOperand is the operand # of the start of a memory operand if present. If 1100226584Sdim/// Not present, it is -1. 1101309124Sdim/// 1102309124Sdim/// Returns true if a REX prefix was used. 1103309124Sdimbool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1104226584Sdim int MemOperand, const MCInst &MI, 1105226584Sdim const MCInstrDesc &Desc, 1106276479Sdim const MCSubtargetInfo &STI, 1107226584Sdim raw_ostream &OS) const { 1108309124Sdim bool Ret = false; 1109226584Sdim // Emit the operand size opcode prefix as needed. 1110280031Sdim if ((TSFlags & X86II::OpSizeMask) == (is16BitMode(STI) ? X86II::OpSize32 1111280031Sdim : X86II::OpSize16)) 1112226584Sdim EmitByte(0x66, CurByte, OS); 1113226584Sdim 1114280031Sdim // Emit the LOCK opcode prefix. 1115327952Sdim if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK) 1116280031Sdim EmitByte(0xF0, CurByte, OS); 1117280031Sdim 1118276479Sdim switch (TSFlags & X86II::OpPrefixMask) { 1119276479Sdim case X86II::PD: // 66 1120276479Sdim EmitByte(0x66, CurByte, OS); 1121226584Sdim break; 1122276479Sdim case X86II::XS: // F3 1123234353Sdim EmitByte(0xF3, CurByte, OS); 1124234353Sdim break; 1125276479Sdim case X86II::XD: // F2 1126226584Sdim EmitByte(0xF2, CurByte, OS); 1127226584Sdim break; 1128226584Sdim } 1129226584Sdim 1130226584Sdim // Handle REX prefix. 1131226584Sdim // FIXME: Can this come before F2 etc to simplify emission? 1132276479Sdim if (is64BitMode(STI)) { 1133309124Sdim if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) { 1134226584Sdim EmitByte(0x40 | REX, CurByte, OS); 1135309124Sdim Ret = true; 1136309124Sdim } 1137327952Sdim } else { 1138327952Sdim assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode."); 1139226584Sdim } 1140226584Sdim 1141226584Sdim // 0x0F escape code must be emitted just before the opcode. 1142276479Sdim switch (TSFlags & X86II::OpMapMask) { 1143276479Sdim case X86II::TB: // Two-byte opcode map 1144276479Sdim case X86II::T8: // 0F 38 1145276479Sdim case X86II::TA: // 0F 3A 1146226584Sdim EmitByte(0x0F, CurByte, OS); 1147276479Sdim break; 1148276479Sdim } 1149226584Sdim 1150276479Sdim switch (TSFlags & X86II::OpMapMask) { 1151226584Sdim case X86II::T8: // 0F 38 1152226584Sdim EmitByte(0x38, CurByte, OS); 1153226584Sdim break; 1154226584Sdim case X86II::TA: // 0F 3A 1155226584Sdim EmitByte(0x3A, CurByte, OS); 1156226584Sdim break; 1157226584Sdim } 1158309124Sdim return Ret; 1159226584Sdim} 1160226584Sdim 1161226584Sdimvoid X86MCCodeEmitter:: 1162288943SdimencodeInstruction(const MCInst &MI, raw_ostream &OS, 1163276479Sdim SmallVectorImpl<MCFixup> &Fixups, 1164276479Sdim const MCSubtargetInfo &STI) const { 1165226584Sdim unsigned Opcode = MI.getOpcode(); 1166226584Sdim const MCInstrDesc &Desc = MCII.get(Opcode); 1167226584Sdim uint64_t TSFlags = Desc.TSFlags; 1168327952Sdim unsigned Flags = MI.getFlags(); 1169226584Sdim 1170226584Sdim // Pseudo instructions don't get encoded. 1171226584Sdim if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1172226584Sdim return; 1173226584Sdim 1174226584Sdim unsigned NumOps = Desc.getNumOperands(); 1175251662Sdim unsigned CurOp = X86II::getOperandBias(Desc); 1176226584Sdim 1177226584Sdim // Keep track of the current byte being emitted. 1178226584Sdim unsigned CurByte = 0; 1179226584Sdim 1180276479Sdim // Encoding type for this instruction. 1181280031Sdim uint64_t Encoding = TSFlags & X86II::EncodingMask; 1182226584Sdim 1183226584Sdim // It uses the VEX.VVVV field? 1184280031Sdim bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1185314564Sdim bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg; 1186226584Sdim 1187261991Sdim // It uses the EVEX.aaa field? 1188280031Sdim bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1189280031Sdim bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 1190280031Sdim 1191309124Sdim // Used if a register is encoded in 7:4 of immediate. 1192309124Sdim unsigned I8RegNum = 0; 1193309124Sdim 1194226584Sdim // Determine where the memory operand starts, if present. 1195309124Sdim int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); 1196226584Sdim if (MemoryOperand != -1) MemoryOperand += CurOp; 1197226584Sdim 1198276479Sdim // Emit segment override opcode prefix as needed. 1199276479Sdim if (MemoryOperand >= 0) 1200276479Sdim EmitSegmentOverridePrefix(CurByte, MemoryOperand+X86::AddrSegmentReg, 1201276479Sdim MI, OS); 1202276479Sdim 1203276479Sdim // Emit the repeat opcode prefix as needed. 1204327952Sdim if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT) 1205276479Sdim EmitByte(0xF3, CurByte, OS); 1206327952Sdim if (Flags & X86::IP_HAS_REPEAT_NE) 1207327952Sdim EmitByte(0xF2, CurByte, OS); 1208276479Sdim 1209276479Sdim // Emit the address size opcode prefix as needed. 1210276479Sdim bool need_address_override; 1211280031Sdim uint64_t AdSize = TSFlags & X86II::AdSizeMask; 1212280031Sdim if ((is16BitMode(STI) && AdSize == X86II::AdSize32) || 1213280031Sdim (is32BitMode(STI) && AdSize == X86II::AdSize16) || 1214280031Sdim (is64BitMode(STI) && AdSize == X86II::AdSize32)) { 1215276479Sdim need_address_override = true; 1216276479Sdim } else if (MemoryOperand < 0) { 1217276479Sdim need_address_override = false; 1218276479Sdim } else if (is64BitMode(STI)) { 1219276479Sdim assert(!Is16BitMemOperand(MI, MemoryOperand, STI)); 1220276479Sdim need_address_override = Is32BitMemOperand(MI, MemoryOperand); 1221276479Sdim } else if (is32BitMode(STI)) { 1222276479Sdim assert(!Is64BitMemOperand(MI, MemoryOperand)); 1223276479Sdim need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI); 1224276479Sdim } else { 1225276479Sdim assert(is16BitMode(STI)); 1226276479Sdim assert(!Is64BitMemOperand(MI, MemoryOperand)); 1227276479Sdim need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI); 1228276479Sdim } 1229276479Sdim 1230276479Sdim if (need_address_override) 1231276479Sdim EmitByte(0x67, CurByte, OS); 1232276479Sdim 1233309124Sdim bool Rex = false; 1234276479Sdim if (Encoding == 0) 1235309124Sdim Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS); 1236226584Sdim else 1237226584Sdim EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 1238226584Sdim 1239309124Sdim uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1240226584Sdim 1241280031Sdim if (TSFlags & X86II::Has3DNow0F0FOpcode) 1242226584Sdim BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1243226584Sdim 1244309124Sdim uint64_t Form = TSFlags & X86II::FormMask; 1245309124Sdim switch (Form) { 1246309124Sdim default: errs() << "FORM: " << Form << "\n"; 1247234353Sdim llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1248226584Sdim case X86II::Pseudo: 1249234353Sdim llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1250276479Sdim case X86II::RawFrmDstSrc: { 1251276479Sdim unsigned siReg = MI.getOperand(1).getReg(); 1252276479Sdim assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 1253276479Sdim (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 1254276479Sdim (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 1255276479Sdim "SI and DI register sizes do not match"); 1256276479Sdim // Emit segment override opcode prefix as needed (not for %ds). 1257276479Sdim if (MI.getOperand(2).getReg() != X86::DS) 1258276479Sdim EmitSegmentOverridePrefix(CurByte, 2, MI, OS); 1259276479Sdim // Emit AdSize prefix as needed. 1260276479Sdim if ((!is32BitMode(STI) && siReg == X86::ESI) || 1261276479Sdim (is32BitMode(STI) && siReg == X86::SI)) 1262276479Sdim EmitByte(0x67, CurByte, OS); 1263276479Sdim CurOp += 3; // Consume operands. 1264276479Sdim EmitByte(BaseOpcode, CurByte, OS); 1265276479Sdim break; 1266276479Sdim } 1267276479Sdim case X86II::RawFrmSrc: { 1268276479Sdim unsigned siReg = MI.getOperand(0).getReg(); 1269276479Sdim // Emit segment override opcode prefix as needed (not for %ds). 1270276479Sdim if (MI.getOperand(1).getReg() != X86::DS) 1271276479Sdim EmitSegmentOverridePrefix(CurByte, 1, MI, OS); 1272276479Sdim // Emit AdSize prefix as needed. 1273276479Sdim if ((!is32BitMode(STI) && siReg == X86::ESI) || 1274276479Sdim (is32BitMode(STI) && siReg == X86::SI)) 1275276479Sdim EmitByte(0x67, CurByte, OS); 1276276479Sdim CurOp += 2; // Consume operands. 1277276479Sdim EmitByte(BaseOpcode, CurByte, OS); 1278276479Sdim break; 1279276479Sdim } 1280276479Sdim case X86II::RawFrmDst: { 1281276479Sdim unsigned siReg = MI.getOperand(0).getReg(); 1282276479Sdim // Emit AdSize prefix as needed. 1283276479Sdim if ((!is32BitMode(STI) && siReg == X86::EDI) || 1284276479Sdim (is32BitMode(STI) && siReg == X86::DI)) 1285276479Sdim EmitByte(0x67, CurByte, OS); 1286276479Sdim ++CurOp; // Consume operand. 1287276479Sdim EmitByte(BaseOpcode, CurByte, OS); 1288276479Sdim break; 1289276479Sdim } 1290226584Sdim case X86II::RawFrm: 1291226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1292226584Sdim break; 1293276479Sdim case X86II::RawFrmMemOffs: 1294276479Sdim // Emit segment override opcode prefix as needed. 1295276479Sdim EmitSegmentOverridePrefix(CurByte, 1, MI, OS); 1296276479Sdim EmitByte(BaseOpcode, CurByte, OS); 1297276479Sdim EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1298276479Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1299276479Sdim CurByte, OS, Fixups); 1300276479Sdim ++CurOp; // skip segment operand 1301276479Sdim break; 1302226584Sdim case X86II::RawFrmImm8: 1303226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1304234353Sdim EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1305226584Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1306226584Sdim CurByte, OS, Fixups); 1307234353Sdim EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1308234353Sdim OS, Fixups); 1309226584Sdim break; 1310226584Sdim case X86II::RawFrmImm16: 1311226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1312234353Sdim EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1313226584Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1314226584Sdim CurByte, OS, Fixups); 1315234353Sdim EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1316234353Sdim OS, Fixups); 1317226584Sdim break; 1318226584Sdim 1319226584Sdim case X86II::AddRegFrm: 1320226584Sdim EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1321226584Sdim break; 1322226584Sdim 1323309124Sdim case X86II::MRMDestReg: { 1324226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1325309124Sdim unsigned SrcRegNum = CurOp + 1; 1326249423Sdim 1327261991Sdim if (HasEVEX_K) // Skip writemask 1328309124Sdim ++SrcRegNum; 1329261991Sdim 1330249423Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1331249423Sdim ++SrcRegNum; 1332249423Sdim 1333226584Sdim EmitRegModRMByte(MI.getOperand(CurOp), 1334249423Sdim GetX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1335249423Sdim CurOp = SrcRegNum + 1; 1336226584Sdim break; 1337309124Sdim } 1338309124Sdim case X86II::MRMDestMem: { 1339226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1340309124Sdim unsigned SrcRegNum = CurOp + X86::AddrNumOperands; 1341226584Sdim 1342261991Sdim if (HasEVEX_K) // Skip writemask 1343309124Sdim ++SrcRegNum; 1344261991Sdim 1345226584Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1346239462Sdim ++SrcRegNum; 1347226584Sdim 1348309124Sdim emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.getOperand(SrcRegNum)), TSFlags, 1349309124Sdim Rex, CurByte, OS, Fixups, STI); 1350226584Sdim CurOp = SrcRegNum + 1; 1351226584Sdim break; 1352309124Sdim } 1353309124Sdim case X86II::MRMSrcReg: { 1354226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1355309124Sdim unsigned SrcRegNum = CurOp + 1; 1356226584Sdim 1357261991Sdim if (HasEVEX_K) // Skip writemask 1358309124Sdim ++SrcRegNum; 1359261991Sdim 1360226584Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1361239462Sdim ++SrcRegNum; 1362226584Sdim 1363226584Sdim EmitRegModRMByte(MI.getOperand(SrcRegNum), 1364226584Sdim GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1365309124Sdim CurOp = SrcRegNum + 1; 1366314564Sdim if (HasVEX_I8Reg) 1367309124Sdim I8RegNum = getX86RegEncoding(MI, CurOp++); 1368276479Sdim // do not count the rounding control operand 1369276479Sdim if (HasEVEX_RC) 1370309124Sdim --NumOps; 1371226584Sdim break; 1372309124Sdim } 1373314564Sdim case X86II::MRMSrcReg4VOp3: { 1374314564Sdim EmitByte(BaseOpcode, CurByte, OS); 1375314564Sdim unsigned SrcRegNum = CurOp + 1; 1376314564Sdim 1377314564Sdim EmitRegModRMByte(MI.getOperand(SrcRegNum), 1378314564Sdim GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1379314564Sdim CurOp = SrcRegNum + 1; 1380314564Sdim ++CurOp; // Encoded in VEX.VVVV 1381314564Sdim break; 1382314564Sdim } 1383314564Sdim case X86II::MRMSrcRegOp4: { 1384314564Sdim EmitByte(BaseOpcode, CurByte, OS); 1385314564Sdim unsigned SrcRegNum = CurOp + 1; 1386314564Sdim 1387314564Sdim // Skip 1st src (which is encoded in VEX_VVVV) 1388314564Sdim ++SrcRegNum; 1389314564Sdim 1390314564Sdim // Capture 2nd src (which is encoded in Imm[7:4]) 1391314564Sdim assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"); 1392314564Sdim I8RegNum = getX86RegEncoding(MI, SrcRegNum++); 1393314564Sdim 1394314564Sdim EmitRegModRMByte(MI.getOperand(SrcRegNum), 1395314564Sdim GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1396314564Sdim CurOp = SrcRegNum + 1; 1397314564Sdim break; 1398314564Sdim } 1399226584Sdim case X86II::MRMSrcMem: { 1400226584Sdim unsigned FirstMemOp = CurOp+1; 1401261991Sdim 1402309124Sdim if (HasEVEX_K) // Skip writemask 1403261991Sdim ++FirstMemOp; 1404261991Sdim 1405309124Sdim if (HasVEX_4V) 1406226584Sdim ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1407226584Sdim 1408226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1409226584Sdim 1410309124Sdim emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1411309124Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1412309124Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1413314564Sdim if (HasVEX_I8Reg) 1414309124Sdim I8RegNum = getX86RegEncoding(MI, CurOp++); 1415226584Sdim break; 1416226584Sdim } 1417314564Sdim case X86II::MRMSrcMem4VOp3: { 1418314564Sdim unsigned FirstMemOp = CurOp+1; 1419226584Sdim 1420314564Sdim EmitByte(BaseOpcode, CurByte, OS); 1421314564Sdim 1422314564Sdim emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1423314564Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1424314564Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1425314564Sdim ++CurOp; // Encoded in VEX.VVVV. 1426314564Sdim break; 1427314564Sdim } 1428314564Sdim case X86II::MRMSrcMemOp4: { 1429314564Sdim unsigned FirstMemOp = CurOp+1; 1430314564Sdim 1431314564Sdim ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1432314564Sdim 1433314564Sdim // Capture second register source (encoded in Imm[7:4]) 1434314564Sdim assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"); 1435314564Sdim I8RegNum = getX86RegEncoding(MI, FirstMemOp++); 1436314564Sdim 1437314564Sdim EmitByte(BaseOpcode, CurByte, OS); 1438314564Sdim 1439314564Sdim emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)), 1440314564Sdim TSFlags, Rex, CurByte, OS, Fixups, STI); 1441314564Sdim CurOp = FirstMemOp + X86::AddrNumOperands; 1442314564Sdim break; 1443314564Sdim } 1444314564Sdim 1445276479Sdim case X86II::MRMXr: 1446226584Sdim case X86II::MRM0r: case X86II::MRM1r: 1447226584Sdim case X86II::MRM2r: case X86II::MRM3r: 1448226584Sdim case X86II::MRM4r: case X86II::MRM5r: 1449321369Sdim case X86II::MRM6r: case X86II::MRM7r: 1450226584Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1451239462Sdim ++CurOp; 1452276479Sdim if (HasEVEX_K) // Skip writemask 1453276479Sdim ++CurOp; 1454226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1455226584Sdim EmitRegModRMByte(MI.getOperand(CurOp++), 1456276479Sdim (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r, 1457226584Sdim CurByte, OS); 1458226584Sdim break; 1459276479Sdim 1460276479Sdim case X86II::MRMXm: 1461226584Sdim case X86II::MRM0m: case X86II::MRM1m: 1462226584Sdim case X86II::MRM2m: case X86II::MRM3m: 1463226584Sdim case X86II::MRM4m: case X86II::MRM5m: 1464321369Sdim case X86II::MRM6m: case X86II::MRM7m: 1465234353Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1466239462Sdim ++CurOp; 1467276479Sdim if (HasEVEX_K) // Skip writemask 1468276479Sdim ++CurOp; 1469226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1470309124Sdim emitMemModRMByte(MI, CurOp, 1471309124Sdim (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags, 1472309124Sdim Rex, CurByte, OS, Fixups, STI); 1473226584Sdim CurOp += X86::AddrNumOperands; 1474226584Sdim break; 1475321369Sdim 1476276479Sdim case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1477288943Sdim case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 1478288943Sdim case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 1479276479Sdim case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1480288943Sdim case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 1481280031Sdim case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 1482288943Sdim case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 1483288943Sdim case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 1484288943Sdim case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 1485288943Sdim case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 1486288943Sdim case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 1487288943Sdim case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 1488288943Sdim case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 1489288943Sdim case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 1490288943Sdim case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1491288943Sdim case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 1492288943Sdim case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 1493288943Sdim case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 1494288943Sdim case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 1495288943Sdim case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 1496288943Sdim case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 1497288943Sdim case X86II::MRM_FF: 1498226584Sdim EmitByte(BaseOpcode, CurByte, OS); 1499288943Sdim EmitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS); 1500226584Sdim break; 1501226584Sdim } 1502226584Sdim 1503314564Sdim if (HasVEX_I8Reg) { 1504226584Sdim // The last source register of a 4 operand instruction in AVX is encoded 1505234353Sdim // in bits[7:4] of a immediate byte. 1506309124Sdim assert(I8RegNum < 16 && "Register encoding out of range"); 1507309124Sdim I8RegNum <<= 4; 1508309124Sdim if (CurOp != NumOps) { 1509309124Sdim unsigned Val = MI.getOperand(CurOp++).getImm(); 1510309124Sdim assert(Val < 16 && "Immediate operand value out of range"); 1511309124Sdim I8RegNum |= Val; 1512309124Sdim } 1513309124Sdim EmitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1, 1514309124Sdim CurByte, OS, Fixups); 1515309124Sdim } else { 1516309124Sdim // If there is a remaining operand, it must be a trailing immediate. Emit it 1517309124Sdim // according to the right size for the instruction. Some instructions 1518309124Sdim // (SSE4a extrq and insertq) have two trailing immediates. 1519309124Sdim while (CurOp != NumOps && NumOps - CurOp <= 2) { 1520234353Sdim EmitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1521276479Sdim X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1522226584Sdim CurByte, OS, Fixups); 1523226584Sdim } 1524226584Sdim } 1525226584Sdim 1526280031Sdim if (TSFlags & X86II::Has3DNow0F0FOpcode) 1527226584Sdim EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1528226584Sdim 1529226584Sdim#ifndef NDEBUG 1530226584Sdim // FIXME: Verify. 1531226584Sdim if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1532226584Sdim errs() << "Cannot encode all operands of: "; 1533226584Sdim MI.dump(); 1534226584Sdim errs() << '\n'; 1535226584Sdim abort(); 1536226584Sdim } 1537226584Sdim#endif 1538226584Sdim} 1539321369Sdim 1540321369SdimMCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 1541321369Sdim const MCRegisterInfo &MRI, 1542321369Sdim MCContext &Ctx) { 1543321369Sdim return new X86MCCodeEmitter(MCII, Ctx); 1544321369Sdim} 1545