WebAssemblyTargetTransformInfo.cpp revision 360784 
1//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the WebAssembly-specific TargetTransformInfo
11/// implementation.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblyTargetTransformInfo.h"
16#include "llvm/CodeGen/CostTable.h"
17#include "llvm/Support/Debug.h"
18using namespace llvm;
19
20#define DEBUG_TYPE "wasmtti"
21
22TargetTransformInfo::PopcntSupportKind
23WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
24  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
25  return TargetTransformInfo::PSK_FastHardware;
26}
27
28unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
29  unsigned Result = BaseT::getNumberOfRegisters(ClassID);
30
31  // For SIMD, use at least 16 registers, as a rough guess.
32  bool Vector = (ClassID == 1);
33  if (Vector)
34    Result = std::max(Result, 16u);
35
36  return Result;
37}
38
39unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
40  if (Vector && getST()->hasSIMD128())
41    return 128;
42
43  return 64;
44}
45
46unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
47    unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
48    TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
49    TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
50    const Instruction *CxtI) {
51
52  unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
53      Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
54
55  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
56    switch (Opcode) {
57    case Instruction::LShr:
58    case Instruction::AShr:
59    case Instruction::Shl:
60      // SIMD128's shifts currently only accept a scalar shift count. For each
61      // element, we'll need to extract, op, insert. The following is a rough
62      // approxmation.
63      if (Opd2Info != TTI::OK_UniformValue &&
64          Opd2Info != TTI::OK_UniformConstantValue)
65        Cost = VTy->getNumElements() *
66               (TargetTransformInfo::TCC_Basic +
67                getArithmeticInstrCost(Opcode, VTy->getElementType()) +
68                TargetTransformInfo::TCC_Basic);
69      break;
70    }
71  }
72  return Cost;
73}
74
75unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
76                                                unsigned Index) {
77  unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
78
79  // SIMD128's insert/extract currently only take constant indices.
80  if (Index == -1u)
81    return Cost + 25 * TargetTransformInfo::TCC_Expensive;
82
83  return Cost;
84}
85