WebAssemblyTargetTransformInfo.cpp revision 327952
1285163Sdim//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===// 2285163Sdim// 3285163Sdim// The LLVM Compiler Infrastructure 4285163Sdim// 5285163Sdim// This file is distributed under the University of Illinois Open Source 6285163Sdim// License. See LICENSE.TXT for details. 7285163Sdim// 8285163Sdim//===----------------------------------------------------------------------===// 9285163Sdim/// 10285163Sdim/// \file 11285163Sdim/// \brief This file defines the WebAssembly-specific TargetTransformInfo 12285163Sdim/// implementation. 13285163Sdim/// 14285163Sdim//===----------------------------------------------------------------------===// 15285163Sdim 16285163Sdim#include "WebAssemblyTargetTransformInfo.h" 17327952Sdim#include "llvm/CodeGen/CostTable.h" 18285163Sdim#include "llvm/Support/Debug.h" 19285163Sdimusing namespace llvm; 20285163Sdim 21285163Sdim#define DEBUG_TYPE "wasmtti" 22285163Sdim 23285163SdimTargetTransformInfo::PopcntSupportKind 24296417SdimWebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const { 25285163Sdim assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 26296417Sdim return TargetTransformInfo::PSK_FastHardware; 27285163Sdim} 28309124Sdim 29309124Sdimunsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) { 30309124Sdim unsigned Result = BaseT::getNumberOfRegisters(Vector); 31309124Sdim 32309124Sdim // For SIMD, use at least 16 registers, as a rough guess. 33309124Sdim if (Vector) 34309124Sdim Result = std::max(Result, 16u); 35309124Sdim 36309124Sdim return Result; 37309124Sdim} 38309124Sdim 39321369Sdimunsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const { 40309124Sdim if (Vector && getST()->hasSIMD128()) 41309124Sdim return 128; 42309124Sdim 43309124Sdim return 64; 44309124Sdim} 45309124Sdim 46309124Sdimunsigned WebAssemblyTTIImpl::getArithmeticInstrCost( 47309124Sdim unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, 48309124Sdim TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, 49314564Sdim TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) { 50309124Sdim 51309124Sdim unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost( 52309124Sdim Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo); 53309124Sdim 54309124Sdim if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 55309124Sdim switch (Opcode) { 56309124Sdim case Instruction::LShr: 57309124Sdim case Instruction::AShr: 58309124Sdim case Instruction::Shl: 59309124Sdim // SIMD128's shifts currently only accept a scalar shift count. For each 60309124Sdim // element, we'll need to extract, op, insert. The following is a rough 61309124Sdim // approxmation. 62309124Sdim if (Opd2Info != TTI::OK_UniformValue && 63309124Sdim Opd2Info != TTI::OK_UniformConstantValue) 64309124Sdim Cost = VTy->getNumElements() * 65309124Sdim (TargetTransformInfo::TCC_Basic + 66309124Sdim getArithmeticInstrCost(Opcode, VTy->getElementType()) + 67309124Sdim TargetTransformInfo::TCC_Basic); 68309124Sdim break; 69309124Sdim } 70309124Sdim } 71309124Sdim return Cost; 72309124Sdim} 73309124Sdim 74309124Sdimunsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 75309124Sdim unsigned Index) { 76309124Sdim unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); 77309124Sdim 78309124Sdim // SIMD128's insert/extract currently only take constant indices. 79309124Sdim if (Index == -1u) 80309124Sdim return Cost + 25 * TargetTransformInfo::TCC_Expensive; 81309124Sdim 82309124Sdim return Cost; 83309124Sdim} 84