WebAssemblySetP2AlignOperands.cpp revision 344779 
1//=- WebAssemblySetP2AlignOperands.cpp - Set alignments on loads and stores -=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// This file sets the p2align operands on load and store instructions.
12///
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
16#include "WebAssembly.h"
17#include "WebAssemblyMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
19#include "llvm/CodeGen/MachineMemOperand.h"
20#include "llvm/CodeGen/Passes.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/raw_ostream.h"
23using namespace llvm;
24
25#define DEBUG_TYPE "wasm-set-p2align-operands"
26
27namespace {
28class WebAssemblySetP2AlignOperands final : public MachineFunctionPass {
29public:
30  static char ID; // Pass identification, replacement for typeid
31  WebAssemblySetP2AlignOperands() : MachineFunctionPass(ID) {}
32
33  StringRef getPassName() const override {
34    return "WebAssembly Set p2align Operands";
35  }
36
37  void getAnalysisUsage(AnalysisUsage &AU) const override {
38    AU.setPreservesCFG();
39    AU.addPreserved<MachineBlockFrequencyInfo>();
40    AU.addPreservedID(MachineDominatorsID);
41    MachineFunctionPass::getAnalysisUsage(AU);
42  }
43
44  bool runOnMachineFunction(MachineFunction &MF) override;
45};
46} // end anonymous namespace
47
48char WebAssemblySetP2AlignOperands::ID = 0;
49INITIALIZE_PASS(WebAssemblySetP2AlignOperands, DEBUG_TYPE,
50                "Set the p2align operands for WebAssembly loads and stores",
51                false, false)
52
53FunctionPass *llvm::createWebAssemblySetP2AlignOperands() {
54  return new WebAssemblySetP2AlignOperands();
55}
56
57static void RewriteP2Align(MachineInstr &MI, unsigned OperandNo) {
58  assert(MI.getOperand(OperandNo).getImm() == 0 &&
59         "ISel should set p2align operands to 0");
60  assert(MI.hasOneMemOperand() &&
61         "Load and store instructions have exactly one mem operand");
62  assert((*MI.memoperands_begin())->getSize() ==
63             (UINT64_C(1) << WebAssembly::GetDefaultP2Align(MI.getOpcode())) &&
64         "Default p2align value should be natural");
65  assert(MI.getDesc().OpInfo[OperandNo].OperandType ==
66             WebAssembly::OPERAND_P2ALIGN &&
67         "Load and store instructions should have a p2align operand");
68  uint64_t P2Align = Log2_64((*MI.memoperands_begin())->getAlignment());
69
70  // WebAssembly does not currently support supernatural alignment.
71  P2Align = std::min(P2Align,
72                     uint64_t(WebAssembly::GetDefaultP2Align(MI.getOpcode())));
73
74  MI.getOperand(OperandNo).setImm(P2Align);
75}
76
77bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) {
78  LLVM_DEBUG({
79    dbgs() << "********** Set p2align Operands **********\n"
80           << "********** Function: " << MF.getName() << '\n';
81  });
82
83  bool Changed = false;
84
85  for (auto &MBB : MF) {
86    for (auto &MI : MBB) {
87      switch (MI.getOpcode()) {
88      case WebAssembly::LOAD_I32:
89      case WebAssembly::LOAD_I64:
90      case WebAssembly::LOAD_F32:
91      case WebAssembly::LOAD_F64:
92      case WebAssembly::LOAD_v16i8:
93      case WebAssembly::LOAD_v8i16:
94      case WebAssembly::LOAD_v4i32:
95      case WebAssembly::LOAD_v2i64:
96      case WebAssembly::LOAD_v4f32:
97      case WebAssembly::LOAD_v2f64:
98      case WebAssembly::LOAD8_S_I32:
99      case WebAssembly::LOAD8_U_I32:
100      case WebAssembly::LOAD16_S_I32:
101      case WebAssembly::LOAD16_U_I32:
102      case WebAssembly::LOAD8_S_I64:
103      case WebAssembly::LOAD8_U_I64:
104      case WebAssembly::LOAD16_S_I64:
105      case WebAssembly::LOAD16_U_I64:
106      case WebAssembly::LOAD32_S_I64:
107      case WebAssembly::LOAD32_U_I64:
108      case WebAssembly::ATOMIC_LOAD_I32:
109      case WebAssembly::ATOMIC_LOAD8_U_I32:
110      case WebAssembly::ATOMIC_LOAD16_U_I32:
111      case WebAssembly::ATOMIC_LOAD_I64:
112      case WebAssembly::ATOMIC_LOAD8_U_I64:
113      case WebAssembly::ATOMIC_LOAD16_U_I64:
114      case WebAssembly::ATOMIC_LOAD32_U_I64:
115      case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
116      case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
117      case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
118      case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
119      case WebAssembly::ATOMIC_RMW8_U_AND_I32:
120      case WebAssembly::ATOMIC_RMW8_U_AND_I64:
121      case WebAssembly::ATOMIC_RMW8_U_OR_I32:
122      case WebAssembly::ATOMIC_RMW8_U_OR_I64:
123      case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
124      case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
125      case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
126      case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
127      case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
128      case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
129      case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
130      case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
131      case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
132      case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
133      case WebAssembly::ATOMIC_RMW16_U_AND_I32:
134      case WebAssembly::ATOMIC_RMW16_U_AND_I64:
135      case WebAssembly::ATOMIC_RMW16_U_OR_I32:
136      case WebAssembly::ATOMIC_RMW16_U_OR_I64:
137      case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
138      case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
139      case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
140      case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
141      case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
142      case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
143      case WebAssembly::ATOMIC_RMW_ADD_I32:
144      case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
145      case WebAssembly::ATOMIC_RMW_SUB_I32:
146      case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
147      case WebAssembly::ATOMIC_RMW_AND_I32:
148      case WebAssembly::ATOMIC_RMW32_U_AND_I64:
149      case WebAssembly::ATOMIC_RMW_OR_I32:
150      case WebAssembly::ATOMIC_RMW32_U_OR_I64:
151      case WebAssembly::ATOMIC_RMW_XOR_I32:
152      case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
153      case WebAssembly::ATOMIC_RMW_XCHG_I32:
154      case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
155      case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
156      case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
157      case WebAssembly::ATOMIC_RMW_ADD_I64:
158      case WebAssembly::ATOMIC_RMW_SUB_I64:
159      case WebAssembly::ATOMIC_RMW_AND_I64:
160      case WebAssembly::ATOMIC_RMW_OR_I64:
161      case WebAssembly::ATOMIC_RMW_XOR_I64:
162      case WebAssembly::ATOMIC_RMW_XCHG_I64:
163      case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
164      case WebAssembly::ATOMIC_NOTIFY:
165      case WebAssembly::ATOMIC_WAIT_I32:
166      case WebAssembly::ATOMIC_WAIT_I64:
167        RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo);
168        break;
169      case WebAssembly::STORE_I32:
170      case WebAssembly::STORE_I64:
171      case WebAssembly::STORE_F32:
172      case WebAssembly::STORE_F64:
173      case WebAssembly::STORE_v16i8:
174      case WebAssembly::STORE_v8i16:
175      case WebAssembly::STORE_v4i32:
176      case WebAssembly::STORE_v2i64:
177      case WebAssembly::STORE_v4f32:
178      case WebAssembly::STORE_v2f64:
179      case WebAssembly::STORE8_I32:
180      case WebAssembly::STORE16_I32:
181      case WebAssembly::STORE8_I64:
182      case WebAssembly::STORE16_I64:
183      case WebAssembly::STORE32_I64:
184      case WebAssembly::ATOMIC_STORE_I32:
185      case WebAssembly::ATOMIC_STORE8_I32:
186      case WebAssembly::ATOMIC_STORE16_I32:
187      case WebAssembly::ATOMIC_STORE_I64:
188      case WebAssembly::ATOMIC_STORE8_I64:
189      case WebAssembly::ATOMIC_STORE16_I64:
190      case WebAssembly::ATOMIC_STORE32_I64:
191        RewriteP2Align(MI, WebAssembly::StoreP2AlignOperandNo);
192        break;
193      default:
194        break;
195      }
196    }
197  }
198
199  return Changed;
200}
201