WebAssemblyRegisterInfo.cpp revision 296417 
1//===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief This file contains the WebAssembly implementation of the
12/// TargetRegisterInfo class.
13///
14//===----------------------------------------------------------------------===//
15
16#include "WebAssemblyRegisterInfo.h"
17#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
18#include "WebAssemblyFrameLowering.h"
19#include "WebAssemblyInstrInfo.h"
20#include "WebAssemblyMachineFunctionInfo.h"
21#include "WebAssemblySubtarget.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/IR/Function.h"
26#include "llvm/Support/raw_ostream.h"
27#include "llvm/Target/TargetFrameLowering.h"
28#include "llvm/Target/TargetOptions.h"
29using namespace llvm;
30
31#define DEBUG_TYPE "wasm-reg-info"
32
33#define GET_REGINFO_TARGET_DESC
34#include "WebAssemblyGenRegisterInfo.inc"
35
36WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT)
37    : WebAssemblyGenRegisterInfo(0), TT(TT) {}
38
39const MCPhysReg *
40WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
41  static const MCPhysReg CalleeSavedRegs[] = {0};
42  return CalleeSavedRegs;
43}
44
45BitVector
46WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
47  BitVector Reserved(getNumRegs());
48  for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
49                   WebAssembly::FP64})
50    Reserved.set(Reg);
51  return Reserved;
52}
53
54void WebAssemblyRegisterInfo::eliminateFrameIndex(
55    MachineBasicBlock::iterator II, int SPAdj,
56    unsigned FIOperandNum, RegScavenger * /*RS*/) const {
57  assert(SPAdj == 0);
58  MachineInstr &MI = *II;
59
60  MachineBasicBlock &MBB = *MI.getParent();
61  MachineFunction &MF = *MBB.getParent();
62  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
63  const MachineFrameInfo& MFI = *MF.getFrameInfo();
64  int64_t FrameOffset = MFI.getStackSize() + MFI.getObjectOffset(FrameIndex);
65
66  if (MI.mayLoadOrStore()) {
67    // If this is a load or store, make it relative to SP and fold the frame
68    // offset directly in.
69    assert(FrameOffset >= 0 && MI.getOperand(1).getImm() >= 0);
70    int64_t Offset = MI.getOperand(1).getImm() + FrameOffset;
71
72    if (static_cast<uint64_t>(Offset) > std::numeric_limits<uint32_t>::max()) {
73      // If this happens the program is invalid, but better to error here than
74      // generate broken code.
75      report_fatal_error("Memory offset field overflow");
76    }
77    MI.getOperand(1).setImm(Offset);
78    MI.getOperand(2).ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false);
79  } else {
80    // Otherwise create an i32.add SP, offset and make it the operand.
81    auto &MRI = MF.getRegInfo();
82    const auto *TII = MF.getSubtarget().getInstrInfo();
83
84    unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
85    BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::CONST_I32), OffsetReg)
86        .addImm(FrameOffset);
87    BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::ADD_I32), OffsetReg)
88        .addReg(WebAssembly::SP32)
89        .addReg(OffsetReg);
90    MI.getOperand(FIOperandNum).ChangeToRegister(OffsetReg, /*IsDef=*/false);
91  }
92}
93
94unsigned
95WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
96  static const unsigned Regs[2][2] = {
97      /*            !isArch64Bit       isArch64Bit      */
98      /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
99      /*  hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
100  const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
101  return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
102}
103
104const TargetRegisterClass *
105WebAssemblyRegisterInfo::getPointerRegClass(const MachineFunction &MF,
106                                            unsigned Kind) const {
107  assert(Kind == 0 && "Only one kind of pointer on WebAssembly");
108  if (MF.getSubtarget<WebAssemblySubtarget>().hasAddr64())
109    return &WebAssembly::I64RegClass;
110  return &WebAssembly::I32RegClass;
111}
112