WebAssemblyInstrSIMD.td revision 355940 
1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// WebAssembly SIMD operand code-gen constructs.
11///
12//===----------------------------------------------------------------------===//
13
14// Instructions requiring HasSIMD128 and the simd128 prefix byte
15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
16                  list<dag> pattern_r, string asmstr_r = "",
17                  string asmstr_s = "", bits<32> simdop = -1> {
18  defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
19              !or(0xfd00, !and(0xff, simdop))>,
20            Requires<[HasSIMD128]>;
21}
22
23defm "" : ARGUMENT<V128, v16i8>;
24defm "" : ARGUMENT<V128, v8i16>;
25defm "" : ARGUMENT<V128, v4i32>;
26defm "" : ARGUMENT<V128, v2i64>;
27defm "" : ARGUMENT<V128, v4f32>;
28defm "" : ARGUMENT<V128, v2f64>;
29
30// Constrained immediate argument types
31foreach SIZE = [8, 16] in
32def ImmI#SIZE : ImmLeaf<i32,
33  "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));"
34>;
35foreach SIZE = [2, 4, 8, 16, 32] in
36def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
37
38//===----------------------------------------------------------------------===//
39// Load and store
40//===----------------------------------------------------------------------===//
41
42// Load: v128.load
43multiclass SIMDLoad<ValueType vec_t> {
44  let mayLoad = 1, UseNamedOperandTable = 1 in
45  defm LOAD_#vec_t :
46    SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
47           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
48           "v128.load\t$dst, ${off}(${addr})$p2align",
49           "v128.load\t$off$p2align", 0>;
50}
51
52foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
53defm "" : SIMDLoad<vec_t>;
54
55// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
56def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
57def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
58def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;
59def : LoadPatGlobalAddr<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
60def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
61def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
62}
63
64// Store: v128.store
65multiclass SIMDStore<ValueType vec_t> {
66  let mayStore = 1, UseNamedOperandTable = 1 in
67  defm STORE_#vec_t :
68    SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
69           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
70           "v128.store\t${off}(${addr})$p2align, $vec",
71           "v128.store\t$off$p2align", 1>;
72}
73
74foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
75defm "" : SIMDStore<vec_t>;
76
77// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
78def : StorePatNoOffset<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
79def : StorePatImmOff<vec_t, store, regPlusImm, !cast<NI>("STORE_"#vec_t)>;
80def : StorePatImmOff<vec_t, store, or_is_add, !cast<NI>("STORE_"#vec_t)>;
81def : StorePatGlobalAddr<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
82def : StorePatOffsetOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
83def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
84}
85
86//===----------------------------------------------------------------------===//
87// Constructing SIMD values
88//===----------------------------------------------------------------------===//
89
90// Constant: v128.const
91multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
92  let isMoveImm = 1, isReMaterializable = 1,
93      Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
94  defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
95                                  [(set V128:$dst, (vec_t pat))],
96                                  "v128.const\t$dst, "#args,
97                                  "v128.const\t"#args, 2>;
98}
99
100defm "" : ConstVec<v16i8,
101                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
102                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
103                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
104                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
105                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
106                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
107                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
108                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
109                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
110                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
111                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
112                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
113                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
114                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
115defm "" : ConstVec<v8i16,
116                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
117                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
118                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
119                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
120                   (build_vector
121                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
122                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
123                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
124let IsCanonical = 1 in
125defm "" : ConstVec<v4i32,
126                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
127                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
128                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
129                                 (i32 imm:$i2), (i32 imm:$i3)),
130                   "$i0, $i1, $i2, $i3">;
131defm "" : ConstVec<v2i64,
132                   (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
133                   (build_vector (i64 imm:$i0), (i64 imm:$i1)),
134                   "$i0, $i1">;
135defm "" : ConstVec<v4f32,
136                   (ins f32imm_op:$i0, f32imm_op:$i1,
137                        f32imm_op:$i2, f32imm_op:$i3),
138                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
139                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
140                   "$i0, $i1, $i2, $i3">;
141defm "" : ConstVec<v2f64,
142                  (ins f64imm_op:$i0, f64imm_op:$i1),
143                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
144                  "$i0, $i1">;
145
146// Shuffle lanes: shuffle
147defm SHUFFLE :
148  SIMD_I<(outs V128:$dst),
149         (ins V128:$x, V128:$y,
150           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
151           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
152           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
153           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
154           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
155           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
156           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
157           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
158         (outs),
159         (ins
160           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
161           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
162           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
163           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
164           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
165           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
166           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
167           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
168         [],
169         "v8x16.shuffle\t$dst, $x, $y, "#
170           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
171           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
172         "v8x16.shuffle\t"#
173           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
174           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
175         3>;
176
177// Shuffles after custom lowering
178def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
179def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
180foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
181def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
182            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
183            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
184            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
185            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
186            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
187            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
188            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
189            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
190          (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
191            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
192            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
193            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
194            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
195            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
196            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
197            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
198            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
199}
200
201// Create vector with identical lanes: splat
202def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
203def splat4 : PatFrag<(ops node:$x), (build_vector
204                       node:$x, node:$x, node:$x, node:$x)>;
205def splat8 : PatFrag<(ops node:$x), (build_vector
206                       node:$x, node:$x, node:$x, node:$x,
207                       node:$x, node:$x, node:$x, node:$x)>;
208def splat16 : PatFrag<(ops node:$x), (build_vector
209                        node:$x, node:$x, node:$x, node:$x,
210                        node:$x, node:$x, node:$x, node:$x,
211                        node:$x, node:$x, node:$x, node:$x,
212                        node:$x, node:$x, node:$x, node:$x)>;
213
214multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
215                 PatFrag splat_pat, bits<32> simdop> {
216  // Prefer splats over v128.const for const splats (65 is lowest that works)
217  let AddedComplexity = 65 in
218  defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
219                             [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
220                             vec#".splat\t$dst, $x", vec#".splat", simdop>;
221}
222
223defm "" : Splat<v16i8, "i8x16", I32, splat16, 4>;
224defm "" : Splat<v8i16, "i16x8", I32, splat8, 8>;
225defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
226defm "" : Splat<v2i64, "i64x2", I64, splat2, 15>;
227defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
228defm "" : Splat<v2f64, "f64x2", F64, splat2, 21>;
229
230// scalar_to_vector leaves high lanes undefined, so can be a splat
231class ScalarSplatPat<ValueType vec_t, ValueType lane_t,
232                     WebAssemblyRegClass reg_t> :
233  Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
234      (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
235
236def : ScalarSplatPat<v16i8, i32, I32>;
237def : ScalarSplatPat<v8i16, i32, I32>;
238def : ScalarSplatPat<v4i32, i32, I32>;
239def : ScalarSplatPat<v2i64, i64, I64>;
240def : ScalarSplatPat<v4f32, f32, F32>;
241def : ScalarSplatPat<v2f64, f64, F64>;
242
243//===----------------------------------------------------------------------===//
244// Accessing lanes
245//===----------------------------------------------------------------------===//
246
247// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
248multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
249                       WebAssemblyRegClass reg_t, bits<32> simdop,
250                       string suffix = "", SDNode extract = vector_extract> {
251  defm EXTRACT_LANE_#vec_t#suffix :
252      SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
253             (outs), (ins vec_i8imm_op:$idx),
254             [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
255             vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
256             vec#".extract_lane"#suffix#"\t$idx", simdop>;
257}
258
259multiclass ExtractPat<ValueType lane_t, int mask> {
260  def _s : PatFrag<(ops node:$vec, node:$idx),
261                   (i32 (sext_inreg
262                     (i32 (vector_extract
263                       node:$vec,
264                       node:$idx
265                     )),
266                     lane_t
267                   ))>;
268  def _u : PatFrag<(ops node:$vec, node:$idx),
269                   (i32 (and
270                     (i32 (vector_extract
271                       node:$vec,
272                       node:$idx
273                     )),
274                     (i32 mask)
275                   ))>;
276}
277
278defm extract_i8x16 : ExtractPat<i8, 0xff>;
279defm extract_i16x8 : ExtractPat<i16, 0xffff>;
280
281multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
282  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
283                        !cast<PatFrag>("extract_i8x16"#sign)>;
284  defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 4), sign,
285                        !cast<PatFrag>("extract_i16x8"#sign)>;
286}
287
288defm "" : ExtractLaneExtended<"_s", 5>;
289let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
290defm "" : ExtractLaneExtended<"_u", 6>;
291defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
292defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
293defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
294defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>;
295
296// It would be more conventional to use unsigned extracts, but v8
297// doesn't implement them yet
298def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
299          (EXTRACT_LANE_v16i8_s V128:$vec, (i32 LaneIdx16:$idx))>;
300def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
301          (EXTRACT_LANE_v8i16_s V128:$vec, (i32 LaneIdx8:$idx))>;
302
303// Lower undef lane indices to zero
304def : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)),
305          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
306def : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)),
307          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
308def : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)),
309          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
310def : Pat<(i32 (vector_extract (v8i16 V128:$vec), undef)),
311          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
312def : Pat<(sext_inreg (i32 (vector_extract (v16i8 V128:$vec), undef)), i8),
313          (EXTRACT_LANE_v16i8_s V128:$vec, 0)>;
314def : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16),
315          (EXTRACT_LANE_v8i16_s V128:$vec, 0)>;
316def : Pat<(vector_extract (v4i32 V128:$vec), undef),
317          (EXTRACT_LANE_v4i32 V128:$vec, 0)>;
318def : Pat<(vector_extract (v2i64 V128:$vec), undef),
319          (EXTRACT_LANE_v2i64 V128:$vec, 0)>;
320def : Pat<(vector_extract (v4f32 V128:$vec), undef),
321          (EXTRACT_LANE_v4f32 V128:$vec, 0)>;
322def : Pat<(vector_extract (v2f64 V128:$vec), undef),
323          (EXTRACT_LANE_v2f64 V128:$vec, 0)>;
324
325// Replace lane value: replace_lane
326multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
327                       WebAssemblyRegClass reg_t, ValueType lane_t,
328                       bits<32> simdop> {
329  defm REPLACE_LANE_#vec_t :
330      SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
331             (outs), (ins vec_i8imm_op:$idx),
332             [(set V128:$dst, (vector_insert
333               (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
334             vec#".replace_lane\t$dst, $vec, $idx, $x",
335             vec#".replace_lane\t$idx", simdop>;
336}
337
338defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 7>;
339defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 11>;
340defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 14>;
341defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 17>;
342defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>;
343defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 23>;
344
345// Lower undef lane indices to zero
346def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
347          (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
348def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
349          (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
350def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
351          (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;
352def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
353          (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>;
354def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
355          (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>;
356def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
357          (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>;
358
359//===----------------------------------------------------------------------===//
360// Comparisons
361//===----------------------------------------------------------------------===//
362
363multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
364                         string name, CondCode cond, bits<32> simdop> {
365  defm _#vec_t :
366    SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
367           [(set (out_t V128:$dst),
368             (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
369           )],
370           vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
371}
372
373multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
374  defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
375  defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
376                          !add(baseInst, 10)>;
377  defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
378                          !add(baseInst, 20)>;
379}
380
381multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
382  defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
383  defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
384                          !add(baseInst, 6)>;
385}
386
387// Equality: eq
388let isCommutable = 1 in {
389defm EQ : SIMDConditionInt<"eq", SETEQ, 24>;
390defm EQ : SIMDConditionFP<"eq", SETOEQ, 64>;
391} // isCommutable = 1
392
393// Non-equality: ne
394let isCommutable = 1 in {
395defm NE : SIMDConditionInt<"ne", SETNE, 25>;
396defm NE : SIMDConditionFP<"ne", SETUNE, 65>;
397} // isCommutable = 1
398
399// Less than: lt_s / lt_u / lt
400defm LT_S : SIMDConditionInt<"lt_s", SETLT, 26>;
401defm LT_U : SIMDConditionInt<"lt_u", SETULT, 27>;
402defm LT : SIMDConditionFP<"lt", SETOLT, 66>;
403
404// Greater than: gt_s / gt_u / gt
405defm GT_S : SIMDConditionInt<"gt_s", SETGT, 28>;
406defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 29>;
407defm GT : SIMDConditionFP<"gt", SETOGT, 67>;
408
409// Less than or equal: le_s / le_u / le
410defm LE_S : SIMDConditionInt<"le_s", SETLE, 30>;
411defm LE_U : SIMDConditionInt<"le_u", SETULE, 31>;
412defm LE : SIMDConditionFP<"le", SETOLE, 68>;
413
414// Greater than or equal: ge_s / ge_u / ge
415defm GE_S : SIMDConditionInt<"ge_s", SETGE, 32>;
416defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>;
417defm GE : SIMDConditionFP<"ge", SETOGE, 69>;
418
419// Lower float comparisons that don't care about NaN to standard WebAssembly
420// float comparisons. These instructions are generated with nnan and in the
421// target-independent expansion of unordered comparisons and ordered ne.
422foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32],
423                 [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in
424def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
425          (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
426
427foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64],
428                 [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in
429def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
430          (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
431
432
433//===----------------------------------------------------------------------===//
434// Bitwise operations
435//===----------------------------------------------------------------------===//
436
437multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
438                      bits<32> simdop> {
439  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
440                        (outs), (ins),
441                        [(set (vec_t V128:$dst),
442                          (node (vec_t V128:$lhs), (vec_t V128:$rhs))
443                        )],
444                        vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
445                        simdop>;
446}
447
448multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
449  defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
450  defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
451  defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
452  defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
453}
454
455multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name,
456                     bits<32> simdop> {
457  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
458                        [(set (vec_t V128:$dst),
459                          (vec_t (node (vec_t V128:$vec)))
460                        )],
461                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
462}
463
464// Bitwise logic: v128.not
465foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
466defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>;
467
468// Bitwise logic: v128.and / v128.or / v128.xor
469let isCommutable = 1 in {
470defm AND : SIMDBitwise<and, "and", 77>;
471defm OR : SIMDBitwise<or, "or", 78>;
472defm XOR : SIMDBitwise<xor, "xor", 79>;
473} // isCommutable = 1
474
475// Bitwise select: v128.bitselect
476foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
477  defm BITSELECT_#vec_t :
478    SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
479           [(set (vec_t V128:$dst),
480             (vec_t (int_wasm_bitselect
481               (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
482             ))
483           )],
484           "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>;
485
486// Bitselect is equivalent to (c & v1) | (~c & v2)
487foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
488  def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
489              (and (vnot V128:$c), (vec_t V128:$v2)))),
490            (!cast<Instruction>("BITSELECT_"#vec_t)
491              V128:$v1, V128:$v2, V128:$c)>;
492
493//===----------------------------------------------------------------------===//
494// Integer unary arithmetic
495//===----------------------------------------------------------------------===//
496
497multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
498  defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>;
499  defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
500  defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
501  defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
502}
503
504multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
505                         bits<32> simdop> {
506  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
507                        [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
508                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
509}
510
511multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
512  defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>;
513  defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>;
514  defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>;
515  defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>;
516}
517
518// Integer vector negation
519def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
520
521// Integer negation: neg
522defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
523
524// Any lane true: any_true
525defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>;
526
527// All lanes true: all_true
528defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>;
529
530// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
531// can be folded out
532foreach reduction =
533  [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
534foreach ty = [v16i8, v8i16, v4i32, v2i64] in {
535def : Pat<(i32 (and
536            (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
537            (i32 1)
538          )),
539          (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
540def : Pat<(i32 (setne
541            (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
542            (i32 0)
543          )),
544          (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
545def : Pat<(i32 (seteq
546            (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
547            (i32 1)
548          )),
549          (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
550}
551
552//===----------------------------------------------------------------------===//
553// Bit shifts
554//===----------------------------------------------------------------------===//
555
556multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec,
557                     string name, bits<32> simdop> {
558  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
559                        (outs), (ins),
560                        [(set (vec_t V128:$dst),
561                          (node V128:$vec, (vec_t shift_vec)))],
562                        vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
563}
564
565multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
566  defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>;
567  defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name,
568                      !add(baseInst, 17)>;
569  defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name,
570                      !add(baseInst, 34)>;
571  defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
572                      name, !add(baseInst, 51)>;
573}
574
575// Left shift by scalar: shl
576defm SHL : SIMDShiftInt<shl, "shl", 84>;
577
578// Right shift by scalar: shr_s / shr_u
579defm SHR_S : SIMDShiftInt<sra, "shr_s", 85>;
580defm SHR_U : SIMDShiftInt<srl, "shr_u", 86>;
581
582// Truncate i64 shift operands to i32s, except if they are already i32s
583foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in {
584def : Pat<(v2i64 (shifts[0]
585            (v2i64 V128:$vec),
586            (v2i64 (splat2 (i64 (sext I32:$x))))
587          )),
588          (v2i64 (shifts[1] (v2i64 V128:$vec), (i32 I32:$x)))>;
589def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))),
590          (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
591}
592
593// 2xi64 shifts with constant shift amounts are custom lowered to avoid wrapping
594def wasm_shift_t : SDTypeProfile<1, 2,
595  [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]
596>;
597def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>;
598def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>;
599def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>;
600foreach shifts = [[wasm_shl, SHL_v2i64],
601                  [wasm_shr_s, SHR_S_v2i64],
602                  [wasm_shr_u, SHR_U_v2i64]] in
603def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)),
604          (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>;
605
606//===----------------------------------------------------------------------===//
607// Integer binary arithmetic
608//===----------------------------------------------------------------------===//
609
610multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
611  defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
612  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
613}
614
615multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
616  defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
617  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
618}
619
620multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
621  defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
622  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
623}
624
625// Integer addition: add / add_saturate_s / add_saturate_u
626let isCommutable = 1 in {
627defm ADD : SIMDBinaryInt<add, "add", 87>;
628defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 88>;
629defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 89>;
630} // isCommutable = 1
631
632// Integer subtraction: sub / sub_saturate_s / sub_saturate_u
633defm SUB : SIMDBinaryInt<sub, "sub", 90>;
634defm SUB_SAT_S :
635  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 91>;
636defm SUB_SAT_U :
637  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>;
638
639// Integer multiplication: mul
640defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>;
641
642//===----------------------------------------------------------------------===//
643// Floating-point unary arithmetic
644//===----------------------------------------------------------------------===//
645
646multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
647  defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
648  defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
649}
650
651// Absolute value: abs
652defm ABS : SIMDUnaryFP<fabs, "abs", 149>;
653
654// Negation: neg
655defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
656
657// Square root: sqrt
658let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
659defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
660
661//===----------------------------------------------------------------------===//
662// Floating-point binary arithmetic
663//===----------------------------------------------------------------------===//
664
665multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
666  defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
667  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
668}
669
670// Addition: add
671let isCommutable = 1 in
672defm ADD : SIMDBinaryFP<fadd, "add", 154>;
673
674// Subtraction: sub
675defm SUB : SIMDBinaryFP<fsub, "sub", 155>;
676
677// Multiplication: mul
678let isCommutable = 1 in
679defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
680
681// Division: div
682let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
683defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
684
685// NaN-propagating minimum: min
686defm MIN : SIMDBinaryFP<fminimum, "min", 158>;
687
688// NaN-propagating maximum: max
689defm MAX : SIMDBinaryFP<fmaximum, "max", 159>;
690
691//===----------------------------------------------------------------------===//
692// Conversions
693//===----------------------------------------------------------------------===//
694
695multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
696                       string name, bits<32> simdop> {
697  defm op#_#vec_t#_#arg_t :
698    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
699           [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
700           name#"\t$dst, $vec", name, simdop>;
701}
702
703// Integer to floating point: convert
704defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
705defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
706defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
707defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
708
709// Floating point to integer with saturation: trunc_sat
710defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
711defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
712defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
713defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
714
715// Lower llvm.wasm.trunc.saturate.* to saturating instructions
716def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
717          (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
718def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
719          (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>;
720def : Pat<(v2i64 (int_wasm_trunc_saturate_signed (v2f64 V128:$src))),
721          (fp_to_sint_v2i64_v2f64 (v2f64 V128:$src))>;
722def : Pat<(v2i64 (int_wasm_trunc_saturate_unsigned (v2f64 V128:$src))),
723          (fp_to_uint_v2i64_v2f64 (v2f64 V128:$src))>;
724
725// Bitcasts are nops
726// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
727foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
728foreach t2 = !foldl(
729  []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
730  acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
731    acc, !listconcat(acc, [cur])
732  )
733) in
734def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
735