WebAssemblyInstrSIMD.td revision 344779 
1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// WebAssembly SIMD operand code-gen constructs.
12///
13//===----------------------------------------------------------------------===//
14
15// Instructions requiring HasSIMD128 and the simd128 prefix byte
16multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
17                  list<dag> pattern_r, string asmstr_r = "",
18                  string asmstr_s = "", bits<32> simdop = -1> {
19  defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
20              !or(0xfd00, !and(0xff, simdop))>,
21            Requires<[HasSIMD128]>;
22}
23
24defm "" : ARGUMENT<V128, v16i8>;
25defm "" : ARGUMENT<V128, v8i16>;
26defm "" : ARGUMENT<V128, v4i32>;
27defm "" : ARGUMENT<V128, v2i64>;
28defm "" : ARGUMENT<V128, v4f32>;
29defm "" : ARGUMENT<V128, v2f64>;
30
31// Constrained immediate argument types
32foreach SIZE = [8, 16] in
33def ImmI#SIZE : ImmLeaf<i32,
34  "return ((uint64_t)Imm & ((1UL << "#SIZE#") - 1)) == (uint64_t)Imm;"
35>;
36foreach SIZE = [2, 4, 8, 16, 32] in
37def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
38
39//===----------------------------------------------------------------------===//
40// Load and store
41//===----------------------------------------------------------------------===//
42
43// Load: v128.load
44multiclass SIMDLoad<ValueType vec_t> {
45  let mayLoad = 1 in
46  defm LOAD_#vec_t :
47    SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
48           (outs), (ins P2Align:$align, offset32_op:$off), [],
49           "v128.load\t$dst, ${off}(${addr})$align",
50           "v128.load\t$off$align", 0>;
51}
52
53foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
54defm "" : SIMDLoad<vec_t>;
55
56// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
57def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
58def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
59def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;
60def : LoadPatGlobalAddr<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
61def : LoadPatExternalSym<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
62def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
63def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
64def : LoadPatExternSymOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
65}
66
67// Store: v128.store
68multiclass SIMDStore<ValueType vec_t> {
69  let mayStore = 1 in
70  defm STORE_#vec_t :
71    SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
72           (outs), (ins P2Align:$align, offset32_op:$off), [],
73           "v128.store\t${off}(${addr})$align, $vec",
74           "v128.store\t$off$align", 1>;
75}
76
77foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
78defm "" : SIMDStore<vec_t>;
79
80// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
81def : StorePatNoOffset<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
82def : StorePatImmOff<vec_t, store, regPlusImm, !cast<NI>("STORE_"#vec_t)>;
83def : StorePatImmOff<vec_t, store, or_is_add, !cast<NI>("STORE_"#vec_t)>;
84def : StorePatGlobalAddr<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
85def : StorePatExternalSym<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
86def : StorePatOffsetOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
87def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
88def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
89}
90
91//===----------------------------------------------------------------------===//
92// Constructing SIMD values
93//===----------------------------------------------------------------------===//
94
95// Constant: v128.const
96multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
97  let isMoveImm = 1, isReMaterializable = 1,
98    Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
99  defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
100                                  [(set V128:$dst, (vec_t pat))],
101                                  "v128.const\t$dst, "#args,
102                                  "v128.const\t"#args, 2>;
103}
104
105defm "" : ConstVec<v16i8,
106                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
107                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
108                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
109                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
110                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
111                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
112                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
113                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
114                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
115                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
116                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
117                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
118                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
119                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
120defm "" : ConstVec<v8i16,
121                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
122                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
123                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
124                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
125                   (build_vector
126                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
127                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
128                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
129defm "" : ConstVec<v4i32,
130                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
131                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
132                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
133                                 (i32 imm:$i2), (i32 imm:$i3)),
134                   "$i0, $i1, $i2, $i3">;
135defm "" : ConstVec<v2i64,
136                   (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
137                   (build_vector (i64 imm:$i0), (i64 imm:$i1)),
138                   "$i0, $i1">;
139defm "" : ConstVec<v4f32,
140                   (ins f32imm_op:$i0, f32imm_op:$i1,
141                        f32imm_op:$i2, f32imm_op:$i3),
142                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
143                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
144                   "$i0, $i1, $i2, $i3">;
145defm "" : ConstVec<v2f64,
146                  (ins f64imm_op:$i0, f64imm_op:$i1),
147                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
148                  "$i0, $i1">;
149
150// Shuffle lanes: shuffle
151defm SHUFFLE :
152  SIMD_I<(outs V128:$dst),
153         (ins V128:$x, V128:$y,
154           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
155           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
156           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
157           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
158           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
159           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
160           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
161           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
162         (outs),
163         (ins
164           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
165           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
166           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
167           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
168           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
169           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
170           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
171           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
172         [],
173         "v8x16.shuffle\t$dst, $x, $y, "#
174           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
175           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
176         "v8x16.shuffle\t"#
177           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
178           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
179         3>;
180
181// Shuffles after custom lowering
182def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
183def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
184foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
185def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
186            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
187            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
188            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
189            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
190            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
191            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
192            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
193            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
194          (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
195            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
196            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
197            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
198            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
199            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
200            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
201            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
202            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
203}
204
205// Create vector with identical lanes: splat
206def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
207def splat4 : PatFrag<(ops node:$x), (build_vector
208                       node:$x, node:$x, node:$x, node:$x)>;
209def splat8 : PatFrag<(ops node:$x), (build_vector
210                       node:$x, node:$x, node:$x, node:$x,
211                       node:$x, node:$x, node:$x, node:$x)>;
212def splat16 : PatFrag<(ops node:$x), (build_vector
213                        node:$x, node:$x, node:$x, node:$x,
214                        node:$x, node:$x, node:$x, node:$x,
215                        node:$x, node:$x, node:$x, node:$x,
216                        node:$x, node:$x, node:$x, node:$x)>;
217
218multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
219                 PatFrag splat_pat, bits<32> simdop> {
220  // Prefer splats over v128.const for const splats (65 is lowest that works)
221  let AddedComplexity = 65 in
222  defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
223                             [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
224                             vec#".splat\t$dst, $x", vec#".splat", simdop>;
225}
226
227defm "" : Splat<v16i8, "i8x16", I32, splat16, 4>;
228defm "" : Splat<v8i16, "i16x8", I32, splat8, 8>;
229defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
230defm "" : Splat<v2i64, "i64x2", I64, splat2, 15>;
231defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
232defm "" : Splat<v2f64, "f64x2", F64, splat2, 21>;
233
234//===----------------------------------------------------------------------===//
235// Accessing lanes
236//===----------------------------------------------------------------------===//
237
238// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
239multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
240                       WebAssemblyRegClass reg_t, bits<32> simdop,
241                       string suffix = "", SDNode extract = vector_extract> {
242  defm EXTRACT_LANE_#vec_t#suffix :
243      SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
244             (outs), (ins vec_i8imm_op:$idx),
245             [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
246             vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
247             vec#".extract_lane"#suffix#"\t$idx", simdop>;
248}
249
250multiclass ExtractPat<ValueType lane_t, int mask> {
251  def _s : PatFrag<(ops node:$vec, node:$idx),
252                   (i32 (sext_inreg
253                     (i32 (vector_extract
254                       node:$vec,
255                       node:$idx
256                     )),
257                     lane_t
258                   ))>;
259  def _u : PatFrag<(ops node:$vec, node:$idx),
260                   (i32 (and
261                     (i32 (vector_extract
262                       node:$vec,
263                       node:$idx
264                     )),
265                     (i32 mask)
266                   ))>;
267}
268
269defm extract_i8x16 : ExtractPat<i8, 0xff>;
270defm extract_i16x8 : ExtractPat<i16, 0xffff>;
271
272multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
273  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
274                        !cast<PatFrag>("extract_i8x16"#sign)>;
275  defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 4), sign,
276                        !cast<PatFrag>("extract_i16x8"#sign)>;
277}
278
279defm "" : ExtractLaneExtended<"_s", 5>;
280let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
281defm "" : ExtractLaneExtended<"_u", 6>;
282defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
283defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
284defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
285defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>;
286
287// It would be more conventional to use unsigned extracts, but v8
288// doesn't implement them yet
289def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
290          (EXTRACT_LANE_v16i8_s V128:$vec, (i32 LaneIdx16:$idx))>;
291def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
292          (EXTRACT_LANE_v8i16_s V128:$vec, (i32 LaneIdx8:$idx))>;
293
294// Lower undef lane indices to zero
295def : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)),
296          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
297def : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)),
298          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
299def : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)),
300          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
301def : Pat<(i32 (vector_extract (v8i16 V128:$vec), undef)),
302          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
303def : Pat<(sext_inreg (i32 (vector_extract (v16i8 V128:$vec), undef)), i8),
304          (EXTRACT_LANE_v16i8_s V128:$vec, 0)>;
305def : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16),
306          (EXTRACT_LANE_v8i16_s V128:$vec, 0)>;
307def : Pat<(vector_extract (v4i32 V128:$vec), undef),
308          (EXTRACT_LANE_v4i32 V128:$vec, 0)>;
309def : Pat<(vector_extract (v2i64 V128:$vec), undef),
310          (EXTRACT_LANE_v2i64 V128:$vec, 0)>;
311def : Pat<(vector_extract (v4f32 V128:$vec), undef),
312          (EXTRACT_LANE_v4f32 V128:$vec, 0)>;
313def : Pat<(vector_extract (v2f64 V128:$vec), undef),
314          (EXTRACT_LANE_v2f64 V128:$vec, 0)>;
315
316// Replace lane value: replace_lane
317multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
318                       WebAssemblyRegClass reg_t, ValueType lane_t,
319                       bits<32> simdop> {
320  defm REPLACE_LANE_#vec_t :
321      SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
322             (outs), (ins vec_i8imm_op:$idx),
323             [(set V128:$dst, (vector_insert
324               (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
325             vec#".replace_lane\t$dst, $vec, $idx, $x",
326             vec#".replace_lane\t$idx", simdop>;
327}
328
329defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 7>;
330defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 11>;
331defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 14>;
332defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 17>;
333defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>;
334defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 23>;
335
336// Lower undef lane indices to zero
337def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
338          (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
339def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
340          (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
341def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
342          (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;
343def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
344          (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>;
345def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
346          (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>;
347def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
348          (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>;
349
350// Arbitrary other BUILD_VECTOR patterns
351def : Pat<(v16i8 (build_vector
352            (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
353            (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7),
354            (i32 I32:$x8), (i32 I32:$x9), (i32 I32:$x10), (i32 I32:$x11),
355            (i32 I32:$x12), (i32 I32:$x13), (i32 I32:$x14), (i32 I32:$x15)
356          )),
357          (v16i8 (REPLACE_LANE_v16i8
358            (v16i8 (REPLACE_LANE_v16i8
359              (v16i8 (REPLACE_LANE_v16i8
360                (v16i8 (REPLACE_LANE_v16i8
361                  (v16i8 (REPLACE_LANE_v16i8
362                    (v16i8 (REPLACE_LANE_v16i8
363                      (v16i8 (REPLACE_LANE_v16i8
364                        (v16i8 (REPLACE_LANE_v16i8
365                          (v16i8 (REPLACE_LANE_v16i8
366                            (v16i8 (REPLACE_LANE_v16i8
367                              (v16i8 (REPLACE_LANE_v16i8
368                                (v16i8 (REPLACE_LANE_v16i8
369                                  (v16i8 (REPLACE_LANE_v16i8
370                                    (v16i8 (REPLACE_LANE_v16i8
371                                      (v16i8 (REPLACE_LANE_v16i8
372                                        (v16i8 (SPLAT_v16i8 (i32 I32:$x0))),
373                                        1, I32:$x1
374                                      )),
375                                      2, I32:$x2
376                                    )),
377                                    3, I32:$x3
378                                  )),
379                                  4, I32:$x4
380                                )),
381                                5, I32:$x5
382                              )),
383                              6, I32:$x6
384                            )),
385                            7, I32:$x7
386                          )),
387                          8, I32:$x8
388                        )),
389                        9, I32:$x9
390                      )),
391                      10, I32:$x10
392                    )),
393                    11, I32:$x11
394                  )),
395                  12, I32:$x12
396                )),
397                13, I32:$x13
398              )),
399              14, I32:$x14
400            )),
401            15, I32:$x15
402          ))>;
403def : Pat<(v8i16 (build_vector
404            (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
405            (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7)
406          )),
407          (v8i16 (REPLACE_LANE_v8i16
408            (v8i16 (REPLACE_LANE_v8i16
409              (v8i16 (REPLACE_LANE_v8i16
410                (v8i16 (REPLACE_LANE_v8i16
411                  (v8i16 (REPLACE_LANE_v8i16
412                    (v8i16 (REPLACE_LANE_v8i16
413                      (v8i16 (REPLACE_LANE_v8i16
414                        (v8i16 (SPLAT_v8i16 (i32 I32:$x0))),
415                        1, I32:$x1
416                      )),
417                      2, I32:$x2
418                    )),
419                    3, I32:$x3
420                  )),
421                  4, I32:$x4
422                )),
423                5, I32:$x5
424              )),
425              6, I32:$x6
426            )),
427            7, I32:$x7
428          ))>;
429def : Pat<(v4i32 (build_vector
430            (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3)
431          )),
432          (v4i32 (REPLACE_LANE_v4i32
433            (v4i32 (REPLACE_LANE_v4i32
434              (v4i32 (REPLACE_LANE_v4i32
435                (v4i32 (SPLAT_v4i32 (i32 I32:$x0))),
436                1, I32:$x1
437              )),
438              2, I32:$x2
439            )),
440            3, I32:$x3
441          ))>;
442def : Pat<(v2i64 (build_vector (i64 I64:$x0), (i64 I64:$x1))),
443          (v2i64 (REPLACE_LANE_v2i64
444            (v2i64 (SPLAT_v2i64 (i64 I64:$x0))), 1, I64:$x1))>;
445def : Pat<(v4f32 (build_vector
446            (f32 F32:$x0), (f32 F32:$x1), (f32 F32:$x2), (f32 F32:$x3)
447          )),
448          (v4f32 (REPLACE_LANE_v4f32
449            (v4f32 (REPLACE_LANE_v4f32
450              (v4f32 (REPLACE_LANE_v4f32
451                (v4f32 (SPLAT_v4f32 (f32 F32:$x0))),
452                1, F32:$x1
453              )),
454              2, F32:$x2
455            )),
456            3, F32:$x3
457          ))>;
458def : Pat<(v2f64 (build_vector (f64 F64:$x0), (f64 F64:$x1))),
459          (v2f64 (REPLACE_LANE_v2f64
460            (v2f64 (SPLAT_v2f64 (f64 F64:$x0))), 1, F64:$x1))>;
461
462//===----------------------------------------------------------------------===//
463// Comparisons
464//===----------------------------------------------------------------------===//
465
466multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
467                         string name, CondCode cond, bits<32> simdop> {
468  defm _#vec_t :
469    SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
470           [(set (out_t V128:$dst),
471             (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
472           )],
473           vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
474}
475
476multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
477  defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
478  defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
479                          !add(baseInst, 10)>;
480  defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
481                          !add(baseInst, 20)>;
482}
483
484multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
485  defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
486  defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
487                          !add(baseInst, 6)>;
488}
489
490// Equality: eq
491let isCommutable = 1 in {
492defm EQ : SIMDConditionInt<"eq", SETEQ, 24>;
493defm EQ : SIMDConditionFP<"eq", SETOEQ, 64>;
494} // isCommutable = 1
495
496// Non-equality: ne
497let isCommutable = 1 in {
498defm NE : SIMDConditionInt<"ne", SETNE, 25>;
499defm NE : SIMDConditionFP<"ne", SETUNE, 65>;
500} // isCommutable = 1
501
502// Less than: lt_s / lt_u / lt
503defm LT_S : SIMDConditionInt<"lt_s", SETLT, 26>;
504defm LT_U : SIMDConditionInt<"lt_u", SETULT, 27>;
505defm LT : SIMDConditionFP<"lt", SETOLT, 66>;
506
507// Greater than: gt_s / gt_u / gt
508defm GT_S : SIMDConditionInt<"gt_s", SETGT, 28>;
509defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 29>;
510defm GT : SIMDConditionFP<"gt", SETOGT, 67>;
511
512// Less than or equal: le_s / le_u / le
513defm LE_S : SIMDConditionInt<"le_s", SETLE, 30>;
514defm LE_U : SIMDConditionInt<"le_u", SETULE, 31>;
515defm LE : SIMDConditionFP<"le", SETOLE, 68>;
516
517// Greater than or equal: ge_s / ge_u / ge
518defm GE_S : SIMDConditionInt<"ge_s", SETGE, 32>;
519defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>;
520defm GE : SIMDConditionFP<"ge", SETOGE, 69>;
521
522// Lower float comparisons that don't care about NaN to standard WebAssembly
523// float comparisons. These instructions are generated in the target-independent
524// expansion of unordered comparisons and ordered ne.
525def : Pat<(v4i32 (seteq (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
526          (v4i32 (EQ_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
527def : Pat<(v4i32 (setne (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
528          (v4i32 (NE_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
529def : Pat<(v2i64 (seteq (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
530          (v2i64 (EQ_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
531def : Pat<(v2i64 (setne (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
532          (v2i64 (NE_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
533
534//===----------------------------------------------------------------------===//
535// Bitwise operations
536//===----------------------------------------------------------------------===//
537
538multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
539                      bits<32> simdop> {
540  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
541                        (outs), (ins),
542                        [(set (vec_t V128:$dst),
543                          (node (vec_t V128:$lhs), (vec_t V128:$rhs))
544                        )],
545                        vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
546                        simdop>;
547}
548
549multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
550  defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
551  defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
552  defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
553  defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
554}
555
556multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name,
557                     bits<32> simdop> {
558  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
559                        [(set (vec_t V128:$dst),
560                          (vec_t (node (vec_t V128:$vec)))
561                        )],
562                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
563}
564
565// Bitwise logic: v128.not
566foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
567defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>;
568
569// Bitwise logic: v128.and / v128.or / v128.xor
570let isCommutable = 1 in {
571defm AND : SIMDBitwise<and, "and", 77>;
572defm OR : SIMDBitwise<or, "or", 78>;
573defm XOR : SIMDBitwise<xor, "xor", 79>;
574} // isCommutable = 1
575
576// Bitwise select: v128.bitselect
577foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
578  defm BITSELECT_#vec_t :
579    SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
580           [(set (vec_t V128:$dst),
581             (vec_t (int_wasm_bitselect
582               (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
583             ))
584           )],
585           "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>;
586
587// Bitselect is equivalent to (c & v1) | (~c & v2)
588foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
589  def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
590              (and (vnot V128:$c), (vec_t V128:$v2)))),
591            (!cast<Instruction>("BITSELECT_"#vec_t)
592              V128:$v1, V128:$v2, V128:$c)>;
593
594//===----------------------------------------------------------------------===//
595// Integer unary arithmetic
596//===----------------------------------------------------------------------===//
597
598multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
599  defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>;
600  defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
601  defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
602  defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
603}
604
605multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
606                         bits<32> simdop> {
607  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
608                        [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
609                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
610}
611
612multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
613  defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>;
614  defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>;
615  defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>;
616  defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>;
617}
618
619// Integer vector negation
620def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
621
622// Integer negation: neg
623defm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
624
625// Any lane true: any_true
626defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>;
627
628// All lanes true: all_true
629defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>;
630
631//===----------------------------------------------------------------------===//
632// Bit shifts
633//===----------------------------------------------------------------------===//
634
635multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec,
636                     string name, bits<32> simdop> {
637  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
638                        (outs), (ins),
639                        [(set (vec_t V128:$dst),
640                          (node V128:$vec, (vec_t shift_vec)))],
641                        vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
642}
643
644multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
645  defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>;
646  defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name,
647                      !add(baseInst, 17)>;
648  defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name,
649                      !add(baseInst, 34)>;
650  defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
651                      name, !add(baseInst, 51)>;
652}
653
654// Left shift by scalar: shl
655defm SHL : SIMDShiftInt<shl, "shl", 84>;
656
657// Right shift by scalar: shr_s / shr_u
658defm SHR_S : SIMDShiftInt<sra, "shr_s", 85>;
659defm SHR_U : SIMDShiftInt<srl, "shr_u", 86>;
660
661// Truncate i64 shift operands to i32s
662foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in
663def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))),
664          (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
665
666// 2xi64 shifts with constant shift amounts are custom lowered to avoid wrapping
667def wasm_shift_t : SDTypeProfile<1, 2,
668  [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]
669>;
670def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>;
671def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>;
672def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>;
673foreach shifts = [[wasm_shl, SHL_v2i64],
674                  [wasm_shr_s, SHR_S_v2i64],
675                  [wasm_shr_u, SHR_U_v2i64]] in
676def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)),
677          (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>;
678
679//===----------------------------------------------------------------------===//
680// Integer binary arithmetic
681//===----------------------------------------------------------------------===//
682
683multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
684  defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
685  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
686}
687
688multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
689  defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
690  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
691}
692
693multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
694  defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
695  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
696}
697
698// Integer addition: add / add_saturate_s / add_saturate_u
699let isCommutable = 1 in {
700defm ADD : SIMDBinaryInt<add, "add", 87>;
701defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 88>;
702defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 89>;
703} // isCommutable = 1
704
705// Integer subtraction: sub / sub_saturate_s / sub_saturate_u
706defm SUB : SIMDBinaryInt<sub, "sub", 90>;
707defm SUB_SAT_S :
708  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 91>;
709defm SUB_SAT_U :
710  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>;
711
712// Integer multiplication: mul
713defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>;
714
715//===----------------------------------------------------------------------===//
716// Floating-point unary arithmetic
717//===----------------------------------------------------------------------===//
718
719multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
720  defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
721  defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
722}
723
724// Absolute value: abs
725defm ABS : SIMDUnaryFP<fabs, "abs", 149>;
726
727// Negation: neg
728defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
729
730// Square root: sqrt
731let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
732defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
733
734//===----------------------------------------------------------------------===//
735// Floating-point binary arithmetic
736//===----------------------------------------------------------------------===//
737
738multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
739  defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
740  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
741}
742
743// Addition: add
744let isCommutable = 1 in
745defm ADD : SIMDBinaryFP<fadd, "add", 154>;
746
747// Subtraction: sub
748defm SUB : SIMDBinaryFP<fsub, "sub", 155>;
749
750// Multiplication: mul
751let isCommutable = 1 in
752defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
753
754// Division: div
755let Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
756defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
757
758// NaN-propagating minimum: min
759defm MIN : SIMDBinaryFP<fminimum, "min", 158>;
760
761// NaN-propagating maximum: max
762defm MAX : SIMDBinaryFP<fmaximum, "max", 159>;
763
764//===----------------------------------------------------------------------===//
765// Conversions
766//===----------------------------------------------------------------------===//
767
768multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
769                       string name, bits<32> simdop> {
770  defm op#_#vec_t#_#arg_t :
771    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
772           [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
773           name#"\t$dst, $vec", name, simdop>;
774}
775
776// Integer to floating point: convert
777defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
778defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
779defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
780defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
781
782// Floating point to integer with saturation: trunc_sat
783defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
784defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
785defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
786defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
787
788// Lower llvm.wasm.trunc.saturate.* to saturating instructions
789def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
790          (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
791def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
792          (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>;
793def : Pat<(v2i64 (int_wasm_trunc_saturate_signed (v2f64 V128:$src))),
794          (fp_to_sint_v2i64_v2f64 (v2f64 V128:$src))>;
795def : Pat<(v2i64 (int_wasm_trunc_saturate_unsigned (v2f64 V128:$src))),
796          (fp_to_uint_v2i64_v2f64 (v2f64 V128:$src))>;
797
798// Bitcasts are nops
799// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
800foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
801foreach t2 = !foldl(
802  []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
803  acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
804    acc, !listconcat(acc, [cur])
805  )
806) in
807def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
808