WebAssemblyInstrInfo.cpp revision 321369
1285163Sdim//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===// 2285163Sdim// 3285163Sdim// The LLVM Compiler Infrastructure 4285163Sdim// 5285163Sdim// This file is distributed under the University of Illinois Open Source 6285163Sdim// License. See LICENSE.TXT for details. 7285163Sdim// 8285163Sdim//===----------------------------------------------------------------------===// 9285163Sdim/// 10285163Sdim/// \file 11285163Sdim/// \brief This file contains the WebAssembly implementation of the 12285163Sdim/// TargetInstrInfo class. 13285163Sdim/// 14285163Sdim//===----------------------------------------------------------------------===// 15285163Sdim 16285163Sdim#include "WebAssemblyInstrInfo.h" 17285163Sdim#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 18309124Sdim#include "WebAssemblyMachineFunctionInfo.h" 19285163Sdim#include "WebAssemblySubtarget.h" 20285163Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 21285163Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 22285163Sdim#include "llvm/CodeGen/MachineMemOperand.h" 23285163Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 24285163Sdimusing namespace llvm; 25285163Sdim 26285163Sdim#define DEBUG_TYPE "wasm-instr-info" 27285163Sdim 28296417Sdim#define GET_INSTRINFO_CTOR_DTOR 29296417Sdim#include "WebAssemblyGenInstrInfo.inc" 30296417Sdim 31285163SdimWebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI) 32296417Sdim : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN, 33296417Sdim WebAssembly::ADJCALLSTACKUP), 34296417Sdim RI(STI.getTargetTriple()) {} 35296417Sdim 36309124Sdimbool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable( 37309124Sdim const MachineInstr &MI, AliasAnalysis *AA) const { 38309124Sdim switch (MI.getOpcode()) { 39309124Sdim case WebAssembly::CONST_I32: 40309124Sdim case WebAssembly::CONST_I64: 41309124Sdim case WebAssembly::CONST_F32: 42309124Sdim case WebAssembly::CONST_F64: 43309124Sdim // isReallyTriviallyReMaterializableGeneric misses these because of the 44309124Sdim // ARGUMENTS implicit def, so we manualy override it here. 45309124Sdim return true; 46309124Sdim default: 47309124Sdim return false; 48309124Sdim } 49309124Sdim} 50309124Sdim 51296417Sdimvoid WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 52296417Sdim MachineBasicBlock::iterator I, 53309124Sdim const DebugLoc &DL, unsigned DestReg, 54296417Sdim unsigned SrcReg, bool KillSrc) const { 55296417Sdim // This method is called by post-RA expansion, which expects only pregs to 56296417Sdim // exist. However we need to handle both here. 57296417Sdim auto &MRI = MBB.getParent()->getRegInfo(); 58309124Sdim const TargetRegisterClass *RC = 59309124Sdim TargetRegisterInfo::isVirtualRegister(DestReg) 60309124Sdim ? MRI.getRegClass(DestReg) 61309124Sdim : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); 62296417Sdim 63314564Sdim unsigned CopyOpcode; 64296417Sdim if (RC == &WebAssembly::I32RegClass) 65314564Sdim CopyOpcode = WebAssembly::COPY_I32; 66296417Sdim else if (RC == &WebAssembly::I64RegClass) 67314564Sdim CopyOpcode = WebAssembly::COPY_I64; 68296417Sdim else if (RC == &WebAssembly::F32RegClass) 69314564Sdim CopyOpcode = WebAssembly::COPY_F32; 70296417Sdim else if (RC == &WebAssembly::F64RegClass) 71314564Sdim CopyOpcode = WebAssembly::COPY_F64; 72296417Sdim else 73296417Sdim llvm_unreachable("Unexpected register class"); 74296417Sdim 75314564Sdim BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) 76296417Sdim .addReg(SrcReg, KillSrc ? RegState::Kill : 0); 77296417Sdim} 78296417Sdim 79309124SdimMachineInstr * 80309124SdimWebAssemblyInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, 81309124Sdim unsigned OpIdx1, 82309124Sdim unsigned OpIdx2) const { 83309124Sdim // If the operands are stackified, we can't reorder them. 84309124Sdim WebAssemblyFunctionInfo &MFI = 85309124Sdim *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>(); 86309124Sdim if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) || 87309124Sdim MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg())) 88309124Sdim return nullptr; 89309124Sdim 90309124Sdim // Otherwise use the default implementation. 91309124Sdim return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); 92309124Sdim} 93309124Sdim 94296417Sdim// Branch analysis. 95309124Sdimbool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, 96296417Sdim MachineBasicBlock *&TBB, 97296417Sdim MachineBasicBlock *&FBB, 98296417Sdim SmallVectorImpl<MachineOperand> &Cond, 99296417Sdim bool /*AllowModify*/) const { 100296417Sdim bool HaveCond = false; 101296417Sdim for (MachineInstr &MI : MBB.terminators()) { 102296417Sdim switch (MI.getOpcode()) { 103296417Sdim default: 104296417Sdim // Unhandled instruction; bail out. 105296417Sdim return true; 106296417Sdim case WebAssembly::BR_IF: 107296417Sdim if (HaveCond) 108296417Sdim return true; 109296417Sdim // If we're running after CFGStackify, we can't optimize further. 110309124Sdim if (!MI.getOperand(0).isMBB()) 111296417Sdim return true; 112296417Sdim Cond.push_back(MachineOperand::CreateImm(true)); 113309124Sdim Cond.push_back(MI.getOperand(1)); 114309124Sdim TBB = MI.getOperand(0).getMBB(); 115296417Sdim HaveCond = true; 116296417Sdim break; 117296417Sdim case WebAssembly::BR_UNLESS: 118296417Sdim if (HaveCond) 119296417Sdim return true; 120296417Sdim // If we're running after CFGStackify, we can't optimize further. 121309124Sdim if (!MI.getOperand(0).isMBB()) 122296417Sdim return true; 123296417Sdim Cond.push_back(MachineOperand::CreateImm(false)); 124309124Sdim Cond.push_back(MI.getOperand(1)); 125309124Sdim TBB = MI.getOperand(0).getMBB(); 126296417Sdim HaveCond = true; 127296417Sdim break; 128296417Sdim case WebAssembly::BR: 129296417Sdim // If we're running after CFGStackify, we can't optimize further. 130296417Sdim if (!MI.getOperand(0).isMBB()) 131296417Sdim return true; 132296417Sdim if (!HaveCond) 133296417Sdim TBB = MI.getOperand(0).getMBB(); 134296417Sdim else 135296417Sdim FBB = MI.getOperand(0).getMBB(); 136296417Sdim break; 137296417Sdim } 138296417Sdim if (MI.isBarrier()) 139296417Sdim break; 140296417Sdim } 141296417Sdim 142296417Sdim return false; 143296417Sdim} 144296417Sdim 145314564Sdimunsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, 146314564Sdim int *BytesRemoved) const { 147314564Sdim assert(!BytesRemoved && "code size not handled"); 148314564Sdim 149296417Sdim MachineBasicBlock::instr_iterator I = MBB.instr_end(); 150296417Sdim unsigned Count = 0; 151296417Sdim 152296417Sdim while (I != MBB.instr_begin()) { 153296417Sdim --I; 154296417Sdim if (I->isDebugValue()) 155296417Sdim continue; 156296417Sdim if (!I->isTerminator()) 157296417Sdim break; 158296417Sdim // Remove the branch. 159296417Sdim I->eraseFromParent(); 160296417Sdim I = MBB.instr_end(); 161296417Sdim ++Count; 162296417Sdim } 163296417Sdim 164296417Sdim return Count; 165296417Sdim} 166296417Sdim 167314564Sdimunsigned WebAssemblyInstrInfo::insertBranch(MachineBasicBlock &MBB, 168296417Sdim MachineBasicBlock *TBB, 169296417Sdim MachineBasicBlock *FBB, 170296417Sdim ArrayRef<MachineOperand> Cond, 171314564Sdim const DebugLoc &DL, 172314564Sdim int *BytesAdded) const { 173314564Sdim assert(!BytesAdded && "code size not handled"); 174314564Sdim 175296417Sdim if (Cond.empty()) { 176296417Sdim if (!TBB) 177296417Sdim return 0; 178296417Sdim 179296417Sdim BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB); 180296417Sdim return 1; 181296417Sdim } 182296417Sdim 183296417Sdim assert(Cond.size() == 2 && "Expected a flag and a successor block"); 184296417Sdim 185296417Sdim if (Cond[0].getImm()) { 186321369Sdim BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); 187296417Sdim } else { 188321369Sdim BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]); 189296417Sdim } 190296417Sdim if (!FBB) 191296417Sdim return 1; 192296417Sdim 193296417Sdim BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB); 194296417Sdim return 2; 195296417Sdim} 196296417Sdim 197314564Sdimbool WebAssemblyInstrInfo::reverseBranchCondition( 198296417Sdim SmallVectorImpl<MachineOperand> &Cond) const { 199296417Sdim assert(Cond.size() == 2 && "Expected a flag and a successor block"); 200296417Sdim Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm()); 201296417Sdim return false; 202296417Sdim} 203