WebAssemblyInstrFormats.td revision 344779
1//=- WebAssemblyInstrFormats.td - WebAssembly Instr. Formats -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// WebAssembly instruction format definitions. 12/// 13//===----------------------------------------------------------------------===// 14 15// WebAssembly Instruction Format. 16// We instantiate 2 of these for every actual instruction (register based 17// and stack based), see below. 18class WebAssemblyInst<bits<32> inst, string asmstr, string stack> : StackRel, 19 Instruction { 20 bits<32> Inst = inst; // Instruction encoding. 21 string StackBased = stack; 22 string BaseName = NAME; 23 let Namespace = "WebAssembly"; 24 let Pattern = []; 25 let AsmString = asmstr; 26} 27 28// Normal instructions. Default instantiation of a WebAssemblyInst. 29class NI<dag oops, dag iops, list<dag> pattern, string stack, 30 string asmstr = "", bits<32> inst = -1> 31 : WebAssemblyInst<inst, asmstr, stack> { 32 dag OutOperandList = oops; 33 dag InOperandList = iops; 34 let Pattern = pattern; 35 let Defs = [ARGUMENTS]; 36} 37 38// Generates both register and stack based versions of one actual instruction. 39// We have 2 sets of operands (oops & iops) for the register and stack 40// based version of this instruction, as well as the corresponding asmstr. 41// The register versions have virtual-register operands which correspond to wasm 42// locals or stack locations. Each use and def of the register corresponds to an 43// implicit local.get / local.set or access of stack operands in wasm. These 44// instructions are used for ISel and all MI passes. The stack versions of the 45// instructions do not have register operands (they implicitly operate on the 46// stack), and local.gets and local.sets are explicit. The register instructions 47// are converted to their corresponding stack instructions before lowering to 48// MC. 49// Every instruction should want to be based on this multi-class to guarantee 50// there is always an equivalent pair of instructions. 51multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 52 list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "", 53 bits<32> inst = -1> { 54 let isCodeGenOnly = 1 in 55 def "" : NI<oops_r, iops_r, pattern_r, "false", asmstr_r, inst>; 56 let BaseName = NAME in 57 def _S : NI<oops_s, iops_s, [], "true", asmstr_s, inst>; 58} 59 60// For instructions that have no register ops, so both sets are the same. 61multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "", 62 bits<32> inst = -1> { 63 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>; 64} 65