WebAssemblyInstrFormats.td revision 341825
1//=- WebAssemblyInstrFormats.td - WebAssembly Instr. Formats -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// WebAssembly instruction format definitions. 12/// 13//===----------------------------------------------------------------------===// 14 15// WebAssembly Instruction Format. 16// We instantiate 2 of these for every actual instruction (register based 17// and stack based), see below. 18class WebAssemblyInst<bits<32> inst, string asmstr, bit stack> : Instruction { 19 field bits<32> Inst = inst; // Instruction encoding. 20 field bit StackBased = stack; 21 let Namespace = "WebAssembly"; 22 let Pattern = []; 23 let AsmString = asmstr; 24} 25 26// Normal instructions. Default instantiation of a WebAssemblyInst. 27class NI<dag oops, dag iops, list<dag> pattern, bit stack, string asmstr = "", 28 bits<32> inst = -1> 29 : WebAssemblyInst<inst, asmstr, stack> { 30 dag OutOperandList = oops; 31 dag InOperandList = iops; 32 let Pattern = pattern; 33} 34 35// Generates both register and stack based versions of one actual instruction. 36// We have 2 sets of operands (oops & iops) for the register and stack 37// based version of this instruction, as well as the corresponding asmstr. 38// The register versions have virtual-register operands which correspond to wasm 39// locals or stack locations. Each use and def of the register corresponds to an 40// implicit get_local / set_local or access of stack operands in wasm. These 41// instructions are used for ISel and all MI passes. The stack versions of the 42// instructions do not have register operands (they implicitly operate on the 43// stack), and get_locals and set_locals are explicit. The register instructions 44// are converted to their corresponding stack instructions before lowering to 45// MC. 46// Every instruction should want to be based on this multi-class to guarantee 47// there is always an equivalent pair of instructions. 48multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 49 list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "", 50 bits<32> inst = -1> { 51 def "" : NI<oops_r, iops_r, pattern_r, 0, asmstr_r, inst>; 52 def _S : NI<oops_s, iops_s, [], 1, asmstr_s, inst>; 53} 54 55// For instructions that have no register ops, so both sets are the same. 56multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "", 57 bits<32> inst = -1> { 58 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>; 59} 60 61multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 62 list<dag> pattern_r, string asmstr_r = "", 63 string asmstr_s = "", bits<32> inst = -1> { 64 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 65 inst>, 66 Requires<[HasSIMD128]>; 67} 68 69multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 70 list<dag> pattern_r, string asmstr_r = "", 71 string asmstr_s = "", bits<32> inst = -1> { 72 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 73 inst>, 74 Requires<[HasAtomics]>; 75} 76 77// Unary and binary instructions, for the local types that WebAssembly supports. 78multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst, 79 bits<32> i64Inst> { 80 defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins), 81 [(set I32:$dst, (node I32:$src))], 82 !strconcat("i32.", !strconcat(name, "\t$dst, $src")), 83 !strconcat("i32.", name), i32Inst>; 84 defm _I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins), 85 [(set I64:$dst, (node I64:$src))], 86 !strconcat("i64.", !strconcat(name, "\t$dst, $src")), 87 !strconcat("i64.", name), i64Inst>; 88} 89multiclass BinaryInt<SDNode node, string name, bits<32> i32Inst, 90 bits<32> i64Inst> { 91 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins), 92 [(set I32:$dst, (node I32:$lhs, I32:$rhs))], 93 !strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")), 94 !strconcat("i32.", name), i32Inst>; 95 defm _I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins), 96 [(set I64:$dst, (node I64:$lhs, I64:$rhs))], 97 !strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")), 98 !strconcat("i64.", name), i64Inst>; 99} 100multiclass UnaryFP<SDNode node, string name, bits<32> f32Inst, 101 bits<32> f64Inst> { 102 defm _F32 : I<(outs F32:$dst), (ins F32:$src), (outs), (ins), 103 [(set F32:$dst, (node F32:$src))], 104 !strconcat("f32.", !strconcat(name, "\t$dst, $src")), 105 !strconcat("f32.", name), f32Inst>; 106 defm _F64 : I<(outs F64:$dst), (ins F64:$src), (outs), (ins), 107 [(set F64:$dst, (node F64:$src))], 108 !strconcat("f64.", !strconcat(name, "\t$dst, $src")), 109 !strconcat("f64.", name), f64Inst>; 110} 111multiclass BinaryFP<SDNode node, string name, bits<32> f32Inst, 112 bits<32> f64Inst> { 113 defm _F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins), 114 [(set F32:$dst, (node F32:$lhs, F32:$rhs))], 115 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")), 116 !strconcat("f32.", name), f32Inst>; 117 defm _F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins), 118 [(set F64:$dst, (node F64:$lhs, F64:$rhs))], 119 !strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")), 120 !strconcat("f64.", name), f64Inst>; 121} 122multiclass SIMDBinary<SDNode node, SDNode fnode, string name> { 123 defm _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 124 (outs), (ins), 125 [(set (v16i8 V128:$dst), (node V128:$lhs, V128:$rhs))], 126 !strconcat("i8x16.", 127 !strconcat(name, "\t$dst, $lhs, $rhs")), 128 !strconcat("i8x16.", name)>; 129 defm _I16x8 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 130 (outs), (ins), 131 [(set (v8i16 V128:$dst), (node V128:$lhs, V128:$rhs))], 132 !strconcat("i16x8.", 133 !strconcat(name, "\t$dst, $lhs, $rhs")), 134 !strconcat("i16x8.", name)>; 135 defm _I32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 136 (outs), (ins), 137 [(set (v4i32 V128:$dst), (node V128:$lhs, V128:$rhs))], 138 !strconcat("i32x4.", 139 !strconcat(name, "\t$dst, $lhs, $rhs")), 140 !strconcat("i32x4.", name)>; 141 defm _F32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 142 (outs), (ins), 143 [(set (v4f32 V128:$dst), (fnode V128:$lhs, V128:$rhs))], 144 !strconcat("f32x4.", 145 !strconcat(name, "\t$dst, $lhs, $rhs")), 146 !strconcat("f32x4.", name)>; 147} 148multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> { 149 defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins), 150 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))], 151 !strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")), 152 !strconcat("i32.", name), i32Inst>; 153 defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins), 154 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))], 155 !strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")), 156 !strconcat("i64.", name), i64Inst>; 157} 158multiclass ComparisonFP<CondCode cond, string name, bits<32> f32Inst, bits<32> f64Inst> { 159 defm _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs), (outs), (ins), 160 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))], 161 !strconcat("f32.", !strconcat(name, "\t$dst, $lhs, $rhs")), 162 !strconcat("f32.", name), f32Inst>; 163 defm _F64 : I<(outs I32:$dst), (ins F64:$lhs, F64:$rhs), (outs), (ins), 164 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))], 165 !strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")), 166 !strconcat("f64.", name), f64Inst>; 167} 168