WebAssembly.td revision 285163 
1//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the WebAssembly architecture, which is
11// also known as "wasm".
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Target-independent interfaces which we are implementing
17//===----------------------------------------------------------------------===//
18
19include "llvm/Target/Target.td"
20
21//===----------------------------------------------------------------------===//
22// WebAssembly Subtarget features.
23//===----------------------------------------------------------------------===//
24
25def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
26                                      "Enable 128-bit SIMD">;
27
28//===----------------------------------------------------------------------===//
29// Architectures.
30//===----------------------------------------------------------------------===//
31
32//===----------------------------------------------------------------------===//
33// Register File Description
34//===----------------------------------------------------------------------===//
35
36include "WebAssemblyRegisterInfo.td"
37
38//===----------------------------------------------------------------------===//
39// Instruction Descriptions
40//===----------------------------------------------------------------------===//
41
42include "WebAssemblyInstrInfo.td"
43
44def WebAssemblyInstrInfo : InstrInfo;
45
46//===----------------------------------------------------------------------===//
47// WebAssembly Processors supported.
48//===----------------------------------------------------------------------===//
49
50// Minimal Viable Product.
51def : ProcessorModel<"mvp", NoSchedModel, []>;
52
53// Latest and greatest experimental version of WebAssembly. Bugs included!
54def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
55
56//===----------------------------------------------------------------------===//
57// Target Declaration
58//===----------------------------------------------------------------------===//
59
60def WebAssembly : Target {
61  let InstructionSet = WebAssemblyInstrInfo;
62}
63