SystemZRegisterInfo.td revision 314564
1251607Sdim//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim 10251607Sdim//===----------------------------------------------------------------------===// 11251607Sdim// Class definitions. 12251607Sdim//===----------------------------------------------------------------------===// 13251607Sdim 14251607Sdimclass SystemZReg<string n> : Register<n> { 15251607Sdim let Namespace = "SystemZ"; 16251607Sdim} 17251607Sdim 18251607Sdimclass SystemZRegWithSubregs<string n, list<Register> subregs> 19251607Sdim : RegisterWithSubRegs<n, subregs> { 20251607Sdim let Namespace = "SystemZ"; 21251607Sdim} 22251607Sdim 23251607Sdimlet Namespace = "SystemZ" in { 24261991Sdimdef subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32. 25261991Sdimdef subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32. 26261991Sdimdef subreg_l64 : SubRegIndex<64, 0>; 27261991Sdimdef subreg_h64 : SubRegIndex<64, 64>; 28288943Sdimdef subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits. 29288943Sdimdef subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits. 30261991Sdimdef subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>; 31261991Sdimdef subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>; 32288943Sdimdef subreg_hr32 : ComposedSubRegIndex<subreg_h64, subreg_r32>; 33251607Sdim} 34251607Sdim 35288943Sdim// Define a register class that contains values of types TYPES and an 36251607Sdim// associated operand called NAME. SIZE is the size and alignment 37251607Sdim// of the registers and REGLIST is the list of individual registers. 38288943Sdimmulticlass SystemZRegClass<string name, list<ValueType> types, int size, 39314564Sdim dag regList, bit allocatable = 1> { 40251607Sdim def AsmOperand : AsmOperandClass { 41251607Sdim let Name = name; 42251607Sdim let ParserMethod = "parse"##name; 43251607Sdim let RenderMethod = "addRegOperands"; 44251607Sdim } 45314564Sdim let isAllocatable = allocatable in 46314564Sdim def Bit : RegisterClass<"SystemZ", types, size, regList> { 47314564Sdim let Size = size; 48314564Sdim } 49251607Sdim def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> { 50251607Sdim let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand"); 51251607Sdim } 52251607Sdim} 53251607Sdim 54251607Sdim//===----------------------------------------------------------------------===// 55251607Sdim// General-purpose registers 56251607Sdim//===----------------------------------------------------------------------===// 57251607Sdim 58251607Sdim// Lower 32 bits of one of the 16 64-bit general-purpose registers 59251607Sdimclass GPR32<bits<16> num, string n> : SystemZReg<n> { 60251607Sdim let HWEncoding = num; 61251607Sdim} 62251607Sdim 63251607Sdim// One of the 16 64-bit general-purpose registers. 64261991Sdimclass GPR64<bits<16> num, string n, GPR32 low, GPR32 high> 65261991Sdim : SystemZRegWithSubregs<n, [low, high]> { 66251607Sdim let HWEncoding = num; 67261991Sdim let SubRegIndices = [subreg_l32, subreg_h32]; 68251607Sdim} 69251607Sdim 70251607Sdim// 8 even-odd pairs of GPR64s. 71261991Sdimclass GPR128<bits<16> num, string n, GPR64 low, GPR64 high> 72261991Sdim : SystemZRegWithSubregs<n, [low, high]> { 73251607Sdim let HWEncoding = num; 74261991Sdim let SubRegIndices = [subreg_l64, subreg_h64]; 75251607Sdim} 76251607Sdim 77251607Sdim// General-purpose registers 78251607Sdimforeach I = 0-15 in { 79261991Sdim def R#I#L : GPR32<I, "r"#I>; 80261991Sdim def R#I#H : GPR32<I, "r"#I>; 81261991Sdim def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>, 82261991Sdim DwarfRegNum<[I]>; 83251607Sdim} 84251607Sdim 85251607Sdimforeach I = [0, 2, 4, 6, 8, 10, 12, 14] in { 86261991Sdim def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"), 87261991Sdim !cast<GPR64>("R"#I#"D")>; 88251607Sdim} 89251607Sdim 90251607Sdim/// Allocate the callee-saved R6-R13 backwards. That way they can be saved 91251607Sdim/// together with R14 and R15 in one prolog instruction. 92288943Sdimdefm GR32 : SystemZRegClass<"GR32", [i32], 32, 93288943Sdim (add (sequence "R%uL", 0, 5), 94288943Sdim (sequence "R%uL", 15, 6))>; 95288943Sdimdefm GRH32 : SystemZRegClass<"GRH32", [i32], 32, 96288943Sdim (add (sequence "R%uH", 0, 5), 97288943Sdim (sequence "R%uH", 15, 6))>; 98288943Sdimdefm GR64 : SystemZRegClass<"GR64", [i64], 64, 99288943Sdim (add (sequence "R%uD", 0, 5), 100288943Sdim (sequence "R%uD", 15, 6))>; 101251607Sdim 102261991Sdim// Combine the low and high GR32s into a single class. This can only be 103261991Sdim// used for virtual registers if the high-word facility is available. 104288943Sdimdefm GRX32 : SystemZRegClass<"GRX32", [i32], 32, 105261991Sdim (add (sequence "R%uL", 0, 5), 106261991Sdim (sequence "R%uH", 0, 5), 107261991Sdim R15L, R15H, R14L, R14H, R13L, R13H, 108261991Sdim R12L, R12H, R11L, R11H, R10L, R10H, 109261991Sdim R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>; 110261991Sdim 111251607Sdim// The architecture doesn't really have any i128 support, so model the 112251607Sdim// register pairs as untyped instead. 113288943Sdimdefm GR128 : SystemZRegClass<"GR128", [untyped], 128, 114288943Sdim (add R0Q, R2Q, R4Q, R12Q, R10Q, R8Q, R6Q, R14Q)>; 115251607Sdim 116251607Sdim// Base and index registers. Everything except R0, which in an address 117251607Sdim// context evaluates as 0. 118288943Sdimdefm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>; 119288943Sdimdefm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>; 120251607Sdim 121251607Sdim// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs 122251607Sdim// of a GR128. 123288943Sdimdefm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>; 124251607Sdim 125314564Sdim// Any type register. Used for .insn directives when we don't know what the 126314564Sdim// register types could be. 127314564Sdimdefm AnyReg : SystemZRegClass<"AnyReg", 128314564Sdim [i64, f64, v8i8, v4i16, v2i32, v2f32], 64, 129314564Sdim (add (sequence "R%uD", 0, 15), 130314564Sdim (sequence "F%uD", 0, 15), 131314564Sdim (sequence "V%u", 0, 15))>; 132314564Sdim 133251607Sdim//===----------------------------------------------------------------------===// 134251607Sdim// Floating-point registers 135251607Sdim//===----------------------------------------------------------------------===// 136251607Sdim 137276479Sdim// Maps FPR register numbers to their DWARF encoding. 138276479Sdimclass DwarfMapping<int id> { int Id = id; } 139276479Sdim 140276479Sdimdef F0Dwarf : DwarfMapping<16>; 141276479Sdimdef F2Dwarf : DwarfMapping<17>; 142276479Sdimdef F4Dwarf : DwarfMapping<18>; 143276479Sdimdef F6Dwarf : DwarfMapping<19>; 144276479Sdim 145276479Sdimdef F1Dwarf : DwarfMapping<20>; 146276479Sdimdef F3Dwarf : DwarfMapping<21>; 147276479Sdimdef F5Dwarf : DwarfMapping<22>; 148276479Sdimdef F7Dwarf : DwarfMapping<23>; 149276479Sdim 150276479Sdimdef F8Dwarf : DwarfMapping<24>; 151276479Sdimdef F10Dwarf : DwarfMapping<25>; 152276479Sdimdef F12Dwarf : DwarfMapping<26>; 153276479Sdimdef F14Dwarf : DwarfMapping<27>; 154276479Sdim 155276479Sdimdef F9Dwarf : DwarfMapping<28>; 156276479Sdimdef F11Dwarf : DwarfMapping<29>; 157276479Sdimdef F13Dwarf : DwarfMapping<30>; 158276479Sdimdef F15Dwarf : DwarfMapping<31>; 159276479Sdim 160288943Sdimdef F16Dwarf : DwarfMapping<68>; 161288943Sdimdef F18Dwarf : DwarfMapping<69>; 162288943Sdimdef F20Dwarf : DwarfMapping<70>; 163288943Sdimdef F22Dwarf : DwarfMapping<71>; 164288943Sdim 165288943Sdimdef F17Dwarf : DwarfMapping<72>; 166288943Sdimdef F19Dwarf : DwarfMapping<73>; 167288943Sdimdef F21Dwarf : DwarfMapping<74>; 168288943Sdimdef F23Dwarf : DwarfMapping<75>; 169288943Sdim 170288943Sdimdef F24Dwarf : DwarfMapping<76>; 171288943Sdimdef F26Dwarf : DwarfMapping<77>; 172288943Sdimdef F28Dwarf : DwarfMapping<78>; 173288943Sdimdef F30Dwarf : DwarfMapping<79>; 174288943Sdim 175288943Sdimdef F25Dwarf : DwarfMapping<80>; 176288943Sdimdef F27Dwarf : DwarfMapping<81>; 177288943Sdimdef F29Dwarf : DwarfMapping<82>; 178288943Sdimdef F31Dwarf : DwarfMapping<83>; 179288943Sdim 180288943Sdim// Upper 32 bits of one of the floating-point registers 181251607Sdimclass FPR32<bits<16> num, string n> : SystemZReg<n> { 182251607Sdim let HWEncoding = num; 183251607Sdim} 184251607Sdim 185288943Sdim// One of the floating-point registers. 186288943Sdimclass FPR64<bits<16> num, string n, FPR32 high> 187288943Sdim : SystemZRegWithSubregs<n, [high]> { 188251607Sdim let HWEncoding = num; 189288943Sdim let SubRegIndices = [subreg_r32]; 190251607Sdim} 191251607Sdim 192251607Sdim// 8 pairs of FPR64s, with a one-register gap inbetween. 193261991Sdimclass FPR128<bits<16> num, string n, FPR64 low, FPR64 high> 194261991Sdim : SystemZRegWithSubregs<n, [low, high]> { 195251607Sdim let HWEncoding = num; 196261991Sdim let SubRegIndices = [subreg_l64, subreg_h64]; 197251607Sdim} 198251607Sdim 199288943Sdim// Floating-point registers. Registers 16-31 require the vector facility. 200251607Sdimforeach I = 0-15 in { 201251607Sdim def F#I#S : FPR32<I, "f"#I>; 202251607Sdim def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>, 203276479Sdim DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; 204251607Sdim} 205288943Sdimforeach I = 16-31 in { 206288943Sdim def F#I#S : FPR32<I, "v"#I>; 207288943Sdim def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>, 208288943Sdim DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; 209288943Sdim} 210251607Sdim 211251607Sdimforeach I = [0, 1, 4, 5, 8, 9, 12, 13] in { 212261991Sdim def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"), 213261991Sdim !cast<FPR64>("F"#I#"D")>; 214251607Sdim} 215251607Sdim 216251607Sdim// There's no store-multiple instruction for FPRs, so we're not fussy 217251607Sdim// about the order in which call-saved registers are allocated. 218288943Sdimdefm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>; 219288943Sdimdefm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>; 220288943Sdimdefm FP128 : SystemZRegClass<"FP128", [f128], 128, 221288943Sdim (add F0Q, F1Q, F4Q, F5Q, F8Q, F9Q, F12Q, F13Q)>; 222251607Sdim 223251607Sdim//===----------------------------------------------------------------------===// 224288943Sdim// Vector registers 225288943Sdim//===----------------------------------------------------------------------===// 226288943Sdim 227288943Sdim// A full 128-bit vector register, with an FPR64 as its high part. 228288943Sdimclass VR128<bits<16> num, string n, FPR64 high> 229288943Sdim : SystemZRegWithSubregs<n, [high]> { 230288943Sdim let HWEncoding = num; 231288943Sdim let SubRegIndices = [subreg_r64]; 232288943Sdim} 233288943Sdim 234288943Sdim// Full vector registers. 235288943Sdimforeach I = 0-31 in { 236288943Sdim def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>, 237288943Sdim DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>; 238288943Sdim} 239288943Sdim 240288943Sdim// Class used to store 32-bit values in the first element of a vector 241288943Sdim// register. f32 scalars are used for the WLEDB and WLDEB instructions. 242288943Sdimdefm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32, 243288943Sdim (add (sequence "F%uS", 0, 7), 244288943Sdim (sequence "F%uS", 16, 31), 245288943Sdim (sequence "F%uS", 8, 15))>; 246288943Sdim 247288943Sdim// Class used to store 64-bit values in the upper half of a vector register. 248288943Sdim// The vector facility also includes scalar f64 instructions that operate 249288943Sdim// on the full vector register set. 250288943Sdimdefm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64, 251288943Sdim (add (sequence "F%uD", 0, 7), 252288943Sdim (sequence "F%uD", 16, 31), 253288943Sdim (sequence "F%uD", 8, 15))>; 254288943Sdim 255288943Sdim// The subset of vector registers that can be used for floating-point 256288943Sdim// operations too. 257288943Sdimdefm VF128 : SystemZRegClass<"VF128", 258288943Sdim [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, 259288943Sdim (sequence "V%u", 0, 15)>; 260288943Sdim 261288943Sdim// All vector registers. 262288943Sdimdefm VR128 : SystemZRegClass<"VR128", 263288943Sdim [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, 264288943Sdim (add (sequence "V%u", 0, 7), 265288943Sdim (sequence "V%u", 16, 31), 266288943Sdim (sequence "V%u", 8, 15))>; 267288943Sdim 268288943Sdim// Attaches a ValueType to a register operand, to make the instruction 269288943Sdim// definitions easier. 270288943Sdimclass TypedReg<ValueType vtin, RegisterOperand opin> { 271288943Sdim ValueType vt = vtin; 272288943Sdim RegisterOperand op = opin; 273288943Sdim} 274288943Sdim 275288943Sdimdef v32eb : TypedReg<f32, VR32>; 276288943Sdimdef v64g : TypedReg<i64, VR64>; 277288943Sdimdef v64db : TypedReg<f64, VR64>; 278288943Sdimdef v128b : TypedReg<v16i8, VR128>; 279288943Sdimdef v128h : TypedReg<v8i16, VR128>; 280288943Sdimdef v128f : TypedReg<v4i32, VR128>; 281288943Sdimdef v128g : TypedReg<v2i64, VR128>; 282288943Sdimdef v128q : TypedReg<v16i8, VR128>; 283288943Sdimdef v128eb : TypedReg<v4f32, VR128>; 284288943Sdimdef v128db : TypedReg<v2f64, VR128>; 285288943Sdimdef v128any : TypedReg<untyped, VR128>; 286288943Sdim 287288943Sdim//===----------------------------------------------------------------------===// 288251607Sdim// Other registers 289251607Sdim//===----------------------------------------------------------------------===// 290251607Sdim 291261991Sdim// The 2-bit condition code field of the PSW. Every register named in an 292261991Sdim// inline asm needs a class associated with it. 293261991Sdimdef CC : SystemZReg<"cc">; 294296417Sdimlet isAllocatable = 0 in 295296417Sdim def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>; 296314564Sdim 297314564Sdim// Access registers. 298314564Sdimclass ACR32<bits<16> num, string n> : SystemZReg<n> { 299314564Sdim let HWEncoding = num; 300314564Sdim} 301314564Sdimforeach I = 0-15 in { 302314564Sdim def A#I : ACR32<I, "a"#I>, DwarfRegNum<[!add(I, 48)]>; 303314564Sdim} 304314564Sdimdefm AR32 : SystemZRegClass<"AR32", [i32], 32, 305314564Sdim (add (sequence "A%u", 0, 15)), 0>; 306314564Sdim 307