SystemZRegisterInfo.td revision 251607
1251607Sdim//==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim 10251607Sdim//===----------------------------------------------------------------------===// 11251607Sdim// Class definitions. 12251607Sdim//===----------------------------------------------------------------------===// 13251607Sdim 14251607Sdimclass SystemZReg<string n> : Register<n> { 15251607Sdim let Namespace = "SystemZ"; 16251607Sdim} 17251607Sdim 18251607Sdimclass SystemZRegWithSubregs<string n, list<Register> subregs> 19251607Sdim : RegisterWithSubRegs<n, subregs> { 20251607Sdim let Namespace = "SystemZ"; 21251607Sdim} 22251607Sdim 23251607Sdimlet Namespace = "SystemZ" in { 24251607Sdimdef subreg_32bit : SubRegIndex; // could also be known as "subreg_high32" 25251607Sdimdef subreg_high : SubRegIndex; 26251607Sdimdef subreg_low : SubRegIndex; 27251607Sdimdef subreg_low32 : SubRegIndex<[subreg_low, subreg_32bit]>; 28251607Sdim} 29251607Sdim 30251607Sdim// Define a register class that contains values of type TYPE and an 31251607Sdim// associated operand called NAME. SIZE is the size and alignment 32251607Sdim// of the registers and REGLIST is the list of individual registers. 33251607Sdimmulticlass SystemZRegClass<string name, ValueType type, int size, dag regList> { 34251607Sdim def AsmOperand : AsmOperandClass { 35251607Sdim let Name = name; 36251607Sdim let ParserMethod = "parse"##name; 37251607Sdim let RenderMethod = "addRegOperands"; 38251607Sdim } 39251607Sdim def Bit : RegisterClass<"SystemZ", [type], size, regList> { 40251607Sdim let Size = size; 41251607Sdim } 42251607Sdim def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> { 43251607Sdim let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand"); 44251607Sdim } 45251607Sdim} 46251607Sdim 47251607Sdim//===----------------------------------------------------------------------===// 48251607Sdim// General-purpose registers 49251607Sdim//===----------------------------------------------------------------------===// 50251607Sdim 51251607Sdim// Lower 32 bits of one of the 16 64-bit general-purpose registers 52251607Sdimclass GPR32<bits<16> num, string n> : SystemZReg<n> { 53251607Sdim let HWEncoding = num; 54251607Sdim} 55251607Sdim 56251607Sdim// One of the 16 64-bit general-purpose registers. 57251607Sdimclass GPR64<bits<16> num, string n, GPR32 low> 58251607Sdim : SystemZRegWithSubregs<n, [low]> { 59251607Sdim let HWEncoding = num; 60251607Sdim let SubRegIndices = [subreg_32bit]; 61251607Sdim} 62251607Sdim 63251607Sdim// 8 even-odd pairs of GPR64s. 64251607Sdimclass GPR128<bits<16> num, string n, GPR64 high, GPR64 low> 65251607Sdim : SystemZRegWithSubregs<n, [high, low]> { 66251607Sdim let HWEncoding = num; 67251607Sdim let SubRegIndices = [subreg_high, subreg_low]; 68251607Sdim} 69251607Sdim 70251607Sdim// General-purpose registers 71251607Sdimforeach I = 0-15 in { 72251607Sdim def R#I#W : GPR32<I, "r"#I>; 73251607Sdim def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"W")>, DwarfRegNum<[I]>; 74251607Sdim} 75251607Sdim 76251607Sdimforeach I = [0, 2, 4, 6, 8, 10, 12, 14] in { 77251607Sdim def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#I#"D"), 78251607Sdim !cast<GPR64>("R"#!add(I, 1)#"D")>; 79251607Sdim} 80251607Sdim 81251607Sdim/// Allocate the callee-saved R6-R13 backwards. That way they can be saved 82251607Sdim/// together with R14 and R15 in one prolog instruction. 83251607Sdimdefm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uW", 0, 5), 84251607Sdim (sequence "R%uW", 15, 6))>; 85251607Sdimdefm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5), 86251607Sdim (sequence "R%uD", 15, 6))>; 87251607Sdim 88251607Sdim// The architecture doesn't really have any i128 support, so model the 89251607Sdim// register pairs as untyped instead. 90251607Sdimdefm GR128 : SystemZRegClass<"GR128", untyped, 128, (add R0Q, R2Q, R4Q, 91251607Sdim R12Q, R10Q, R8Q, R6Q, 92251607Sdim R14Q)>; 93251607Sdim 94251607Sdim// Base and index registers. Everything except R0, which in an address 95251607Sdim// context evaluates as 0. 96251607Sdimdefm ADDR32 : SystemZRegClass<"ADDR32", i32, 32, (sub GR32Bit, R0W)>; 97251607Sdimdefm ADDR64 : SystemZRegClass<"ADDR64", i64, 64, (sub GR64Bit, R0D)>; 98251607Sdim 99251607Sdim// Not used directly, but needs to exist for ADDR32 and ADDR64 subregs 100251607Sdim// of a GR128. 101251607Sdimdefm ADDR128 : SystemZRegClass<"ADDR128", untyped, 128, (sub GR128Bit, R0Q)>; 102251607Sdim 103251607Sdim//===----------------------------------------------------------------------===// 104251607Sdim// Floating-point registers 105251607Sdim//===----------------------------------------------------------------------===// 106251607Sdim 107251607Sdim// Lower 32 bits of one of the 16 64-bit floating-point registers 108251607Sdimclass FPR32<bits<16> num, string n> : SystemZReg<n> { 109251607Sdim let HWEncoding = num; 110251607Sdim} 111251607Sdim 112251607Sdim// One of the 16 64-bit floating-point registers 113251607Sdimclass FPR64<bits<16> num, string n, FPR32 low> 114251607Sdim : SystemZRegWithSubregs<n, [low]> { 115251607Sdim let HWEncoding = num; 116251607Sdim let SubRegIndices = [subreg_32bit]; 117251607Sdim} 118251607Sdim 119251607Sdim// 8 pairs of FPR64s, with a one-register gap inbetween. 120251607Sdimclass FPR128<bits<16> num, string n, FPR64 high, FPR64 low> 121251607Sdim : SystemZRegWithSubregs<n, [high, low]> { 122251607Sdim let HWEncoding = num; 123251607Sdim let SubRegIndices = [subreg_high, subreg_low]; 124251607Sdim} 125251607Sdim 126251607Sdim// Floating-point registers 127251607Sdimforeach I = 0-15 in { 128251607Sdim def F#I#S : FPR32<I, "f"#I>; 129251607Sdim def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>, 130251607Sdim DwarfRegNum<[!add(I, 16)]>; 131251607Sdim} 132251607Sdim 133251607Sdimforeach I = [0, 1, 4, 5, 8, 9, 12, 13] in { 134251607Sdim def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#I#"D"), 135251607Sdim !cast<FPR64>("F"#!add(I, 2)#"D")>; 136251607Sdim} 137251607Sdim 138251607Sdim// There's no store-multiple instruction for FPRs, so we're not fussy 139251607Sdim// about the order in which call-saved registers are allocated. 140251607Sdimdefm FP32 : SystemZRegClass<"FP32", f32, 32, (sequence "F%uS", 0, 15)>; 141251607Sdimdefm FP64 : SystemZRegClass<"FP64", f64, 64, (sequence "F%uD", 0, 15)>; 142251607Sdimdefm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q, 143251607Sdim F8Q, F9Q, F12Q, F13Q)>; 144251607Sdim 145251607Sdim//===----------------------------------------------------------------------===// 146251607Sdim// Other registers 147251607Sdim//===----------------------------------------------------------------------===// 148251607Sdim 149251607Sdim// Status register 150251607Sdimdef PSW : SystemZReg<"psw">; 151