SystemZInstrVector.td revision 360660
1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Move instructions 11//===----------------------------------------------------------------------===// 12 13let Predicates = [FeatureVector] in { 14 // Register move. 15 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 16 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; 17 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 18 19 // Load GR from VR element. 20 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 21 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 22 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 23 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 24 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 25 26 // Load VR element from GR. 27 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 28 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 29 v128b, v128b, GR32, 0>; 30 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 31 v128h, v128h, GR32, 1>; 32 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 33 v128f, v128f, GR32, 2>; 34 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 35 v128g, v128g, GR64, 3>; 36 37 // Load VR from GRs disjoint. 38 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 39 def VLVGP32 : BinaryAliasVRRf<GR32>; 40} 41 42// Extractions always assign to the full GR64, even if the element would 43// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 44// subreg of the result. 45class VectorExtractSubreg<ValueType type, Instruction insn> 46 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 47 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 48 49def : VectorExtractSubreg<v16i8, VLGVB>; 50def : VectorExtractSubreg<v8i16, VLGVH>; 51def : VectorExtractSubreg<v4i32, VLGVF>; 52 53//===----------------------------------------------------------------------===// 54// Immediate instructions 55//===----------------------------------------------------------------------===// 56 57let Predicates = [FeatureVector] in { 58 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 59 60 // Generate byte mask. 61 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 62 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 63 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; 64 65 // Generate mask. 66 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 67 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 68 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 69 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 70 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 71 72 // Replicate immediate. 73 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 74 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; 75 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; 76 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; 77 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; 78 } 79 80 // Load element immediate. 81 // 82 // We want these instructions to be used ahead of VLVG* where possible. 83 // However, VLVG* takes a variable BD-format index whereas VLEI takes 84 // a plain immediate index. This means that VLVG* has an extra "base" 85 // register operand and is 3 units more complex. Bumping the complexity 86 // of the VLEI* instructions by 4 means that they are strictly better 87 // than VLVG* in cases where both forms match. 88 let AddedComplexity = 4 in { 89 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 90 v128b, v128b, imm32sx16trunc, imm32zx4>; 91 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 92 v128h, v128h, imm32sx16trunc, imm32zx3>; 93 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 94 v128f, v128f, imm32sx16, imm32zx2>; 95 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 96 v128g, v128g, imm64sx16, imm32zx1>; 97 } 98} 99 100//===----------------------------------------------------------------------===// 101// Loads 102//===----------------------------------------------------------------------===// 103 104let Predicates = [FeatureVector] in { 105 // Load. 106 defm VL : UnaryVRXAlign<"vl", 0xE706>; 107 108 // Load to block boundary. The number of loaded bytes is only known 109 // at run time. The instruction is really polymorphic, but v128b matches 110 // the return type of the associated intrinsic. 111 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 112 113 // Load count to block boundary. 114 let Defs = [CC] in 115 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 116 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 117 "lcbb\t$R1, $XBD2, $M3", 118 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 119 imm32zx4:$M3))]>; 120 121 // Load with length. The number of loaded bytes is only known at run time. 122 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 123 124 // Load multiple. 125 defm VLM : LoadMultipleVRSaAlign<"vlm", 0xE736>; 126 127 // Load and replicate 128 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 129 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 130 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 131 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 132 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 133 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 134 (VLREPF bdxaddr12only:$addr)>; 135 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 136 (VLREPG bdxaddr12only:$addr)>; 137 138 // Use VLREP to load subvectors. These patterns use "12pair" because 139 // LEY and LDY offer full 20-bit displacement fields. It's often better 140 // to use those instructions rather than force a 20-bit displacement 141 // into a GPR temporary. 142 let mayLoad = 1 in { 143 def VL32 : UnaryAliasVRX<load, v32sb, bdxaddr12pair>; 144 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 145 } 146 147 // Load logical element and zero. 148 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 149 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 150 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 151 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 152 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 153 def : Pat<(z_vllezf32 bdxaddr12only:$addr), 154 (VLLEZF bdxaddr12only:$addr)>; 155 def : Pat<(z_vllezf64 bdxaddr12only:$addr), 156 (VLLEZG bdxaddr12only:$addr)>; 157 let Predicates = [FeatureVectorEnhancements1] in { 158 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; 159 def : Pat<(z_vllezlf32 bdxaddr12only:$addr), 160 (VLLEZLF bdxaddr12only:$addr)>; 161 } 162 163 // Load element. 164 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 165 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 166 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 167 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 169 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 170 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 171 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 172 173 // Gather element. 174 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 175 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 176} 177 178let Predicates = [FeatureVectorPackedDecimal] in { 179 // Load rightmost with length. The number of loaded bytes is only known 180 // at run time. 181 def VLRL : BinaryVSI<"vlrl", 0xE635, int_s390_vlrl, 0>; 182 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; 183} 184 185// Use replicating loads if we're inserting a single element into an 186// undefined vector. This avoids a false dependency on the previous 187// register contents. 188multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 189 SDPatternOperator load, ValueType scalartype> { 190 def : Pat<(vectype (z_vector_insert 191 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 192 (vlrep bdxaddr12only:$addr)>; 193 def : Pat<(vectype (scalar_to_vector 194 (scalartype (load bdxaddr12only:$addr)))), 195 (vlrep bdxaddr12only:$addr)>; 196} 197defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 198defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 199defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 200defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 201defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 202defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 203 204//===----------------------------------------------------------------------===// 205// Stores 206//===----------------------------------------------------------------------===// 207 208let Predicates = [FeatureVector] in { 209 // Store. 210 defm VST : StoreVRXAlign<"vst", 0xE70E>; 211 212 // Store with length. The number of stored bytes is only known at run time. 213 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 214 215 // Store multiple. 216 defm VSTM : StoreMultipleVRSaAlign<"vstm", 0xE73E>; 217 218 // Store element. 219 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 220 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 221 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 222 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 223 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 224 imm32zx2:$index), 225 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 226 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 227 imm32zx1:$index), 228 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 229 230 // Use VSTE to store subvectors. These patterns use "12pair" because 231 // STEY and STDY offer full 20-bit displacement fields. It's often better 232 // to use those instructions rather than force a 20-bit displacement 233 // into a GPR temporary. 234 let mayStore = 1 in { 235 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>; 236 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 237 } 238 239 // Scatter element. 240 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 241 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 242} 243 244let Predicates = [FeatureVectorPackedDecimal] in { 245 // Store rightmost with length. The number of stored bytes is only known 246 // at run time. 247 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, int_s390_vstrl, 0>; 248 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; 249} 250 251//===----------------------------------------------------------------------===// 252// Byte swaps 253//===----------------------------------------------------------------------===// 254 255let Predicates = [FeatureVectorEnhancements2] in { 256 // Load byte-reversed elements. 257 def VLBR : UnaryVRXGeneric<"vlbr", 0xE606>; 258 def VLBRH : UnaryVRX<"vlbrh", 0xE606, z_loadbswap, v128h, 16, 1>; 259 def VLBRF : UnaryVRX<"vlbrf", 0xE606, z_loadbswap, v128f, 16, 2>; 260 def VLBRG : UnaryVRX<"vlbrg", 0xE606, z_loadbswap, v128g, 16, 3>; 261 def VLBRQ : UnaryVRX<"vlbrq", 0xE606, null_frag, v128q, 16, 4>; 262 263 // Load elements reversed. 264 def VLER : UnaryVRXGeneric<"vler", 0xE607>; 265 def VLERH : UnaryVRX<"vlerh", 0xE607, z_loadeswap, v128h, 16, 1>; 266 def VLERF : UnaryVRX<"vlerf", 0xE607, z_loadeswap, v128f, 16, 2>; 267 def VLERG : UnaryVRX<"vlerg", 0xE607, z_loadeswap, v128g, 16, 3>; 268 def : Pat<(v4f32 (z_loadeswap bdxaddr12only:$addr)), 269 (VLERF bdxaddr12only:$addr)>; 270 def : Pat<(v2f64 (z_loadeswap bdxaddr12only:$addr)), 271 (VLERG bdxaddr12only:$addr)>; 272 def : Pat<(v16i8 (z_loadeswap bdxaddr12only:$addr)), 273 (VLBRQ bdxaddr12only:$addr)>; 274 275 // Load byte-reversed element. 276 def VLEBRH : TernaryVRX<"vlebrh", 0xE601, z_vlebri16, v128h, v128h, 2, imm32zx3>; 277 def VLEBRF : TernaryVRX<"vlebrf", 0xE603, z_vlebri32, v128f, v128f, 4, imm32zx2>; 278 def VLEBRG : TernaryVRX<"vlebrg", 0xE602, z_vlebri64, v128g, v128g, 8, imm32zx1>; 279 280 // Load byte-reversed element and zero. 281 def VLLEBRZ : UnaryVRXGeneric<"vllebrz", 0xE604>; 282 def VLLEBRZH : UnaryVRX<"vllebrzh", 0xE604, z_vllebrzi16, v128h, 2, 1>; 283 def VLLEBRZF : UnaryVRX<"vllebrzf", 0xE604, z_vllebrzi32, v128f, 4, 2>; 284 def VLLEBRZG : UnaryVRX<"vllebrzg", 0xE604, z_vllebrzi64, v128g, 8, 3>; 285 def VLLEBRZE : UnaryVRX<"vllebrze", 0xE604, z_vllebrzli32, v128f, 4, 6>; 286 def : InstAlias<"lerv\t$V1, $XBD2", 287 (VLLEBRZE VR128:$V1, bdxaddr12only:$XBD2), 0>; 288 def : InstAlias<"ldrv\t$V1, $XBD2", 289 (VLLEBRZG VR128:$V1, bdxaddr12only:$XBD2), 0>; 290 291 // Load byte-reversed element and replicate. 292 def VLBRREP : UnaryVRXGeneric<"vlbrrep", 0xE605>; 293 def VLBRREPH : UnaryVRX<"vlbrreph", 0xE605, z_replicate_loadbswapi16, v128h, 2, 1>; 294 def VLBRREPF : UnaryVRX<"vlbrrepf", 0xE605, z_replicate_loadbswapi32, v128f, 4, 2>; 295 def VLBRREPG : UnaryVRX<"vlbrrepg", 0xE605, z_replicate_loadbswapi64, v128g, 8, 3>; 296 297 // Store byte-reversed elements. 298 def VSTBR : StoreVRXGeneric<"vstbr", 0xE60E>; 299 def VSTBRH : StoreVRX<"vstbrh", 0xE60E, z_storebswap, v128h, 16, 1>; 300 def VSTBRF : StoreVRX<"vstbrf", 0xE60E, z_storebswap, v128f, 16, 2>; 301 def VSTBRG : StoreVRX<"vstbrg", 0xE60E, z_storebswap, v128g, 16, 3>; 302 def VSTBRQ : StoreVRX<"vstbrq", 0xE60E, null_frag, v128q, 16, 4>; 303 304 // Store elements reversed. 305 def VSTER : StoreVRXGeneric<"vster", 0xE60F>; 306 def VSTERH : StoreVRX<"vsterh", 0xE60F, z_storeeswap, v128h, 16, 1>; 307 def VSTERF : StoreVRX<"vsterf", 0xE60F, z_storeeswap, v128f, 16, 2>; 308 def VSTERG : StoreVRX<"vsterg", 0xE60F, z_storeeswap, v128g, 16, 3>; 309 def : Pat<(z_storeeswap (v4f32 VR128:$val), bdxaddr12only:$addr), 310 (VSTERF VR128:$val, bdxaddr12only:$addr)>; 311 def : Pat<(z_storeeswap (v2f64 VR128:$val), bdxaddr12only:$addr), 312 (VSTERG VR128:$val, bdxaddr12only:$addr)>; 313 def : Pat<(z_storeeswap (v16i8 VR128:$val), bdxaddr12only:$addr), 314 (VSTBRQ VR128:$val, bdxaddr12only:$addr)>; 315 316 // Store byte-reversed element. 317 def VSTEBRH : StoreBinaryVRX<"vstebrh", 0xE609, z_vstebri16, v128h, 2, imm32zx3>; 318 def VSTEBRF : StoreBinaryVRX<"vstebrf", 0xE60B, z_vstebri32, v128f, 4, imm32zx2>; 319 def VSTEBRG : StoreBinaryVRX<"vstebrg", 0xE60A, z_vstebri64, v128g, 8, imm32zx1>; 320 def : InstAlias<"sterv\t$V1, $XBD2", 321 (VSTEBRF VR128:$V1, bdxaddr12only:$XBD2, 0), 0>; 322 def : InstAlias<"stdrv\t$V1, $XBD2", 323 (VSTEBRG VR128:$V1, bdxaddr12only:$XBD2, 0), 0>; 324} 325 326//===----------------------------------------------------------------------===// 327// Selects and permutes 328//===----------------------------------------------------------------------===// 329 330let Predicates = [FeatureVector] in { 331 // Merge high. 332 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 333 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 334 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 335 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 336 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 337 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 338 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 339 340 // Merge low. 341 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 342 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 343 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 344 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 345 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 346 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 347 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 348 349 // Permute. 350 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 351 352 // Permute doubleword immediate. 353 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 354 355 // Bit Permute. 356 let Predicates = [FeatureVectorEnhancements1] in 357 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; 358 359 // Replicate. 360 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 361 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 362 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 363 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 364 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 365 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)), 366 (VREPF VR128:$vec, imm32zx16:$index)>; 367 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 368 (VREPG VR128:$vec, imm32zx16:$index)>; 369 370 // Select. 371 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 372} 373 374//===----------------------------------------------------------------------===// 375// Widening and narrowing 376//===----------------------------------------------------------------------===// 377 378let Predicates = [FeatureVector] in { 379 // Pack 380 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 381 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 382 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 383 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 384 385 // Pack saturate. 386 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 387 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 388 v128b, v128h, 1>; 389 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 390 v128h, v128f, 2>; 391 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 392 v128f, v128g, 3>; 393 394 // Pack saturate logical. 395 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 396 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 397 v128b, v128h, 1>; 398 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 399 v128h, v128f, 2>; 400 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 401 v128f, v128g, 3>; 402 403 // Sign-extend to doubleword. 404 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 405 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 406 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 407 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 408 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 409 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 410 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 411 412 // Unpack high. 413 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 414 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 415 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 416 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 417 418 // Unpack logical high. 419 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 420 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 421 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 422 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 423 424 // Unpack low. 425 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 426 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 427 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 428 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 429 430 // Unpack logical low. 431 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 432 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 433 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 434 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 435} 436 437//===----------------------------------------------------------------------===// 438// Instantiating generic operations for specific types. 439//===----------------------------------------------------------------------===// 440 441multiclass GenericVectorOps<ValueType type, ValueType inttype> { 442 let Predicates = [FeatureVector] in { 443 def : Pat<(type (load bdxaddr12only:$addr)), 444 (VL bdxaddr12only:$addr)>; 445 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 446 (VST VR128:$src, bdxaddr12only:$addr)>; 447 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 448 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 449 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 450 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 451 } 452} 453 454defm : GenericVectorOps<v16i8, v16i8>; 455defm : GenericVectorOps<v8i16, v8i16>; 456defm : GenericVectorOps<v4i32, v4i32>; 457defm : GenericVectorOps<v2i64, v2i64>; 458defm : GenericVectorOps<v4f32, v4i32>; 459defm : GenericVectorOps<v2f64, v2i64>; 460 461//===----------------------------------------------------------------------===// 462// Integer arithmetic 463//===----------------------------------------------------------------------===// 464 465let Predicates = [FeatureVector] in { 466 // Add. 467 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 468 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 469 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 470 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 471 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 472 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 473 474 // Add compute carry. 475 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 476 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 477 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 478 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 479 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 480 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 481 482 // Add with carry. 483 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 484 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 485 486 // Add with carry compute carry. 487 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 488 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 489 490 // And. 491 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 492 493 // And with complement. 494 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 495 496 // Average. 497 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 498 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 499 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 500 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 501 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 502 503 // Average logical. 504 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 505 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 506 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 507 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 508 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 509 510 // Checksum. 511 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 512 513 // Count leading zeros. 514 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 515 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 516 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 517 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 518 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 519 520 // Count trailing zeros. 521 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 522 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 523 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 524 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 525 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 526 527 // Not exclusive or. 528 let Predicates = [FeatureVectorEnhancements1] in 529 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; 530 531 // Exclusive or. 532 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 533 534 // Galois field multiply sum. 535 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 536 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 537 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 538 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 539 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 540 541 // Galois field multiply sum and accumulate. 542 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 543 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 544 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 545 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 546 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 547 548 // Load complement. 549 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 550 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 551 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 552 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 553 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 554 555 // Load positive. 556 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 557 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 558 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 559 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 560 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 561 562 // Maximum. 563 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 564 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 565 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 566 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 567 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 568 569 // Maximum logical. 570 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 571 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 572 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 573 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 574 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 575 576 // Minimum. 577 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 578 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 579 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 580 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 581 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 582 583 // Minimum logical. 584 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 585 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 586 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 587 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 588 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 589 590 // Multiply and add low. 591 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 592 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 593 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 594 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 595 596 // Multiply and add high. 597 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 598 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 599 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 600 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 601 602 // Multiply and add logical high. 603 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 604 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 605 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 606 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 607 608 // Multiply and add even. 609 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 610 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 611 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 612 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 613 614 // Multiply and add logical even. 615 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 616 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 617 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 618 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 619 620 // Multiply and add odd. 621 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 622 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 623 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 624 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 625 626 // Multiply and add logical odd. 627 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 628 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 629 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 630 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 631 632 // Multiply high. 633 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 634 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 635 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 636 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 637 638 // Multiply logical high. 639 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 640 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 641 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 642 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 643 644 // Multiply low. 645 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 646 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 647 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 648 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 649 650 // Multiply even. 651 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 652 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 653 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 654 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 655 656 // Multiply logical even. 657 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 658 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 659 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 660 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 661 662 // Multiply odd. 663 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 664 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 665 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 666 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 667 668 // Multiply logical odd. 669 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 670 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 671 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 672 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 673 674 // Multiply sum logical. 675 let Predicates = [FeatureVectorEnhancements1] in { 676 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; 677 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, 678 v128q, v128g, v128g, v128q, 3>; 679 } 680 681 // Nand. 682 let Predicates = [FeatureVectorEnhancements1] in 683 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; 684 685 // Nor. 686 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 687 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 688 689 // Or. 690 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 691 692 // Or with complement. 693 let Predicates = [FeatureVectorEnhancements1] in 694 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; 695 696 // Population count. 697 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 698 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 699 let Predicates = [FeatureVectorEnhancements1] in { 700 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; 701 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; 702 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; 703 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; 704 } 705 706 // Element rotate left logical (with vector shift amount). 707 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 708 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 709 v128b, v128b, 0>; 710 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 711 v128h, v128h, 1>; 712 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 713 v128f, v128f, 2>; 714 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 715 v128g, v128g, 3>; 716 717 // Element rotate left logical (with scalar shift amount). 718 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 719 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 720 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 721 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 722 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 723 724 // Element rotate and insert under mask. 725 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 726 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 727 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 728 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 729 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 730 731 // Element shift left (with vector shift amount). 732 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 733 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 734 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 735 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 736 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 737 738 // Element shift left (with scalar shift amount). 739 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 740 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 741 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 742 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 743 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 744 745 // Element shift right arithmetic (with vector shift amount). 746 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 747 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 748 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 749 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 750 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 751 752 // Element shift right arithmetic (with scalar shift amount). 753 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 754 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 755 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 756 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 757 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 758 759 // Element shift right logical (with vector shift amount). 760 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 761 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 762 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 763 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 764 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 765 766 // Element shift right logical (with scalar shift amount). 767 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 768 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 769 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 770 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 771 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 772 773 // Shift left. 774 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 775 776 // Shift left by byte. 777 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 778 779 // Shift left double by byte. 780 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 781 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z), 782 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 783 784 // Shift left double by bit. 785 let Predicates = [FeatureVectorEnhancements2] in 786 def VSLD : TernaryVRId<"vsld", 0xE786, int_s390_vsld, v128b, v128b, 0>; 787 788 // Shift right arithmetic. 789 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 790 791 // Shift right arithmetic by byte. 792 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 793 794 // Shift right logical. 795 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 796 797 // Shift right logical by byte. 798 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 799 800 // Shift right double by bit. 801 let Predicates = [FeatureVectorEnhancements2] in 802 def VSRD : TernaryVRId<"vsrd", 0xE787, int_s390_vsrd, v128b, v128b, 0>; 803 804 // Subtract. 805 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 806 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 807 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 808 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 809 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 810 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 811 812 // Subtract compute borrow indication. 813 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 814 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 815 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 816 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 817 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 818 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 819 820 // Subtract with borrow indication. 821 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 822 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 823 824 // Subtract with borrow compute borrow indication. 825 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 826 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 827 v128q, v128q, 4>; 828 829 // Sum across doubleword. 830 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 831 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 832 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 833 834 // Sum across quadword. 835 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 836 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 837 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 838 839 // Sum across word. 840 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 841 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 842 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 843} 844 845// Instantiate the bitwise ops for type TYPE. 846multiclass BitwiseVectorOps<ValueType type> { 847 let Predicates = [FeatureVector] in { 848 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 849 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 850 (VNC VR128:$x, VR128:$y)>; 851 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 852 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 853 def : Pat<(type (or (and VR128:$x, VR128:$z), 854 (and VR128:$y, (z_vnot VR128:$z)))), 855 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 856 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 857 (VNO VR128:$x, VR128:$y)>; 858 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 859 } 860 let Predicates = [FeatureVectorEnhancements1] in { 861 def : Pat<(type (z_vnot (xor VR128:$x, VR128:$y))), 862 (VNX VR128:$x, VR128:$y)>; 863 def : Pat<(type (z_vnot (and VR128:$x, VR128:$y))), 864 (VNN VR128:$x, VR128:$y)>; 865 def : Pat<(type (or VR128:$x, (z_vnot VR128:$y))), 866 (VOC VR128:$x, VR128:$y)>; 867 } 868} 869 870defm : BitwiseVectorOps<v16i8>; 871defm : BitwiseVectorOps<v8i16>; 872defm : BitwiseVectorOps<v4i32>; 873defm : BitwiseVectorOps<v2i64>; 874 875// Instantiate additional patterns for absolute-related expressions on 876// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 877// instruction. 878multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 879 Instruction lp, int shift> { 880 let Predicates = [FeatureVector] in { 881 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 882 (z_vneg VR128:$x), VR128:$x)), 883 (lc (lp VR128:$x))>; 884 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 885 VR128:$x, (z_vneg VR128:$x))), 886 (lc (lp VR128:$x))>; 887 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 888 VR128:$x, (z_vneg VR128:$x))), 889 (lc (lp VR128:$x))>; 890 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 891 (z_vneg VR128:$x), VR128:$x)), 892 (lc (lp VR128:$x))>; 893 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 894 (z_vneg VR128:$x)), 895 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 896 VR128:$x))), 897 (lp VR128:$x)>; 898 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 899 VR128:$x), 900 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 901 (z_vneg VR128:$x)))), 902 (lc (lp VR128:$x))>; 903 } 904} 905 906defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 907defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 908defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 909defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 910 911// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 912// signed or unsigned "set if greater than" comparison instruction and 913// MIN and MAX are the associated minimum and maximum instructions. 914multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 915 Instruction min, Instruction max> { 916 let Predicates = [FeatureVector] in { 917 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 918 (max VR128:$x, VR128:$y)>; 919 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 920 (min VR128:$x, VR128:$y)>; 921 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 922 VR128:$x, VR128:$y)), 923 (min VR128:$x, VR128:$y)>; 924 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 925 VR128:$y, VR128:$x)), 926 (max VR128:$x, VR128:$y)>; 927 } 928} 929 930// Signed min/max. 931defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 932defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 933defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 934defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 935 936// Unsigned min/max. 937defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 938defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 939defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 940defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 941 942//===----------------------------------------------------------------------===// 943// Integer comparison 944//===----------------------------------------------------------------------===// 945 946let Predicates = [FeatureVector] in { 947 // Element compare. 948 let Defs = [CC] in { 949 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 950 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 951 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 952 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 953 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 954 } 955 956 // Element compare logical. 957 let Defs = [CC] in { 958 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 959 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 960 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 961 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 962 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 963 } 964 965 // Compare equal. 966 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 967 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 968 v128b, v128b, 0>; 969 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 970 v128h, v128h, 1>; 971 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 972 v128f, v128f, 2>; 973 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 974 v128g, v128g, 3>; 975 976 // Compare high. 977 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 978 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 979 v128b, v128b, 0>; 980 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 981 v128h, v128h, 1>; 982 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 983 v128f, v128f, 2>; 984 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 985 v128g, v128g, 3>; 986 987 // Compare high logical. 988 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 989 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 990 v128b, v128b, 0>; 991 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 992 v128h, v128h, 1>; 993 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 994 v128f, v128f, 2>; 995 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 996 v128g, v128g, 3>; 997 998 // Test under mask. 999 let Defs = [CC] in 1000 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 1001} 1002 1003//===----------------------------------------------------------------------===// 1004// Floating-point arithmetic 1005//===----------------------------------------------------------------------===// 1006 1007// See comments in SystemZInstrFP.td for the suppression flags and 1008// rounding modes. 1009multiclass VectorRounding<Instruction insn, TypedReg tr> { 1010 def : FPConversion<insn, any_frint, tr, tr, 0, 0>; 1011 def : FPConversion<insn, any_fnearbyint, tr, tr, 4, 0>; 1012 def : FPConversion<insn, any_ffloor, tr, tr, 4, 7>; 1013 def : FPConversion<insn, any_fceil, tr, tr, 4, 6>; 1014 def : FPConversion<insn, any_ftrunc, tr, tr, 4, 5>; 1015 def : FPConversion<insn, any_fround, tr, tr, 4, 1>; 1016} 1017 1018let Predicates = [FeatureVector] in { 1019 // Add. 1020 let Uses = [FPC], mayRaiseFPException = 1 in { 1021 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 1022 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, any_fadd, v128db, v128db, 3, 0>; 1023 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, any_fadd, v64db, v64db, 3, 8>; 1024 let Predicates = [FeatureVectorEnhancements1] in { 1025 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, any_fadd, v128sb, v128sb, 2, 0>; 1026 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, any_fadd, v32sb, v32sb, 2, 8>; 1027 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, any_fadd, v128xb, v128xb, 4, 8>; 1028 } 1029 } 1030 1031 // Convert from fixed. 1032 let Uses = [FPC], mayRaiseFPException = 1 in { 1033 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 1034 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 1035 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 1036 } 1037 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>; 1038 let Predicates = [FeatureVectorEnhancements2] in { 1039 let Uses = [FPC], mayRaiseFPException = 1 in { 1040 let isAsmParserOnly = 1 in 1041 def VCFPS : TernaryVRRaFloatGeneric<"vcfps", 0xE7C3>; 1042 def VCEFB : TernaryVRRa<"vcefb", 0xE7C3, null_frag, v128sb, v128g, 2, 0>; 1043 def WCEFB : TernaryVRRa<"wcefb", 0xE7C3, null_frag, v32sb, v32f, 2, 8>; 1044 } 1045 def : FPConversion<VCEFB, sint_to_fp, v128sb, v128f, 0, 0>; 1046 } 1047 1048 // Convert from logical. 1049 let Uses = [FPC], mayRaiseFPException = 1 in { 1050 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 1051 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 1052 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 1053 } 1054 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>; 1055 let Predicates = [FeatureVectorEnhancements2] in { 1056 let Uses = [FPC], mayRaiseFPException = 1 in { 1057 let isAsmParserOnly = 1 in 1058 def VCFPL : TernaryVRRaFloatGeneric<"vcfpl", 0xE7C1>; 1059 def VCELFB : TernaryVRRa<"vcelfb", 0xE7C1, null_frag, v128sb, v128g, 2, 0>; 1060 def WCELFB : TernaryVRRa<"wcelfb", 0xE7C1, null_frag, v32sb, v32f, 2, 8>; 1061 } 1062 def : FPConversion<VCELFB, uint_to_fp, v128sb, v128f, 0, 0>; 1063 } 1064 1065 // Convert to fixed. 1066 let Uses = [FPC], mayRaiseFPException = 1 in { 1067 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 1068 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 1069 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 1070 } 1071 // Rounding mode should agree with SystemZInstrFP.td. 1072 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>; 1073 let Predicates = [FeatureVectorEnhancements2] in { 1074 let Uses = [FPC], mayRaiseFPException = 1 in { 1075 let isAsmParserOnly = 1 in 1076 def VCSFP : TernaryVRRaFloatGeneric<"vcsfp", 0xE7C2>; 1077 def VCFEB : TernaryVRRa<"vcfeb", 0xE7C2, null_frag, v128sb, v128g, 2, 0>; 1078 def WCFEB : TernaryVRRa<"wcfeb", 0xE7C2, null_frag, v32sb, v32f, 2, 8>; 1079 } 1080 // Rounding mode should agree with SystemZInstrFP.td. 1081 def : FPConversion<VCFEB, fp_to_sint, v128f, v128sb, 0, 5>; 1082 } 1083 1084 // Convert to logical. 1085 let Uses = [FPC], mayRaiseFPException = 1 in { 1086 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 1087 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 1088 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 1089 } 1090 // Rounding mode should agree with SystemZInstrFP.td. 1091 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>; 1092 let Predicates = [FeatureVectorEnhancements2] in { 1093 let Uses = [FPC], mayRaiseFPException = 1 in { 1094 let isAsmParserOnly = 1 in 1095 def VCLFP : TernaryVRRaFloatGeneric<"vclfp", 0xE7C0>; 1096 def VCLFEB : TernaryVRRa<"vclfeb", 0xE7C0, null_frag, v128sb, v128g, 2, 0>; 1097 def WCLFEB : TernaryVRRa<"wclfeb", 0xE7C0, null_frag, v32sb, v32f, 2, 8>; 1098 } 1099 // Rounding mode should agree with SystemZInstrFP.td. 1100 def : FPConversion<VCLFEB, fp_to_uint, v128f, v128sb, 0, 5>; 1101 } 1102 1103 // Divide. 1104 let Uses = [FPC], mayRaiseFPException = 1 in { 1105 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 1106 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, any_fdiv, v128db, v128db, 3, 0>; 1107 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, any_fdiv, v64db, v64db, 3, 8>; 1108 let Predicates = [FeatureVectorEnhancements1] in { 1109 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, any_fdiv, v128sb, v128sb, 2, 0>; 1110 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, any_fdiv, v32sb, v32sb, 2, 8>; 1111 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, any_fdiv, v128xb, v128xb, 4, 8>; 1112 } 1113 } 1114 1115 // Load FP integer. 1116 let Uses = [FPC], mayRaiseFPException = 1 in { 1117 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 1118 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 1119 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 1120 } 1121 defm : VectorRounding<VFIDB, v128db>; 1122 defm : VectorRounding<WFIDB, v64db>; 1123 let Predicates = [FeatureVectorEnhancements1] in { 1124 let Uses = [FPC], mayRaiseFPException = 1 in { 1125 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>; 1126 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>; 1127 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>; 1128 } 1129 defm : VectorRounding<VFISB, v128sb>; 1130 defm : VectorRounding<WFISB, v32sb>; 1131 defm : VectorRounding<WFIXB, v128xb>; 1132 } 1133 1134 // Load lengthened. 1135 let Uses = [FPC], mayRaiseFPException = 1 in { 1136 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 1137 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128sb, 2, 0>; 1138 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, any_fpextend, v64db, v32sb, 2, 8>; 1139 } 1140 let Predicates = [FeatureVectorEnhancements1] in { 1141 let Uses = [FPC], mayRaiseFPException = 1 in { 1142 let isAsmParserOnly = 1 in { 1143 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>; 1144 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>; 1145 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>; 1146 } 1147 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, any_fpextend, v128xb, v64db, 3, 8>; 1148 } 1149 def : Pat<(f128 (any_fpextend (f32 VR32:$src))), 1150 (WFLLD (WLDEB VR32:$src))>; 1151 } 1152 1153 // Load rounded. 1154 let Uses = [FPC], mayRaiseFPException = 1 in { 1155 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 1156 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1157 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1158 } 1159 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 1160 def : FPConversion<WLEDB, any_fpround, v32sb, v64db, 0, 0>; 1161 let Predicates = [FeatureVectorEnhancements1] in { 1162 let Uses = [FPC], mayRaiseFPException = 1 in { 1163 let isAsmParserOnly = 1 in { 1164 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>; 1165 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1166 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1167 } 1168 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>; 1169 } 1170 def : FPConversion<WFLRX, any_fpround, v64db, v128xb, 0, 0>; 1171 def : Pat<(f32 (any_fpround (f128 VR128:$src))), 1172 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>; 1173 } 1174 1175 // Maximum. 1176 multiclass VectorMax<Instruction insn, TypedReg tr> { 1177 def : FPMinMax<insn, any_fmaxnum, tr, 4>; 1178 def : FPMinMax<insn, fmaximum, tr, 1>; 1179 } 1180 let Predicates = [FeatureVectorEnhancements1] in { 1181 let Uses = [FPC], mayRaiseFPException = 1 in { 1182 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; 1183 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, 1184 v128db, v128db, 3, 0>; 1185 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, 1186 v64db, v64db, 3, 8>; 1187 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb, 1188 v128sb, v128sb, 2, 0>; 1189 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag, 1190 v32sb, v32sb, 2, 8>; 1191 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag, 1192 v128xb, v128xb, 4, 8>; 1193 } 1194 defm : VectorMax<VFMAXDB, v128db>; 1195 defm : VectorMax<WFMAXDB, v64db>; 1196 defm : VectorMax<VFMAXSB, v128sb>; 1197 defm : VectorMax<WFMAXSB, v32sb>; 1198 defm : VectorMax<WFMAXXB, v128xb>; 1199 } 1200 1201 // Minimum. 1202 multiclass VectorMin<Instruction insn, TypedReg tr> { 1203 def : FPMinMax<insn, any_fminnum, tr, 4>; 1204 def : FPMinMax<insn, fminimum, tr, 1>; 1205 } 1206 let Predicates = [FeatureVectorEnhancements1] in { 1207 let Uses = [FPC], mayRaiseFPException = 1 in { 1208 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; 1209 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, 1210 v128db, v128db, 3, 0>; 1211 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, 1212 v64db, v64db, 3, 8>; 1213 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb, 1214 v128sb, v128sb, 2, 0>; 1215 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag, 1216 v32sb, v32sb, 2, 8>; 1217 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag, 1218 v128xb, v128xb, 4, 8>; 1219 } 1220 defm : VectorMin<VFMINDB, v128db>; 1221 defm : VectorMin<WFMINDB, v64db>; 1222 defm : VectorMin<VFMINSB, v128sb>; 1223 defm : VectorMin<WFMINSB, v32sb>; 1224 defm : VectorMin<WFMINXB, v128xb>; 1225 } 1226 1227 // Multiply. 1228 let Uses = [FPC], mayRaiseFPException = 1 in { 1229 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 1230 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, any_fmul, v128db, v128db, 3, 0>; 1231 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, any_fmul, v64db, v64db, 3, 8>; 1232 let Predicates = [FeatureVectorEnhancements1] in { 1233 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, any_fmul, v128sb, v128sb, 2, 0>; 1234 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, any_fmul, v32sb, v32sb, 2, 8>; 1235 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, any_fmul, v128xb, v128xb, 4, 8>; 1236 } 1237 } 1238 1239 // Multiply and add. 1240 let Uses = [FPC], mayRaiseFPException = 1 in { 1241 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 1242 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, any_fma, v128db, v128db, 0, 3>; 1243 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, any_fma, v64db, v64db, 8, 3>; 1244 let Predicates = [FeatureVectorEnhancements1] in { 1245 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, any_fma, v128sb, v128sb, 0, 2>; 1246 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, any_fma, v32sb, v32sb, 8, 2>; 1247 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, any_fma, v128xb, v128xb, 8, 4>; 1248 } 1249 } 1250 1251 // Multiply and subtract. 1252 let Uses = [FPC], mayRaiseFPException = 1 in { 1253 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 1254 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, any_fms, v128db, v128db, 0, 3>; 1255 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, any_fms, v64db, v64db, 8, 3>; 1256 let Predicates = [FeatureVectorEnhancements1] in { 1257 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, any_fms, v128sb, v128sb, 0, 2>; 1258 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, any_fms, v32sb, v32sb, 8, 2>; 1259 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, any_fms, v128xb, v128xb, 8, 4>; 1260 } 1261 } 1262 1263 // Negative multiply and add. 1264 let Uses = [FPC], mayRaiseFPException = 1, 1265 Predicates = [FeatureVectorEnhancements1] in { 1266 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; 1267 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, any_fnma, v128db, v128db, 0, 3>; 1268 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, any_fnma, v64db, v64db, 8, 3>; 1269 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, any_fnma, v128sb, v128sb, 0, 2>; 1270 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, any_fnma, v32sb, v32sb, 8, 2>; 1271 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, any_fnma, v128xb, v128xb, 8, 4>; 1272 } 1273 1274 // Negative multiply and subtract. 1275 let Uses = [FPC], mayRaiseFPException = 1, 1276 Predicates = [FeatureVectorEnhancements1] in { 1277 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; 1278 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, any_fnms, v128db, v128db, 0, 3>; 1279 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, any_fnms, v64db, v64db, 8, 3>; 1280 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, any_fnms, v128sb, v128sb, 0, 2>; 1281 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, any_fnms, v32sb, v32sb, 8, 2>; 1282 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, any_fnms, v128xb, v128xb, 8, 4>; 1283 } 1284 1285 // Perform sign operation. 1286 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 1287 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 1288 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 1289 let Predicates = [FeatureVectorEnhancements1] in { 1290 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>; 1291 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>; 1292 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>; 1293 } 1294 1295 // Load complement. 1296 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 1297 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 1298 let Predicates = [FeatureVectorEnhancements1] in { 1299 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>; 1300 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>; 1301 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>; 1302 } 1303 1304 // Load negative. 1305 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 1306 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 1307 let Predicates = [FeatureVectorEnhancements1] in { 1308 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>; 1309 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>; 1310 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>; 1311 } 1312 1313 // Load positive. 1314 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 1315 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 1316 let Predicates = [FeatureVectorEnhancements1] in { 1317 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>; 1318 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>; 1319 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>; 1320 } 1321 1322 // Square root. 1323 let Uses = [FPC], mayRaiseFPException = 1 in { 1324 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 1325 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, any_fsqrt, v128db, v128db, 3, 0>; 1326 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, any_fsqrt, v64db, v64db, 3, 8>; 1327 let Predicates = [FeatureVectorEnhancements1] in { 1328 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, any_fsqrt, v128sb, v128sb, 2, 0>; 1329 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, any_fsqrt, v32sb, v32sb, 2, 8>; 1330 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, any_fsqrt, v128xb, v128xb, 4, 8>; 1331 } 1332 } 1333 1334 // Subtract. 1335 let Uses = [FPC], mayRaiseFPException = 1 in { 1336 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 1337 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, any_fsub, v128db, v128db, 3, 0>; 1338 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, any_fsub, v64db, v64db, 3, 8>; 1339 let Predicates = [FeatureVectorEnhancements1] in { 1340 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, any_fsub, v128sb, v128sb, 2, 0>; 1341 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, any_fsub, v32sb, v32sb, 2, 8>; 1342 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, any_fsub, v128xb, v128xb, 4, 8>; 1343 } 1344 } 1345 1346 // Test data class immediate. 1347 let Defs = [CC] in { 1348 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 1349 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 1350 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 1351 let Predicates = [FeatureVectorEnhancements1] in { 1352 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>; 1353 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>; 1354 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>; 1355 } 1356 } 1357} 1358 1359//===----------------------------------------------------------------------===// 1360// Floating-point comparison 1361//===----------------------------------------------------------------------===// 1362 1363let Predicates = [FeatureVector] in { 1364 // Compare scalar. 1365 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 1366 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 1367 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>; 1368 let Predicates = [FeatureVectorEnhancements1] in { 1369 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_fcmp, v32sb, 2>; 1370 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_fcmp, v128xb, 4>; 1371 } 1372 } 1373 1374 // Compare and signal scalar. 1375 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 1376 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 1377 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; 1378 let Predicates = [FeatureVectorEnhancements1] in { 1379 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, null_frag, v32sb, 2>; 1380 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, null_frag, v128xb, 4>; 1381 } 1382 } 1383 1384 // Compare equal. 1385 let Uses = [FPC], mayRaiseFPException = 1 in { 1386 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1387 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1388 v128g, v128db, 3, 0>; 1389 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1390 v64g, v64db, 3, 8>; 1391 let Predicates = [FeatureVectorEnhancements1] in { 1392 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1393 v128f, v128sb, 2, 0>; 1394 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag, 1395 v32f, v32sb, 2, 8>; 1396 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag, 1397 v128q, v128xb, 4, 8>; 1398 } 1399 } 1400 1401 // Compare and signal equal. 1402 let Uses = [FPC], mayRaiseFPException = 1, 1403 Predicates = [FeatureVectorEnhancements1] in { 1404 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, null_frag, null_frag, 1405 v128g, v128db, 3, 4>; 1406 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, 1407 v64g, v64db, 3, 12>; 1408 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, null_frag, null_frag, 1409 v128f, v128sb, 2, 4>; 1410 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag, 1411 v32f, v32sb, 2, 12>; 1412 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag, 1413 v128q, v128xb, 4, 12>; 1414 } 1415 1416 // Compare high. 1417 let Uses = [FPC], mayRaiseFPException = 1 in { 1418 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1419 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, 1420 v128g, v128db, 3, 0>; 1421 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1422 v64g, v64db, 3, 8>; 1423 let Predicates = [FeatureVectorEnhancements1] in { 1424 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_vfcmph, z_vfcmphs, 1425 v128f, v128sb, 2, 0>; 1426 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag, 1427 v32f, v32sb, 2, 8>; 1428 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag, 1429 v128q, v128xb, 4, 8>; 1430 } 1431 } 1432 1433 // Compare and signal high. 1434 let Uses = [FPC], mayRaiseFPException = 1, 1435 Predicates = [FeatureVectorEnhancements1] in { 1436 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, null_frag, null_frag, 1437 v128g, v128db, 3, 4>; 1438 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, 1439 v64g, v64db, 3, 12>; 1440 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, null_frag, null_frag, 1441 v128f, v128sb, 2, 4>; 1442 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag, 1443 v32f, v32sb, 2, 12>; 1444 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag, 1445 v128q, v128xb, 4, 12>; 1446 } 1447 1448 // Compare high or equal. 1449 let Uses = [FPC], mayRaiseFPException = 1 in { 1450 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1451 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1452 v128g, v128db, 3, 0>; 1453 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1454 v64g, v64db, 3, 8>; 1455 let Predicates = [FeatureVectorEnhancements1] in { 1456 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1457 v128f, v128sb, 2, 0>; 1458 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag, 1459 v32f, v32sb, 2, 8>; 1460 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag, 1461 v128q, v128xb, 4, 8>; 1462 } 1463 } 1464 1465 // Compare and signal high or equal. 1466 let Uses = [FPC], mayRaiseFPException = 1, 1467 Predicates = [FeatureVectorEnhancements1] in { 1468 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, null_frag, null_frag, 1469 v128g, v128db, 3, 4>; 1470 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, 1471 v64g, v64db, 3, 12>; 1472 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, null_frag, null_frag, 1473 v128f, v128sb, 2, 4>; 1474 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag, 1475 v32f, v32sb, 2, 12>; 1476 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag, 1477 v128q, v128xb, 4, 12>; 1478 } 1479} 1480 1481//===----------------------------------------------------------------------===// 1482// Conversions 1483//===----------------------------------------------------------------------===// 1484 1485def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1486def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1487def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1488def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1489def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1490def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>; 1491 1492def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1493def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1494def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1495def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1496def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1497def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>; 1498 1499def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1500def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1501def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1502def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1503def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1504def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>; 1505 1506def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1507def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1508def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1509def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1510def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1511def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>; 1512 1513def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1514def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1515def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1516def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1517def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1518def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>; 1519 1520def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1521def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1522def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1523def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1524def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1525def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>; 1526 1527def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>; 1528def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>; 1529def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>; 1530def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>; 1531def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>; 1532def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>; 1533 1534//===----------------------------------------------------------------------===// 1535// Replicating scalars 1536//===----------------------------------------------------------------------===// 1537 1538// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1539// INDEX is 8 minus the element size in bytes. 1540class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1541 : Pat<(type (z_replicate GR32:$scalar)), 1542 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1543 1544def : VectorReplicateScalar<v16i8, VREPB, 7>; 1545def : VectorReplicateScalar<v8i16, VREPH, 3>; 1546def : VectorReplicateScalar<v4i32, VREPF, 1>; 1547 1548// i64 replications are just a single isntruction. 1549def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1550 (VLVGP GR64:$scalar, GR64:$scalar)>; 1551 1552//===----------------------------------------------------------------------===// 1553// Floating-point insertion and extraction 1554//===----------------------------------------------------------------------===// 1555 1556// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1557// and VLGVF. 1558let Predicates = [FeatureVector] in { 1559 def LEFR : UnaryAliasVRS<VR32, GR32>; 1560 def LFER : UnaryAliasVRS<GR64, VR32>; 1561 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1562 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1563 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1564} 1565 1566// Floating-point values are stored in element 0 of the corresponding 1567// vector register. Scalar to vector conversion is just a subreg and 1568// scalar replication can just replicate element 0 of the vector register. 1569multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1570 SubRegIndex subreg> { 1571 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1572 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1573 def : Pat<(vt (z_replicate cls:$scalar)), 1574 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1575 subreg), 0)>; 1576} 1577defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>; 1578defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>; 1579 1580// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1581// TableGen for the base register operand in VLVG-based integer insertions 1582// and ensures that this version is strictly better. 1583let AddedComplexity = 4 in { 1584 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1585 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1586 subreg_h64), VR128:$vec, 1)>; 1587 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1588 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1589 subreg_h64), 0)>; 1590} 1591 1592// We extract floating-point element X by replicating (for elements other 1593// than 0) and then taking a high subreg. The AddedComplexity counters the 1594// 3 added by TableGen for the base register operand in VLGV-based integer 1595// extractions and ensures that this version is strictly better. 1596let AddedComplexity = 4 in { 1597 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1598 (EXTRACT_SUBREG VR128:$vec, subreg_h32)>; 1599 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1600 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_h32)>; 1601 1602 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1603 (EXTRACT_SUBREG VR128:$vec, subreg_h64)>; 1604 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1605 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_h64)>; 1606} 1607 1608//===----------------------------------------------------------------------===// 1609// Support for 128-bit floating-point values in vector registers 1610//===----------------------------------------------------------------------===// 1611 1612let Predicates = [FeatureVectorEnhancements1] in { 1613 def : Pat<(f128 (load bdxaddr12only:$addr)), 1614 (VL bdxaddr12only:$addr)>; 1615 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr), 1616 (VST VR128:$src, bdxaddr12only:$addr)>; 1617 1618 def : Pat<(f128 fpimm0), (VZERO)>; 1619 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>; 1620} 1621 1622//===----------------------------------------------------------------------===// 1623// String instructions 1624//===----------------------------------------------------------------------===// 1625 1626let Predicates = [FeatureVector] in { 1627 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1628 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1629 z_vfae_cc, v128b, v128b, 0>; 1630 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1631 z_vfae_cc, v128h, v128h, 1>; 1632 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1633 z_vfae_cc, v128f, v128f, 2>; 1634 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1635 z_vfaez_cc, v128b, v128b, 0, 2>; 1636 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1637 z_vfaez_cc, v128h, v128h, 1, 2>; 1638 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1639 z_vfaez_cc, v128f, v128f, 2, 2>; 1640 1641 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1642 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1643 z_vfee_cc, v128b, v128b, 0>; 1644 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1645 z_vfee_cc, v128h, v128h, 1>; 1646 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1647 z_vfee_cc, v128f, v128f, 2>; 1648 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1649 z_vfeez_cc, v128b, v128b, 0, 2>; 1650 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1651 z_vfeez_cc, v128h, v128h, 1, 2>; 1652 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1653 z_vfeez_cc, v128f, v128f, 2, 2>; 1654 1655 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1656 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1657 z_vfene_cc, v128b, v128b, 0>; 1658 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1659 z_vfene_cc, v128h, v128h, 1>; 1660 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1661 z_vfene_cc, v128f, v128f, 2>; 1662 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1663 z_vfenez_cc, v128b, v128b, 0, 2>; 1664 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1665 z_vfenez_cc, v128h, v128h, 1, 2>; 1666 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1667 z_vfenez_cc, v128f, v128f, 2, 2>; 1668 1669 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1670 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1671 z_vistr_cc, v128b, v128b, 0>; 1672 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1673 z_vistr_cc, v128h, v128h, 1>; 1674 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1675 z_vistr_cc, v128f, v128f, 2>; 1676 1677 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1678 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1679 z_vstrc_cc, v128b, v128b, 0>; 1680 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1681 z_vstrc_cc, v128h, v128h, 1>; 1682 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1683 z_vstrc_cc, v128f, v128f, 2>; 1684 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1685 z_vstrcz_cc, v128b, v128b, 0, 2>; 1686 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1687 z_vstrcz_cc, v128h, v128h, 1, 2>; 1688 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1689 z_vstrcz_cc, v128f, v128f, 2, 2>; 1690} 1691 1692let Predicates = [FeatureVectorEnhancements2] in { 1693 defm VSTRS : TernaryExtraVRRdGeneric<"vstrs", 0xE78B>; 1694 defm VSTRSB : TernaryExtraVRRd<"vstrsb", 0xE78B, 1695 z_vstrs_cc, v128b, v128b, 0>; 1696 defm VSTRSH : TernaryExtraVRRd<"vstrsh", 0xE78B, 1697 z_vstrs_cc, v128b, v128h, 1>; 1698 defm VSTRSF : TernaryExtraVRRd<"vstrsf", 0xE78B, 1699 z_vstrs_cc, v128b, v128f, 2>; 1700 let Defs = [CC] in { 1701 def VSTRSZB : TernaryVRRd<"vstrszb", 0xE78B, 1702 z_vstrsz_cc, v128b, v128b, 0, 2>; 1703 def VSTRSZH : TernaryVRRd<"vstrszh", 0xE78B, 1704 z_vstrsz_cc, v128b, v128h, 1, 2>; 1705 def VSTRSZF : TernaryVRRd<"vstrszf", 0xE78B, 1706 z_vstrsz_cc, v128b, v128f, 2, 2>; 1707 } 1708} 1709 1710//===----------------------------------------------------------------------===// 1711// Packed-decimal instructions 1712//===----------------------------------------------------------------------===// 1713 1714let Predicates = [FeatureVectorPackedDecimal] in { 1715 def VLIP : BinaryVRIh<"vlip", 0xE649>; 1716 1717 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; 1718 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; 1719 1720 let Defs = [CC] in { 1721 let Predicates = [FeatureVectorPackedDecimalEnhancement] in { 1722 def VCVBOpt : TernaryVRRi<"vcvb", 0xE650, GR32>; 1723 def VCVBGOpt : TernaryVRRi<"vcvbg", 0xE652, GR64>; 1724 } 1725 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; 1726 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; 1727 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; 1728 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; 1729 1730 def VAP : QuaternaryVRIf<"vap", 0xE671>; 1731 def VSP : QuaternaryVRIf<"vsp", 0xE673>; 1732 1733 def VMP : QuaternaryVRIf<"vmp", 0xE678>; 1734 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; 1735 1736 def VDP : QuaternaryVRIf<"vdp", 0xE67A>; 1737 def VRP : QuaternaryVRIf<"vrp", 0xE67B>; 1738 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; 1739 1740 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; 1741 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; 1742 1743 def VTP : TestVRRg<"vtp", 0xE65F>; 1744 def VCP : CompareVRRh<"vcp", 0xE677>; 1745 } 1746} 1747