SystemZInstrVector.td revision 327952
1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Move instructions 12//===----------------------------------------------------------------------===// 13 14let Predicates = [FeatureVector] in { 15 // Register move. 16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 17 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; 18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 19 20 // Load GR from VR element. 21 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 22 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 23 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 24 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 25 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 26 27 // Load VR element from GR. 28 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 29 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 30 v128b, v128b, GR32, 0>; 31 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 32 v128h, v128h, GR32, 1>; 33 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 34 v128f, v128f, GR32, 2>; 35 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 36 v128g, v128g, GR64, 3>; 37 38 // Load VR from GRs disjoint. 39 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 40 def VLVGP32 : BinaryAliasVRRf<GR32>; 41} 42 43// Extractions always assign to the full GR64, even if the element would 44// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 45// subreg of the result. 46class VectorExtractSubreg<ValueType type, Instruction insn> 47 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 48 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 49 50def : VectorExtractSubreg<v16i8, VLGVB>; 51def : VectorExtractSubreg<v8i16, VLGVH>; 52def : VectorExtractSubreg<v4i32, VLGVF>; 53 54//===----------------------------------------------------------------------===// 55// Immediate instructions 56//===----------------------------------------------------------------------===// 57 58let Predicates = [FeatureVector] in { 59 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 60 61 // Generate byte mask. 62 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 63 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 64 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; 65 66 // Generate mask. 67 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 68 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 69 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 70 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 71 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 72 73 // Replicate immediate. 74 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 75 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; 76 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; 77 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; 78 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; 79 } 80 81 // Load element immediate. 82 // 83 // We want these instructions to be used ahead of VLVG* where possible. 84 // However, VLVG* takes a variable BD-format index whereas VLEI takes 85 // a plain immediate index. This means that VLVG* has an extra "base" 86 // register operand and is 3 units more complex. Bumping the complexity 87 // of the VLEI* instructions by 4 means that they are strictly better 88 // than VLVG* in cases where both forms match. 89 let AddedComplexity = 4 in { 90 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 91 v128b, v128b, imm32sx16trunc, imm32zx4>; 92 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 93 v128h, v128h, imm32sx16trunc, imm32zx3>; 94 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 95 v128f, v128f, imm32sx16, imm32zx2>; 96 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 97 v128g, v128g, imm64sx16, imm32zx1>; 98 } 99} 100 101//===----------------------------------------------------------------------===// 102// Loads 103//===----------------------------------------------------------------------===// 104 105let Predicates = [FeatureVector] in { 106 // Load. 107 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>; 108 109 // Load to block boundary. The number of loaded bytes is only known 110 // at run time. The instruction is really polymorphic, but v128b matches 111 // the return type of the associated intrinsic. 112 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 113 114 // Load count to block boundary. 115 let Defs = [CC] in 116 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 117 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 118 "lcbb\t$R1, $XBD2, $M3", 119 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 120 imm32zx4:$M3))]>; 121 122 // Load with length. The number of loaded bytes is only known at run time. 123 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 124 125 // Load multiple. 126 def VLM : LoadMultipleVRSa<"vlm", 0xE736>; 127 128 // Load and replicate 129 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 130 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 131 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 132 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 133 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 134 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 135 (VLREPF bdxaddr12only:$addr)>; 136 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 137 (VLREPG bdxaddr12only:$addr)>; 138 139 // Use VLREP to load subvectors. These patterns use "12pair" because 140 // LEY and LDY offer full 20-bit displacement fields. It's often better 141 // to use those instructions rather than force a 20-bit displacement 142 // into a GPR temporary. 143 let mayLoad = 1 in { 144 def VL32 : UnaryAliasVRX<load, v32sb, bdxaddr12pair>; 145 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 146 } 147 148 // Load logical element and zero. 149 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 150 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 151 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 152 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 153 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 154 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)), 155 (VLLEZF bdxaddr12only:$addr)>; 156 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)), 157 (VLLEZG bdxaddr12only:$addr)>; 158 let Predicates = [FeatureVectorEnhancements1] in { 159 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; 160 def : Pat<(v4f32 (z_vllezlf32 bdxaddr12only:$addr)), 161 (VLLEZLF bdxaddr12only:$addr)>; 162 } 163 164 // Load element. 165 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 166 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 167 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 168 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 169 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 170 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 171 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 172 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 173 174 // Gather element. 175 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 176 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 177} 178 179let Predicates = [FeatureVectorPackedDecimal] in { 180 // Load rightmost with length. The number of loaded bytes is only known 181 // at run time. 182 def VLRL : BinaryVSI<"vlrl", 0xE635, int_s390_vlrl, 0>; 183 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; 184} 185 186// Use replicating loads if we're inserting a single element into an 187// undefined vector. This avoids a false dependency on the previous 188// register contents. 189multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 190 SDPatternOperator load, ValueType scalartype> { 191 def : Pat<(vectype (z_vector_insert 192 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 193 (vlrep bdxaddr12only:$addr)>; 194 def : Pat<(vectype (scalar_to_vector 195 (scalartype (load bdxaddr12only:$addr)))), 196 (vlrep bdxaddr12only:$addr)>; 197} 198defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 199defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 200defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 201defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 202defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 203defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 204 205//===----------------------------------------------------------------------===// 206// Stores 207//===----------------------------------------------------------------------===// 208 209let Predicates = [FeatureVector] in { 210 // Store. 211 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>; 212 213 // Store with length. The number of stored bytes is only known at run time. 214 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 215 216 // Store multiple. 217 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>; 218 219 // Store element. 220 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 221 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 222 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 223 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 224 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 225 imm32zx2:$index), 226 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 227 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 228 imm32zx1:$index), 229 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 230 231 // Use VSTE to store subvectors. These patterns use "12pair" because 232 // STEY and STDY offer full 20-bit displacement fields. It's often better 233 // to use those instructions rather than force a 20-bit displacement 234 // into a GPR temporary. 235 let mayStore = 1 in { 236 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>; 237 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 238 } 239 240 // Scatter element. 241 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 242 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 243} 244 245let Predicates = [FeatureVectorPackedDecimal] in { 246 // Store rightmost with length. The number of stored bytes is only known 247 // at run time. 248 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, int_s390_vstrl, 0>; 249 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; 250} 251 252//===----------------------------------------------------------------------===// 253// Selects and permutes 254//===----------------------------------------------------------------------===// 255 256let Predicates = [FeatureVector] in { 257 // Merge high. 258 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 259 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 260 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 261 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 262 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 263 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 264 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 265 266 // Merge low. 267 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 268 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 269 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 270 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 271 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 272 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 273 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 274 275 // Permute. 276 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 277 278 // Permute doubleword immediate. 279 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 280 281 // Bit Permute. 282 let Predicates = [FeatureVectorEnhancements1] in 283 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; 284 285 // Replicate. 286 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 287 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 288 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 289 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 290 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 291 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)), 292 (VREPF VR128:$vec, imm32zx16:$index)>; 293 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 294 (VREPG VR128:$vec, imm32zx16:$index)>; 295 296 // Select. 297 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 298} 299 300//===----------------------------------------------------------------------===// 301// Widening and narrowing 302//===----------------------------------------------------------------------===// 303 304let Predicates = [FeatureVector] in { 305 // Pack 306 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 307 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 308 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 309 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 310 311 // Pack saturate. 312 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 313 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 314 v128b, v128h, 1>; 315 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 316 v128h, v128f, 2>; 317 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 318 v128f, v128g, 3>; 319 320 // Pack saturate logical. 321 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 322 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 323 v128b, v128h, 1>; 324 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 325 v128h, v128f, 2>; 326 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 327 v128f, v128g, 3>; 328 329 // Sign-extend to doubleword. 330 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 331 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 332 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 333 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 334 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 335 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 336 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 337 338 // Unpack high. 339 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 340 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 341 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 342 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 343 344 // Unpack logical high. 345 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 346 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 347 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 348 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 349 350 // Unpack low. 351 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 352 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 353 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 354 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 355 356 // Unpack logical low. 357 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 358 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 359 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 360 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 361} 362 363//===----------------------------------------------------------------------===// 364// Instantiating generic operations for specific types. 365//===----------------------------------------------------------------------===// 366 367multiclass GenericVectorOps<ValueType type, ValueType inttype> { 368 let Predicates = [FeatureVector] in { 369 def : Pat<(type (load bdxaddr12only:$addr)), 370 (VL bdxaddr12only:$addr)>; 371 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 372 (VST VR128:$src, bdxaddr12only:$addr)>; 373 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 374 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 375 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 376 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 377 } 378} 379 380defm : GenericVectorOps<v16i8, v16i8>; 381defm : GenericVectorOps<v8i16, v8i16>; 382defm : GenericVectorOps<v4i32, v4i32>; 383defm : GenericVectorOps<v2i64, v2i64>; 384defm : GenericVectorOps<v4f32, v4i32>; 385defm : GenericVectorOps<v2f64, v2i64>; 386 387//===----------------------------------------------------------------------===// 388// Integer arithmetic 389//===----------------------------------------------------------------------===// 390 391let Predicates = [FeatureVector] in { 392 // Add. 393 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 394 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 395 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 396 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 397 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 398 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 399 400 // Add compute carry. 401 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 402 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 403 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 404 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 405 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 406 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 407 408 // Add with carry. 409 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 410 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 411 412 // Add with carry compute carry. 413 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 414 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 415 416 // And. 417 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 418 419 // And with complement. 420 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 421 422 // Average. 423 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 424 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 425 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 426 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 427 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 428 429 // Average logical. 430 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 431 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 432 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 433 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 434 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 435 436 // Checksum. 437 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 438 439 // Count leading zeros. 440 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 441 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 442 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 443 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 444 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 445 446 // Count trailing zeros. 447 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 448 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 449 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 450 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 451 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 452 453 // Not exclusive or. 454 let Predicates = [FeatureVectorEnhancements1] in 455 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; 456 457 // Exclusive or. 458 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 459 460 // Galois field multiply sum. 461 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 462 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 463 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 464 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 465 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 466 467 // Galois field multiply sum and accumulate. 468 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 469 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 470 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 471 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 472 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 473 474 // Load complement. 475 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 476 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 477 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 478 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 479 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 480 481 // Load positive. 482 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 483 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 484 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 485 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 486 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 487 488 // Maximum. 489 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 490 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 491 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 492 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 493 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 494 495 // Maximum logical. 496 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 497 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 498 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 499 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 500 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 501 502 // Minimum. 503 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 504 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 505 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 506 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 507 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 508 509 // Minimum logical. 510 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 511 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 512 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 513 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 514 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 515 516 // Multiply and add low. 517 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 518 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 519 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 520 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 521 522 // Multiply and add high. 523 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 524 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 525 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 526 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 527 528 // Multiply and add logical high. 529 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 530 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 531 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 532 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 533 534 // Multiply and add even. 535 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 536 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 537 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 538 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 539 540 // Multiply and add logical even. 541 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 542 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 543 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 544 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 545 546 // Multiply and add odd. 547 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 548 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 549 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 550 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 551 552 // Multiply and add logical odd. 553 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 554 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 555 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 556 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 557 558 // Multiply high. 559 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 560 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 561 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 562 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 563 564 // Multiply logical high. 565 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 566 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 567 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 568 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 569 570 // Multiply low. 571 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 572 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 573 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 574 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 575 576 // Multiply even. 577 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 578 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 579 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 580 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 581 582 // Multiply logical even. 583 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 584 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 585 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 586 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 587 588 // Multiply odd. 589 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 590 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 591 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 592 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 593 594 // Multiply logical odd. 595 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 596 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 597 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 598 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 599 600 // Multiply sum logical. 601 let Predicates = [FeatureVectorEnhancements1] in { 602 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; 603 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, 604 v128q, v128g, v128g, v128q, 3>; 605 } 606 607 // Nand. 608 let Predicates = [FeatureVectorEnhancements1] in 609 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; 610 611 // Nor. 612 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 613 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 614 615 // Or. 616 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 617 618 // Or with complement. 619 let Predicates = [FeatureVectorEnhancements1] in 620 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; 621 622 // Population count. 623 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 624 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 625 let Predicates = [FeatureVectorEnhancements1] in { 626 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; 627 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; 628 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; 629 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; 630 } 631 632 // Element rotate left logical (with vector shift amount). 633 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 634 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 635 v128b, v128b, 0>; 636 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 637 v128h, v128h, 1>; 638 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 639 v128f, v128f, 2>; 640 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 641 v128g, v128g, 3>; 642 643 // Element rotate left logical (with scalar shift amount). 644 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 645 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 646 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 647 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 648 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 649 650 // Element rotate and insert under mask. 651 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 652 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 653 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 654 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 655 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 656 657 // Element shift left (with vector shift amount). 658 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 659 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 660 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 661 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 662 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 663 664 // Element shift left (with scalar shift amount). 665 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 666 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 667 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 668 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 669 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 670 671 // Element shift right arithmetic (with vector shift amount). 672 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 673 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 674 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 675 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 676 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 677 678 // Element shift right arithmetic (with scalar shift amount). 679 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 680 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 681 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 682 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 683 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 684 685 // Element shift right logical (with vector shift amount). 686 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 687 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 688 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 689 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 690 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 691 692 // Element shift right logical (with scalar shift amount). 693 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 694 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 695 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 696 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 697 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 698 699 // Shift left. 700 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 701 702 // Shift left by byte. 703 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 704 705 // Shift left double by byte. 706 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 707 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z), 708 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 709 710 // Shift right arithmetic. 711 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 712 713 // Shift right arithmetic by byte. 714 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 715 716 // Shift right logical. 717 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 718 719 // Shift right logical by byte. 720 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 721 722 // Subtract. 723 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 724 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 725 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 726 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 727 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 728 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 729 730 // Subtract compute borrow indication. 731 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 732 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 733 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 734 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 735 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 736 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 737 738 // Subtract with borrow indication. 739 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 740 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 741 742 // Subtract with borrow compute borrow indication. 743 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 744 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 745 v128q, v128q, 4>; 746 747 // Sum across doubleword. 748 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 749 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 750 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 751 752 // Sum across quadword. 753 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 754 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 755 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 756 757 // Sum across word. 758 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 759 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 760 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 761} 762 763// Instantiate the bitwise ops for type TYPE. 764multiclass BitwiseVectorOps<ValueType type> { 765 let Predicates = [FeatureVector] in { 766 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 767 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 768 (VNC VR128:$x, VR128:$y)>; 769 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 770 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 771 def : Pat<(type (or (and VR128:$x, VR128:$z), 772 (and VR128:$y, (z_vnot VR128:$z)))), 773 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 774 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 775 (VNO VR128:$x, VR128:$y)>; 776 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 777 } 778 let Predicates = [FeatureVectorEnhancements1] in { 779 def : Pat<(type (z_vnot (xor VR128:$x, VR128:$y))), 780 (VNX VR128:$x, VR128:$y)>; 781 def : Pat<(type (z_vnot (and VR128:$x, VR128:$y))), 782 (VNN VR128:$x, VR128:$y)>; 783 def : Pat<(type (or VR128:$x, (z_vnot VR128:$y))), 784 (VOC VR128:$x, VR128:$y)>; 785 } 786} 787 788defm : BitwiseVectorOps<v16i8>; 789defm : BitwiseVectorOps<v8i16>; 790defm : BitwiseVectorOps<v4i32>; 791defm : BitwiseVectorOps<v2i64>; 792 793// Instantiate additional patterns for absolute-related expressions on 794// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 795// instruction. 796multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 797 Instruction lp, int shift> { 798 let Predicates = [FeatureVector] in { 799 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 800 (z_vneg VR128:$x), VR128:$x)), 801 (lc (lp VR128:$x))>; 802 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 803 VR128:$x, (z_vneg VR128:$x))), 804 (lc (lp VR128:$x))>; 805 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 806 VR128:$x, (z_vneg VR128:$x))), 807 (lc (lp VR128:$x))>; 808 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 809 (z_vneg VR128:$x), VR128:$x)), 810 (lc (lp VR128:$x))>; 811 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 812 (z_vneg VR128:$x)), 813 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 814 VR128:$x))), 815 (lp VR128:$x)>; 816 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 817 VR128:$x), 818 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 819 (z_vneg VR128:$x)))), 820 (lc (lp VR128:$x))>; 821 } 822} 823 824defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 825defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 826defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 827defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 828 829// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 830// signed or unsigned "set if greater than" comparison instruction and 831// MIN and MAX are the associated minimum and maximum instructions. 832multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 833 Instruction min, Instruction max> { 834 let Predicates = [FeatureVector] in { 835 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 836 (max VR128:$x, VR128:$y)>; 837 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 838 (min VR128:$x, VR128:$y)>; 839 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 840 VR128:$x, VR128:$y)), 841 (min VR128:$x, VR128:$y)>; 842 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 843 VR128:$y, VR128:$x)), 844 (max VR128:$x, VR128:$y)>; 845 } 846} 847 848// Signed min/max. 849defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 850defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 851defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 852defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 853 854// Unsigned min/max. 855defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 856defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 857defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 858defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 859 860//===----------------------------------------------------------------------===// 861// Integer comparison 862//===----------------------------------------------------------------------===// 863 864let Predicates = [FeatureVector] in { 865 // Element compare. 866 let Defs = [CC] in { 867 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 868 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 869 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 870 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 871 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 872 } 873 874 // Element compare logical. 875 let Defs = [CC] in { 876 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 877 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 878 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 879 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 880 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 881 } 882 883 // Compare equal. 884 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 885 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 886 v128b, v128b, 0>; 887 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 888 v128h, v128h, 1>; 889 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 890 v128f, v128f, 2>; 891 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 892 v128g, v128g, 3>; 893 894 // Compare high. 895 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 896 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 897 v128b, v128b, 0>; 898 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 899 v128h, v128h, 1>; 900 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 901 v128f, v128f, 2>; 902 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 903 v128g, v128g, 3>; 904 905 // Compare high logical. 906 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 907 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 908 v128b, v128b, 0>; 909 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 910 v128h, v128h, 1>; 911 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 912 v128f, v128f, 2>; 913 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 914 v128g, v128g, 3>; 915 916 // Test under mask. 917 let Defs = [CC] in 918 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 919} 920 921//===----------------------------------------------------------------------===// 922// Floating-point arithmetic 923//===----------------------------------------------------------------------===// 924 925// See comments in SystemZInstrFP.td for the suppression flags and 926// rounding modes. 927multiclass VectorRounding<Instruction insn, TypedReg tr> { 928 def : FPConversion<insn, frint, tr, tr, 0, 0>; 929 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>; 930 def : FPConversion<insn, ffloor, tr, tr, 4, 7>; 931 def : FPConversion<insn, fceil, tr, tr, 4, 6>; 932 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>; 933 def : FPConversion<insn, fround, tr, tr, 4, 1>; 934} 935 936let Predicates = [FeatureVector] in { 937 // Add. 938 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 939 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>; 940 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>; 941 let Predicates = [FeatureVectorEnhancements1] in { 942 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, fadd, v128sb, v128sb, 2, 0>; 943 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, fadd, v32sb, v32sb, 2, 8>; 944 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, fadd, v128xb, v128xb, 4, 8>; 945 } 946 947 // Convert from fixed 64-bit. 948 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 949 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 950 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 951 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>; 952 953 // Convert from logical 64-bit. 954 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 955 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 956 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 957 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>; 958 959 // Convert to fixed 64-bit. 960 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 961 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 962 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 963 // Rounding mode should agree with SystemZInstrFP.td. 964 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>; 965 966 // Convert to logical 64-bit. 967 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 968 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 969 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 970 // Rounding mode should agree with SystemZInstrFP.td. 971 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>; 972 973 // Divide. 974 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 975 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>; 976 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>; 977 let Predicates = [FeatureVectorEnhancements1] in { 978 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, fdiv, v128sb, v128sb, 2, 0>; 979 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, fdiv, v32sb, v32sb, 2, 8>; 980 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, fdiv, v128xb, v128xb, 4, 8>; 981 } 982 983 // Load FP integer. 984 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 985 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 986 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 987 defm : VectorRounding<VFIDB, v128db>; 988 defm : VectorRounding<WFIDB, v64db>; 989 let Predicates = [FeatureVectorEnhancements1] in { 990 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>; 991 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>; 992 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>; 993 defm : VectorRounding<VFISB, v128sb>; 994 defm : VectorRounding<WFISB, v32sb>; 995 defm : VectorRounding<WFIXB, v128xb>; 996 } 997 998 // Load lengthened. 999 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 1000 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128sb, 2, 0>; 1001 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fpextend, v64db, v32sb, 2, 8>; 1002 let Predicates = [FeatureVectorEnhancements1] in { 1003 let isAsmParserOnly = 1 in { 1004 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>; 1005 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>; 1006 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>; 1007 } 1008 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, fpextend, v128xb, v64db, 3, 8>; 1009 def : Pat<(f128 (fpextend (f32 VR32:$src))), 1010 (WFLLD (WLDEB VR32:$src))>; 1011 } 1012 1013 // Load rounded. 1014 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 1015 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1016 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1017 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 1018 def : FPConversion<WLEDB, fpround, v32sb, v64db, 0, 0>; 1019 let Predicates = [FeatureVectorEnhancements1] in { 1020 let isAsmParserOnly = 1 in { 1021 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>; 1022 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1023 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1024 } 1025 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>; 1026 def : FPConversion<WFLRX, fpround, v64db, v128xb, 0, 0>; 1027 def : Pat<(f32 (fpround (f128 VR128:$src))), 1028 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>; 1029 } 1030 1031 // Maximum. 1032 multiclass VectorMax<Instruction insn, TypedReg tr> { 1033 def : FPMinMax<insn, fmaxnum, tr, 4>; 1034 def : FPMinMax<insn, fmaxnan, tr, 1>; 1035 } 1036 let Predicates = [FeatureVectorEnhancements1] in { 1037 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; 1038 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, 1039 v128db, v128db, 3, 0>; 1040 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, 1041 v64db, v64db, 3, 8>; 1042 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb, 1043 v128sb, v128sb, 2, 0>; 1044 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag, 1045 v32sb, v32sb, 2, 8>; 1046 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag, 1047 v128xb, v128xb, 4, 8>; 1048 defm : VectorMax<VFMAXDB, v128db>; 1049 defm : VectorMax<WFMAXDB, v64db>; 1050 defm : VectorMax<VFMAXSB, v128sb>; 1051 defm : VectorMax<WFMAXSB, v32sb>; 1052 defm : VectorMax<WFMAXXB, v128xb>; 1053 } 1054 1055 // Minimum. 1056 multiclass VectorMin<Instruction insn, TypedReg tr> { 1057 def : FPMinMax<insn, fminnum, tr, 4>; 1058 def : FPMinMax<insn, fminnan, tr, 1>; 1059 } 1060 let Predicates = [FeatureVectorEnhancements1] in { 1061 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; 1062 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, 1063 v128db, v128db, 3, 0>; 1064 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, 1065 v64db, v64db, 3, 8>; 1066 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb, 1067 v128sb, v128sb, 2, 0>; 1068 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag, 1069 v32sb, v32sb, 2, 8>; 1070 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag, 1071 v128xb, v128xb, 4, 8>; 1072 defm : VectorMin<VFMINDB, v128db>; 1073 defm : VectorMin<WFMINDB, v64db>; 1074 defm : VectorMin<VFMINSB, v128sb>; 1075 defm : VectorMin<WFMINSB, v32sb>; 1076 defm : VectorMin<WFMINXB, v128xb>; 1077 } 1078 1079 // Multiply. 1080 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 1081 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>; 1082 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>; 1083 let Predicates = [FeatureVectorEnhancements1] in { 1084 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, fmul, v128sb, v128sb, 2, 0>; 1085 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, fmul, v32sb, v32sb, 2, 8>; 1086 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, fmul, v128xb, v128xb, 4, 8>; 1087 } 1088 1089 // Multiply and add. 1090 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 1091 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>; 1092 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>; 1093 let Predicates = [FeatureVectorEnhancements1] in { 1094 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, fma, v128sb, v128sb, 0, 2>; 1095 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, fma, v32sb, v32sb, 8, 2>; 1096 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, fma, v128xb, v128xb, 8, 4>; 1097 } 1098 1099 // Multiply and subtract. 1100 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 1101 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>; 1102 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>; 1103 let Predicates = [FeatureVectorEnhancements1] in { 1104 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, fms, v128sb, v128sb, 0, 2>; 1105 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, fms, v32sb, v32sb, 8, 2>; 1106 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, fms, v128xb, v128xb, 8, 4>; 1107 } 1108 1109 // Negative multiply and add. 1110 let Predicates = [FeatureVectorEnhancements1] in { 1111 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; 1112 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, fnma, v128db, v128db, 0, 3>; 1113 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, fnma, v64db, v64db, 8, 3>; 1114 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, fnma, v128sb, v128sb, 0, 2>; 1115 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, fnma, v32sb, v32sb, 8, 2>; 1116 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, fnma, v128xb, v128xb, 8, 4>; 1117 } 1118 1119 // Negative multiply and subtract. 1120 let Predicates = [FeatureVectorEnhancements1] in { 1121 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; 1122 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, fnms, v128db, v128db, 0, 3>; 1123 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, fnms, v64db, v64db, 8, 3>; 1124 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, fnms, v128sb, v128sb, 0, 2>; 1125 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, fnms, v32sb, v32sb, 8, 2>; 1126 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, fnms, v128xb, v128xb, 8, 4>; 1127 } 1128 1129 // Perform sign operation. 1130 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 1131 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 1132 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 1133 let Predicates = [FeatureVectorEnhancements1] in { 1134 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>; 1135 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>; 1136 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>; 1137 } 1138 1139 // Load complement. 1140 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 1141 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 1142 let Predicates = [FeatureVectorEnhancements1] in { 1143 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>; 1144 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>; 1145 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>; 1146 } 1147 1148 // Load negative. 1149 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 1150 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 1151 let Predicates = [FeatureVectorEnhancements1] in { 1152 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>; 1153 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>; 1154 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>; 1155 } 1156 1157 // Load positive. 1158 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 1159 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 1160 let Predicates = [FeatureVectorEnhancements1] in { 1161 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>; 1162 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>; 1163 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>; 1164 } 1165 1166 // Square root. 1167 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 1168 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>; 1169 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>; 1170 let Predicates = [FeatureVectorEnhancements1] in { 1171 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, fsqrt, v128sb, v128sb, 2, 0>; 1172 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, fsqrt, v32sb, v32sb, 2, 8>; 1173 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, fsqrt, v128xb, v128xb, 4, 8>; 1174 } 1175 1176 // Subtract. 1177 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 1178 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>; 1179 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>; 1180 let Predicates = [FeatureVectorEnhancements1] in { 1181 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, fsub, v128sb, v128sb, 2, 0>; 1182 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, fsub, v32sb, v32sb, 2, 8>; 1183 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, fsub, v128xb, v128xb, 4, 8>; 1184 } 1185 1186 // Test data class immediate. 1187 let Defs = [CC] in { 1188 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 1189 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 1190 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 1191 let Predicates = [FeatureVectorEnhancements1] in { 1192 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>; 1193 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>; 1194 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>; 1195 } 1196 } 1197} 1198 1199//===----------------------------------------------------------------------===// 1200// Floating-point comparison 1201//===----------------------------------------------------------------------===// 1202 1203let Predicates = [FeatureVector] in { 1204 // Compare scalar. 1205 let Defs = [CC] in { 1206 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 1207 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>; 1208 let Predicates = [FeatureVectorEnhancements1] in { 1209 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_fcmp, v32sb, 2>; 1210 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_fcmp, v128xb, 4>; 1211 } 1212 } 1213 1214 // Compare and signal scalar. 1215 let Defs = [CC] in { 1216 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 1217 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; 1218 let Predicates = [FeatureVectorEnhancements1] in { 1219 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, null_frag, v32sb, 2>; 1220 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, null_frag, v128xb, 4>; 1221 } 1222 } 1223 1224 // Compare equal. 1225 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1226 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1227 v128g, v128db, 3, 0>; 1228 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1229 v64g, v64db, 3, 8>; 1230 let Predicates = [FeatureVectorEnhancements1] in { 1231 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1232 v128f, v128sb, 2, 0>; 1233 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag, 1234 v32f, v32sb, 2, 8>; 1235 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag, 1236 v128q, v128xb, 4, 8>; 1237 } 1238 1239 // Compare and signal equal. 1240 let Predicates = [FeatureVectorEnhancements1] in { 1241 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, null_frag, null_frag, 1242 v128g, v128db, 3, 4>; 1243 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, 1244 v64g, v64db, 3, 12>; 1245 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, null_frag, null_frag, 1246 v128f, v128sb, 2, 4>; 1247 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag, 1248 v32f, v32sb, 2, 12>; 1249 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag, 1250 v128q, v128xb, 4, 12>; 1251 } 1252 1253 // Compare high. 1254 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1255 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, 1256 v128g, v128db, 3, 0>; 1257 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1258 v64g, v64db, 3, 8>; 1259 let Predicates = [FeatureVectorEnhancements1] in { 1260 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_vfcmph, z_vfcmphs, 1261 v128f, v128sb, 2, 0>; 1262 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag, 1263 v32f, v32sb, 2, 8>; 1264 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag, 1265 v128q, v128xb, 4, 8>; 1266 } 1267 1268 // Compare and signal high. 1269 let Predicates = [FeatureVectorEnhancements1] in { 1270 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, null_frag, null_frag, 1271 v128g, v128db, 3, 4>; 1272 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, 1273 v64g, v64db, 3, 12>; 1274 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, null_frag, null_frag, 1275 v128f, v128sb, 2, 4>; 1276 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag, 1277 v32f, v32sb, 2, 12>; 1278 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag, 1279 v128q, v128xb, 4, 12>; 1280 } 1281 1282 // Compare high or equal. 1283 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1284 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1285 v128g, v128db, 3, 0>; 1286 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1287 v64g, v64db, 3, 8>; 1288 let Predicates = [FeatureVectorEnhancements1] in { 1289 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1290 v128f, v128sb, 2, 0>; 1291 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag, 1292 v32f, v32sb, 2, 8>; 1293 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag, 1294 v128q, v128xb, 4, 8>; 1295 } 1296 1297 // Compare and signal high or equal. 1298 let Predicates = [FeatureVectorEnhancements1] in { 1299 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, null_frag, null_frag, 1300 v128g, v128db, 3, 4>; 1301 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, 1302 v64g, v64db, 3, 12>; 1303 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, null_frag, null_frag, 1304 v128f, v128sb, 2, 4>; 1305 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag, 1306 v32f, v32sb, 2, 12>; 1307 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag, 1308 v128q, v128xb, 4, 12>; 1309 } 1310} 1311 1312//===----------------------------------------------------------------------===// 1313// Conversions 1314//===----------------------------------------------------------------------===// 1315 1316def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1317def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1318def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1319def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1320def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1321def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>; 1322 1323def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1324def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1325def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1326def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1327def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1328def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>; 1329 1330def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1331def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1332def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1333def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1334def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1335def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>; 1336 1337def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1338def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1339def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1340def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1341def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1342def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>; 1343 1344def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1345def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1346def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1347def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1348def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1349def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>; 1350 1351def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1352def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1353def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1354def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1355def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1356def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>; 1357 1358def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>; 1359def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>; 1360def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>; 1361def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>; 1362def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>; 1363def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>; 1364 1365//===----------------------------------------------------------------------===// 1366// Replicating scalars 1367//===----------------------------------------------------------------------===// 1368 1369// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1370// INDEX is 8 minus the element size in bytes. 1371class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1372 : Pat<(type (z_replicate GR32:$scalar)), 1373 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1374 1375def : VectorReplicateScalar<v16i8, VREPB, 7>; 1376def : VectorReplicateScalar<v8i16, VREPH, 3>; 1377def : VectorReplicateScalar<v4i32, VREPF, 1>; 1378 1379// i64 replications are just a single isntruction. 1380def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1381 (VLVGP GR64:$scalar, GR64:$scalar)>; 1382 1383//===----------------------------------------------------------------------===// 1384// Floating-point insertion and extraction 1385//===----------------------------------------------------------------------===// 1386 1387// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1388// and VLGVF. 1389let Predicates = [FeatureVector] in { 1390 def LEFR : UnaryAliasVRS<VR32, GR32>; 1391 def LFER : UnaryAliasVRS<GR64, VR32>; 1392 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1393 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1394 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1395} 1396 1397// Floating-point values are stored in element 0 of the corresponding 1398// vector register. Scalar to vector conversion is just a subreg and 1399// scalar replication can just replicate element 0 of the vector register. 1400multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1401 SubRegIndex subreg> { 1402 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1403 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1404 def : Pat<(vt (z_replicate cls:$scalar)), 1405 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1406 subreg), 0)>; 1407} 1408defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_r32>; 1409defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>; 1410 1411// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1412// TableGen for the base register operand in VLVG-based integer insertions 1413// and ensures that this version is strictly better. 1414let AddedComplexity = 4 in { 1415 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1416 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1417 subreg_r64), VR128:$vec, 1)>; 1418 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1419 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1420 subreg_r64), 0)>; 1421} 1422 1423// We extract floating-point element X by replicating (for elements other 1424// than 0) and then taking a high subreg. The AddedComplexity counters the 1425// 3 added by TableGen for the base register operand in VLGV-based integer 1426// extractions and ensures that this version is strictly better. 1427let AddedComplexity = 4 in { 1428 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1429 (EXTRACT_SUBREG VR128:$vec, subreg_r32)>; 1430 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1431 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>; 1432 1433 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1434 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>; 1435 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1436 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>; 1437} 1438 1439//===----------------------------------------------------------------------===// 1440// Support for 128-bit floating-point values in vector registers 1441//===----------------------------------------------------------------------===// 1442 1443let Predicates = [FeatureVectorEnhancements1] in { 1444 def : Pat<(f128 (load bdxaddr12only:$addr)), 1445 (VL bdxaddr12only:$addr)>; 1446 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr), 1447 (VST VR128:$src, bdxaddr12only:$addr)>; 1448 1449 def : Pat<(f128 fpimm0), (VZERO)>; 1450 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>; 1451} 1452 1453//===----------------------------------------------------------------------===// 1454// String instructions 1455//===----------------------------------------------------------------------===// 1456 1457let Predicates = [FeatureVector] in { 1458 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1459 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1460 z_vfae_cc, v128b, v128b, 0>; 1461 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1462 z_vfae_cc, v128h, v128h, 1>; 1463 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1464 z_vfae_cc, v128f, v128f, 2>; 1465 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1466 z_vfaez_cc, v128b, v128b, 0, 2>; 1467 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1468 z_vfaez_cc, v128h, v128h, 1, 2>; 1469 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1470 z_vfaez_cc, v128f, v128f, 2, 2>; 1471 1472 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1473 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1474 z_vfee_cc, v128b, v128b, 0>; 1475 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1476 z_vfee_cc, v128h, v128h, 1>; 1477 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1478 z_vfee_cc, v128f, v128f, 2>; 1479 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1480 z_vfeez_cc, v128b, v128b, 0, 2>; 1481 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1482 z_vfeez_cc, v128h, v128h, 1, 2>; 1483 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1484 z_vfeez_cc, v128f, v128f, 2, 2>; 1485 1486 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1487 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1488 z_vfene_cc, v128b, v128b, 0>; 1489 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1490 z_vfene_cc, v128h, v128h, 1>; 1491 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1492 z_vfene_cc, v128f, v128f, 2>; 1493 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1494 z_vfenez_cc, v128b, v128b, 0, 2>; 1495 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1496 z_vfenez_cc, v128h, v128h, 1, 2>; 1497 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1498 z_vfenez_cc, v128f, v128f, 2, 2>; 1499 1500 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1501 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1502 z_vistr_cc, v128b, v128b, 0>; 1503 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1504 z_vistr_cc, v128h, v128h, 1>; 1505 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1506 z_vistr_cc, v128f, v128f, 2>; 1507 1508 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1509 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1510 z_vstrc_cc, v128b, v128b, 0>; 1511 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1512 z_vstrc_cc, v128h, v128h, 1>; 1513 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1514 z_vstrc_cc, v128f, v128f, 2>; 1515 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1516 z_vstrcz_cc, v128b, v128b, 0, 2>; 1517 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1518 z_vstrcz_cc, v128h, v128h, 1, 2>; 1519 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1520 z_vstrcz_cc, v128f, v128f, 2, 2>; 1521} 1522 1523//===----------------------------------------------------------------------===// 1524// Packed-decimal instructions 1525//===----------------------------------------------------------------------===// 1526 1527let Predicates = [FeatureVectorPackedDecimal] in { 1528 def VLIP : BinaryVRIh<"vlip", 0xE649>; 1529 1530 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; 1531 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; 1532 1533 let Defs = [CC] in { 1534 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; 1535 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; 1536 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; 1537 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; 1538 1539 def VAP : QuaternaryVRIf<"vap", 0xE671>; 1540 def VSP : QuaternaryVRIf<"vsp", 0xE673>; 1541 1542 def VMP : QuaternaryVRIf<"vmp", 0xE678>; 1543 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; 1544 1545 def VDP : QuaternaryVRIf<"vdp", 0xE67A>; 1546 def VRP : QuaternaryVRIf<"vrp", 0xE67B>; 1547 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; 1548 1549 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; 1550 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; 1551 1552 def VTP : TestVRRg<"vtp", 0xE65F>; 1553 def VCP : CompareVRRh<"vcp", 0xE677>; 1554 } 1555} 1556