111394Sswallace//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===// 211394Sswallace// 311394Sswallace// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 411394Sswallace// See https://llvm.org/LICENSE.txt for license information. 511394Sswallace// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 611394Sswallace// 711394Sswallace//===----------------------------------------------------------------------===// 811394Sswallace// 911394Sswallace// This file contains instruction formats, definitions and patterns needed for 1011394Sswallace// VIS, VIS II, VIS II instructions on SPARC. 1111394Sswallace//===----------------------------------------------------------------------===// 1211394Sswallace 1311394Sswallace// VIS Instruction Format. 1411394Sswallaceclass VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr, 1511394Sswallace list<dag> pattern> 1611394Sswallace : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>; 1711394Sswallace 1811394Sswallaceclass VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 1911394Sswallace : VISInstFormat<opfval, 2011394Sswallace (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 2111394Sswallace !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 2211394Sswallace 2311394Sswallace// VIS Instruction with integer destination register. 2411394Sswallaceclass VISInstID<bits<9> opfval, string OpcStr> 2511394Sswallace : VISInstFormat<opfval, 2611527Sswallace (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 2712218Sbde !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 2811394Sswallace 2911394Sswallace// For VIS Instructions with no operand. 3011394Sswallacelet rd = 0, rs1 = 0, rs2 = 0 in 3111394Sswallaceclass VISInst0<bits<9> opfval, string asmstr> 3211394Sswallace : VISInstFormat<opfval, (outs), (ins), asmstr, []>; 3311394Sswallace 3411394Sswallace// For VIS Instructions with only rs1, rd operands. 3511394Sswallacelet rs2 = 0 in 3611394Sswallaceclass VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 3711394Sswallace : VISInstFormat<opfval, 3811394Sswallace (outs RC:$rd), (ins RC:$rs1), 3911394Sswallace !strconcat(OpcStr, " $rs1, $rd"), []>; 4011394Sswallace 4111397Sswallace// For VIS Instructions with only rs2, rd operands. 4211394Sswallacelet rs1 = 0 in 4311397Sswallaceclass VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 4411397Sswallace : VISInstFormat<opfval, 4511397Sswallace (outs RC:$rd), (ins RC:$rs2), 4611397Sswallace !strconcat(OpcStr, " $rs2, $rd"), []>; 4711397Sswallace 4811394Sswallace// For VIS Instructions with only rd operand. 4911397Sswallacelet Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in 5011397Sswallaceclass VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs> 5111397Sswallace : VISInstFormat<opfval, 5211397Sswallace (outs RC:$rd), (ins RC:$f), 5311397Sswallace !strconcat(OpcStr, " $rd"), []>; 5411394Sswallace 5511394Sswallace// VIS 1 Instructions 5611394Sswallacelet Predicates = [HasVIS] in { 5711394Sswallace 5811394Sswallacedef FPADD16 : VISInst<0b001010000, "fpadd16">; 5911394Sswallacedef FPADD16S : VISInst<0b001010001, "fpadd16s">; 6011394Sswallacedef FPADD32 : VISInst<0b001010010, "fpadd32">; 6111394Sswallacedef FPADD32S : VISInst<0b001010011, "fpadd32s">; 6211394Sswallacedef FPSUB16 : VISInst<0b001010100, "fpsub16">; 6311397Sswallacedef FPSUB16S : VISInst<0b001010101, "fpsub16S">; 6411394Sswallacedef FPSUB32 : VISInst<0b001010110, "fpsub32">; 6511394Sswallacedef FPSUB32S : VISInst<0b001010111, "fpsub32S">; 6611397Sswallace 6711397Sswallacedef FPACK16 : VISInst2<0b000111011, "fpack16">; 6811397Sswallacedef FPACK32 : VISInst <0b000111010, "fpack32">; 6911397Sswallacedef FPACKFIX : VISInst2<0b000111101, "fpackfix">; 7011397Sswallacedef FEXPAND : VISInst2<0b001001101, "fexpand">; 7111397Sswallacedef FPMERGE : VISInst <0b001001011, "fpmerge">; 7211397Sswallace 7311394Sswallacedef FMUL8X16 : VISInst<0b000110001, "fmul8x16">; 7411394Sswallacedef FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">; 7511394Sswallacedef FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">; 7611394Sswallacedef FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">; 7711394Sswallacedef FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">; 7811394Sswallacedef FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">; 7911394Sswallacedef FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">; 8011394Sswallace 8111394Sswallacedef ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>; 8211394Sswallacedef ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>; 8311394Sswallacedef FALIGNADATA : VISInst<0b001001000, "faligndata">; 8411394Sswallace 8511394Sswallacedef FZERO : VISInstD<0b001100000, "fzero">; 8611394Sswallacedef FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>; 8711394Sswallacedef FONE : VISInstD<0b001111110, "fone">; 8811394Sswallacedef FONES : VISInstD<0b001111111, "fones", FPRegs>; 8911394Sswallacedef FSRC1 : VISInst1<0b001110100, "fsrc1">; 9011394Sswallacedef FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>; 9111394Sswallacedef FSRC2 : VISInst2<0b001111000, "fsrc2">; 9211394Sswallacedef FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>; 9311394Sswallacedef FNOT1 : VISInst1<0b001101010, "fnot1">; 9411394Sswallacedef FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>; 9511394Sswallacedef FNOT2 : VISInst2<0b001100110, "fnot2">; 9611394Sswallacedef FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>; 9711394Sswallacedef FOR : VISInst<0b001111100, "for">; 9811394Sswallacedef FORS : VISInst<0b001111101, "fors", FPRegs>; 9911397Sswallacedef FNOR : VISInst<0b001100010, "fnor">; 10011394Sswallacedef FNORS : VISInst<0b001100011, "fnors", FPRegs>; 10111397Sswallacedef FAND : VISInst<0b001110000, "fand">; 10211397Sswallacedef FANDS : VISInst<0b001110001, "fands", FPRegs>; 10311397Sswallacedef FNAND : VISInst<0b001101110, "fnand">; 10411397Sswallacedef FNANDS : VISInst<0b001101111, "fnands", FPRegs>; 10511397Sswallacedef FXOR : VISInst<0b001101100, "fxor">; 10611397Sswallacedef FXORS : VISInst<0b001101101, "fxors", FPRegs>; 10711397Sswallacedef FXNOR : VISInst<0b001110010, "fxnor">; 10811397Sswallacedef FXNORS : VISInst<0b001110011, "fxnors", FPRegs>; 10911397Sswallace 11011394Sswallacedef FORNOT1 : VISInst<0b001111010, "fornot1">; 11111394Sswallacedef FORNOT1S : VISInst<0b001111011, "fornot1s", FPRegs>; 11211394Sswallacedef FORNOT2 : VISInst<0b001110110, "fornot2">; 11311394Sswallacedef FORNOT2S : VISInst<0b001110111, "fornot2s", FPRegs>; 11411394Sswallacedef FANDNOT1 : VISInst<0b001101000, "fandnot1">; 11511394Sswallacedef FANDNOT1S : VISInst<0b001101001, "fandnot1s", FPRegs>; 11611394Sswallacedef FANDNOT2 : VISInst<0b001100100, "fandnot2">; 11711394Sswallacedef FANDNOT2S : VISInst<0b001100101, "fandnot2s", FPRegs>; 11811394Sswallace 11911394Sswallacedef FCMPGT16 : VISInstID<0b000101000, "fcmpgt16">; 12011394Sswallacedef FCMPGT32 : VISInstID<0b000101100, "fcmpgt32">; 12111394Sswallacedef FCMPLE16 : VISInstID<0b000100000, "fcmple16">; 12211394Sswallacedef FCMPLE32 : VISInstID<0b000100100, "fcmple32">; 12311394Sswallacedef FCMPNE16 : VISInstID<0b000100010, "fcmpne16">; 12411394Sswallacedef FCMPNE32 : VISInstID<0b000100110, "fcmpne32">; 12511394Sswallacedef FCMPEQ16 : VISInstID<0b000101010, "fcmpeq16">; 12611394Sswallacedef FCMPEQ32 : VISInstID<0b000101110, "fcmpeq32">; 12711394Sswallace 12811394Sswallace 12911394Sswallacedef EDGE8 : VISInst<0b000000000, "edge8", I64Regs>; 13011394Sswallacedef EDGE8L : VISInst<0b000000010, "edge8l", I64Regs>; 13111394Sswallacedef EDGE16 : VISInst<0b000000100, "edge16", I64Regs>; 13211394Sswallacedef EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>; 13311394Sswallacedef EDGE32 : VISInst<0b000001000, "edge32", I64Regs>; 13411394Sswallacedef EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>; 13511394Sswallace 13611394Sswallacedef PDIST : VISInst<0b000111110, "pdist">; 13711394Sswallace 13811394Sswallacedef ARRAY8 : VISInst<0b000010000, "array8", I64Regs>; 13911394Sswallacedef ARRAY16 : VISInst<0b000010010, "array16", I64Regs>; 14011394Sswallacedef ARRAY32 : VISInst<0b000010100, "array32", I64Regs>; 14111394Sswallace 14211394Sswallacedef SHUTDOWN : VISInst0<0b010000000, "shutdown">; 14311394Sswallace 14411394Sswallace} // Predicates = [HasVIS] 14511394Sswallace 14611394Sswallace 14711394Sswallace// VIS 2 Instructions. 14811394Sswallacelet Predicates = [HasVIS2] in { 14911394Sswallace 15011394Sswallacedef BMASK : VISInst<0b000011001, "bmask", I64Regs>; 15111394Sswallacedef BSHUFFLE : VISInst<0b000011100, "bshuffle">; 15211394Sswallace 15311394Sswallacedef SIAM : VISInst0<0b010000001, "siam">; 15411394Sswallace 15511394Sswallacedef EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>; 15611394Sswallacedef EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>; 15711394Sswallacedef EDGE16N : VISInst<0b000000101, "edge16n", I64Regs>; 15811394Sswallacedef EDGE16LN : VISInst<0b000000111, "edge16ln", I64Regs>; 15911394Sswallacedef EDGE32N : VISInst<0b000001001, "edge32n", I64Regs>; 16011394Sswallacedef EDGE32LN : VISInst<0b000001011, "edge32ln", I64Regs>; 16111394Sswallace} // Predicates = [HasVIS2] 16211394Sswallace 16311394Sswallace 16411394Sswallace// VIS 3 Instructions. 16511394Sswallacelet Predicates = [HasVIS3] in { 16611394Sswallace 16711394Sswallacelet Uses = [ICC] in 16811394Sswallacedef ADDXC : VISInst<0b000010001, "addxc", I64Regs>; 16911394Sswallace 17011394Sswallacelet Defs = [ICC], Uses = [ICC] in 17111394Sswallacedef ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>; 17211394Sswallace 17311394Sswallacelet rd = 0, rs1 = 0 in { 17411394Sswallacedef CMASK8 : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2), 17511394Sswallace "cmask8 $rs2", []>; 17611394Sswallacedef CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2), 17711394Sswallace "cmask16 $rs2", []>; 17811394Sswallacedef CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2), 17911394Sswallace "cmask32 $rs2", []>; 18011394Sswallace 18111394Sswallace} 18211394Sswallace 18311394Sswallacedef FCHKSM16 : VISInst<0b001000100, "fchksm16">; 18411394Sswallace 18511394Sswallacedef FHADDS : F3_3<0b10, 0b110100, 0b001100001, 18611394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 18711394Sswallace "fhadds $rs1, $rs2, $rd", []>; 18811397Sswallacedef FHADDD : F3_3<0b10, 0b110100, 0b001100010, 18911394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 19011527Sswallace "fhaddd $rs1, $rs2, $rd", []>; 19111527Sswallacedef FHSUBS : F3_3<0b10, 0b110100, 0b001100101, 19211527Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 19311527Sswallace "fhsubs $rs1, $rs2, $rd", []>; 19411527Sswallacedef FHSUBD : F3_3<0b10, 0b110100, 0b001100110, 19511527Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 19611394Sswallace "fhsubd $rs1, $rs2, $rd", []>; 19711394Sswallacedef FLCMPS : VISInstFormat<0b101010001, (outs FCCRegs:$rd), 19811394Sswallace (ins DFPRegs:$rs1, DFPRegs:$rs2), 19911394Sswallace "flcmps $rd, $rs1, $rs2", []>; 20011394Sswallacedef FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd), 20111394Sswallace (ins DFPRegs:$rs1, DFPRegs:$rs2), 20211394Sswallace "flcmpd $rd, $rs1, $rs2", []>; 20311394Sswallace 20411394Sswallacedef FMEAN16 : VISInst<0b001000000, "fmean16">; 20511394Sswallace 20611394Sswallacedef FNADDS : F3_3<0b10, 0b110100, 0b001010001, 20711394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 20811394Sswallace "fnadds $rs1, $rs2, $rd", []>; 20911394Sswallacedef FNADDD : F3_3<0b10, 0b110100, 0b001010010, 21011394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 21111394Sswallace "fnaddd $rs1, $rs2, $rd", []>; 21211394Sswallacedef FNHADDS : F3_3<0b10, 0b110100, 0b001110001, 21311394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 21411394Sswallace "fnhadds $rs1, $rs2, $rd", []>; 21511394Sswallacedef FNHADDD : F3_3<0b10, 0b110100, 0b001110010, 21611394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 21711394Sswallace "fnhaddd $rs1, $rs2, $rd", []>; 21811394Sswallace 21911394Sswallacedef FNMULS : F3_3<0b10, 0b110100, 0b001011001, 22011394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 22111394Sswallace "fnhadds $rs1, $rs2, $rd", []>; 22211394Sswallacedef FNMULD : F3_3<0b10, 0b110100, 0b001011010, 22311394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 22411394Sswallace "fnhaddd $rs1, $rs2, $rd", []>; 22511394Sswallacedef FNSMULD : F3_3<0b10, 0b110100, 0b001111001, 22611394Sswallace (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 22711394Sswallace "fnhadds $rs1, $rs2, $rd", []>; 22811394Sswallace 22911394Sswallacedef FPADD64 : VISInst<0b001000010, "fpadd64">; 23011394Sswallace 23111394Sswallacedef FSLL16 : VISInst<0b000100001, "fsll16">; 23211394Sswallacedef FSRL16 : VISInst<0b000100011, "fsrl16">; 23311394Sswallacedef FSLL32 : VISInst<0b000100101, "fsll32">; 23411394Sswallacedef FSRL32 : VISInst<0b000100111, "fsrl32">; 23511394Sswallacedef FSLAS16 : VISInst<0b000101001, "fslas16">; 23611394Sswallacedef FSRA16 : VISInst<0b000101011, "fsra16">; 23711394Sswallacedef FSLAS32 : VISInst<0b000101101, "fslas32">; 23811394Sswallacedef FSRA32 : VISInst<0b000101111, "fsra32">; 23911394Sswallace 24011394Sswallacelet rs1 = 0 in 24111394Sswallacedef LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd), 24211394Sswallace (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>; 24311394Sswallace 24411394Sswallacelet rs1 = 0 in { 24511394Sswallacedef MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd), 24611394Sswallace (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>; 24711394Sswallacedef MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd), 24811394Sswallace (ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>; 24911394Sswallacedef MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd), 25011394Sswallace (ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>; 25111394Sswallacedef MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd), 25211394Sswallace (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>; 25312218Sbdedef MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd), 25411394Sswallace (ins I64Regs:$rs2), "movdtox $rs2, $rd", []>; 25511394Sswallace} 25611394Sswallace 25711394Sswallacedef PDISTN : VISInst<0b000111111, "pdistn">; 25812218Sbde 25911394Sswallacedef UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>; 26011394Sswallacedef XMULX : VISInst<0b100010101, "xmulx", I64Regs>; 26111394Sswallacedef XMULXHI : VISInst<0b100010111, "xmulxhi", I64Regs>; 26211394Sswallace} // Predicates = [IsVIS3] 26312218Sbde