SparcAsmPrinter.cpp revision 355940 
1//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format SPARC assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/SparcInstPrinter.h"
15#include "MCTargetDesc/SparcMCExpr.h"
16#include "MCTargetDesc/SparcTargetStreamer.h"
17#include "Sparc.h"
18#include "SparcInstrInfo.h"
19#include "SparcTargetMachine.h"
20#include "TargetInfo/SparcTargetInfo.h"
21#include "llvm/CodeGen/AsmPrinter.h"
22#include "llvm/CodeGen/MachineInstr.h"
23#include "llvm/CodeGen/MachineModuleInfoImpls.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26#include "llvm/IR/Mangler.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCContext.h"
29#include "llvm/MC/MCInst.h"
30#include "llvm/MC/MCStreamer.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Support/TargetRegistry.h"
33#include "llvm/Support/raw_ostream.h"
34using namespace llvm;
35
36#define DEBUG_TYPE "asm-printer"
37
38namespace {
39  class SparcAsmPrinter : public AsmPrinter {
40    SparcTargetStreamer &getTargetStreamer() {
41      return static_cast<SparcTargetStreamer &>(
42          *OutStreamer->getTargetStreamer());
43    }
44  public:
45    explicit SparcAsmPrinter(TargetMachine &TM,
46                             std::unique_ptr<MCStreamer> Streamer)
47        : AsmPrinter(TM, std::move(Streamer)) {}
48
49    StringRef getPassName() const override { return "Sparc Assembly Printer"; }
50
51    void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
52    void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
53                         const char *Modifier = nullptr);
54
55    void EmitFunctionBodyStart() override;
56    void EmitInstruction(const MachineInstr *MI) override;
57
58    static const char *getRegisterName(unsigned RegNo) {
59      return SparcInstPrinter::getRegisterName(RegNo);
60    }
61
62    bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
63                         const char *ExtraCode, raw_ostream &O) override;
64    bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
65                               const char *ExtraCode, raw_ostream &O) override;
66
67    void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
68                                   const MCSubtargetInfo &STI);
69
70  };
71} // end of anonymous namespace
72
73static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind,
74                                      MCSymbol *Sym, MCContext &OutContext) {
75  const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym,
76                                                         OutContext);
77  const SparcMCExpr *expr = SparcMCExpr::create(Kind, MCSym, OutContext);
78  return MCOperand::createExpr(expr);
79
80}
81static MCOperand createPCXCallOP(MCSymbol *Label,
82                                 MCContext &OutContext) {
83  return createSparcMCOperand(SparcMCExpr::VK_Sparc_None, Label, OutContext);
84}
85
86static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind,
87                                    MCSymbol *GOTLabel, MCSymbol *StartLabel,
88                                    MCSymbol *CurLabel,
89                                    MCContext &OutContext)
90{
91  const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
92  const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
93                                                         OutContext);
94  const MCSymbolRefExpr *Cur = MCSymbolRefExpr::create(CurLabel,
95                                                       OutContext);
96
97  const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
98  const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
99  const SparcMCExpr *expr = SparcMCExpr::create(Kind,
100                                                Add, OutContext);
101  return MCOperand::createExpr(expr);
102}
103
104static void EmitCall(MCStreamer &OutStreamer,
105                     MCOperand &Callee,
106                     const MCSubtargetInfo &STI)
107{
108  MCInst CallInst;
109  CallInst.setOpcode(SP::CALL);
110  CallInst.addOperand(Callee);
111  OutStreamer.EmitInstruction(CallInst, STI);
112}
113
114static void EmitSETHI(MCStreamer &OutStreamer,
115                      MCOperand &Imm, MCOperand &RD,
116                      const MCSubtargetInfo &STI)
117{
118  MCInst SETHIInst;
119  SETHIInst.setOpcode(SP::SETHIi);
120  SETHIInst.addOperand(RD);
121  SETHIInst.addOperand(Imm);
122  OutStreamer.EmitInstruction(SETHIInst, STI);
123}
124
125static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode,
126                       MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
127                       const MCSubtargetInfo &STI)
128{
129  MCInst Inst;
130  Inst.setOpcode(Opcode);
131  Inst.addOperand(RD);
132  Inst.addOperand(RS1);
133  Inst.addOperand(Src2);
134  OutStreamer.EmitInstruction(Inst, STI);
135}
136
137static void EmitOR(MCStreamer &OutStreamer,
138                   MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
139                   const MCSubtargetInfo &STI) {
140  EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
141}
142
143static void EmitADD(MCStreamer &OutStreamer,
144                    MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
145                    const MCSubtargetInfo &STI) {
146  EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
147}
148
149static void EmitSHL(MCStreamer &OutStreamer,
150                    MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
151                    const MCSubtargetInfo &STI) {
152  EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, STI);
153}
154
155
156static void EmitHiLo(MCStreamer &OutStreamer,  MCSymbol *GOTSym,
157                     SparcMCExpr::VariantKind HiKind,
158                     SparcMCExpr::VariantKind LoKind,
159                     MCOperand &RD,
160                     MCContext &OutContext,
161                     const MCSubtargetInfo &STI) {
162
163  MCOperand hi = createSparcMCOperand(HiKind, GOTSym, OutContext);
164  MCOperand lo = createSparcMCOperand(LoKind, GOTSym, OutContext);
165  EmitSETHI(OutStreamer, hi, RD, STI);
166  EmitOR(OutStreamer, RD, lo, RD, STI);
167}
168
169void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
170                                                const MCSubtargetInfo &STI)
171{
172  MCSymbol *GOTLabel   =
173    OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_"));
174
175  const MachineOperand &MO = MI->getOperand(0);
176  assert(MO.getReg() != SP::O7 &&
177         "%o7 is assigned as destination for getpcx!");
178
179  MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
180
181
182  if (!isPositionIndependent()) {
183    // Just load the address of GOT to MCRegOP.
184    switch(TM.getCodeModel()) {
185    default:
186      llvm_unreachable("Unsupported absolute code model");
187    case CodeModel::Small:
188      EmitHiLo(*OutStreamer, GOTLabel,
189               SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
190               MCRegOP, OutContext, STI);
191      break;
192    case CodeModel::Medium: {
193      EmitHiLo(*OutStreamer, GOTLabel,
194               SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44,
195               MCRegOP, OutContext, STI);
196      MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(12,
197                                                                   OutContext));
198      EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
199      MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44,
200                                          GOTLabel, OutContext);
201      EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI);
202      break;
203    }
204    case CodeModel::Large: {
205      EmitHiLo(*OutStreamer, GOTLabel,
206               SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM,
207               MCRegOP, OutContext, STI);
208      MCOperand imm = MCOperand::createExpr(MCConstantExpr::create(32,
209                                                                   OutContext));
210      EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI);
211      // Use register %o7 to load the lower 32 bits.
212      MCOperand RegO7 = MCOperand::createReg(SP::O7);
213      EmitHiLo(*OutStreamer, GOTLabel,
214               SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO,
215               RegO7, OutContext, STI);
216      EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
217    }
218    }
219    return;
220  }
221
222  MCSymbol *StartLabel = OutContext.createTempSymbol();
223  MCSymbol *EndLabel   = OutContext.createTempSymbol();
224  MCSymbol *SethiLabel = OutContext.createTempSymbol();
225
226  MCOperand RegO7   = MCOperand::createReg(SP::O7);
227
228  // <StartLabel>:
229  //   call <EndLabel>
230  // <SethiLabel>:
231  //     sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
232  // <EndLabel>:
233  //   or  <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
234  //   add <MO>, %o7, <MO>
235
236  OutStreamer->EmitLabel(StartLabel);
237  MCOperand Callee =  createPCXCallOP(EndLabel, OutContext);
238  EmitCall(*OutStreamer, Callee, STI);
239  OutStreamer->EmitLabel(SethiLabel);
240  MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22,
241                                       GOTLabel, StartLabel, SethiLabel,
242                                       OutContext);
243  EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
244  OutStreamer->EmitLabel(EndLabel);
245  MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10,
246                                       GOTLabel, StartLabel, EndLabel,
247                                       OutContext);
248  EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
249  EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
250}
251
252void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
253{
254
255  switch (MI->getOpcode()) {
256  default: break;
257  case TargetOpcode::DBG_VALUE:
258    // FIXME: Debug Value.
259    return;
260  case SP::GETPCX:
261    LowerGETPCXAndEmitMCInsts(MI, getSubtargetInfo());
262    return;
263  }
264  MachineBasicBlock::const_instr_iterator I = MI->getIterator();
265  MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
266  do {
267    MCInst TmpInst;
268    LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
269    EmitToStreamer(*OutStreamer, TmpInst);
270  } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
271}
272
273void SparcAsmPrinter::EmitFunctionBodyStart() {
274  if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
275    return;
276
277  const MachineRegisterInfo &MRI = MF->getRegInfo();
278  const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
279  for (unsigned i = 0; globalRegs[i] != 0; ++i) {
280    unsigned reg = globalRegs[i];
281    if (MRI.use_empty(reg))
282      continue;
283
284    if  (reg == SP::G6 || reg == SP::G7)
285      getTargetStreamer().emitSparcRegisterIgnore(reg);
286    else
287      getTargetStreamer().emitSparcRegisterScratch(reg);
288  }
289}
290
291void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
292                                   raw_ostream &O) {
293  const DataLayout &DL = getDataLayout();
294  const MachineOperand &MO = MI->getOperand (opNum);
295  SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
296
297#ifndef NDEBUG
298  // Verify the target flags.
299  if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
300    if (MI->getOpcode() == SP::CALL)
301      assert(TF == SparcMCExpr::VK_Sparc_None &&
302             "Cannot handle target flags on call address");
303    else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
304      assert((TF == SparcMCExpr::VK_Sparc_HI
305              || TF == SparcMCExpr::VK_Sparc_H44
306              || TF == SparcMCExpr::VK_Sparc_HH
307              || TF == SparcMCExpr::VK_Sparc_TLS_GD_HI22
308              || TF == SparcMCExpr::VK_Sparc_TLS_LDM_HI22
309              || TF == SparcMCExpr::VK_Sparc_TLS_LDO_HIX22
310              || TF == SparcMCExpr::VK_Sparc_TLS_IE_HI22
311              || TF == SparcMCExpr::VK_Sparc_TLS_LE_HIX22) &&
312             "Invalid target flags for address operand on sethi");
313    else if (MI->getOpcode() == SP::TLS_CALL)
314      assert((TF == SparcMCExpr::VK_Sparc_None
315              || TF == SparcMCExpr::VK_Sparc_TLS_GD_CALL
316              || TF == SparcMCExpr::VK_Sparc_TLS_LDM_CALL) &&
317             "Cannot handle target flags on tls call address");
318    else if (MI->getOpcode() == SP::TLS_ADDrr)
319      assert((TF == SparcMCExpr::VK_Sparc_TLS_GD_ADD
320              || TF == SparcMCExpr::VK_Sparc_TLS_LDM_ADD
321              || TF == SparcMCExpr::VK_Sparc_TLS_LDO_ADD
322              || TF == SparcMCExpr::VK_Sparc_TLS_IE_ADD) &&
323             "Cannot handle target flags on add for TLS");
324    else if (MI->getOpcode() == SP::TLS_LDrr)
325      assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LD &&
326             "Cannot handle target flags on ld for TLS");
327    else if (MI->getOpcode() == SP::TLS_LDXrr)
328      assert(TF == SparcMCExpr::VK_Sparc_TLS_IE_LDX &&
329             "Cannot handle target flags on ldx for TLS");
330    else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
331      assert((TF == SparcMCExpr::VK_Sparc_TLS_LDO_LOX10
332              || TF == SparcMCExpr::VK_Sparc_TLS_LE_LOX10) &&
333             "Cannot handle target flags on xor for TLS");
334    else
335      assert((TF == SparcMCExpr::VK_Sparc_LO
336              || TF == SparcMCExpr::VK_Sparc_M44
337              || TF == SparcMCExpr::VK_Sparc_L44
338              || TF == SparcMCExpr::VK_Sparc_HM
339              || TF == SparcMCExpr::VK_Sparc_TLS_GD_LO10
340              || TF == SparcMCExpr::VK_Sparc_TLS_LDM_LO10
341              || TF == SparcMCExpr::VK_Sparc_TLS_IE_LO10 ) &&
342             "Invalid target flags for small address operand");
343  }
344#endif
345
346
347  bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
348
349  switch (MO.getType()) {
350  case MachineOperand::MO_Register:
351    O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
352    break;
353
354  case MachineOperand::MO_Immediate:
355    O << (int)MO.getImm();
356    break;
357  case MachineOperand::MO_MachineBasicBlock:
358    MO.getMBB()->getSymbol()->print(O, MAI);
359    return;
360  case MachineOperand::MO_GlobalAddress:
361    PrintSymbolOperand(MO, O);
362    break;
363  case MachineOperand::MO_BlockAddress:
364    O <<  GetBlockAddressSymbol(MO.getBlockAddress())->getName();
365    break;
366  case MachineOperand::MO_ExternalSymbol:
367    O << MO.getSymbolName();
368    break;
369  case MachineOperand::MO_ConstantPoolIndex:
370    O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
371      << MO.getIndex();
372    break;
373  case MachineOperand::MO_Metadata:
374    MO.getMetadata()->printAsOperand(O, MMI->getModule());
375    break;
376  default:
377    llvm_unreachable("<unknown operand type>");
378  }
379  if (CloseParen) O << ")";
380}
381
382void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
383                                      raw_ostream &O, const char *Modifier) {
384  printOperand(MI, opNum, O);
385
386  // If this is an ADD operand, emit it like normal operands.
387  if (Modifier && !strcmp(Modifier, "arith")) {
388    O << ", ";
389    printOperand(MI, opNum+1, O);
390    return;
391  }
392
393  if (MI->getOperand(opNum+1).isReg() &&
394      MI->getOperand(opNum+1).getReg() == SP::G0)
395    return;   // don't print "+%g0"
396  if (MI->getOperand(opNum+1).isImm() &&
397      MI->getOperand(opNum+1).getImm() == 0)
398    return;   // don't print "+0"
399
400  O << "+";
401  printOperand(MI, opNum+1, O);
402}
403
404/// PrintAsmOperand - Print out an operand for an inline asm expression.
405///
406bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
407                                      const char *ExtraCode,
408                                      raw_ostream &O) {
409  if (ExtraCode && ExtraCode[0]) {
410    if (ExtraCode[1] != 0) return true; // Unknown modifier.
411
412    switch (ExtraCode[0]) {
413    default:
414      // See if this is a generic print operand
415      return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
416    case 'f':
417    case 'r':
418     break;
419    }
420  }
421
422  printOperand(MI, OpNo, O);
423
424  return false;
425}
426
427bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
428                                            unsigned OpNo,
429                                            const char *ExtraCode,
430                                            raw_ostream &O) {
431  if (ExtraCode && ExtraCode[0])
432    return true;  // Unknown modifier
433
434  O << '[';
435  printMemOperand(MI, OpNo, O);
436  O << ']';
437
438  return false;
439}
440
441// Force static initialization.
442extern "C" void LLVMInitializeSparcAsmPrinter() {
443  RegisterAsmPrinter<SparcAsmPrinter> X(getTheSparcTarget());
444  RegisterAsmPrinter<SparcAsmPrinter> Y(getTheSparcV9Target());
445  RegisterAsmPrinter<SparcAsmPrinter> Z(getTheSparcelTarget());
446}
447