1357937Sdim//==- RISCVSchedRocket64.td - Rocket Scheduling Definitions -*- tablegen -*-=// 2357937Sdim// 3357937Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4357937Sdim// See https://llvm.org/LICENSE.txt for license information. 5357937Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6357937Sdim// 7357937Sdim//===----------------------------------------------------------------------===// 8357937Sdim 9357937Sdim// ===---------------------------------------------------------------------===// 10357937Sdim// The following definitions describe the simpler per-operand machine model. 11357937Sdim// This works with MachineScheduler. See MCSchedule.h for details. 12357937Sdim 13357937Sdim// Rocket machine model for scheduling and other instruction cost heuristics. 14357937Sdimdef Rocket64Model : SchedMachineModel { 15357937Sdim let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order. 16357937Sdim let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. 17357937Sdim let LoadLatency = 3; 18357937Sdim let MispredictPenalty = 3; 19357937Sdim} 20357937Sdim 21357937Sdim//===----------------------------------------------------------------------===// 22357937Sdim// Define each kind of processor resource and number available. 23357937Sdim 24357937Sdim// Modeling each pipeline as a ProcResource using the BufferSize = 0 since 25357937Sdim// Rocket is in-order. 26357937Sdim 27357937Sdimlet BufferSize = 0 in { 28357937Sdimdef Rocket64UnitALU : ProcResource<1>; // Int ALU 29357937Sdimdef Rocket64UnitIMul : ProcResource<1>; // Int Multiply 30357937Sdimdef Rocket64UnitMem : ProcResource<1>; // Load/Store 31357937Sdimdef Rocket64UnitB : ProcResource<1>; // Branch 32357937Sdim 33357937Sdimdef Rocket64UnitFPALU : ProcResource<1>; // FP ALU 34357937Sdim} 35357937Sdim 36357937Sdimlet BufferSize = 1 in { 37357937Sdimdef Rocket64UnitIDiv : ProcResource<1>; // Int Division 38357937Sdimdef Rocket64UnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt 39357937Sdim} 40357937Sdim 41357937Sdim//===----------------------------------------------------------------------===// 42357937Sdim// Subtarget-specific SchedWrite types which both map the ProcResources and 43357937Sdim// set the latency. 44357937Sdim 45357937Sdimlet SchedModel = Rocket64Model in { 46357937Sdim 47357937Sdimdef : WriteRes<WriteJmp, [Rocket64UnitB]>; 48357937Sdimdef : WriteRes<WriteJal, [Rocket64UnitB]>; 49357937Sdimdef : WriteRes<WriteJalr, [Rocket64UnitB]>; 50357937Sdimdef : WriteRes<WriteJmpReg, [Rocket64UnitB]>; 51357937Sdim 52357937Sdimdef : WriteRes<WriteIALU32, [Rocket64UnitALU]>; 53357937Sdimdef : WriteRes<WriteIALU, [Rocket64UnitALU]>; 54357937Sdimdef : WriteRes<WriteShift32, [Rocket64UnitALU]>; 55357937Sdimdef : WriteRes<WriteShift, [Rocket64UnitALU]>; 56357937Sdim 57357937Sdimlet Latency = 4 in { 58357937Sdimdef : WriteRes<WriteIMul, [Rocket64UnitIMul]>; 59357937Sdimdef : WriteRes<WriteIMul32, [Rocket64UnitIMul]>; 60357937Sdim} 61357937Sdim 62357937Sdim// Integer divide varies based on operand magnitude and sign; worse case latency is 34. 63357937Sdimdef : WriteRes<WriteIDiv32, [Rocket64UnitIDiv]> { 64357937Sdim let Latency = 34; 65357937Sdim let ResourceCycles = [34]; 66357937Sdim} 67357937Sdimdef : WriteRes<WriteIDiv, [Rocket64UnitIDiv]> { 68357937Sdim let Latency = 33; 69357937Sdim let ResourceCycles = [33]; 70357937Sdim} 71357937Sdim 72357937Sdim// Memory 73357937Sdimdef : WriteRes<WriteSTB, [Rocket64UnitMem]>; 74357937Sdimdef : WriteRes<WriteSTH, [Rocket64UnitMem]>; 75357937Sdimdef : WriteRes<WriteSTW, [Rocket64UnitMem]>; 76357937Sdimdef : WriteRes<WriteSTD, [Rocket64UnitMem]>; 77357937Sdimdef : WriteRes<WriteFST32, [Rocket64UnitMem]>; 78357937Sdimdef : WriteRes<WriteFST64, [Rocket64UnitMem]>; 79357937Sdim 80357937Sdimlet Latency = 3 in { 81357937Sdimdef : WriteRes<WriteLDB, [Rocket64UnitMem]>; 82357937Sdimdef : WriteRes<WriteLDH, [Rocket64UnitMem]>; 83357937Sdimdef : WriteRes<WriteCSR, [Rocket64UnitALU]>; 84357937Sdim} 85357937Sdim 86357937Sdimlet Latency = 2 in { 87357937Sdimdef : WriteRes<WriteLDW, [Rocket64UnitMem]>; 88357937Sdimdef : WriteRes<WriteLDWU, [Rocket64UnitMem]>; 89357937Sdimdef : WriteRes<WriteLDD, [Rocket64UnitMem]>; 90357937Sdimdef : WriteRes<WriteFLD32, [Rocket64UnitMem]>; 91357937Sdimdef : WriteRes<WriteFLD64, [Rocket64UnitMem]>; 92357937Sdim 93357937Sdimdef : WriteRes<WriteAtomicW, [Rocket64UnitMem]>; 94357937Sdimdef : WriteRes<WriteAtomicD, [Rocket64UnitMem]>; 95357937Sdim 96357937Sdimdef : WriteRes<WriteAtomicLDW, [Rocket64UnitMem]>; 97357937Sdimdef : WriteRes<WriteAtomicLDD, [Rocket64UnitMem]>; 98357937Sdim} 99357937Sdim 100357937Sdimdef : WriteRes<WriteAtomicSTW, [Rocket64UnitMem]>; 101357937Sdimdef : WriteRes<WriteAtomicSTD, [Rocket64UnitMem]>; 102357937Sdim 103357937Sdim// Most FP single precision operations are 4 cycles 104357937Sdimdef : WriteRes<WriteFALU32, [Rocket64UnitFPALU]> { let Latency = 4; } 105357937Sdim 106357937Sdim// Most FP double precision operations are 6 cycles 107357937Sdimdef : WriteRes<WriteFALU64, [Rocket64UnitFPALU]> { let Latency = 6; } 108357937Sdim 109357937Sdim// Conversion instructions 110357937Sdimlet Latency = 2 in { 111357937Sdimdef : WriteRes<WriteFCvtI32ToF32, [Rocket32UnitFPALU]>; 112357937Sdimdef : WriteRes<WriteFCvtI32ToF64, [Rocket32UnitFPALU]>; 113357937Sdimdef : WriteRes<WriteFCvtI64ToF32, [Rocket32UnitFPALU]>; 114357937Sdimdef : WriteRes<WriteFCvtI64ToF64, [Rocket32UnitFPALU]>; 115357937Sdimdef : WriteRes<WriteFCvtF32ToI32, [Rocket32UnitFPALU]>; 116357937Sdimdef : WriteRes<WriteFCvtF32ToI64, [Rocket32UnitFPALU]>; 117357937Sdimdef : WriteRes<WriteFCvtF64ToI32, [Rocket32UnitFPALU]>; 118357937Sdimdef : WriteRes<WriteFCvtF64ToI64, [Rocket32UnitFPALU]>; 119357937Sdimdef : WriteRes<WriteFCvtF32ToF64, [Rocket32UnitFPALU]>; 120357937Sdimdef : WriteRes<WriteFCvtF64ToF32, [Rocket32UnitFPALU]>; 121357937Sdim 122357937Sdimdef : WriteRes<WriteFClass32, [Rocket64UnitFPALU]>; 123357937Sdimdef : WriteRes<WriteFClass64, [Rocket64UnitFPALU]>; 124357937Sdimdef : WriteRes<WriteFCmp32, [Rocket64UnitFPALU]>; 125357937Sdimdef : WriteRes<WriteFCmp64, [Rocket64UnitFPALU]>; 126357937Sdimdef : WriteRes<WriteFMovF32ToI32, [Rocket64UnitFPALU]>; 127357937Sdimdef : WriteRes<WriteFMovI32ToF32, [Rocket64UnitFPALU]>; 128357937Sdimdef : WriteRes<WriteFMovF64ToI64, [Rocket64UnitFPALU]>; 129357937Sdimdef : WriteRes<WriteFMovI64ToF64, [Rocket64UnitFPALU]>; 130357937Sdim} 131357937Sdim 132357937Sdimlet Latency = 5 in { 133357937Sdimdef : WriteRes<WriteFMul32, [Rocket64UnitFPALU]>; 134357937Sdimdef : WriteRes<WriteFMulAdd32, [Rocket64UnitFPALU]>; 135357937Sdimdef : WriteRes<WriteFMulSub32, [Rocket64UnitFPALU]>; 136357937Sdim} 137357937Sdim 138357937Sdimlet Latency = 7 in { 139357937Sdimdef : WriteRes<WriteFMul64, [Rocket64UnitFPALU]>; 140357937Sdimdef : WriteRes<WriteFMulAdd64, [Rocket64UnitFPALU]>; 141357937Sdimdef : WriteRes<WriteFMulSub64, [Rocket64UnitFPALU]>; 142357937Sdim} 143357937Sdim 144357937Sdim// FP Divide unit on Rocket is not pipelined, so set resource cycles to latency 145357937Sdimlet Latency = 20, ResourceCycles = [20] in { 146357937Sdimdef : WriteRes<WriteFDiv32, [Rocket64UnitFPDivSqrt]>; 147357937Sdimdef : WriteRes<WriteFDiv64, [Rocket64UnitFPDivSqrt]>; 148357937Sdim} 149357937Sdim 150357937Sdim// FP Sqrt unit on Rocket is not pipelined, so set resource cycles to latency 151357937Sdimdef : WriteRes<WriteFSqrt32, [Rocket64UnitFPDivSqrt]> { let Latency = 20; 152357937Sdim let ResourceCycles = [20]; } 153357937Sdimdef : WriteRes<WriteFSqrt64, [Rocket64UnitFPDivSqrt]> { let Latency = 25; 154357937Sdim let ResourceCycles = [25]; } 155357937Sdim 156357937Sdimdef : WriteRes<WriteNop, []>; 157357937Sdim 158357937Sdimdef : InstRW<[WriteIALU], (instrs COPY)>; 159357937Sdim 160357937Sdim//===----------------------------------------------------------------------===// 161357937Sdim// Subtarget-specific SchedRead types with cycles. 162357937Sdim// Dummy definitions for RocketCore. 163357937Sdimdef : ReadAdvance<ReadJmp, 0>; 164357937Sdimdef : ReadAdvance<ReadJalr, 0>; 165357937Sdimdef : ReadAdvance<ReadCSR, 0>; 166357937Sdimdef : ReadAdvance<ReadStoreData, 0>; 167357937Sdimdef : ReadAdvance<ReadMemBase, 0>; 168357937Sdimdef : ReadAdvance<ReadIALU, 0>; 169357937Sdimdef : ReadAdvance<ReadIALU32, 0>; 170357937Sdimdef : ReadAdvance<ReadShift, 0>; 171357937Sdimdef : ReadAdvance<ReadShift32, 0>; 172357937Sdimdef : ReadAdvance<ReadIDiv, 0>; 173357937Sdimdef : ReadAdvance<ReadIDiv32, 0>; 174357937Sdimdef : ReadAdvance<ReadIMul, 0>; 175357937Sdimdef : ReadAdvance<ReadIMul32, 0>; 176357937Sdimdef : ReadAdvance<ReadAtomicWA, 0>; 177357937Sdimdef : ReadAdvance<ReadAtomicWD, 0>; 178357937Sdimdef : ReadAdvance<ReadAtomicDA, 0>; 179357937Sdimdef : ReadAdvance<ReadAtomicDD, 0>; 180357937Sdimdef : ReadAdvance<ReadAtomicLDW, 0>; 181357937Sdimdef : ReadAdvance<ReadAtomicLDD, 0>; 182357937Sdimdef : ReadAdvance<ReadAtomicSTW, 0>; 183357937Sdimdef : ReadAdvance<ReadAtomicSTD, 0>; 184357937Sdimdef : ReadAdvance<ReadFALU32, 0>; 185357937Sdimdef : ReadAdvance<ReadFALU64, 0>; 186357937Sdimdef : ReadAdvance<ReadFMul32, 0>; 187357937Sdimdef : ReadAdvance<ReadFMulAdd32, 0>; 188357937Sdimdef : ReadAdvance<ReadFMulSub32, 0>; 189357937Sdimdef : ReadAdvance<ReadFMul64, 0>; 190357937Sdimdef : ReadAdvance<ReadFMulAdd64, 0>; 191357937Sdimdef : ReadAdvance<ReadFMulSub64, 0>; 192357937Sdimdef : ReadAdvance<ReadFDiv32, 0>; 193357937Sdimdef : ReadAdvance<ReadFDiv64, 0>; 194357937Sdimdef : ReadAdvance<ReadFSqrt32, 0>; 195357937Sdimdef : ReadAdvance<ReadFSqrt64, 0>; 196357937Sdimdef : ReadAdvance<ReadFCmp32, 0>; 197357937Sdimdef : ReadAdvance<ReadFCmp64, 0>; 198357937Sdimdef : ReadAdvance<ReadFCvtF32ToI32, 0>; 199357937Sdimdef : ReadAdvance<ReadFCvtF32ToI64, 0>; 200357937Sdimdef : ReadAdvance<ReadFCvtF64ToI32, 0>; 201357937Sdimdef : ReadAdvance<ReadFCvtF64ToI64, 0>; 202357937Sdimdef : ReadAdvance<ReadFCvtI32ToF32, 0>; 203357937Sdimdef : ReadAdvance<ReadFCvtI32ToF64, 0>; 204357937Sdimdef : ReadAdvance<ReadFCvtI64ToF32, 0>; 205357937Sdimdef : ReadAdvance<ReadFCvtI64ToF64, 0>; 206357937Sdimdef : ReadAdvance<ReadFCvtF32ToF64, 0>; 207357937Sdimdef : ReadAdvance<ReadFCvtF64ToF32, 0>; 208357937Sdimdef : ReadAdvance<ReadFMovF32ToI32, 0>; 209357937Sdimdef : ReadAdvance<ReadFMovI32ToF32, 0>; 210357937Sdimdef : ReadAdvance<ReadFMovF64ToI64, 0>; 211357937Sdimdef : ReadAdvance<ReadFMovI64ToF64, 0>; 212357937Sdimdef : ReadAdvance<ReadFClass32, 0>; 213357937Sdimdef : ReadAdvance<ReadFClass64, 0>; 214357937Sdim} 215