1277323Sdim//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===// 2277323Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6277323Sdim// 7277323Sdim//===----------------------------------------------------------------------===// 8277323Sdim// 9277323Sdim// This file defines the itinerary class data for the POWER8 processor. 10277323Sdim// 11277323Sdim//===----------------------------------------------------------------------===// 12277323Sdim 13277323Sdim// Scheduling for the P8 involves tracking two types of resources: 14277323Sdim// 1. The dispatch bundle slots 15277323Sdim// 2. The functional unit resources 16277323Sdim 17277323Sdim// Dispatch units: 18277323Sdimdef P8_DU1 : FuncUnit; 19277323Sdimdef P8_DU2 : FuncUnit; 20277323Sdimdef P8_DU3 : FuncUnit; 21277323Sdimdef P8_DU4 : FuncUnit; 22277323Sdimdef P8_DU5 : FuncUnit; 23277323Sdimdef P8_DU6 : FuncUnit; 24277323Sdimdef P8_DU7 : FuncUnit; // Only branch instructions will use DU7,DU8 25277323Sdimdef P8_DU8 : FuncUnit; 26277323Sdim 27277323Sdim// 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU). 28277323Sdim 29277323Sdimdef P8_LU1 : FuncUnit; // Loads or fixed-point operations 1 30277323Sdimdef P8_LU2 : FuncUnit; // Loads or fixed-point operations 2 31277323Sdim 32277323Sdim// Load/Store pipelines can handle Stores, fixed-point loads, and simple 33277323Sdim// fixed-point operations. 34277323Sdimdef P8_LSU1 : FuncUnit; // Load/Store pipeline 1 35277323Sdimdef P8_LSU2 : FuncUnit; // Load/Store pipeline 2 36277323Sdim 37277323Sdim// Fixed Point unit 38277323Sdimdef P8_FXU1 : FuncUnit; // FX pipeline 1 39277323Sdimdef P8_FXU2 : FuncUnit; // FX pipeline 2 40277323Sdim 41277323Sdim// The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units 42277323Sdim// are combined on P7 and newer into a Vector Scalar Unit (VSU). 43277323Sdim// The P8 Instruction latency documents still refers to the unit as the 44277323Sdim// FPU, so keep in mind that FPU==VSU. 45277323Sdim// In contrast to the P7, the VMX units on P8 are symmetric, so no need to 46277323Sdim// split vector integer ops or 128-bit load/store/perms to the specific units. 47277323Sdimdef P8_FPU1 : FuncUnit; // VS pipeline 1 48277323Sdimdef P8_FPU2 : FuncUnit; // VS pipeline 2 49277323Sdim 50277323Sdimdef P8_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs) 51277323Sdimdef P8_BRU : FuncUnit; // BR unit 52277323Sdim 53277323Sdimdef P8Itineraries : ProcessorItineraries< 54277323Sdim [P8_DU1, P8_DU2, P8_DU3, P8_DU4, P8_DU5, P8_DU6, P8_DU7, P8_DU8, 55277323Sdim P8_LU1, P8_LU2, P8_LSU1, P8_LSU2, P8_FXU1, P8_FXU2, 56277323Sdim P8_FPU1, P8_FPU2, P8_CRU, P8_BRU], [], [ 57277323Sdim InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 58277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 59277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2, 60277323Sdim P8_LU1, P8_LU2, 61277323Sdim P8_LSU1, P8_LSU2]>], 62277323Sdim [1, 1, 1]>, 63277323Sdim InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 64277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 65277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1, 66277323Sdim P8_LU2, P8_LSU1, P8_LSU2]>], 67277323Sdim [1, 1, 1]>, 68288943Sdim InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>, 69288943Sdim InstrStage<1, [P8_FXU1, P8_FXU2], 0>, 70288943Sdim InstrStage<1, [P8_BRU]>], 71288943Sdim [1, 1, 1, 1]>, 72277323Sdim InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 73277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 74277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 75277323Sdim [1, 1, 1]>, 76277323Sdim InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 77277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 78277323Sdim InstrStage<15, [P8_FXU1, P8_FXU2]>], 79277323Sdim [15, 1, 1]>, 80277323Sdim InstrItinData<IIC_IntDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 81277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 82277323Sdim InstrStage<23, [P8_FXU1, P8_FXU2]>], 83277323Sdim [23, 1, 1]>, 84277323Sdim InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 85277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 86277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 87277323Sdim [4, 1, 1]>, 88277323Sdim InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 89277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 90277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 91277323Sdim [4, 1, 1]>, 92344779Sdim InstrItinData<IIC_IntMulHD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 93344779Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 94344779Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 95344779Sdim [4, 1, 1]>, 96277323Sdim InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 97277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 98277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 99277323Sdim [4, 1, 1]>, 100277323Sdim InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 101277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 102277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 103277323Sdim [1, 1, 1]>, 104277323Sdim InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 105277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 106277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 107277323Sdim [1, 1, 1]>, 108344779Sdim InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 109344779Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 110344779Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 111344779Sdim [1, 1, 1]>, 112277323Sdim InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 113277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 114277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 115277323Sdim [1, 1, 1]>, 116277323Sdim InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 117277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 118277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 119277323Sdim [1, 1]>, 120277323Sdim InstrItinData<IIC_IntTrapD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 121277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 122277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 123277323Sdim [1, 1]>, 124277323Sdim InstrItinData<IIC_BrB , [InstrStage<1, [P8_DU7, P8_DU8], 0>, 125277323Sdim InstrStage<1, [P8_BRU]>], 126277323Sdim [3, 1, 1]>, 127277323Sdim // FIXME - the Br* groups below are not branch related, so should probably 128277323Sdim // be renamed. 129277323Sdim // IIC_BrCR consists of the cr* instructions. (crand,crnor,creqv, etc). 130277323Sdim // and should be 'First' in dispatch. 131277323Sdim InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>, 132277323Sdim InstrStage<1, [P8_CRU]>], 133277323Sdim [3, 1, 1]>, 134277323Sdim // IIC_BrMCR consists of the mcrf instruction. 135277323Sdim InstrItinData<IIC_BrMCR , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 136277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 137277323Sdim InstrStage<1, [P8_CRU]>], 138277323Sdim [3, 1, 1]>, 139277323Sdim // IIC_BrMCRX consists of mcrxr (obsolete instruction) and mtcrf, which 140277323Sdim // should be first in the dispatch group. 141277323Sdim InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>, 142277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 143277323Sdim [3, 1, 1]>, 144277323Sdim InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>, 145277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 146277323Sdim [3, 1]>, 147277323Sdim InstrItinData<IIC_LdStLoad , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 148277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 149277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 150277323Sdim P8_LU1, P8_LU2]>], 151277323Sdim [2, 1, 1]>, 152277323Sdim InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>, 153277323Sdim InstrStage<1, [P8_DU2], 0>, 154277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 155277323Sdim P8_LU1, P8_LU2 ], 0>, 156277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 157277323Sdim [2, 2, 1, 1]>, 158277323Sdim // Update-Indexed form loads/stores are no longer first and last in the 159277323Sdim // dispatch group. They are simply cracked, so require DU1,DU2. 160277323Sdim InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P8_DU1], 0>, 161277323Sdim InstrStage<1, [P8_DU2], 0>, 162277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 163277323Sdim P8_LU1, P8_LU2], 0>, 164277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 165277323Sdim [3, 3, 1, 1]>, 166277323Sdim InstrItinData<IIC_LdStLD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 167277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 168277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 169277323Sdim P8_LU1, P8_LU2]>], 170277323Sdim [2, 1, 1]>, 171277323Sdim InstrItinData<IIC_LdStLDU , [InstrStage<1, [P8_DU1], 0>, 172277323Sdim InstrStage<1, [P8_DU2], 0>, 173277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 174277323Sdim P8_LU1, P8_LU2], 0>, 175277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 176277323Sdim [2, 2, 1, 1]>, 177277323Sdim InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P8_DU1], 0>, 178277323Sdim InstrStage<1, [P8_DU2], 0>, 179277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 180277323Sdim P8_LU1, P8_LU2], 0>, 181277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 182277323Sdim [3, 3, 1, 1]>, 183277323Sdim InstrItinData<IIC_LdStLFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 184277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 185277323Sdim InstrStage<1, [P8_LU1, P8_LU2]>], 186277323Sdim [3, 1, 1]>, 187277323Sdim InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 188277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 189277323Sdim InstrStage<1, [P8_LU1, P8_LU2]>], 190277323Sdim [3, 1, 1]>, 191277323Sdim InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P8_DU1], 0>, 192277323Sdim InstrStage<1, [P8_DU2], 0>, 193277323Sdim InstrStage<1, [P8_LU1, P8_LU2], 0>, 194277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 195277323Sdim [3, 3, 1, 1]>, 196277323Sdim InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P8_DU1], 0>, 197277323Sdim InstrStage<1, [P8_DU2], 0>, 198277323Sdim InstrStage<1, [P8_LU1, P8_LU2], 0>, 199277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 200277323Sdim [3, 3, 1, 1]>, 201277323Sdim InstrItinData<IIC_LdStLHA , [InstrStage<1, [P8_DU1], 0>, 202277323Sdim InstrStage<1, [P8_DU2], 0>, 203277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 204277323Sdim P8_LU1, P8_LU2], 0>, 205277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2, 206277323Sdim P8_LU1, P8_LU2]>], 207277323Sdim [3, 1, 1]>, 208277323Sdim InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P8_DU1], 0>, 209277323Sdim InstrStage<1, [P8_DU2], 0>, 210277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 211277323Sdim P8_LU1, P8_LU2], 0>, 212277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>, 213277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 214277323Sdim [4, 4, 1, 1]>, 215277323Sdim // first+last in dispatch group. 216277323Sdim InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P8_DU1], 0>, 217277323Sdim InstrStage<1, [P8_DU2], 0>, 218277323Sdim InstrStage<1, [P8_DU3], 0>, 219277323Sdim InstrStage<1, [P8_DU4], 0>, 220277323Sdim InstrStage<1, [P8_DU5], 0>, 221277323Sdim InstrStage<1, [P8_DU6], 0>, 222277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 223277323Sdim P8_LU1, P8_LU2], 0>, 224277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>, 225277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 226277323Sdim [4, 4, 1, 1]>, 227277323Sdim InstrItinData<IIC_LdStLWA , [InstrStage<1, [P8_DU1], 0>, 228277323Sdim InstrStage<1, [P8_DU2], 0>, 229277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 230277323Sdim P8_LU1, P8_LU2]>, 231277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 232277323Sdim [3, 1, 1]>, 233277323Sdim InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P8_DU1], 0>, 234277323Sdim InstrStage<1, [P8_DU2], 0>, 235277323Sdim InstrStage<1, [P8_DU3], 0>, 236277323Sdim InstrStage<1, [P8_DU4], 0>, 237277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 238277323Sdim P8_LU1, P8_LU2]>], 239277323Sdim [3, 1, 1]>, 240277323Sdim // first+last 241277323Sdim InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P8_DU1], 0>, 242277323Sdim InstrStage<1, [P8_DU2], 0>, 243277323Sdim InstrStage<1, [P8_DU3], 0>, 244277323Sdim InstrStage<1, [P8_DU4], 0>, 245277323Sdim InstrStage<1, [P8_DU5], 0>, 246277323Sdim InstrStage<1, [P8_DU6], 0>, 247277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 248277323Sdim P8_LU1, P8_LU2]>], 249277323Sdim [3, 1, 1]>, 250277323Sdim InstrItinData<IIC_LdStLMW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 251277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 252277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2, 253277323Sdim P8_LU1, P8_LU2]>], 254277323Sdim [2, 1, 1]>, 255277323Sdim// Stores are dual-issued from the issue queue, so may only take up one 256277323Sdim// dispatch slot. The instruction will be broken into two IOPS. The agen 257277323Sdim// op is issued to the LSU, and the data op (register fetch) is issued 258277323Sdim// to either the LU (GPR store) or the VSU (FPR store). 259277323Sdim InstrItinData<IIC_LdStStore , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 260277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 261277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2]>, 262277323Sdim InstrStage<1, [P8_LU1, P8_LU2]>], 263277323Sdim [1, 1, 1]>, 264277323Sdim InstrItinData<IIC_LdStSTD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 265277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 266277323Sdim InstrStage<1, [P8_LU1, P8_LU2, 267277323Sdim P8_LSU1, P8_LSU2]>] 268277323Sdim [1, 1, 1]>, 269344779Sdim InstrItinData<IIC_LdStSTU , [InstrStage<1, [P8_DU1], 0>, 270277323Sdim InstrStage<1, [P8_DU2], 0>, 271277323Sdim InstrStage<1, [P8_LU1, P8_LU2, 272277323Sdim P8_LSU1, P8_LSU2], 0>, 273277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 274277323Sdim [2, 1, 1, 1]>, 275277323Sdim // First+last 276344779Sdim InstrItinData<IIC_LdStSTUX , [InstrStage<1, [P8_DU1], 0>, 277277323Sdim InstrStage<1, [P8_DU2], 0>, 278277323Sdim InstrStage<1, [P8_DU3], 0>, 279277323Sdim InstrStage<1, [P8_DU4], 0>, 280277323Sdim InstrStage<1, [P8_DU5], 0>, 281277323Sdim InstrStage<1, [P8_DU6], 0>, 282277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2], 0>, 283277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>, 284277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 285277323Sdim [2, 1, 1, 1]>, 286277323Sdim InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 287277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 288277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2], 0>, 289277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 290277323Sdim [1, 1, 1]>, 291277323Sdim InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P8_DU1], 0>, 292277323Sdim InstrStage<1, [P8_DU2], 0>, 293277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2], 0>, 294277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2], 0>, 295277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 296277323Sdim [2, 1, 1, 1]>, 297277323Sdim InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 298277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 299277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2], 0>, 300277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 301277323Sdim [1, 1, 1]>, 302277323Sdim InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P8_DU1], 0>, 303277323Sdim InstrStage<1, [P8_DU2], 0>, 304277323Sdim InstrStage<1, [P8_DU3], 0>, 305277323Sdim InstrStage<1, [P8_DU4], 0>, 306277323Sdim InstrStage<1, [P8_DU5], 0>, 307277323Sdim InstrStage<1, [P8_DU6], 0>, 308277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2], 0>, 309277323Sdim InstrStage<1, [P8_LU1, P8_LU2]>], 310277323Sdim [1, 1, 1]>, 311277323Sdim InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P8_DU1], 0>, 312277323Sdim InstrStage<1, [P8_DU2], 0>, 313277323Sdim InstrStage<1, [P8_DU3], 0>, 314277323Sdim InstrStage<1, [P8_DU4], 0>, 315277323Sdim InstrStage<1, [P8_DU5], 0>, 316277323Sdim InstrStage<1, [P8_DU6], 0>, 317277323Sdim InstrStage<1, [P8_LSU1, P8_LSU2], 0>, 318277323Sdim InstrStage<1, [P8_LU1, P8_LU2]>], 319277323Sdim [1, 1, 1]>, 320277323Sdim InstrItinData<IIC_SprMFCR , [InstrStage<1, [P8_DU1], 0>, 321277323Sdim InstrStage<1, [P8_CRU]>], 322277323Sdim [6, 1]>, 323277323Sdim InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P8_DU1], 0>, 324277323Sdim InstrStage<1, [P8_CRU]>], 325277323Sdim [3, 1]>, 326277323Sdim InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P8_DU1], 0>, 327277323Sdim InstrStage<1, [P8_FXU1, P8_FXU2]>], 328277323Sdim [4, 1]>, // mtctr 329277323Sdim InstrItinData<IIC_FPGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 330277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 331277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 332277323Sdim [5, 1, 1]>, 333288943Sdim InstrItinData<IIC_FPAddSub , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 334288943Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 335288943Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 336288943Sdim [5, 1, 1]>, 337277323Sdim InstrItinData<IIC_FPCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 338277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 339277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 340277323Sdim [8, 1, 1]>, 341277323Sdim InstrItinData<IIC_FPDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 342277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 343277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 344277323Sdim [33, 1, 1]>, 345277323Sdim InstrItinData<IIC_FPDivS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 346277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 347277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 348277323Sdim [27, 1, 1]>, 349277323Sdim InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 350277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 351277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 352277323Sdim [44, 1, 1]>, 353277323Sdim InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 354277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 355277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 356277323Sdim [32, 1, 1]>, 357277323Sdim InstrItinData<IIC_FPFused , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 358277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 359277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 360277323Sdim [5, 1, 1, 1]>, 361277323Sdim InstrItinData<IIC_FPRes , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 362277323Sdim P8_DU4, P8_DU5, P8_DU6], 0>, 363277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 364277323Sdim [5, 1, 1]>, 365277323Sdim InstrItinData<IIC_VecGeneral , [InstrStage<1, [P8_DU1], 0>, 366277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 367277323Sdim [2, 1, 1]>, 368277323Sdim InstrItinData<IIC_VecVSL , [InstrStage<1, [P8_DU1], 0>, 369277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 370277323Sdim [2, 1, 1]>, 371277323Sdim InstrItinData<IIC_VecVSR , [InstrStage<1, [P8_DU1], 0>, 372277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 373277323Sdim [2, 1, 1]>, 374277323Sdim InstrItinData<IIC_VecFP , [InstrStage<1, [P8_DU1], 0>, 375277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 376277323Sdim [6, 1, 1]>, 377277323Sdim InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P8_DU1], 0>, 378277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 379277323Sdim [6, 1, 1]>, 380277323Sdim InstrItinData<IIC_VecFPRound , [InstrStage<1, [P8_DU1], 0>, 381277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 382277323Sdim [6, 1, 1]>, 383277323Sdim InstrItinData<IIC_VecComplex , [InstrStage<1, [P8_DU1], 0>, 384277323Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 385277323Sdim [7, 1, 1]>, 386277323Sdim InstrItinData<IIC_VecPerm , [InstrStage<1, [P8_DU1, P8_DU2], 0>, 387321369Sdim InstrStage<1, [P8_FPU1, P8_FPU2]>], 388277323Sdim [3, 1, 1]> 389277323Sdim]>; 390277323Sdim 391277323Sdim// ===---------------------------------------------------------------------===// 392277323Sdim// P8 machine model for scheduling and other instruction cost heuristics. 393277323Sdim// P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up 394277323Sdim// to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU). 395277323Sdim 396277323Sdimdef P8Model : SchedMachineModel { 397277323Sdim let IssueWidth = 8; // up to 8 instructions dispatched per cycle. 398277323Sdim // up to six non-branch instructions. 399277323Sdim // up to two branches in a dispatch group. 400277323Sdim 401277323Sdim let LoadLatency = 3; // Optimistic load latency assuming bypass. 402277323Sdim // This is overriden by OperandCycles if the 403277323Sdim // Itineraries are queried instead. 404277323Sdim let MispredictPenalty = 16; 405277323Sdim 406277323Sdim // Try to make sure we have at least 10 dispatch groups in a loop. 407277323Sdim let LoopMicroOpBufferSize = 60; 408277323Sdim 409309124Sdim let CompleteModel = 0; 410309124Sdim 411277323Sdim let Itineraries = P8Itineraries; 412277323Sdim} 413277323Sdim 414