PPC.td revision 363496
1132718Skan//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2132718Skan// 3169689Skan// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4169689Skan// See https://llvm.org/LICENSE.txt for license information. 5132718Skan// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6132718Skan// 7132718Skan//===----------------------------------------------------------------------===// 8132718Skan// 9132718Skan// This is the top level entry point for the PowerPC target. 10132718Skan// 11132718Skan//===----------------------------------------------------------------------===// 12132718Skan 13132718Skan// Get the target-independent interfaces which we are implementing. 14132718Skan// 15132718Skaninclude "llvm/Target/Target.td" 16132718Skan 17132718Skan//===----------------------------------------------------------------------===// 18132718Skan// PowerPC Subtarget features. 19132718Skan// 20169689Skan 21169689Skan//===----------------------------------------------------------------------===// 22132718Skan// CPU Directives // 23132718Skan//===----------------------------------------------------------------------===// 24132718Skan 25132718Skandef Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26132718Skandef Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27132718Skandef Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28132718Skandef Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29132718Skandef Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30132718Skandef Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31132718Skandef Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32132718Skandef Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33132718Skandef Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34132718Skandef Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35132718Skandef Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36132718Skandef DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37132718Skandef DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38132718Skan "PPC::DIR_E500", "">; 39132718Skandef DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40132718Skan "PPC::DIR_E500mc", "">; 41132718Skandef DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42132718Skan "PPC::DIR_E5500", "">; 43132718Skandef DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44132718Skandef DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45132718Skandef DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46132718Skandef DirectivePwr5x 47132718Skan : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48132718Skandef DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49132718Skandef DirectivePwr6x 50132718Skan : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51132718Skandef DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52132718Skandef DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53132718Skandef DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54132718Skandef DirectivePwrFuture 55169689Skan : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 56132718Skan 57132718Skandef Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 58132718Skan "Enable 64-bit instructions">; 59132718Skandef FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 60169689Skan "Enable floating-point instructions">; 61169689Skandef Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 62132718Skan "Enable 64-bit registers usage for ppc32 [beta]">; 63132718Skandef FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 64169689Skan "Use condition-register bits individually">; 65169689Skandef FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 66132718Skan "Enable classic FPU instructions", 67132718Skan [FeatureHardFloat]>; 68132718Skandef FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 69169689Skan "Enable Altivec instructions", 70132718Skan [FeatureFPU]>; 71132718Skandef FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 72132718Skan "Enable SPE instructions", 73132718Skan [FeatureHardFloat]>; 74132718Skandef FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 75132718Skan "Enable the MFOCRF instruction">; 76132718Skandef FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 77132718Skan "Enable the fsqrt instruction", 78132718Skan [FeatureFPU]>; 79132718Skandef FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 80132718Skan "Enable the fcpsgn instruction", 81132718Skan [FeatureFPU]>; 82132718Skandef FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 83132718Skan "Enable the fre instruction", 84132718Skan [FeatureFPU]>; 85169689Skandef FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 86169689Skan "Enable the fres instruction", 87169689Skan [FeatureFPU]>; 88132718Skandef FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 89169689Skan "Enable the frsqrte instruction", 90132718Skan [FeatureFPU]>; 91132718Skandef FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 92132718Skan "Enable the frsqrtes instruction", 93132718Skan [FeatureFPU]>; 94132718Skandef FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 95169689Skan "Assume higher precision reciprocal estimates">; 96132718Skandef FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 97169689Skan "Enable the stfiwx instruction", 98132718Skan [FeatureFPU]>; 99132718Skandef FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 100132718Skan "Enable the lfiwax instruction", 101169689Skan [FeatureFPU]>; 102169689Skandef FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 103132718Skan "Enable the fri[mnpz] instructions", 104169689Skan [FeatureFPU]>; 105169689Skandef FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 106169689Skan "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 107169689Skan [FeatureFPU]>; 108132718Skandef FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 109132718Skan "Enable the isel instruction">; 110132718Skandef FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 111169689Skan "Enable the bpermd instruction">; 112169689Skandef FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 113169689Skan "Enable extended divide instructions">; 114132718Skandef FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 115169689Skan "Enable the ldbrx instruction">; 116169689Skandef FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 117169689Skan "Enable the cmpb instruction">; 118169689Skandef FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 119169689Skan "Enable icbt instruction">; 120169689Skandef FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 121169689Skan "Enable Book E instructions", 122169689Skan [FeatureICBT]>; 123169689Skandef FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 124169689Skan "Has only the msync instruction instead of sync", 125169689Skan [FeatureBookE]>; 126169689Skandef FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 127169689Skan "Enable E500/E500mc instructions">; 128132718Skandef FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 129132718Skan "Enable secure plt mode">; 130132718Skandef FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 131132718Skan "Enable PPC 4xx instructions">; 132132718Skandef FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 133132718Skan "Enable PPC 6xx instructions">; 134132718Skandef FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 135169689Skan "Enable QPX instructions", 136169689Skan [FeatureFPU]>; 137169689Skandef FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 138169689Skan "Enable VSX instructions", 139169689Skan [FeatureAltivec]>; 140132718Skandef FeatureTwoConstNR : 141132718Skan SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 142132718Skan "Requires two constant Newton-Raphson computation">; 143132718Skandef FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 144132718Skan "Enable POWER8 Altivec instructions", 145132718Skan [FeatureAltivec]>; 146132718Skandef FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 147132718Skan "Enable POWER8 Crypto instructions", 148132718Skan [FeatureP8Altivec]>; 149132718Skandef FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 150132718Skan "Enable POWER8 vector instructions", 151132718Skan [FeatureVSX, FeatureP8Altivec]>; 152169689Skandef FeatureDirectMove : 153169689Skan SubtargetFeature<"direct-move", "HasDirectMove", "true", 154169689Skan "Enable Power8 direct move instructions", 155169689Skan [FeatureVSX]>; 156132718Skandef FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 157132718Skan "HasPartwordAtomics", "true", 158132718Skan "Enable l[bh]arx and st[bh]cx.">; 159132718Skandef FeatureInvariantFunctionDescriptors : 160169689Skan SubtargetFeature<"invariant-function-descriptors", 161169689Skan "HasInvariantFunctionDescriptors", "true", 162132718Skan "Assume function descriptors are invariant">; 163132718Skandef FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 164132718Skan "Always use indirect calls">; 165132718Skandef FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 166132718Skan "Enable Hardware Transactional Memory instructions">; 167132718Skandef FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 168132718Skan "Implement mftb using the mfspr instruction">; 169169689Skandef FeatureUnalignedFloats : 170132718Skan SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 171169689Skan "true", "CPU does not trap on unaligned FP access">; 172169689Skandef FeaturePPCPreRASched: 173169689Skan SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 174169689Skan "Use PowerPC pre-RA scheduling strategy">; 175132718Skandef FeaturePPCPostRASched: 176169689Skan SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 177169689Skan "Use PowerPC post-RA scheduling strategy">; 178169689Skandef FeatureFloat128 : 179169689Skan SubtargetFeature<"float128", "HasFloat128", "true", 180169689Skan "Enable the __float128 data type for IEEE-754R Binary128.", 181169689Skan [FeatureVSX]>; 182169689Skandef FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 183132718Skan "POPCNTD_Fast", 184132718Skan "Enable the popcnt[dw] instructions">; 185132718Skan// Note that for the a2/a2q processor models we should not use popcnt[dw] by 186132718Skan// default. These processors do support the instructions, but they're 187132718Skan// microcoded, and the software emulation is about twice as fast. 188132718Skandef FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 189169689Skan "POPCNTD_Slow", 190132718Skan "Has slow popcnt[dw] instructions">; 191132718Skan 192132718Skandef DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 193132718Skan "Treat vector data stream cache control instructions as deprecated">; 194132718Skan 195132718Skandef FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 196132718Skan "true", 197132718Skan "Enable instructions added in ISA 3.0.">; 198132718Skandef FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 199132718Skan "Enable POWER9 Altivec instructions", 200132718Skan [FeatureISA3_0, FeatureP8Altivec]>; 201132718Skandef FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 202132718Skan "Enable POWER9 vector instructions", 203132718Skan [FeatureISA3_0, FeatureP8Vector, 204132718Skan FeatureP9Altivec]>; 205132718Skan// A separate feature for this even though it is equivalent to P9Vector 206132718Skan// because this is a feature of the implementation rather than the architecture 207132718Skan// and may go away with future CPU's. 208169689Skandef FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 209169689Skan "VectorsUseTwoUnits", 210132718Skan "true", 211132718Skan "Vectors use two units">; 212132718Skan 213132718Skan// Since new processors generally contain a superset of features of those that 214132718Skan// came before them, the idea is to make implementations of new processors 215132718Skan// less error prone and easier to read. 216132718Skan// Namely: 217132718Skan// list<SubtargetFeature> P8InheritableFeatures = ... 218132718Skan// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 219169689Skan// [ features that Power8 does not support but inheritable ] 220169689Skan// list<SubtargetFeature> FutureProcessorSpecificFeatures = 221132718Skan// [ features that Power8 does not support and not inheritable ] 222132718Skan// list<SubtargetFeature> FutureProcessorInheritableFeatures = 223132718Skan// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 224132718Skan// list<SubtargetFeature> FutureProcessorFeatures = 225132718Skan// !listconcat(FutureProcessorInheritableFeatures, 226132718Skan// FutureProcessorSpecificFeatures) 227132718Skan 228132718Skan// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as 229132718Skan// well as providing a single point of definition if the feature set will be 230132718Skan// used elsewhere. 231169689Skandef ProcessorFeatures { 232132718Skan // Power7 233132718Skan list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 234132718Skan FeatureAltivec, 235132718Skan FeatureVSX, 236132718Skan FeatureMFOCRF, 237132718Skan FeatureFCPSGN, 238169689Skan FeatureFSqrt, 239169689Skan FeatureFRE, 240132718Skan FeatureFRES, 241132718Skan FeatureFRSQRTE, 242132718Skan FeatureFRSQRTES, 243132718Skan FeatureRecipPrec, 244132718Skan FeatureSTFIWX, 245132718Skan FeatureLFIWAX, 246169689Skan FeatureFPRND, 247132718Skan FeatureFPCVT, 248132718Skan FeatureISEL, 249132718Skan FeaturePOPCNTD, 250132718Skan FeatureCMPB, 251132718Skan FeatureLDBRX, 252132718Skan Feature64Bit, 253132718Skan /* Feature64BitRegs, */ 254132718Skan FeatureBPERMD, 255132718Skan FeatureExtDiv, 256169689Skan FeatureMFTB, 257169689Skan DeprecatedDST, 258169689Skan FeatureTwoConstNR, 259169689Skan FeatureUnalignedFloats]; 260169689Skan list<SubtargetFeature> P7SpecificFeatures = []; 261132718Skan list<SubtargetFeature> P7Features = 262169689Skan !listconcat(P7InheritableFeatures, P7SpecificFeatures); 263169689Skan 264169689Skan // Power8 265132718Skan list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8, 266169689Skan FeatureP8Altivec, 267169689Skan FeatureP8Vector, 268132718Skan FeatureP8Crypto, 269132718Skan FeatureHTM, 270169689Skan FeatureDirectMove, 271169689Skan FeatureICBT, 272132718Skan FeaturePartwordAtomic]; 273132718Skan list<SubtargetFeature> P8SpecificFeatures = []; 274132718Skan list<SubtargetFeature> P8InheritableFeatures = 275169689Skan !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 276169689Skan list<SubtargetFeature> P8Features = 277169689Skan !listconcat(P8InheritableFeatures, P8SpecificFeatures); 278169689Skan 279169689Skan // Power9 280169689Skan list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9, 281132718Skan FeatureP9Altivec, 282132718Skan FeatureP9Vector, 283132718Skan FeatureISA3_0]; 284132718Skan // Some features are unique to Power9 and there is no reason to assume 285132718Skan // they will be part of any future CPUs. One example is the narrower 286132718Skan // dispatch for vector operations than scalar ones. For the time being, 287132718Skan // this list also includes scheduling-related features since we do not have 288132718Skan // enough info to create custom scheduling strategies for future CPUs. 289169689Skan list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits, 290132718Skan FeaturePPCPreRASched, 291169689Skan FeaturePPCPostRASched]; 292169689Skan list<SubtargetFeature> P9InheritableFeatures = 293169689Skan !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 294169689Skan list<SubtargetFeature> P9Features = 295169689Skan !listconcat(P9InheritableFeatures, P9SpecificFeatures); 296169689Skan 297169689Skan // Future 298169689Skan // For future CPU we assume that all of the existing features from Power 9 299169689Skan // still exist with the exception of those we know are Power 9 specific. 300169689Skan list<SubtargetFeature> FutureAdditionalFeatures = []; 301169689Skan list<SubtargetFeature> FutureSpecificFeatures = []; 302169689Skan list<SubtargetFeature> FutureInheritableFeatures = 303169689Skan !listconcat(P9InheritableFeatures, FutureAdditionalFeatures); 304169689Skan list<SubtargetFeature> FutureFeatures = 305169689Skan !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 306169689Skan} 307169689Skan 308169689Skan// Note: Future features to add when support is extended to more 309169689Skan// recent ISA levels: 310169689Skan// 311169689Skan// DFP p6, p6x, p7 decimal floating-point instructions 312169689Skan// POPCNTB p5 through p7 popcntb and related instructions 313169689Skan 314169689Skan//===----------------------------------------------------------------------===// 315169689Skan// Classes used for relation maps. 316169689Skan//===----------------------------------------------------------------------===// 317169689Skan// RecFormRel - Filter class used to relate non-record-form instructions with 318169689Skan// their record-form variants. 319169689Skanclass RecFormRel; 320169689Skan 321169689Skan// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 322169689Skan// FMA instruction forms with their corresponding factor-killing forms. 323169689Skanclass AltVSXFMARel { 324169689Skan bit IsVSXFMAAlt = 0; 325} 326 327//===----------------------------------------------------------------------===// 328// Relation Map Definitions. 329//===----------------------------------------------------------------------===// 330 331def getRecordFormOpcode : InstrMapping { 332 let FilterClass = "RecFormRel"; 333 // Instructions with the same BaseName and Interpretation64Bit values 334 // form a row. 335 let RowFields = ["BaseName", "Interpretation64Bit"]; 336 // Instructions with the same RC value form a column. 337 let ColFields = ["RC"]; 338 // The key column are the non-record-form instructions. 339 let KeyCol = ["0"]; 340 // Value columns RC=1 341 let ValueCols = [["1"]]; 342} 343 344def getNonRecordFormOpcode : InstrMapping { 345 let FilterClass = "RecFormRel"; 346 // Instructions with the same BaseName and Interpretation64Bit values 347 // form a row. 348 let RowFields = ["BaseName", "Interpretation64Bit"]; 349 // Instructions with the same RC value form a column. 350 let ColFields = ["RC"]; 351 // The key column are the record-form instructions. 352 let KeyCol = ["1"]; 353 // Value columns are RC=0 354 let ValueCols = [["0"]]; 355} 356 357def getAltVSXFMAOpcode : InstrMapping { 358 let FilterClass = "AltVSXFMARel"; 359 // Instructions with the same BaseName value form a row. 360 let RowFields = ["BaseName"]; 361 // Instructions with the same IsVSXFMAAlt value form a column. 362 let ColFields = ["IsVSXFMAAlt"]; 363 // The key column are the (default) addend-killing instructions. 364 let KeyCol = ["0"]; 365 // Value columns IsVSXFMAAlt=1 366 let ValueCols = [["1"]]; 367} 368 369//===----------------------------------------------------------------------===// 370// Register File Description 371//===----------------------------------------------------------------------===// 372 373include "PPCRegisterInfo.td" 374include "PPCSchedule.td" 375 376//===----------------------------------------------------------------------===// 377// PowerPC processors supported. 378// 379 380def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 381 FeatureMFTB]>; 382def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 383 FeatureFRES, FeatureFRSQRTE, 384 FeatureICBT, FeatureBookE, 385 FeatureMSYNC, FeatureMFTB]>; 386def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 387 FeatureFRES, FeatureFRSQRTE, 388 FeatureICBT, FeatureBookE, 389 FeatureMSYNC, FeatureMFTB]>; 390def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 391def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 392 FeatureMFTB]>; 393def : Processor<"603", G3Itineraries, [Directive603, 394 FeatureFRES, FeatureFRSQRTE, 395 FeatureMFTB]>; 396def : Processor<"603e", G3Itineraries, [Directive603, 397 FeatureFRES, FeatureFRSQRTE, 398 FeatureMFTB]>; 399def : Processor<"603ev", G3Itineraries, [Directive603, 400 FeatureFRES, FeatureFRSQRTE, 401 FeatureMFTB]>; 402def : Processor<"604", G3Itineraries, [Directive604, 403 FeatureFRES, FeatureFRSQRTE, 404 FeatureMFTB]>; 405def : Processor<"604e", G3Itineraries, [Directive604, 406 FeatureFRES, FeatureFRSQRTE, 407 FeatureMFTB]>; 408def : Processor<"620", G3Itineraries, [Directive620, 409 FeatureFRES, FeatureFRSQRTE, 410 FeatureMFTB]>; 411def : Processor<"750", G4Itineraries, [Directive750, 412 FeatureFRES, FeatureFRSQRTE, 413 FeatureMFTB]>; 414def : Processor<"g3", G3Itineraries, [Directive750, 415 FeatureFRES, FeatureFRSQRTE, 416 FeatureMFTB]>; 417def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 418 FeatureFRES, FeatureFRSQRTE, 419 FeatureMFTB]>; 420def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 421 FeatureFRES, FeatureFRSQRTE, 422 FeatureMFTB]>; 423def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 424 FeatureFRES, FeatureFRSQRTE, 425 FeatureMFTB]>; 426def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 427 FeatureFRES, FeatureFRSQRTE, 428 FeatureMFTB]>; 429 430def : ProcessorModel<"970", G5Model, 431 [Directive970, FeatureAltivec, 432 FeatureMFOCRF, FeatureFSqrt, 433 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 434 Feature64Bit /*, Feature64BitRegs */, 435 FeatureMFTB]>; 436def : ProcessorModel<"g5", G5Model, 437 [Directive970, FeatureAltivec, 438 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 439 FeatureFRES, FeatureFRSQRTE, 440 Feature64Bit /*, Feature64BitRegs */, 441 FeatureMFTB, DeprecatedDST]>; 442def : ProcessorModel<"e500", PPCE500Model, 443 [DirectiveE500, 444 FeatureICBT, FeatureBookE, 445 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 446def : ProcessorModel<"e500mc", PPCE500mcModel, 447 [DirectiveE500mc, 448 FeatureSTFIWX, FeatureICBT, FeatureBookE, 449 FeatureISEL, FeatureMFTB]>; 450def : ProcessorModel<"e5500", PPCE5500Model, 451 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 452 FeatureSTFIWX, FeatureICBT, FeatureBookE, 453 FeatureISEL, FeatureMFTB]>; 454def : ProcessorModel<"a2", PPCA2Model, 455 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 456 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 457 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 458 FeatureSTFIWX, FeatureLFIWAX, 459 FeatureFPRND, FeatureFPCVT, FeatureISEL, 460 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 461 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 462def : ProcessorModel<"a2q", PPCA2Model, 463 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 464 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 465 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 466 FeatureSTFIWX, FeatureLFIWAX, 467 FeatureFPRND, FeatureFPCVT, FeatureISEL, 468 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 469 Feature64Bit /*, Feature64BitRegs */, FeatureQPX, 470 FeatureMFTB]>; 471def : ProcessorModel<"pwr3", G5Model, 472 [DirectivePwr3, FeatureAltivec, 473 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 474 FeatureSTFIWX, Feature64Bit]>; 475def : ProcessorModel<"pwr4", G5Model, 476 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 477 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 478 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 479def : ProcessorModel<"pwr5", G5Model, 480 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 481 FeatureFSqrt, FeatureFRE, FeatureFRES, 482 FeatureFRSQRTE, FeatureFRSQRTES, 483 FeatureSTFIWX, Feature64Bit, 484 FeatureMFTB, DeprecatedDST]>; 485def : ProcessorModel<"pwr5x", G5Model, 486 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 487 FeatureFSqrt, FeatureFRE, FeatureFRES, 488 FeatureFRSQRTE, FeatureFRSQRTES, 489 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 490 FeatureMFTB, DeprecatedDST]>; 491def : ProcessorModel<"pwr6", G5Model, 492 [DirectivePwr6, FeatureAltivec, 493 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 494 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 495 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 496 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 497 FeatureMFTB, DeprecatedDST]>; 498def : ProcessorModel<"pwr6x", G5Model, 499 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 500 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 501 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 502 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 503 FeatureFPRND, Feature64Bit, 504 FeatureMFTB, DeprecatedDST]>; 505def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 506def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 507def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 508// No scheduler model for future CPU. 509def : ProcessorModel<"future", NoSchedModel, 510 ProcessorFeatures.FutureFeatures>; 511def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 512 FeatureMFTB]>; 513def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 514 FeatureMFTB]>; 515def : ProcessorModel<"ppc64", G5Model, 516 [Directive64, FeatureAltivec, 517 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 518 FeatureFRSQRTE, FeatureSTFIWX, 519 Feature64Bit /*, Feature64BitRegs */, 520 FeatureMFTB]>; 521def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 522 523//===----------------------------------------------------------------------===// 524// Calling Conventions 525//===----------------------------------------------------------------------===// 526 527include "PPCCallingConv.td" 528 529def PPCInstrInfo : InstrInfo { 530 let isLittleEndianEncoding = 1; 531 532 // FIXME: Unset this when no longer needed! 533 let decodePositionallyEncodedOperands = 1; 534 535 let noNamedPositionallyEncodedOperands = 1; 536} 537 538def PPCAsmParser : AsmParser { 539 let ShouldEmitMatchRegisterName = 0; 540} 541 542def PPCAsmParserVariant : AsmParserVariant { 543 int Variant = 0; 544 545 // We do not use hard coded registers in asm strings. However, some 546 // InstAlias definitions use immediate literals. Set RegisterPrefix 547 // so that those are not misinterpreted as registers. 548 string RegisterPrefix = "%"; 549 string BreakCharacters = "."; 550} 551 552def PPC : Target { 553 // Information about the instructions. 554 let InstructionSet = PPCInstrInfo; 555 556 let AssemblyParsers = [PPCAsmParser]; 557 let AssemblyParserVariants = [PPCAsmParserVariant]; 558 let AllowRegisterRenaming = 1; 559} 560 561//===----------------------------------------------------------------------===// 562// Pfm Counters 563//===----------------------------------------------------------------------===// 564 565include "PPCPfmCounters.td" 566