MipsTargetMachine.cpp revision 355940 
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Mips target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsTargetMachine.h"
14#include "MCTargetDesc/MipsABIInfo.h"
15#include "MCTargetDesc/MipsMCTargetDesc.h"
16#include "Mips.h"
17#include "Mips16ISelDAGToDAG.h"
18#include "MipsSEISelDAGToDAG.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetObjectFile.h"
21#include "TargetInfo/MipsTargetInfo.h"
22#include "llvm/ADT/Optional.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringRef.h"
25#include "llvm/Analysis/TargetTransformInfo.h"
26#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
27#include "llvm/CodeGen/GlobalISel/Legalizer.h"
28#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30#include "llvm/CodeGen/BasicTTIImpl.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/CodeGen/TargetPassConfig.h"
34#include "llvm/IR/Attributes.h"
35#include "llvm/IR/Function.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/Target/TargetOptions.h"
41#include <string>
42
43using namespace llvm;
44
45#define DEBUG_TYPE "mips"
46
47extern "C" void LLVMInitializeMipsTarget() {
48  // Register the target.
49  RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
50  RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
51  RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
52  RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
53
54  PassRegistry *PR = PassRegistry::getPassRegistry();
55  initializeGlobalISel(*PR);
56  initializeMipsDelaySlotFillerPass(*PR);
57  initializeMipsBranchExpansionPass(*PR);
58  initializeMicroMipsSizeReducePass(*PR);
59  initializeMipsPreLegalizerCombinerPass(*PR);
60}
61
62static std::string computeDataLayout(const Triple &TT, StringRef CPU,
63                                     const TargetOptions &Options,
64                                     bool isLittle) {
65  std::string Ret;
66  MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
67
68  // There are both little and big endian mips.
69  if (isLittle)
70    Ret += "e";
71  else
72    Ret += "E";
73
74  if (ABI.IsO32())
75    Ret += "-m:m";
76  else
77    Ret += "-m:e";
78
79  // Pointers are 32 bit on some ABIs.
80  if (!ABI.IsN64())
81    Ret += "-p:32:32";
82
83  // 8 and 16 bit integers only need to have natural alignment, but try to
84  // align them to 32 bits. 64 bit integers have natural alignment.
85  Ret += "-i8:8:32-i16:16:32-i64:64";
86
87  // 32 bit registers are always available and the stack is at least 64 bit
88  // aligned. On N64 64 bit registers are also available and the stack is
89  // 128 bit aligned.
90  if (ABI.IsN64() || ABI.IsN32())
91    Ret += "-n32:64-S128";
92  else
93    Ret += "-n32-S64";
94
95  return Ret;
96}
97
98static Reloc::Model getEffectiveRelocModel(bool JIT,
99                                           Optional<Reloc::Model> RM) {
100  if (!RM.hasValue() || JIT)
101    return Reloc::Static;
102  return *RM;
103}
104
105// On function prologue, the stack is created by decrementing
106// its pointer. Once decremented, all references are done with positive
107// offset from the stack/frame pointer, using StackGrowsUp enables
108// an easier handling.
109// Using CodeModel::Large enables different CALL behavior.
110MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
111                                     StringRef CPU, StringRef FS,
112                                     const TargetOptions &Options,
113                                     Optional<Reloc::Model> RM,
114                                     Optional<CodeModel::Model> CM,
115                                     CodeGenOpt::Level OL, bool JIT,
116                                     bool isLittle)
117    : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
118                        CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
119                        getEffectiveCodeModel(CM, CodeModel::Small), OL),
120      isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
121      ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
122      Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
123                                           Options.StackAlignmentOverride),
124      NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
125                        isLittle, *this, Options.StackAlignmentOverride),
126      Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
127                      isLittle, *this, Options.StackAlignmentOverride) {
128  Subtarget = &DefaultSubtarget;
129  initAsmInfo();
130}
131
132MipsTargetMachine::~MipsTargetMachine() = default;
133
134void MipsebTargetMachine::anchor() {}
135
136MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
137                                         StringRef CPU, StringRef FS,
138                                         const TargetOptions &Options,
139                                         Optional<Reloc::Model> RM,
140                                         Optional<CodeModel::Model> CM,
141                                         CodeGenOpt::Level OL, bool JIT)
142    : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
143
144void MipselTargetMachine::anchor() {}
145
146MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
147                                         StringRef CPU, StringRef FS,
148                                         const TargetOptions &Options,
149                                         Optional<Reloc::Model> RM,
150                                         Optional<CodeModel::Model> CM,
151                                         CodeGenOpt::Level OL, bool JIT)
152    : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
153
154const MipsSubtarget *
155MipsTargetMachine::getSubtargetImpl(const Function &F) const {
156  Attribute CPUAttr = F.getFnAttribute("target-cpu");
157  Attribute FSAttr = F.getFnAttribute("target-features");
158
159  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
160                        ? CPUAttr.getValueAsString().str()
161                        : TargetCPU;
162  std::string FS = !FSAttr.hasAttribute(Attribute::None)
163                       ? FSAttr.getValueAsString().str()
164                       : TargetFS;
165  bool hasMips16Attr =
166      !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
167  bool hasNoMips16Attr =
168      !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
169
170  bool HasMicroMipsAttr =
171      !F.getFnAttribute("micromips").hasAttribute(Attribute::None);
172  bool HasNoMicroMipsAttr =
173      !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
174
175  // FIXME: This is related to the code below to reset the target options,
176  // we need to know whether or not the soft float flag is set on the
177  // function, so we can enable it as a subtarget feature.
178  bool softFloat =
179      F.hasFnAttribute("use-soft-float") &&
180      F.getFnAttribute("use-soft-float").getValueAsString() == "true";
181
182  if (hasMips16Attr)
183    FS += FS.empty() ? "+mips16" : ",+mips16";
184  else if (hasNoMips16Attr)
185    FS += FS.empty() ? "-mips16" : ",-mips16";
186  if (HasMicroMipsAttr)
187    FS += FS.empty() ? "+micromips" : ",+micromips";
188  else if (HasNoMicroMipsAttr)
189    FS += FS.empty() ? "-micromips" : ",-micromips";
190  if (softFloat)
191    FS += FS.empty() ? "+soft-float" : ",+soft-float";
192
193  auto &I = SubtargetMap[CPU + FS];
194  if (!I) {
195    // This needs to be done before we create a new subtarget since any
196    // creation will depend on the TM and the code generation flags on the
197    // function that reside in TargetOptions.
198    resetTargetOptions(F);
199    I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this,
200                                         Options.StackAlignmentOverride);
201  }
202  return I.get();
203}
204
205void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
206  LLVM_DEBUG(dbgs() << "resetSubtarget\n");
207
208  Subtarget = &MF->getSubtarget<MipsSubtarget>();
209}
210
211namespace {
212
213/// Mips Code Generator Pass Configuration Options.
214class MipsPassConfig : public TargetPassConfig {
215public:
216  MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
217      : TargetPassConfig(TM, PM) {
218    // The current implementation of long branch pass requires a scratch
219    // register ($at) to be available before branch instructions. Tail merging
220    // can break this requirement, so disable it when long branch pass is
221    // enabled.
222    EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
223  }
224
225  MipsTargetMachine &getMipsTargetMachine() const {
226    return getTM<MipsTargetMachine>();
227  }
228
229  const MipsSubtarget &getMipsSubtarget() const {
230    return *getMipsTargetMachine().getSubtargetImpl();
231  }
232
233  void addIRPasses() override;
234  bool addInstSelector() override;
235  void addPreEmitPass() override;
236  void addPreRegAlloc() override;
237  bool addIRTranslator() override;
238  void addPreLegalizeMachineIR() override;
239  bool addLegalizeMachineIR() override;
240  bool addRegBankSelect() override;
241  bool addGlobalInstructionSelect() override;
242
243  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
244};
245
246} // end anonymous namespace
247
248TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
249  return new MipsPassConfig(*this, PM);
250}
251
252std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
253  return getStandardCSEConfigForOpt(TM->getOptLevel());
254}
255
256void MipsPassConfig::addIRPasses() {
257  TargetPassConfig::addIRPasses();
258  addPass(createAtomicExpandPass());
259  if (getMipsSubtarget().os16())
260    addPass(createMipsOs16Pass());
261  if (getMipsSubtarget().inMips16HardFloat())
262    addPass(createMips16HardFloatPass());
263}
264// Install an instruction selector pass using
265// the ISelDag to gen Mips code.
266bool MipsPassConfig::addInstSelector() {
267  addPass(createMipsModuleISelDagPass());
268  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
269  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
270  return false;
271}
272
273void MipsPassConfig::addPreRegAlloc() {
274  addPass(createMipsOptimizePICCallPass());
275}
276
277TargetTransformInfo
278MipsTargetMachine::getTargetTransformInfo(const Function &F) {
279  if (Subtarget->allowMixed16_32()) {
280    LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
281    // FIXME: This is no longer necessary as the TTI returned is per-function.
282    return TargetTransformInfo(F.getParent()->getDataLayout());
283  }
284
285  LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
286  return TargetTransformInfo(BasicTTIImpl(this, F));
287}
288
289// Implemented by targets that want to run passes immediately before
290// machine code is emitted. return true if -print-machineinstrs should
291// print out the code after the passes.
292void MipsPassConfig::addPreEmitPass() {
293  // Expand pseudo instructions that are sensitive to register allocation.
294  addPass(createMipsExpandPseudoPass());
295
296  // The microMIPS size reduction pass performs instruction reselection for
297  // instructions which can be remapped to a 16 bit instruction.
298  addPass(createMicroMipsSizeReducePass());
299
300  // The delay slot filler pass can potientially create forbidden slot hazards
301  // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
302  addPass(createMipsDelaySlotFillerPass());
303
304  // This pass expands branches and takes care about the forbidden slot hazards.
305  // Expanding branches may potentially create forbidden slot hazards for
306  // MIPSR6, and fixing such hazard may potentially break a branch by extending
307  // its offset out of range. That's why this pass combine these two tasks, and
308  // runs them alternately until one of them finishes without any changes. Only
309  // then we can be sure that all branches are expanded properly and no hazards
310  // exists.
311  // Any new pass should go before this pass.
312  addPass(createMipsBranchExpansion());
313
314  addPass(createMipsConstantIslandPass());
315}
316
317bool MipsPassConfig::addIRTranslator() {
318  addPass(new IRTranslator());
319  return false;
320}
321
322void MipsPassConfig::addPreLegalizeMachineIR() {
323  addPass(createMipsPreLegalizeCombiner());
324}
325
326bool MipsPassConfig::addLegalizeMachineIR() {
327  addPass(new Legalizer());
328  return false;
329}
330
331bool MipsPassConfig::addRegBankSelect() {
332  addPass(new RegBankSelect());
333  return false;
334}
335
336bool MipsPassConfig::addGlobalInstructionSelect() {
337  addPass(new InstructionSelect());
338  return false;
339}
340