MipsTargetMachine.cpp revision 234353 
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Mips target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsTargetMachine.h"
15#include "Mips.h"
16#include "llvm/PassManager.h"
17#include "llvm/CodeGen/Passes.h"
18#include "llvm/Support/TargetRegistry.h"
19using namespace llvm;
20
21extern "C" void LLVMInitializeMipsTarget() {
22  // Register the target.
23  RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
24  RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
25  RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
26  RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
27}
28
29// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
30// The stack is always 8 byte aligned
31// On function prologue, the stack is created by decrementing
32// its pointer. Once decremented, all references are done with positive
33// offset from the stack/frame pointer, using StackGrowsUp enables
34// an easier handling.
35// Using CodeModel::Large enables different CALL behavior.
36MipsTargetMachine::
37MipsTargetMachine(const Target &T, StringRef TT,
38                  StringRef CPU, StringRef FS, const TargetOptions &Options,
39                  Reloc::Model RM, CodeModel::Model CM,
40                  CodeGenOpt::Level OL,
41                  bool isLittle)
42  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
43    Subtarget(TT, CPU, FS, isLittle),
44    DataLayout(isLittle ?
45               (Subtarget.isABI_N64() ?
46                "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
47                "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
48               (Subtarget.isABI_N64() ?
49                "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
50                "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
51    InstrInfo(*this),
52    FrameLowering(Subtarget),
53    TLInfo(*this), TSInfo(*this), JITInfo() {
54}
55
56void MipsebTargetMachine::anchor() { }
57
58MipsebTargetMachine::
59MipsebTargetMachine(const Target &T, StringRef TT,
60                    StringRef CPU, StringRef FS, const TargetOptions &Options,
61                    Reloc::Model RM, CodeModel::Model CM,
62                    CodeGenOpt::Level OL)
63  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
64
65void MipselTargetMachine::anchor() { }
66
67MipselTargetMachine::
68MipselTargetMachine(const Target &T, StringRef TT,
69                    StringRef CPU, StringRef FS, const TargetOptions &Options,
70                    Reloc::Model RM, CodeModel::Model CM,
71                    CodeGenOpt::Level OL)
72  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
73
74void Mips64ebTargetMachine::anchor() { }
75
76Mips64ebTargetMachine::
77Mips64ebTargetMachine(const Target &T, StringRef TT,
78                      StringRef CPU, StringRef FS, const TargetOptions &Options,
79                      Reloc::Model RM, CodeModel::Model CM,
80                      CodeGenOpt::Level OL)
81  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
82
83void Mips64elTargetMachine::anchor() { }
84
85Mips64elTargetMachine::
86Mips64elTargetMachine(const Target &T, StringRef TT,
87                      StringRef CPU, StringRef FS, const TargetOptions &Options,
88                      Reloc::Model RM, CodeModel::Model CM,
89                      CodeGenOpt::Level OL)
90  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
91
92namespace {
93/// Mips Code Generator Pass Configuration Options.
94class MipsPassConfig : public TargetPassConfig {
95public:
96  MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
97    : TargetPassConfig(TM, PM) {}
98
99  MipsTargetMachine &getMipsTargetMachine() const {
100    return getTM<MipsTargetMachine>();
101  }
102
103  const MipsSubtarget &getMipsSubtarget() const {
104    return *getMipsTargetMachine().getSubtargetImpl();
105  }
106
107  virtual bool addInstSelector();
108  virtual bool addPreRegAlloc();
109  virtual bool addPreSched2();
110  virtual bool addPreEmitPass();
111};
112} // namespace
113
114TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
115  return new MipsPassConfig(this, PM);
116}
117
118// Install an instruction selector pass using
119// the ISelDag to gen Mips code.
120bool MipsPassConfig::addInstSelector()
121{
122  PM.add(createMipsISelDag(getMipsTargetMachine()));
123  return false;
124}
125
126// Implemented by targets that want to run passes immediately before
127// machine code is emitted. return true if -print-machineinstrs should
128// print out the code after the passes.
129bool MipsPassConfig::addPreEmitPass()
130{
131  PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
132  return true;
133}
134
135bool MipsPassConfig::addPreRegAlloc() {
136  // Do not restore $gp if target is Mips64.
137  // In N32/64, $gp is a callee-saved register.
138  if (!getMipsSubtarget().hasMips64())
139    PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
140  return true;
141}
142
143bool MipsPassConfig::addPreSched2() {
144  PM.add(createMipsExpandPseudoPass(getMipsTargetMachine()));
145  return true;
146}
147
148bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
149                                       JITCodeEmitter &JCE) {
150  // Machine code emitter pass for Mips.
151  PM.add(createMipsJITCodeEmitterPass(*this, JCE));
152  return false;
153}
154