1234353Sdim//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2193323Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed 9193323Sed//===----------------------------------------------------------------------===// 10193323Sed// Describe MIPS instructions format 11193323Sed// 12193323Sed// CPU INSTRUCTION FORMATS 13193323Sed// 14193323Sed// opcode - operation code. 15193323Sed// rs - src reg. 16193323Sed// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 17193323Sed// rd - dst reg, only used on 3 regs instr. 18193323Sed// shamt - only used on shift instructions, contains the shift amount. 19193323Sed// funct - combined with opcode field give us an operation code. 20193323Sed// 21193323Sed//===----------------------------------------------------------------------===// 22193323Sed 23228379Sdim// Format specifies the encoding used by the instruction. This is part of the 24228379Sdim// ad-hoc solution used to emit machine instruction encodings by our machine 25228379Sdim// code emitter. 26228379Sdimclass Format<bits<4> val> { 27228379Sdim bits<4> Value = val; 28228379Sdim} 29228379Sdim 30228379Sdimdef Pseudo : Format<0>; 31228379Sdimdef FrmR : Format<1>; 32228379Sdimdef FrmI : Format<2>; 33228379Sdimdef FrmJ : Format<3>; 34228379Sdimdef FrmFR : Format<4>; 35228379Sdimdef FrmFI : Format<5>; 36228379Sdimdef FrmOther : Format<6>; // Instruction w/ a custom format 37228379Sdim 38251662Sdimclass MMRel; 39251662Sdim 40251662Sdimdef Std2MicroMips : InstrMapping { 41251662Sdim let FilterClass = "MMRel"; 42251662Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 43251662Sdim let RowFields = ["BaseOpcode"]; 44251662Sdim // Instructions with the same predicate sense form a column. 45251662Sdim let ColFields = ["Arch"]; 46251662Sdim // The key column is the unpredicated instructions. 47251662Sdim let KeyCol = ["se"]; 48251662Sdim // Value columns are PredSense=true and PredSense=false 49251662Sdim let ValueCols = [["se"], ["micromips"]]; 50251662Sdim} 51251662Sdim 52288943Sdimclass StdMMR6Rel; 53288943Sdim 54288943Sdimdef Std2MicroMipsR6 : InstrMapping { 55288943Sdim let FilterClass = "StdMMR6Rel"; 56288943Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 57288943Sdim let RowFields = ["BaseOpcode"]; 58288943Sdim // Instructions with the same predicate sense form a column. 59288943Sdim let ColFields = ["Arch"]; 60288943Sdim // The key column is the unpredicated instructions. 61288943Sdim let KeyCol = ["se"]; 62288943Sdim // Value columns are PredSense=true and PredSense=false 63288943Sdim let ValueCols = [["se"], ["micromipsr6"]]; 64288943Sdim} 65288943Sdim 66251662Sdimclass StdArch { 67251662Sdim string Arch = "se"; 68251662Sdim} 69251662Sdim 70193323Sed// Generic Mips Format 71221345Sdimclass MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 72341825Sdim InstrItinClass itin, Format f>: Instruction, PredicateControl 73193323Sed{ 74193323Sed field bits<32> Inst; 75228379Sdim Format Form = f; 76193323Sed 77193323Sed let Namespace = "Mips"; 78193323Sed 79234982Sdim let Size = 4; 80234982Sdim 81228379Sdim bits<6> Opcode = 0; 82193323Sed 83228379Sdim // Top 6 bits are the 'opcode' field 84228379Sdim let Inst{31-26} = Opcode; 85221345Sdim 86228379Sdim let OutOperandList = outs; 87228379Sdim let InOperandList = ins; 88193323Sed 89193323Sed let AsmString = asmstr; 90193323Sed let Pattern = pattern; 91193323Sed let Itinerary = itin; 92228379Sdim 93228379Sdim // 94228379Sdim // Attributes specific to Mips instructions... 95228379Sdim // 96309124Sdim bits<4> FormBits = Form.Value; 97309124Sdim bit isCTI = 0; // Any form of Control Transfer Instruction. 98309124Sdim // Required for MIPSR6 99309124Sdim bit hasForbiddenSlot = 0; // Instruction has a forbidden slot. 100314564Sdim bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is 101314564Sdim // present in MIPS-I to MIPS-III. 102228379Sdim 103314564Sdim // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h. 104228379Sdim let TSFlags{3-0} = FormBits; 105309124Sdim let TSFlags{4} = isCTI; 106309124Sdim let TSFlags{5} = hasForbiddenSlot; 107360784Sdim let TSFlags{6} = hasFCCRegOperand; 108234982Sdim 109234982Sdim let DecoderNamespace = "Mips"; 110234982Sdim 111234982Sdim field bits<32> SoftFail = 0; 112193323Sed} 113193323Sed 114239462Sdim// Mips32/64 Instruction Format 115239462Sdimclass InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 116251662Sdim InstrItinClass itin, Format f, string opstr = ""> : 117341825Sdim MipsInst<outs, ins, asmstr, pattern, itin, f> { 118341825Sdim let EncodingPredicates = [NotInMips16Mode]; 119251662Sdim string BaseOpcode = opstr; 120251662Sdim string Arch; 121239462Sdim} 122239462Sdim 123193323Sed// Mips Pseudo Instructions Format 124249423Sdimclass MipsPseudo<dag outs, dag ins, list<dag> pattern, 125249423Sdim InstrItinClass itin = IIPseudo> : 126341825Sdim MipsInst<outs, ins, "", pattern, itin, Pseudo> { 127228379Sdim let isCodeGenOnly = 1; 128226633Sdim let isPseudo = 1; 129226633Sdim} 130193323Sed 131239462Sdim// Mips32/64 Pseudo Instruction Format 132249423Sdimclass PseudoSE<dag outs, dag ins, list<dag> pattern, 133276479Sdim InstrItinClass itin = IIPseudo> : 134335799Sdim MipsPseudo<outs, ins, pattern, itin> { 135341825Sdim let EncodingPredicates = [NotInMips16Mode]; 136239462Sdim} 137239462Sdim 138243830Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 139243830Sdim// These are aliases that require C++ handling to convert to the target 140243830Sdim// instruction, while InstAliases can be handled directly by tblgen. 141243830Sdimclass MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 142341825Sdim MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 143243830Sdim let isPseudo = 1; 144353358Sdim let hasNoSchedulingInfo = 1; 145243830Sdim let Pattern = []; 146243830Sdim} 147193323Sed//===----------------------------------------------------------------------===// 148193323Sed// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 149193323Sed//===----------------------------------------------------------------------===// 150193323Sed 151193323Sedclass FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 152193323Sed list<dag> pattern, InstrItinClass itin>: 153239462Sdim InstSE<outs, ins, asmstr, pattern, itin, FrmR> 154193323Sed{ 155193323Sed bits<5> rd; 156193323Sed bits<5> rs; 157193323Sed bits<5> rt; 158193323Sed bits<5> shamt; 159193323Sed bits<6> funct; 160193323Sed 161228379Sdim let Opcode = op; 162193323Sed let funct = _funct; 163193323Sed 164193323Sed let Inst{25-21} = rs; 165221345Sdim let Inst{20-16} = rt; 166193323Sed let Inst{15-11} = rd; 167193323Sed let Inst{10-6} = shamt; 168193323Sed let Inst{5-0} = funct; 169193323Sed} 170193323Sed 171193323Sed//===----------------------------------------------------------------------===// 172193323Sed// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 173193323Sed//===----------------------------------------------------------------------===// 174193323Sed 175193323Sedclass FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 176239462Sdim InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 177193323Sed{ 178193323Sed bits<5> rt; 179193323Sed bits<5> rs; 180193323Sed bits<16> imm16; 181193323Sed 182228379Sdim let Opcode = op; 183193323Sed 184193323Sed let Inst{25-21} = rs; 185221345Sdim let Inst{20-16} = rt; 186193323Sed let Inst{15-0} = imm16; 187193323Sed} 188193323Sed 189234353Sdimclass BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 190226633Sdim list<dag> pattern, InstrItinClass itin>: 191239462Sdim InstSE<outs, ins, asmstr, pattern, itin, FrmI> 192226633Sdim{ 193226633Sdim bits<5> rs; 194226633Sdim bits<5> rt; 195226633Sdim bits<16> imm16; 196226633Sdim 197228379Sdim let Opcode = op; 198226633Sdim 199226633Sdim let Inst{25-21} = rs; 200226633Sdim let Inst{20-16} = rt; 201226633Sdim let Inst{15-0} = imm16; 202226633Sdim} 203226633Sdim 204193323Sed//===----------------------------------------------------------------------===// 205193323Sed// Format J instruction class in Mips : <|opcode|address|> 206193323Sed//===----------------------------------------------------------------------===// 207193323Sed 208261991Sdimclass FJ<bits<6> op> : StdArch 209193323Sed{ 210249423Sdim bits<26> target; 211193323Sed 212249423Sdim bits<32> Inst; 213221345Sdim 214249423Sdim let Inst{31-26} = op; 215249423Sdim let Inst{25-0} = target; 216193323Sed} 217193323Sed 218249423Sdim//===----------------------------------------------------------------------===// 219341825Sdim// MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|> 220193323Sed//===----------------------------------------------------------------------===// 221341825Sdimclass MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch { 222243830Sdim bits<5> rt; 223243830Sdim bits<5> rd; 224243830Sdim bits<3> sel; 225243830Sdim 226249423Sdim bits<32> Inst; 227243830Sdim 228249423Sdim let Inst{31-26} = op; 229243830Sdim let Inst{25-21} = mfmt; 230243830Sdim let Inst{20-16} = rt; 231243830Sdim let Inst{15-11} = rd; 232341825Sdim let Inst{10-8} = guest; 233341825Sdim let Inst{7-3} = 0; 234243830Sdim let Inst{2-0} = sel; 235243830Sdim} 236243830Sdim 237288943Sdimclass MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch { 238288943Sdim bits<5> rt; 239288943Sdim bits<16> imm16; 240288943Sdim 241288943Sdim bits<32> Inst; 242288943Sdim 243288943Sdim let Inst{31-26} = op; 244288943Sdim let Inst{25-21} = mfmt; 245288943Sdim let Inst{20-16} = rt; 246288943Sdim let Inst{15-0} = imm16; 247288943Sdim} 248288943Sdim 249251662Sdimclass ADD_FM<bits<6> op, bits<6> funct> : StdArch { 250249423Sdim bits<5> rd; 251249423Sdim bits<5> rs; 252249423Sdim bits<5> rt; 253249423Sdim 254249423Sdim bits<32> Inst; 255249423Sdim 256249423Sdim let Inst{31-26} = op; 257249423Sdim let Inst{25-21} = rs; 258249423Sdim let Inst{20-16} = rt; 259249423Sdim let Inst{15-11} = rd; 260249423Sdim let Inst{10-6} = 0; 261249423Sdim let Inst{5-0} = funct; 262249423Sdim} 263249423Sdim 264251662Sdimclass ADDI_FM<bits<6> op> : StdArch { 265249423Sdim bits<5> rs; 266249423Sdim bits<5> rt; 267249423Sdim bits<16> imm16; 268249423Sdim 269249423Sdim bits<32> Inst; 270249423Sdim 271249423Sdim let Inst{31-26} = op; 272249423Sdim let Inst{25-21} = rs; 273249423Sdim let Inst{20-16} = rt; 274249423Sdim let Inst{15-0} = imm16; 275249423Sdim} 276249423Sdim 277251662Sdimclass SRA_FM<bits<6> funct, bit rotate> : StdArch { 278249423Sdim bits<5> rd; 279249423Sdim bits<5> rt; 280249423Sdim bits<5> shamt; 281249423Sdim 282249423Sdim bits<32> Inst; 283249423Sdim 284249423Sdim let Inst{31-26} = 0; 285249423Sdim let Inst{25-22} = 0; 286249423Sdim let Inst{21} = rotate; 287249423Sdim let Inst{20-16} = rt; 288249423Sdim let Inst{15-11} = rd; 289249423Sdim let Inst{10-6} = shamt; 290249423Sdim let Inst{5-0} = funct; 291249423Sdim} 292249423Sdim 293251662Sdimclass SRLV_FM<bits<6> funct, bit rotate> : StdArch { 294249423Sdim bits<5> rd; 295249423Sdim bits<5> rt; 296249423Sdim bits<5> rs; 297249423Sdim 298249423Sdim bits<32> Inst; 299249423Sdim 300249423Sdim let Inst{31-26} = 0; 301249423Sdim let Inst{25-21} = rs; 302249423Sdim let Inst{20-16} = rt; 303249423Sdim let Inst{15-11} = rd; 304249423Sdim let Inst{10-7} = 0; 305249423Sdim let Inst{6} = rotate; 306249423Sdim let Inst{5-0} = funct; 307249423Sdim} 308249423Sdim 309261991Sdimclass BEQ_FM<bits<6> op> : StdArch { 310249423Sdim bits<5> rs; 311249423Sdim bits<5> rt; 312249423Sdim bits<16> offset; 313249423Sdim 314249423Sdim bits<32> Inst; 315249423Sdim 316249423Sdim let Inst{31-26} = op; 317249423Sdim let Inst{25-21} = rs; 318249423Sdim let Inst{20-16} = rt; 319249423Sdim let Inst{15-0} = offset; 320249423Sdim} 321249423Sdim 322261991Sdimclass BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 323249423Sdim bits<5> rs; 324249423Sdim bits<16> offset; 325249423Sdim 326249423Sdim bits<32> Inst; 327249423Sdim 328249423Sdim let Inst{31-26} = op; 329249423Sdim let Inst{25-21} = rs; 330249423Sdim let Inst{20-16} = funct; 331249423Sdim let Inst{15-0} = offset; 332249423Sdim} 333249423Sdim 334288943Sdimclass BBIT_FM<bits<6> op> : StdArch { 335288943Sdim bits<5> rs; 336288943Sdim bits<5> p; 337288943Sdim bits<16> offset; 338288943Sdim 339288943Sdim bits<32> Inst; 340288943Sdim 341288943Sdim let Inst{31-26} = op; 342288943Sdim let Inst{25-21} = rs; 343288943Sdim let Inst{20-16} = p; 344288943Sdim let Inst{15-0} = offset; 345288943Sdim} 346288943Sdim 347251662Sdimclass SLTI_FM<bits<6> op> : StdArch { 348249423Sdim bits<5> rt; 349249423Sdim bits<5> rs; 350249423Sdim bits<16> imm16; 351249423Sdim 352249423Sdim bits<32> Inst; 353249423Sdim 354249423Sdim let Inst{31-26} = op; 355249423Sdim let Inst{25-21} = rs; 356249423Sdim let Inst{20-16} = rt; 357249423Sdim let Inst{15-0} = imm16; 358249423Sdim} 359249423Sdim 360261991Sdimclass MFLO_FM<bits<6> funct> : StdArch { 361249423Sdim bits<5> rd; 362249423Sdim 363249423Sdim bits<32> Inst; 364249423Sdim 365249423Sdim let Inst{31-26} = 0; 366249423Sdim let Inst{25-16} = 0; 367249423Sdim let Inst{15-11} = rd; 368249423Sdim let Inst{10-6} = 0; 369249423Sdim let Inst{5-0} = funct; 370249423Sdim} 371249423Sdim 372261991Sdimclass MTLO_FM<bits<6> funct> : StdArch { 373249423Sdim bits<5> rs; 374249423Sdim 375249423Sdim bits<32> Inst; 376249423Sdim 377249423Sdim let Inst{31-26} = 0; 378249423Sdim let Inst{25-21} = rs; 379249423Sdim let Inst{20-6} = 0; 380249423Sdim let Inst{5-0} = funct; 381249423Sdim} 382249423Sdim 383261991Sdimclass SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 384249423Sdim bits<5> rd; 385249423Sdim bits<5> rt; 386249423Sdim 387249423Sdim bits<32> Inst; 388249423Sdim 389249423Sdim let Inst{31-26} = 0x1f; 390249423Sdim let Inst{25-21} = 0; 391249423Sdim let Inst{20-16} = rt; 392249423Sdim let Inst{15-11} = rd; 393249423Sdim let Inst{10-6} = funct; 394249423Sdim let Inst{5-0} = funct2; 395249423Sdim} 396249423Sdim 397261991Sdimclass CLO_FM<bits<6> funct> : StdArch { 398249423Sdim bits<5> rd; 399249423Sdim bits<5> rs; 400249423Sdim bits<5> rt; 401249423Sdim 402249423Sdim bits<32> Inst; 403249423Sdim 404249423Sdim let Inst{31-26} = 0x1c; 405249423Sdim let Inst{25-21} = rs; 406249423Sdim let Inst{20-16} = rt; 407249423Sdim let Inst{15-11} = rd; 408249423Sdim let Inst{10-6} = 0; 409249423Sdim let Inst{5-0} = funct; 410249423Sdim let rt = rd; 411249423Sdim} 412249423Sdim 413261991Sdimclass LUI_FM : StdArch { 414249423Sdim bits<5> rt; 415249423Sdim bits<16> imm16; 416249423Sdim 417249423Sdim bits<32> Inst; 418249423Sdim 419249423Sdim let Inst{31-26} = 0xf; 420249423Sdim let Inst{25-21} = 0; 421249423Sdim let Inst{20-16} = rt; 422249423Sdim let Inst{15-0} = imm16; 423249423Sdim} 424249423Sdim 425276479Sdimclass JALR_FM { 426249423Sdim bits<5> rd; 427249423Sdim bits<5> rs; 428249423Sdim 429249423Sdim bits<32> Inst; 430249423Sdim 431249423Sdim let Inst{31-26} = 0; 432249423Sdim let Inst{25-21} = rs; 433249423Sdim let Inst{20-16} = 0; 434249423Sdim let Inst{15-11} = rd; 435249423Sdim let Inst{10-6} = 0; 436249423Sdim let Inst{5-0} = 9; 437249423Sdim} 438249423Sdim 439261991Sdimclass BGEZAL_FM<bits<5> funct> : StdArch { 440249423Sdim bits<5> rs; 441249423Sdim bits<16> offset; 442249423Sdim 443249423Sdim bits<32> Inst; 444249423Sdim 445249423Sdim let Inst{31-26} = 1; 446249423Sdim let Inst{25-21} = rs; 447249423Sdim let Inst{20-16} = funct; 448249423Sdim let Inst{15-0} = offset; 449249423Sdim} 450249423Sdim 451276479Sdimclass SYNC_FM : StdArch { 452249423Sdim bits<5> stype; 453249423Sdim 454249423Sdim bits<32> Inst; 455249423Sdim 456249423Sdim let Inst{31-26} = 0; 457249423Sdim let Inst{10-6} = stype; 458249423Sdim let Inst{5-0} = 0xf; 459249423Sdim} 460249423Sdim 461280031Sdimclass SYNCI_FM : StdArch { 462280031Sdim // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding). 463280031Sdim bits<21> addr; 464280031Sdim bits<5> rs = addr{20-16}; 465280031Sdim bits<16> offset = addr{15-0}; 466280031Sdim 467280031Sdim bits<32> Inst; 468280031Sdim 469280031Sdim let Inst{31-26} = 0b000001; 470280031Sdim let Inst{25-21} = rs; 471280031Sdim let Inst{20-16} = 0b11111; 472280031Sdim let Inst{15-0} = offset; 473280031Sdim} 474280031Sdim 475251662Sdimclass MULT_FM<bits<6> op, bits<6> funct> : StdArch { 476249423Sdim bits<5> rs; 477249423Sdim bits<5> rt; 478249423Sdim 479249423Sdim bits<32> Inst; 480249423Sdim 481249423Sdim let Inst{31-26} = op; 482249423Sdim let Inst{25-21} = rs; 483249423Sdim let Inst{20-16} = rt; 484249423Sdim let Inst{15-6} = 0; 485249423Sdim let Inst{5-0} = funct; 486249423Sdim} 487249423Sdim 488261991Sdimclass EXT_FM<bits<6> funct> : StdArch { 489249423Sdim bits<5> rt; 490249423Sdim bits<5> rs; 491249423Sdim bits<5> pos; 492249423Sdim bits<5> size; 493249423Sdim 494249423Sdim bits<32> Inst; 495249423Sdim 496249423Sdim let Inst{31-26} = 0x1f; 497249423Sdim let Inst{25-21} = rs; 498249423Sdim let Inst{20-16} = rt; 499249423Sdim let Inst{15-11} = size; 500249423Sdim let Inst{10-6} = pos; 501249423Sdim let Inst{5-0} = funct; 502249423Sdim} 503249423Sdim 504280031Sdimclass RDHWR_FM : StdArch { 505249423Sdim bits<5> rt; 506249423Sdim bits<5> rd; 507341825Sdim bits<3> sel; 508249423Sdim 509249423Sdim bits<32> Inst; 510249423Sdim 511249423Sdim let Inst{31-26} = 0x1f; 512249423Sdim let Inst{25-21} = 0; 513249423Sdim let Inst{20-16} = rt; 514249423Sdim let Inst{15-11} = rd; 515341825Sdim let Inst{10-9} = 0b00; 516341825Sdim let Inst{8-6} = sel; 517249423Sdim let Inst{5-0} = 0x3b; 518249423Sdim} 519249423Sdim 520261991Sdimclass TEQ_FM<bits<6> funct> : StdArch { 521261991Sdim bits<5> rs; 522261991Sdim bits<5> rt; 523261991Sdim bits<10> code_; 524261991Sdim 525261991Sdim bits<32> Inst; 526261991Sdim 527261991Sdim let Inst{31-26} = 0; 528261991Sdim let Inst{25-21} = rs; 529261991Sdim let Inst{20-16} = rt; 530261991Sdim let Inst{15-6} = code_; 531261991Sdim let Inst{5-0} = funct; 532261991Sdim} 533261991Sdim 534261991Sdimclass TEQI_FM<bits<5> funct> : StdArch { 535261991Sdim bits<5> rs; 536261991Sdim bits<16> imm16; 537261991Sdim 538261991Sdim bits<32> Inst; 539261991Sdim 540261991Sdim let Inst{31-26} = 1; 541261991Sdim let Inst{25-21} = rs; 542261991Sdim let Inst{20-16} = funct; 543261991Sdim let Inst{15-0} = imm16; 544261991Sdim} 545276479Sdim 546276479Sdimclass WAIT_FM : StdArch { 547276479Sdim bits<32> Inst; 548276479Sdim 549276479Sdim let Inst{31-26} = 0x10; 550276479Sdim let Inst{25} = 1; 551276479Sdim let Inst{24-6} = 0; 552276479Sdim let Inst{5-0} = 0x20; 553276479Sdim} 554276479Sdim 555276479Sdimclass EXTS_FM<bits<6> funct> : StdArch { 556276479Sdim bits<5> rt; 557276479Sdim bits<5> rs; 558276479Sdim bits<5> pos; 559276479Sdim bits<5> lenm1; 560276479Sdim 561276479Sdim bits<32> Inst; 562276479Sdim 563276479Sdim let Inst{31-26} = 0x1c; 564276479Sdim let Inst{25-21} = rs; 565276479Sdim let Inst{20-16} = rt; 566276479Sdim let Inst{15-11} = lenm1; 567276479Sdim let Inst{10-6} = pos; 568276479Sdim let Inst{5-0} = funct; 569276479Sdim} 570276479Sdim 571276479Sdimclass MTMR_FM<bits<6> funct> : StdArch { 572276479Sdim bits<5> rs; 573276479Sdim 574276479Sdim bits<32> Inst; 575276479Sdim 576276479Sdim let Inst{31-26} = 0x1c; 577276479Sdim let Inst{25-21} = rs; 578276479Sdim let Inst{20-6} = 0; 579276479Sdim let Inst{5-0} = funct; 580276479Sdim} 581276479Sdim 582276479Sdimclass POP_FM<bits<6> funct> : StdArch { 583276479Sdim bits<5> rd; 584276479Sdim bits<5> rs; 585276479Sdim 586276479Sdim bits<32> Inst; 587276479Sdim 588276479Sdim let Inst{31-26} = 0x1c; 589276479Sdim let Inst{25-21} = rs; 590276479Sdim let Inst{20-16} = 0; 591276479Sdim let Inst{15-11} = rd; 592276479Sdim let Inst{10-6} = 0; 593276479Sdim let Inst{5-0} = funct; 594276479Sdim} 595276479Sdim 596276479Sdimclass SEQ_FM<bits<6> funct> : StdArch { 597276479Sdim bits<5> rd; 598276479Sdim bits<5> rs; 599276479Sdim bits<5> rt; 600276479Sdim 601276479Sdim bits<32> Inst; 602276479Sdim 603276479Sdim let Inst{31-26} = 0x1c; 604276479Sdim let Inst{25-21} = rs; 605276479Sdim let Inst{20-16} = rt; 606276479Sdim let Inst{15-11} = rd; 607276479Sdim let Inst{10-6} = 0; 608276479Sdim let Inst{5-0} = funct; 609276479Sdim} 610276479Sdim 611276479Sdimclass SEQI_FM<bits<6> funct> : StdArch { 612276479Sdim bits<5> rs; 613276479Sdim bits<5> rt; 614276479Sdim bits<10> imm10; 615276479Sdim 616276479Sdim bits<32> Inst; 617276479Sdim 618276479Sdim let Inst{31-26} = 0x1c; 619276479Sdim let Inst{25-21} = rs; 620276479Sdim let Inst{20-16} = rt; 621276479Sdim let Inst{15-6} = imm10; 622276479Sdim let Inst{5-0} = funct; 623276479Sdim} 624276479Sdim 625354979Sdimclass SAA_FM<bits<6> funct> : StdArch { 626354979Sdim bits<5> rt; 627354979Sdim bits<5> rs; 628354979Sdim 629354979Sdim bits<32> Inst; 630354979Sdim 631354979Sdim let Inst{31-26} = 0x1c; 632354979Sdim let Inst{25-21} = rs; 633354979Sdim let Inst{20-16} = rt; 634354979Sdim let Inst{15-6} = 0; 635354979Sdim let Inst{5-0} = funct; 636354979Sdim} 637354979Sdim 638243830Sdim//===----------------------------------------------------------------------===// 639261991Sdim// System calls format <op|code_|funct> 640261991Sdim//===----------------------------------------------------------------------===// 641261991Sdim 642276479Sdimclass SYS_FM<bits<6> funct> : StdArch 643261991Sdim{ 644261991Sdim bits<20> code_; 645261991Sdim bits<32> Inst; 646261991Sdim let Inst{31-26} = 0x0; 647261991Sdim let Inst{25-6} = code_; 648261991Sdim let Inst{5-0} = funct; 649261991Sdim} 650261991Sdim 651261991Sdim//===----------------------------------------------------------------------===// 652261991Sdim// Break instruction format <op|code_1|funct> 653261991Sdim//===----------------------------------------------------------------------===// 654261991Sdim 655276479Sdimclass BRK_FM<bits<6> funct> : StdArch 656261991Sdim{ 657261991Sdim bits<10> code_1; 658261991Sdim bits<10> code_2; 659261991Sdim bits<32> Inst; 660261991Sdim let Inst{31-26} = 0x0; 661261991Sdim let Inst{25-16} = code_1; 662261991Sdim let Inst{15-6} = code_2; 663261991Sdim let Inst{5-0} = funct; 664261991Sdim} 665261991Sdim 666261991Sdim//===----------------------------------------------------------------------===// 667261991Sdim// Exception return format <Cop0|1|0|funct> 668261991Sdim//===----------------------------------------------------------------------===// 669261991Sdim 670296417Sdimclass ER_FM<bits<6> funct, bit LLBit> : StdArch 671261991Sdim{ 672261991Sdim bits<32> Inst; 673261991Sdim let Inst{31-26} = 0x10; 674261991Sdim let Inst{25} = 1; 675296417Sdim let Inst{24-7} = 0; 676296417Sdim let Inst{6} = LLBit; 677261991Sdim let Inst{5-0} = funct; 678261991Sdim} 679261991Sdim 680261991Sdim//===----------------------------------------------------------------------===// 681261991Sdim// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 682261991Sdim//===----------------------------------------------------------------------===// 683261991Sdim 684276479Sdimclass EI_FM<bits<1> sc> : StdArch 685261991Sdim{ 686261991Sdim bits<32> Inst; 687261991Sdim bits<5> rt; 688261991Sdim let Inst{31-26} = 0x10; 689261991Sdim let Inst{25-21} = 0xb; 690261991Sdim let Inst{20-16} = rt; 691261991Sdim let Inst{15-11} = 0xc; 692261991Sdim let Inst{10-6} = 0; 693261991Sdim let Inst{5} = sc; 694261991Sdim let Inst{4-0} = 0; 695261991Sdim} 696261991Sdim 697261991Sdim//===----------------------------------------------------------------------===// 698193323Sed// 699193323Sed// FLOATING POINT INSTRUCTION FORMATS 700193323Sed// 701193323Sed// opcode - operation code. 702193323Sed// fs - src reg. 703193323Sed// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 704193323Sed// fd - dst reg, only used on 3 regs instr. 705193323Sed// fmt - double or single precision. 706193323Sed// funct - combined with opcode field give us an operation code. 707193323Sed// 708193323Sed//===----------------------------------------------------------------------===// 709193323Sed 710193323Sed//===----------------------------------------------------------------------===// 711193323Sed// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 712193323Sed//===----------------------------------------------------------------------===// 713193323Sed 714221345Sdimclass FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 715239462Sdim InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 716193323Sed{ 717193323Sed bits<5> ft; 718193323Sed bits<5> base; 719193323Sed bits<16> imm16; 720193323Sed 721228379Sdim let Opcode = op; 722193323Sed 723193323Sed let Inst{25-21} = base; 724221345Sdim let Inst{20-16} = ft; 725193323Sed let Inst{15-0} = imm16; 726193323Sed} 727193323Sed 728276479Sdimclass ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch { 729249423Sdim bits<5> fd; 730249423Sdim bits<5> fs; 731249423Sdim bits<5> ft; 732193323Sed 733249423Sdim bits<32> Inst; 734193323Sed 735249423Sdim let Inst{31-26} = 0x11; 736193323Sed let Inst{25-21} = fmt; 737221345Sdim let Inst{20-16} = ft; 738193323Sed let Inst{15-11} = fs; 739249423Sdim let Inst{10-6} = fd; 740249423Sdim let Inst{5-0} = funct; 741193323Sed} 742221345Sdim 743276479Sdimclass ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch { 744249423Sdim bits<5> fd; 745249423Sdim bits<5> fs; 746221345Sdim 747249423Sdim bits<32> Inst; 748221345Sdim 749249423Sdim let Inst{31-26} = 0x11; 750249423Sdim let Inst{25-21} = fmt; 751249423Sdim let Inst{20-16} = 0; 752249423Sdim let Inst{15-11} = fs; 753249423Sdim let Inst{10-6} = fd; 754249423Sdim let Inst{5-0} = funct; 755221345Sdim} 756221345Sdim 757276479Sdimclass MFC1_FM<bits<5> funct> : StdArch { 758249423Sdim bits<5> rt; 759249423Sdim bits<5> fs; 760221345Sdim 761249423Sdim bits<32> Inst; 762221345Sdim 763249423Sdim let Inst{31-26} = 0x11; 764249423Sdim let Inst{25-21} = funct; 765249423Sdim let Inst{20-16} = rt; 766221345Sdim let Inst{15-11} = fs; 767249423Sdim let Inst{10-0} = 0; 768226633Sdim} 769226633Sdim 770251662Sdimclass LW_FM<bits<6> op> : StdArch { 771249423Sdim bits<5> rt; 772249423Sdim bits<21> addr; 773226633Sdim 774249423Sdim bits<32> Inst; 775249423Sdim 776249423Sdim let Inst{31-26} = op; 777249423Sdim let Inst{25-21} = addr{20-16}; 778249423Sdim let Inst{20-16} = rt; 779249423Sdim let Inst{15-0} = addr{15-0}; 780226633Sdim} 781226633Sdim 782276479Sdimclass MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch { 783234353Sdim bits<5> fd; 784234353Sdim bits<5> fr; 785234353Sdim bits<5> fs; 786234353Sdim bits<5> ft; 787234353Sdim 788249423Sdim bits<32> Inst; 789249423Sdim 790249423Sdim let Inst{31-26} = 0x13; 791234353Sdim let Inst{25-21} = fr; 792234353Sdim let Inst{20-16} = ft; 793234353Sdim let Inst{15-11} = fs; 794249423Sdim let Inst{10-6} = fd; 795249423Sdim let Inst{5-3} = funct; 796249423Sdim let Inst{2-0} = fmt; 797234353Sdim} 798234353Sdim 799276479Sdimclass LWXC1_FM<bits<6> funct> : StdArch { 800249423Sdim bits<5> fd; 801249423Sdim bits<5> base; 802249423Sdim bits<5> index; 803234353Sdim 804249423Sdim bits<32> Inst; 805234353Sdim 806249423Sdim let Inst{31-26} = 0x13; 807234353Sdim let Inst{25-21} = base; 808234353Sdim let Inst{20-16} = index; 809249423Sdim let Inst{15-11} = 0; 810249423Sdim let Inst{10-6} = fd; 811249423Sdim let Inst{5-0} = funct; 812249423Sdim} 813249423Sdim 814276479Sdimclass SWXC1_FM<bits<6> funct> : StdArch { 815249423Sdim bits<5> fs; 816249423Sdim bits<5> base; 817249423Sdim bits<5> index; 818249423Sdim 819249423Sdim bits<32> Inst; 820249423Sdim 821249423Sdim let Inst{31-26} = 0x13; 822249423Sdim let Inst{25-21} = base; 823249423Sdim let Inst{20-16} = index; 824234353Sdim let Inst{15-11} = fs; 825249423Sdim let Inst{10-6} = 0; 826249423Sdim let Inst{5-0} = funct; 827249423Sdim} 828249423Sdim 829276479Sdimclass BC1F_FM<bit nd, bit tf> : StdArch { 830261991Sdim bits<3> fcc; 831249423Sdim bits<16> offset; 832249423Sdim 833249423Sdim bits<32> Inst; 834249423Sdim 835249423Sdim let Inst{31-26} = 0x11; 836249423Sdim let Inst{25-21} = 0x8; 837261991Sdim let Inst{20-18} = fcc; 838249423Sdim let Inst{17} = nd; 839249423Sdim let Inst{16} = tf; 840249423Sdim let Inst{15-0} = offset; 841249423Sdim} 842249423Sdim 843276479Sdimclass CEQS_FM<bits<5> fmt> : StdArch { 844249423Sdim bits<5> fs; 845249423Sdim bits<5> ft; 846314564Sdim bits<3> fcc; 847249423Sdim bits<4> cond; 848249423Sdim 849249423Sdim bits<32> Inst; 850249423Sdim 851249423Sdim let Inst{31-26} = 0x11; 852249423Sdim let Inst{25-21} = fmt; 853249423Sdim let Inst{20-16} = ft; 854249423Sdim let Inst{15-11} = fs; 855314564Sdim let Inst{10-8} = fcc; 856249423Sdim let Inst{7-4} = 0x3; 857249423Sdim let Inst{3-0} = cond; 858249423Sdim} 859249423Sdim 860261991Sdimclass C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 861261991Sdim let cond = c; 862261991Sdim} 863261991Sdim 864276479Sdimclass CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch { 865249423Sdim bits<5> fd; 866249423Sdim bits<5> fs; 867249423Sdim bits<5> rt; 868249423Sdim 869249423Sdim bits<32> Inst; 870249423Sdim 871249423Sdim let Inst{31-26} = 0x11; 872249423Sdim let Inst{25-21} = fmt; 873249423Sdim let Inst{20-16} = rt; 874249423Sdim let Inst{15-11} = fs; 875234353Sdim let Inst{10-6} = fd; 876234353Sdim let Inst{5-0} = funct; 877234353Sdim} 878249423Sdim 879261991Sdimclass CMov_F_I_FM<bit tf> : StdArch { 880249423Sdim bits<5> rd; 881249423Sdim bits<5> rs; 882261991Sdim bits<3> fcc; 883249423Sdim 884249423Sdim bits<32> Inst; 885249423Sdim 886249423Sdim let Inst{31-26} = 0; 887249423Sdim let Inst{25-21} = rs; 888261991Sdim let Inst{20-18} = fcc; 889249423Sdim let Inst{17} = 0; 890249423Sdim let Inst{16} = tf; 891249423Sdim let Inst{15-11} = rd; 892249423Sdim let Inst{10-6} = 0; 893249423Sdim let Inst{5-0} = 1; 894249423Sdim} 895249423Sdim 896276479Sdimclass CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch { 897249423Sdim bits<5> fd; 898249423Sdim bits<5> fs; 899261991Sdim bits<3> fcc; 900249423Sdim 901249423Sdim bits<32> Inst; 902249423Sdim 903249423Sdim let Inst{31-26} = 0x11; 904249423Sdim let Inst{25-21} = fmt; 905261991Sdim let Inst{20-18} = fcc; 906249423Sdim let Inst{17} = 0; 907249423Sdim let Inst{16} = tf; 908249423Sdim let Inst{15-11} = fs; 909249423Sdim let Inst{10-6} = fd; 910249423Sdim let Inst{5-0} = 0x11; 911249423Sdim} 912276479Sdim 913276479Sdimclass BARRIER_FM<bits<5> op> : StdArch { 914276479Sdim bits<32> Inst; 915276479Sdim 916276479Sdim let Inst{31-26} = 0; // SPECIAL 917276479Sdim let Inst{25-21} = 0; 918276479Sdim let Inst{20-16} = 0; // rt = 0 919276479Sdim let Inst{15-11} = 0; // rd = 0 920276479Sdim let Inst{10-6} = op; // Operation 921276479Sdim let Inst{5-0} = 0; // SLL 922276479Sdim} 923276479Sdim 924276479Sdimclass SDBBP_FM : StdArch { 925276479Sdim bits<20> code_; 926276479Sdim 927276479Sdim bits<32> Inst; 928276479Sdim 929276479Sdim let Inst{31-26} = 0b011100; // SPECIAL2 930276479Sdim let Inst{25-6} = code_; 931276479Sdim let Inst{5-0} = 0b111111; // SDBBP 932276479Sdim} 933276479Sdim 934276479Sdimclass JR_HB_FM<bits<6> op> : StdArch{ 935276479Sdim bits<5> rs; 936276479Sdim 937276479Sdim bits<32> Inst; 938276479Sdim 939276479Sdim let Inst{31-26} = 0; // SPECIAL 940276479Sdim let Inst{25-21} = rs; 941276479Sdim let Inst{20-11} = 0; 942276479Sdim let Inst{10} = 1; 943276479Sdim let Inst{9-6} = 0; 944276479Sdim let Inst{5-0} = op; 945276479Sdim} 946276479Sdim 947276479Sdimclass JALR_HB_FM<bits<6> op> : StdArch { 948276479Sdim bits<5> rd; 949276479Sdim bits<5> rs; 950276479Sdim 951276479Sdim bits<32> Inst; 952276479Sdim 953276479Sdim let Inst{31-26} = 0; // SPECIAL 954276479Sdim let Inst{25-21} = rs; 955276479Sdim let Inst{20-16} = 0; 956276479Sdim let Inst{15-11} = rd; 957276479Sdim let Inst{10} = 1; 958276479Sdim let Inst{9-6} = 0; 959276479Sdim let Inst{5-0} = op; 960276479Sdim} 961276479Sdim 962276479Sdimclass COP0_TLB_FM<bits<6> op> : StdArch { 963276479Sdim bits<32> Inst; 964276479Sdim 965276479Sdim let Inst{31-26} = 0x10; // COP0 966276479Sdim let Inst{25} = 1; // CO 967276479Sdim let Inst{24-6} = 0; 968276479Sdim let Inst{5-0} = op; // Operation 969276479Sdim} 970276479Sdim 971276479Sdimclass CACHEOP_FM<bits<6> op> : StdArch { 972276479Sdim bits<21> addr; 973276479Sdim bits<5> hint; 974276479Sdim bits<5> base = addr{20-16}; 975276479Sdim bits<16> offset = addr{15-0}; 976276479Sdim 977276479Sdim bits<32> Inst; 978276479Sdim 979276479Sdim let Inst{31-26} = op; 980276479Sdim let Inst{25-21} = base; 981276479Sdim let Inst{20-16} = hint; 982276479Sdim let Inst{15-0} = offset; 983276479Sdim} 984341825Sdim 985341825Sdimclass HYPCALL_FM<bits<6> op> : StdArch { 986341825Sdim bits<10> code_; 987341825Sdim 988341825Sdim bits<32> Inst; 989341825Sdim 990341825Sdim let Inst{31-26} = 0b010000; 991341825Sdim let Inst{25} = 1; 992341825Sdim let Inst{20-11} = code_; 993341825Sdim let Inst{5-0} = op; 994341825Sdim} 995