MipsDelaySlotFiller.cpp revision 341825
1327952Sdim//===- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler -------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10249423Sdim// Simple pass to fill delay slots with useful instructions. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14276479Sdim#include "MCTargetDesc/MipsMCNaCl.h" 15193323Sed#include "Mips.h" 16249423Sdim#include "MipsInstrInfo.h" 17327952Sdim#include "MipsRegisterInfo.h" 18321369Sdim#include "MipsSubtarget.h" 19249423Sdim#include "llvm/ADT/BitVector.h" 20321369Sdim#include "llvm/ADT/DenseMap.h" 21321369Sdim#include "llvm/ADT/PointerUnion.h" 22249423Sdim#include "llvm/ADT/SmallPtrSet.h" 23321369Sdim#include "llvm/ADT/SmallVector.h" 24249423Sdim#include "llvm/ADT/Statistic.h" 25321369Sdim#include "llvm/ADT/StringRef.h" 26249423Sdim#include "llvm/Analysis/AliasAnalysis.h" 27249423Sdim#include "llvm/Analysis/ValueTracking.h" 28321369Sdim#include "llvm/CodeGen/MachineBasicBlock.h" 29249423Sdim#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 30321369Sdim#include "llvm/CodeGen/MachineFunction.h" 31193323Sed#include "llvm/CodeGen/MachineFunctionPass.h" 32321369Sdim#include "llvm/CodeGen/MachineInstr.h" 33193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 34321369Sdim#include "llvm/CodeGen/MachineOperand.h" 35276479Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 36249423Sdim#include "llvm/CodeGen/PseudoSourceValue.h" 37327952Sdim#include "llvm/CodeGen/TargetRegisterInfo.h" 38327952Sdim#include "llvm/CodeGen/TargetSubtargetInfo.h" 39321369Sdim#include "llvm/MC/MCInstrDesc.h" 40321369Sdim#include "llvm/MC/MCRegisterInfo.h" 41321369Sdim#include "llvm/Support/Casting.h" 42321369Sdim#include "llvm/Support/CodeGen.h" 43226633Sdim#include "llvm/Support/CommandLine.h" 44321369Sdim#include "llvm/Support/ErrorHandling.h" 45226633Sdim#include "llvm/Target/TargetMachine.h" 46321369Sdim#include <algorithm> 47321369Sdim#include <cassert> 48321369Sdim#include <iterator> 49321369Sdim#include <memory> 50321369Sdim#include <utility> 51193323Sed 52193323Sedusing namespace llvm; 53193323Sed 54341825Sdim#define DEBUG_TYPE "mips-delay-slot-filler" 55276479Sdim 56193323SedSTATISTIC(FilledSlots, "Number of delay slots filled"); 57226633SdimSTATISTIC(UsefulSlots, "Number of delay slots filled with instructions that" 58226633Sdim " are not NOP."); 59193323Sed 60243830Sdimstatic cl::opt<bool> DisableDelaySlotFiller( 61243830Sdim "disable-mips-delay-filler", 62226633Sdim cl::init(false), 63249423Sdim cl::desc("Fill all delay slots with NOPs."), 64226633Sdim cl::Hidden); 65226633Sdim 66249423Sdimstatic cl::opt<bool> DisableForwardSearch( 67249423Sdim "disable-mips-df-forward-search", 68249423Sdim cl::init(true), 69249423Sdim cl::desc("Disallow MIPS delay filler to search forward."), 70249423Sdim cl::Hidden); 71249423Sdim 72249423Sdimstatic cl::opt<bool> DisableSuccBBSearch( 73249423Sdim "disable-mips-df-succbb-search", 74249423Sdim cl::init(true), 75249423Sdim cl::desc("Disallow MIPS delay filler to search successor basic blocks."), 76249423Sdim cl::Hidden); 77249423Sdim 78249423Sdimstatic cl::opt<bool> DisableBackwardSearch( 79249423Sdim "disable-mips-df-backward-search", 80239462Sdim cl::init(false), 81249423Sdim cl::desc("Disallow MIPS delay filler to search backward."), 82239462Sdim cl::Hidden); 83239462Sdim 84309124Sdimenum CompactBranchPolicy { 85309124Sdim CB_Never, ///< The policy 'never' may in some circumstances or for some 86309124Sdim ///< ISAs not be absolutely adhered to. 87309124Sdim CB_Optimal, ///< Optimal is the default and will produce compact branches 88309124Sdim ///< when delay slots cannot be filled. 89309124Sdim CB_Always ///< 'always' may in some circumstances may not be 90309124Sdim ///< absolutely adhered to there may not be a corresponding 91309124Sdim ///< compact form of a branch. 92309124Sdim}; 93309124Sdim 94309124Sdimstatic cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy( 95309124Sdim "mips-compact-branches",cl::Optional, 96309124Sdim cl::init(CB_Optimal), 97309124Sdim cl::desc("MIPS Specific: Compact branch policy."), 98309124Sdim cl::values( 99309124Sdim clEnumValN(CB_Never, "never", "Do not use compact branches if possible."), 100309124Sdim clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."), 101314564Sdim clEnumValN(CB_Always, "always", "Always use compact branches if possible.") 102309124Sdim ) 103309124Sdim); 104309124Sdim 105193323Sednamespace { 106321369Sdim 107327952Sdim using Iter = MachineBasicBlock::iterator; 108327952Sdim using ReverseIter = MachineBasicBlock::reverse_iterator; 109327952Sdim using BB2BrMap = SmallDenseMap<MachineBasicBlock *, MachineInstr *, 2>; 110193323Sed 111249423Sdim class RegDefsUses { 112249423Sdim public: 113288943Sdim RegDefsUses(const TargetRegisterInfo &TRI); 114321369Sdim 115249423Sdim void init(const MachineInstr &MI); 116249423Sdim 117249423Sdim /// This function sets all caller-saved registers in Defs. 118249423Sdim void setCallerSaved(const MachineInstr &MI); 119249423Sdim 120249423Sdim /// This function sets all unallocatable registers in Defs. 121249423Sdim void setUnallocatableRegs(const MachineFunction &MF); 122249423Sdim 123249423Sdim /// Set bits in Uses corresponding to MBB's live-out registers except for 124249423Sdim /// the registers that are live-in to SuccBB. 125249423Sdim void addLiveOut(const MachineBasicBlock &MBB, 126249423Sdim const MachineBasicBlock &SuccBB); 127249423Sdim 128249423Sdim bool update(const MachineInstr &MI, unsigned Begin, unsigned End); 129249423Sdim 130249423Sdim private: 131249423Sdim bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, 132249423Sdim bool IsDef) const; 133249423Sdim 134249423Sdim /// Returns true if Reg or its alias is in RegSet. 135249423Sdim bool isRegInSet(const BitVector &RegSet, unsigned Reg) const; 136249423Sdim 137249423Sdim const TargetRegisterInfo &TRI; 138249423Sdim BitVector Defs, Uses; 139249423Sdim }; 140249423Sdim 141249423Sdim /// Base class for inspecting loads and stores. 142249423Sdim class InspectMemInstr { 143249423Sdim public: 144321369Sdim InspectMemInstr(bool ForbidMemInstr_) : ForbidMemInstr(ForbidMemInstr_) {} 145321369Sdim virtual ~InspectMemInstr() = default; 146249423Sdim 147249423Sdim /// Return true if MI cannot be moved to delay slot. 148249423Sdim bool hasHazard(const MachineInstr &MI); 149249423Sdim 150249423Sdim protected: 151249423Sdim /// Flags indicating whether loads or stores have been seen. 152321369Sdim bool OrigSeenLoad = false; 153321369Sdim bool OrigSeenStore = false; 154321369Sdim bool SeenLoad = false; 155321369Sdim bool SeenStore = false; 156249423Sdim 157249423Sdim /// Memory instructions are not allowed to move to delay slot if this flag 158249423Sdim /// is true. 159249423Sdim bool ForbidMemInstr; 160249423Sdim 161249423Sdim private: 162249423Sdim virtual bool hasHazard_(const MachineInstr &MI) = 0; 163249423Sdim }; 164249423Sdim 165249423Sdim /// This subclass rejects any memory instructions. 166249423Sdim class NoMemInstr : public InspectMemInstr { 167249423Sdim public: 168249423Sdim NoMemInstr() : InspectMemInstr(true) {} 169321369Sdim 170249423Sdim private: 171276479Sdim bool hasHazard_(const MachineInstr &MI) override { return true; } 172249423Sdim }; 173249423Sdim 174249423Sdim /// This subclass accepts loads from stacks and constant loads. 175249423Sdim class LoadFromStackOrConst : public InspectMemInstr { 176249423Sdim public: 177249423Sdim LoadFromStackOrConst() : InspectMemInstr(false) {} 178321369Sdim 179249423Sdim private: 180276479Sdim bool hasHazard_(const MachineInstr &MI) override; 181249423Sdim }; 182249423Sdim 183249423Sdim /// This subclass uses memory dependence information to determine whether a 184249423Sdim /// memory instruction can be moved to a delay slot. 185249423Sdim class MemDefsUses : public InspectMemInstr { 186249423Sdim public: 187288943Sdim MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI); 188249423Sdim 189249423Sdim private: 190327952Sdim using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>; 191249423Sdim 192276479Sdim bool hasHazard_(const MachineInstr &MI) override; 193276479Sdim 194249423Sdim /// Update Defs and Uses. Return true if there exist dependences that 195249423Sdim /// disqualify the delay slot candidate between V and values in Uses and 196249423Sdim /// Defs. 197276479Sdim bool updateDefsUses(ValueType V, bool MayStore); 198249423Sdim 199249423Sdim /// Get the list of underlying objects of MI's memory operand. 200249423Sdim bool getUnderlyingObjects(const MachineInstr &MI, 201276479Sdim SmallVectorImpl<ValueType> &Objects) const; 202249423Sdim 203249423Sdim const MachineFrameInfo *MFI; 204276479Sdim SmallPtrSet<ValueType, 4> Uses, Defs; 205288943Sdim const DataLayout &DL; 206249423Sdim 207249423Sdim /// Flags indicating whether loads or stores with no underlying objects have 208249423Sdim /// been seen. 209321369Sdim bool SeenNoObjLoad = false; 210321369Sdim bool SeenNoObjStore = false; 211249423Sdim }; 212249423Sdim 213341825Sdim class MipsDelaySlotFiller : public MachineFunctionPass { 214249423Sdim public: 215341825Sdim MipsDelaySlotFiller() : MachineFunctionPass(ID) { 216341825Sdim initializeMipsDelaySlotFillerPass(*PassRegistry::getPassRegistry()); 217341825Sdim } 218193323Sed 219314564Sdim StringRef getPassName() const override { return "Mips Delay Slot Filler"; } 220193323Sed 221276479Sdim bool runOnMachineFunction(MachineFunction &F) override { 222321369Sdim TM = &F.getTarget(); 223193323Sed bool Changed = false; 224193323Sed for (MachineFunction::iterator FI = F.begin(), FE = F.end(); 225193323Sed FI != FE; ++FI) 226193323Sed Changed |= runOnMachineBasicBlock(*FI); 227276479Sdim 228276479Sdim // This pass invalidates liveness information when it reorders 229276479Sdim // instructions to fill delay slot. Without this, -verify-machineinstrs 230276479Sdim // will fail. 231276479Sdim if (Changed) 232276479Sdim F.getRegInfo().invalidateLiveness(); 233276479Sdim 234193323Sed return Changed; 235193323Sed } 236193323Sed 237309124Sdim MachineFunctionProperties getRequiredProperties() const override { 238309124Sdim return MachineFunctionProperties().set( 239314564Sdim MachineFunctionProperties::Property::NoVRegs); 240309124Sdim } 241309124Sdim 242276479Sdim void getAnalysisUsage(AnalysisUsage &AU) const override { 243249423Sdim AU.addRequired<MachineBranchProbabilityInfo>(); 244249423Sdim MachineFunctionPass::getAnalysisUsage(AU); 245249423Sdim } 246226633Sdim 247341825Sdim static char ID; 248341825Sdim 249249423Sdim private: 250249423Sdim bool runOnMachineBasicBlock(MachineBasicBlock &MBB); 251226633Sdim 252309124Sdim Iter replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch, 253309124Sdim const DebugLoc &DL); 254280031Sdim 255249423Sdim /// This function checks if it is valid to move Candidate to the delay slot 256249423Sdim /// and returns true if it isn't. It also updates memory and register 257249423Sdim /// dependence information. 258249423Sdim bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU, 259249423Sdim InspectMemInstr &IM) const; 260226633Sdim 261249423Sdim /// This function searches range [Begin, End) for an instruction that can be 262249423Sdim /// moved to the delay slot. Returns true on success. 263249423Sdim template<typename IterTy> 264249423Sdim bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, 265288943Sdim RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot, 266288943Sdim IterTy &Filler) const; 267226633Sdim 268249423Sdim /// This function searches in the backward direction for an instruction that 269249423Sdim /// can be moved to the delay slot. Returns true on success. 270314564Sdim bool searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const; 271226633Sdim 272249423Sdim /// This function searches MBB in the forward direction for an instruction 273249423Sdim /// that can be moved to the delay slot. Returns true on success. 274249423Sdim bool searchForward(MachineBasicBlock &MBB, Iter Slot) const; 275226633Sdim 276249423Sdim /// This function searches one of MBB's successor blocks for an instruction 277249423Sdim /// that can be moved to the delay slot and inserts clones of the 278249423Sdim /// instruction into the successor's predecessor blocks. 279249423Sdim bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const; 280226633Sdim 281249423Sdim /// Pick a successor block of MBB. Return NULL if MBB doesn't have a 282249423Sdim /// successor block that is not a landing pad. 283249423Sdim MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const; 284249423Sdim 285249423Sdim /// This function analyzes MBB and returns an instruction with an unoccupied 286249423Sdim /// slot that branches to Dst. 287249423Sdim std::pair<MipsInstrInfo::BranchType, MachineInstr *> 288249423Sdim getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const; 289249423Sdim 290249423Sdim /// Examine Pred and see if it is possible to insert an instruction into 291249423Sdim /// one of its branches delay slot or its end. 292249423Sdim bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 293249423Sdim RegDefsUses &RegDU, bool &HasMultipleSuccs, 294249423Sdim BB2BrMap &BrMap) const; 295249423Sdim 296249423Sdim bool terminateSearch(const MachineInstr &Candidate) const; 297249423Sdim 298327952Sdim const TargetMachine *TM = nullptr; 299193323Sed }; 300321369Sdim 301321369Sdim} // end anonymous namespace 302321369Sdim 303341825Sdimchar MipsDelaySlotFiller::ID = 0; 304327952Sdim 305249423Sdimstatic bool hasUnoccupiedSlot(const MachineInstr *MI) { 306249423Sdim return MI->hasDelaySlot() && !MI->isBundledWithSucc(); 307249423Sdim} 308249423Sdim 309341825SdimINITIALIZE_PASS(MipsDelaySlotFiller, DEBUG_TYPE, 310341825Sdim "Fill delay slot for MIPS", false, false) 311341825Sdim 312249423Sdim/// This function inserts clones of Filler into predecessor blocks. 313249423Sdimstatic void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) { 314249423Sdim MachineFunction *MF = Filler->getParent()->getParent(); 315249423Sdim 316249423Sdim for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) { 317249423Sdim if (I->second) { 318249423Sdim MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler)); 319249423Sdim ++UsefulSlots; 320249423Sdim } else { 321249423Sdim I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler)); 322249423Sdim } 323249423Sdim } 324249423Sdim} 325249423Sdim 326249423Sdim/// This function adds registers Filler defines to MBB's live-in register list. 327249423Sdimstatic void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) { 328249423Sdim for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) { 329249423Sdim const MachineOperand &MO = Filler->getOperand(I); 330249423Sdim unsigned R; 331249423Sdim 332249423Sdim if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg())) 333249423Sdim continue; 334249423Sdim 335249423Sdim#ifndef NDEBUG 336249423Sdim const MachineFunction &MF = *MBB.getParent(); 337288943Sdim assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && 338249423Sdim "Shouldn't move an instruction with unallocatable registers across " 339249423Sdim "basic block boundaries."); 340249423Sdim#endif 341249423Sdim 342249423Sdim if (!MBB.isLiveIn(R)) 343249423Sdim MBB.addLiveIn(R); 344249423Sdim } 345249423Sdim} 346249423Sdim 347288943SdimRegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI) 348288943Sdim : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} 349249423Sdim 350249423Sdimvoid RegDefsUses::init(const MachineInstr &MI) { 351249423Sdim // Add all register operands which are explicit and non-variadic. 352249423Sdim update(MI, 0, MI.getDesc().getNumOperands()); 353249423Sdim 354249423Sdim // If MI is a call, add RA to Defs to prevent users of RA from going into 355249423Sdim // delay slot. 356249423Sdim if (MI.isCall()) 357249423Sdim Defs.set(Mips::RA); 358249423Sdim 359249423Sdim // Add all implicit register operands of branch instructions except 360249423Sdim // register AT. 361249423Sdim if (MI.isBranch()) { 362249423Sdim update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands()); 363249423Sdim Defs.reset(Mips::AT); 364249423Sdim } 365249423Sdim} 366249423Sdim 367249423Sdimvoid RegDefsUses::setCallerSaved(const MachineInstr &MI) { 368249423Sdim assert(MI.isCall()); 369249423Sdim 370288943Sdim // Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into 371288943Sdim // the delay slot. The reason is that RA/RA_64 must not be changed 372288943Sdim // in the delay slot so that the callee can return to the caller. 373288943Sdim if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) { 374288943Sdim Defs.set(Mips::RA); 375288943Sdim Defs.set(Mips::RA_64); 376288943Sdim } 377288943Sdim 378249423Sdim // If MI is a call, add all caller-saved registers to Defs. 379249423Sdim BitVector CallerSavedRegs(TRI.getNumRegs(), true); 380249423Sdim 381249423Sdim CallerSavedRegs.reset(Mips::ZERO); 382249423Sdim CallerSavedRegs.reset(Mips::ZERO_64); 383249423Sdim 384288943Sdim for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent()); 385288943Sdim *R; ++R) 386249423Sdim for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI) 387249423Sdim CallerSavedRegs.reset(*AI); 388249423Sdim 389249423Sdim Defs |= CallerSavedRegs; 390249423Sdim} 391249423Sdim 392249423Sdimvoid RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) { 393249423Sdim BitVector AllocSet = TRI.getAllocatableSet(MF); 394249423Sdim 395321369Sdim for (unsigned R : AllocSet.set_bits()) 396249423Sdim for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI) 397249423Sdim AllocSet.set(*AI); 398249423Sdim 399249423Sdim AllocSet.set(Mips::ZERO); 400249423Sdim AllocSet.set(Mips::ZERO_64); 401249423Sdim 402249423Sdim Defs |= AllocSet.flip(); 403249423Sdim} 404249423Sdim 405249423Sdimvoid RegDefsUses::addLiveOut(const MachineBasicBlock &MBB, 406249423Sdim const MachineBasicBlock &SuccBB) { 407249423Sdim for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), 408249423Sdim SE = MBB.succ_end(); SI != SE; ++SI) 409249423Sdim if (*SI != &SuccBB) 410296417Sdim for (const auto &LI : (*SI)->liveins()) 411296417Sdim Uses.set(LI.PhysReg); 412249423Sdim} 413249423Sdim 414249423Sdimbool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) { 415249423Sdim BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs()); 416249423Sdim bool HasHazard = false; 417249423Sdim 418249423Sdim for (unsigned I = Begin; I != End; ++I) { 419249423Sdim const MachineOperand &MO = MI.getOperand(I); 420249423Sdim 421249423Sdim if (MO.isReg() && MO.getReg()) 422249423Sdim HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef()); 423249423Sdim } 424249423Sdim 425249423Sdim Defs |= NewDefs; 426249423Sdim Uses |= NewUses; 427249423Sdim 428249423Sdim return HasHazard; 429249423Sdim} 430249423Sdim 431249423Sdimbool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, 432249423Sdim unsigned Reg, bool IsDef) const { 433249423Sdim if (IsDef) { 434249423Sdim NewDefs.set(Reg); 435249423Sdim // check whether Reg has already been defined or used. 436249423Sdim return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); 437249423Sdim } 438249423Sdim 439249423Sdim NewUses.set(Reg); 440249423Sdim // check whether Reg has already been defined. 441249423Sdim return isRegInSet(Defs, Reg); 442249423Sdim} 443249423Sdim 444249423Sdimbool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { 445249423Sdim // Check Reg and all aliased Registers. 446249423Sdim for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) 447249423Sdim if (RegSet.test(*AI)) 448249423Sdim return true; 449249423Sdim return false; 450249423Sdim} 451249423Sdim 452249423Sdimbool InspectMemInstr::hasHazard(const MachineInstr &MI) { 453249423Sdim if (!MI.mayStore() && !MI.mayLoad()) 454249423Sdim return false; 455249423Sdim 456249423Sdim if (ForbidMemInstr) 457249423Sdim return true; 458249423Sdim 459249423Sdim OrigSeenLoad = SeenLoad; 460249423Sdim OrigSeenStore = SeenStore; 461249423Sdim SeenLoad |= MI.mayLoad(); 462249423Sdim SeenStore |= MI.mayStore(); 463249423Sdim 464249423Sdim // If MI is an ordered or volatile memory reference, disallow moving 465249423Sdim // subsequent loads and stores to delay slot. 466249423Sdim if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) { 467249423Sdim ForbidMemInstr = true; 468249423Sdim return true; 469249423Sdim } 470249423Sdim 471249423Sdim return hasHazard_(MI); 472249423Sdim} 473249423Sdim 474249423Sdimbool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) { 475249423Sdim if (MI.mayStore()) 476249423Sdim return true; 477249423Sdim 478276479Sdim if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue()) 479249423Sdim return true; 480249423Sdim 481276479Sdim if (const PseudoSourceValue *PSV = 482276479Sdim (*MI.memoperands_begin())->getPseudoValue()) { 483276479Sdim if (isa<FixedStackPseudoSourceValue>(PSV)) 484276479Sdim return false; 485296417Sdim return !PSV->isConstant(nullptr) && !PSV->isStack(); 486276479Sdim } 487249423Sdim 488249423Sdim return true; 489249423Sdim} 490249423Sdim 491288943SdimMemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_) 492321369Sdim : InspectMemInstr(false), MFI(MFI_), DL(DL) {} 493249423Sdim 494249423Sdimbool MemDefsUses::hasHazard_(const MachineInstr &MI) { 495249423Sdim bool HasHazard = false; 496276479Sdim SmallVector<ValueType, 4> Objs; 497249423Sdim 498249423Sdim // Check underlying object list. 499249423Sdim if (getUnderlyingObjects(MI, Objs)) { 500276479Sdim for (SmallVectorImpl<ValueType>::const_iterator I = Objs.begin(); 501249423Sdim I != Objs.end(); ++I) 502249423Sdim HasHazard |= updateDefsUses(*I, MI.mayStore()); 503249423Sdim 504249423Sdim return HasHazard; 505249423Sdim } 506249423Sdim 507249423Sdim // No underlying objects found. 508249423Sdim HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore); 509249423Sdim HasHazard |= MI.mayLoad() || OrigSeenStore; 510249423Sdim 511249423Sdim SeenNoObjLoad |= MI.mayLoad(); 512249423Sdim SeenNoObjStore |= MI.mayStore(); 513249423Sdim 514249423Sdim return HasHazard; 515249423Sdim} 516249423Sdim 517276479Sdimbool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) { 518249423Sdim if (MayStore) 519280031Sdim return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore || 520280031Sdim SeenNoObjLoad; 521249423Sdim 522249423Sdim Uses.insert(V); 523249423Sdim return Defs.count(V) || SeenNoObjStore; 524249423Sdim} 525249423Sdim 526249423Sdimbool MemDefsUses:: 527249423SdimgetUnderlyingObjects(const MachineInstr &MI, 528276479Sdim SmallVectorImpl<ValueType> &Objects) const { 529276479Sdim if (!MI.hasOneMemOperand() || 530276479Sdim (!(*MI.memoperands_begin())->getValue() && 531276479Sdim !(*MI.memoperands_begin())->getPseudoValue())) 532249423Sdim return false; 533249423Sdim 534276479Sdim if (const PseudoSourceValue *PSV = 535276479Sdim (*MI.memoperands_begin())->getPseudoValue()) { 536276479Sdim if (!PSV->isAliased(MFI)) 537276479Sdim return false; 538276479Sdim Objects.push_back(PSV); 539276479Sdim return true; 540276479Sdim } 541276479Sdim 542249423Sdim const Value *V = (*MI.memoperands_begin())->getValue(); 543249423Sdim 544249423Sdim SmallVector<Value *, 4> Objs; 545288943Sdim GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL); 546249423Sdim 547261991Sdim for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end(); 548249423Sdim I != E; ++I) { 549276479Sdim if (!isIdentifiedObject(V)) 550249423Sdim return false; 551249423Sdim 552249423Sdim Objects.push_back(*I); 553249423Sdim } 554249423Sdim 555249423Sdim return true; 556249423Sdim} 557249423Sdim 558280031Sdim// Replace Branch with the compact branch instruction. 559341825SdimIter MipsDelaySlotFiller::replaceWithCompactBranch(MachineBasicBlock &MBB, 560341825Sdim Iter Branch, 561341825Sdim const DebugLoc &DL) { 562309124Sdim const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 563309124Sdim const MipsInstrInfo *TII = STI.getInstrInfo(); 564280031Sdim 565309124Sdim unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); 566309124Sdim Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); 567280031Sdim 568309124Sdim std::next(Branch)->eraseFromParent(); 569280031Sdim return Branch; 570280031Sdim} 571280031Sdim 572280031Sdim// For given opcode returns opcode of corresponding instruction with short 573280031Sdim// delay slot. 574321369Sdim// For the pseudo TAILCALL*_MM instructions return the short delay slot 575314564Sdim// form. Unfortunately, TAILCALL<->b16 is denied as b16 has a limited range 576314564Sdim// that is too short to make use of for tail calls. 577280031Sdimstatic int getEquivalentCallShort(int Opcode) { 578280031Sdim switch (Opcode) { 579280031Sdim case Mips::BGEZAL: 580280031Sdim return Mips::BGEZALS_MM; 581280031Sdim case Mips::BLTZAL: 582280031Sdim return Mips::BLTZALS_MM; 583280031Sdim case Mips::JAL: 584341825Sdim case Mips::JAL_MM: 585280031Sdim return Mips::JALS_MM; 586280031Sdim case Mips::JALR: 587280031Sdim return Mips::JALRS_MM; 588280031Sdim case Mips::JALR16_MM: 589280031Sdim return Mips::JALRS16_MM; 590314564Sdim case Mips::TAILCALL_MM: 591314564Sdim llvm_unreachable("Attempting to shorten the TAILCALL_MM pseudo!"); 592314564Sdim case Mips::TAILCALLREG: 593314564Sdim return Mips::JR16_MM; 594280031Sdim default: 595280031Sdim llvm_unreachable("Unexpected call instruction for microMIPS."); 596280031Sdim } 597280031Sdim} 598280031Sdim 599193323Sed/// runOnMachineBasicBlock - Fill in delay slots for the given basic block. 600226633Sdim/// We assume there is only one delay slot per delayed instruction. 601341825Sdimbool MipsDelaySlotFiller::runOnMachineBasicBlock(MachineBasicBlock &MBB) { 602193323Sed bool Changed = false; 603288943Sdim const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 604288943Sdim bool InMicroMipsMode = STI.inMicroMipsMode(); 605288943Sdim const MipsInstrInfo *TII = STI.getInstrInfo(); 606226633Sdim 607249423Sdim for (Iter I = MBB.begin(); I != MBB.end(); ++I) { 608249423Sdim if (!hasUnoccupiedSlot(&*I)) 609249423Sdim continue; 610218893Sdim 611327952Sdim // Delay slot filling is disabled at -O0, or in microMIPS32R6. 612327952Sdim if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) && 613327952Sdim !(InMicroMipsMode && STI.hasMips32r6())) { 614226633Sdim 615280031Sdim bool Filled = false; 616226633Sdim 617309124Sdim if (MipsCompactBranchPolicy.getValue() != CB_Always || 618309124Sdim !TII->getEquivalentCompactForm(I)) { 619314564Sdim if (searchBackward(MBB, *I)) { 620280031Sdim Filled = true; 621309124Sdim } else if (I->isTerminator()) { 622309124Sdim if (searchSuccBBs(MBB, I)) { 623309124Sdim Filled = true; 624309124Sdim } 625309124Sdim } else if (searchForward(MBB, I)) { 626309124Sdim Filled = true; 627280031Sdim } 628280031Sdim } 629280031Sdim 630280031Sdim if (Filled) { 631280031Sdim // Get instruction with delay slot. 632309124Sdim MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); 633280031Sdim 634314564Sdim if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && 635280031Sdim DSI->isCall()) { 636280031Sdim // If instruction in delay slot is 16b change opcode to 637280031Sdim // corresponding instruction with short delay slot. 638314564Sdim 639314564Sdim // TODO: Implement an instruction mapping table of 16bit opcodes to 640314564Sdim // 32bit opcodes so that an instruction can be expanded. This would 641314564Sdim // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop. 642341825Sdim // TODO: Permit b16 when branching backwards to the same function 643314564Sdim // if it is in range. 644280031Sdim DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); 645280031Sdim } 646327952Sdim ++FilledSlots; 647327952Sdim Changed = true; 648249423Sdim continue; 649249423Sdim } 650249423Sdim } 651239462Sdim 652309124Sdim // For microMIPS if instruction is BEQ or BNE with one ZERO register, then 653309124Sdim // instead of adding NOP replace this instruction with the corresponding 654309124Sdim // compact branch instruction, i.e. BEQZC or BNEZC. Additionally 655309124Sdim // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can 656309124Sdim // be replaced with JRC16_MM. 657309124Sdim 658309124Sdim // For MIPSR6 attempt to produce the corresponding compact (no delay slot) 659309124Sdim // form of the CTI. For indirect jumps this will not require inserting a 660309124Sdim // NOP and for branches will hopefully avoid requiring a NOP. 661309124Sdim if ((InMicroMipsMode || 662309124Sdim (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) && 663309124Sdim TII->getEquivalentCompactForm(I)) { 664309124Sdim I = replaceWithCompactBranch(MBB, I, I->getDebugLoc()); 665327952Sdim Changed = true; 666309124Sdim continue; 667280031Sdim } 668309124Sdim 669288943Sdim // Bundle the NOP to the instruction with the delay slot. 670288943Sdim BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); 671288943Sdim MIBundleBuilder(MBB, I, std::next(I, 2)); 672327952Sdim ++FilledSlots; 673327952Sdim Changed = true; 674249423Sdim } 675249423Sdim 676193323Sed return Changed; 677193323Sed} 678193323Sed 679341825Sdimtemplate <typename IterTy> 680341825Sdimbool MipsDelaySlotFiller::searchRange(MachineBasicBlock &MBB, IterTy Begin, 681341825Sdim IterTy End, RegDefsUses &RegDU, 682341825Sdim InspectMemInstr &IM, Iter Slot, 683341825Sdim IterTy &Filler) const { 684288943Sdim for (IterTy I = Begin; I != End;) { 685288943Sdim IterTy CurrI = I; 686288943Sdim ++I; 687288943Sdim 688226633Sdim // skip debug value 689341825Sdim if (CurrI->isDebugInstr()) 690226633Sdim continue; 691226633Sdim 692288943Sdim if (terminateSearch(*CurrI)) 693226633Sdim break; 694226633Sdim 695288943Sdim assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) && 696249423Sdim "Cannot put calls, returns or branches in delay slot."); 697249423Sdim 698288943Sdim if (CurrI->isKill()) { 699288943Sdim CurrI->eraseFromParent(); 700226633Sdim continue; 701288943Sdim } 702226633Sdim 703288943Sdim if (delayHasHazard(*CurrI, RegDU, IM)) 704288943Sdim continue; 705288943Sdim 706288943Sdim const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 707288943Sdim if (STI.isTargetNaCl()) { 708276479Sdim // In NaCl, instructions that must be masked are forbidden in delay slots. 709276479Sdim // We only check for loads, stores and SP changes. Calls, returns and 710276479Sdim // branches are not checked because non-NaCl targets never put them in 711276479Sdim // delay slots. 712276479Sdim unsigned AddrIdx; 713288943Sdim if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) && 714288943Sdim baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) || 715288943Sdim CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo())) 716276479Sdim continue; 717276479Sdim } 718276479Sdim 719288943Sdim bool InMicroMipsMode = STI.inMicroMipsMode(); 720288943Sdim const MipsInstrInfo *TII = STI.getInstrInfo(); 721280031Sdim unsigned Opcode = (*Slot).getOpcode(); 722314564Sdim // This is complicated by the tail call optimization. For non-PIC code 723314564Sdim // there is only a 32bit sized unconditional branch which can be assumed 724314564Sdim // to be able to reach the target. b16 only has a range of +/- 1 KB. 725314564Sdim // It's entirely possible that the target function is reachable with b16 726314564Sdim // but we don't have enough information to make that decision. 727314564Sdim if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 && 728280031Sdim (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || 729314564Sdim Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL)) 730280031Sdim continue; 731341825Sdim // Instructions LWP/SWP should not be in a delay slot as that 732341825Sdim // results in unpredictable behaviour 733341825Sdim if (InMicroMipsMode && (Opcode == Mips::LWP_MM || Opcode == Mips::SWP_MM)) 734341825Sdim continue; 735280031Sdim 736288943Sdim Filler = CurrI; 737226633Sdim return true; 738226633Sdim } 739226633Sdim 740226633Sdim return false; 741226633Sdim} 742226633Sdim 743341825Sdimbool MipsDelaySlotFiller::searchBackward(MachineBasicBlock &MBB, 744341825Sdim MachineInstr &Slot) const { 745249423Sdim if (DisableBackwardSearch) 746249423Sdim return false; 747226633Sdim 748296417Sdim auto *Fn = MBB.getParent(); 749296417Sdim RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo()); 750314564Sdim MemDefsUses MemDU(Fn->getDataLayout(), &Fn->getFrameInfo()); 751249423Sdim ReverseIter Filler; 752226633Sdim 753314564Sdim RegDU.init(Slot); 754249423Sdim 755314564Sdim MachineBasicBlock::iterator SlotI = Slot; 756314564Sdim if (!searchRange(MBB, ++SlotI.getReverse(), MBB.rend(), RegDU, MemDU, Slot, 757288943Sdim Filler)) 758261991Sdim return false; 759226633Sdim 760314564Sdim MBB.splice(std::next(SlotI), &MBB, Filler.getReverse()); 761314564Sdim MIBundleBuilder(MBB, SlotI, std::next(SlotI, 2)); 762261991Sdim ++UsefulSlots; 763261991Sdim return true; 764249423Sdim} 765226633Sdim 766341825Sdimbool MipsDelaySlotFiller::searchForward(MachineBasicBlock &MBB, 767341825Sdim Iter Slot) const { 768249423Sdim // Can handle only calls. 769249423Sdim if (DisableForwardSearch || !Slot->isCall()) 770249423Sdim return false; 771226633Sdim 772288943Sdim RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 773249423Sdim NoMemInstr NM; 774249423Sdim Iter Filler; 775226633Sdim 776249423Sdim RegDU.setCallerSaved(*Slot); 777249423Sdim 778288943Sdim if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler)) 779261991Sdim return false; 780249423Sdim 781276479Sdim MBB.splice(std::next(Slot), &MBB, Filler); 782276479Sdim MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); 783261991Sdim ++UsefulSlots; 784261991Sdim return true; 785226633Sdim} 786226633Sdim 787341825Sdimbool MipsDelaySlotFiller::searchSuccBBs(MachineBasicBlock &MBB, 788341825Sdim Iter Slot) const { 789249423Sdim if (DisableSuccBBSearch) 790249423Sdim return false; 791234353Sdim 792249423Sdim MachineBasicBlock *SuccBB = selectSuccBB(MBB); 793226633Sdim 794249423Sdim if (!SuccBB) 795249423Sdim return false; 796226633Sdim 797288943Sdim RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 798249423Sdim bool HasMultipleSuccs = false; 799249423Sdim BB2BrMap BrMap; 800276479Sdim std::unique_ptr<InspectMemInstr> IM; 801249423Sdim Iter Filler; 802296417Sdim auto *Fn = MBB.getParent(); 803226633Sdim 804249423Sdim // Iterate over SuccBB's predecessor list. 805249423Sdim for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(), 806249423Sdim PE = SuccBB->pred_end(); PI != PE; ++PI) 807249423Sdim if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap)) 808249423Sdim return false; 809249423Sdim 810249423Sdim // Do not allow moving instructions which have unallocatable register operands 811249423Sdim // across basic block boundaries. 812296417Sdim RegDU.setUnallocatableRegs(*Fn); 813249423Sdim 814249423Sdim // Only allow moving loads from stack or constants if any of the SuccBB's 815249423Sdim // predecessors have multiple successors. 816249423Sdim if (HasMultipleSuccs) { 817249423Sdim IM.reset(new LoadFromStackOrConst()); 818249423Sdim } else { 819314564Sdim const MachineFrameInfo &MFI = Fn->getFrameInfo(); 820314564Sdim IM.reset(new MemDefsUses(Fn->getDataLayout(), &MFI)); 821226633Sdim } 822249423Sdim 823288943Sdim if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot, 824288943Sdim Filler)) 825249423Sdim return false; 826249423Sdim 827249423Sdim insertDelayFiller(Filler, BrMap); 828249423Sdim addLiveInRegs(Filler, *SuccBB); 829249423Sdim Filler->eraseFromParent(); 830249423Sdim 831249423Sdim return true; 832226633Sdim} 833226633Sdim 834341825SdimMachineBasicBlock * 835341825SdimMipsDelaySlotFiller::selectSuccBB(MachineBasicBlock &B) const { 836249423Sdim if (B.succ_empty()) 837276479Sdim return nullptr; 838249423Sdim 839249423Sdim // Select the successor with the larget edge weight. 840276479Sdim auto &Prob = getAnalysis<MachineBranchProbabilityInfo>(); 841296417Sdim MachineBasicBlock *S = *std::max_element( 842296417Sdim B.succ_begin(), B.succ_end(), 843296417Sdim [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) { 844296417Sdim return Prob.getEdgeProbability(&B, Dst0) < 845296417Sdim Prob.getEdgeProbability(&B, Dst1); 846296417Sdim }); 847296417Sdim return S->isEHPad() ? nullptr : S; 848226633Sdim} 849249423Sdim 850249423Sdimstd::pair<MipsInstrInfo::BranchType, MachineInstr *> 851341825SdimMipsDelaySlotFiller::getBranch(MachineBasicBlock &MBB, 852341825Sdim const MachineBasicBlock &Dst) const { 853249423Sdim const MipsInstrInfo *TII = 854288943Sdim MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo(); 855276479Sdim MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr; 856249423Sdim SmallVector<MachineInstr*, 2> BranchInstrs; 857249423Sdim SmallVector<MachineOperand, 2> Cond; 858249423Sdim 859249423Sdim MipsInstrInfo::BranchType R = 860309124Sdim TII->analyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs); 861249423Sdim 862249423Sdim if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch)) 863276479Sdim return std::make_pair(R, nullptr); 864249423Sdim 865249423Sdim if (R != MipsInstrInfo::BT_CondUncond) { 866249423Sdim if (!hasUnoccupiedSlot(BranchInstrs[0])) 867276479Sdim return std::make_pair(MipsInstrInfo::BT_None, nullptr); 868249423Sdim 869249423Sdim assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst))); 870249423Sdim 871249423Sdim return std::make_pair(R, BranchInstrs[0]); 872249423Sdim } 873249423Sdim 874249423Sdim assert((TrueBB == &Dst) || (FalseBB == &Dst)); 875249423Sdim 876249423Sdim // Examine the conditional branch. See if its slot is occupied. 877249423Sdim if (hasUnoccupiedSlot(BranchInstrs[0])) 878249423Sdim return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]); 879249423Sdim 880249423Sdim // If that fails, try the unconditional branch. 881249423Sdim if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst)) 882249423Sdim return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]); 883249423Sdim 884276479Sdim return std::make_pair(MipsInstrInfo::BT_None, nullptr); 885249423Sdim} 886249423Sdim 887341825Sdimbool MipsDelaySlotFiller::examinePred(MachineBasicBlock &Pred, 888341825Sdim const MachineBasicBlock &Succ, 889341825Sdim RegDefsUses &RegDU, 890341825Sdim bool &HasMultipleSuccs, 891341825Sdim BB2BrMap &BrMap) const { 892249423Sdim std::pair<MipsInstrInfo::BranchType, MachineInstr *> P = 893341825Sdim getBranch(Pred, Succ); 894249423Sdim 895249423Sdim // Return if either getBranch wasn't able to analyze the branches or there 896249423Sdim // were no branches with unoccupied slots. 897249423Sdim if (P.first == MipsInstrInfo::BT_None) 898249423Sdim return false; 899249423Sdim 900249423Sdim if ((P.first != MipsInstrInfo::BT_Uncond) && 901249423Sdim (P.first != MipsInstrInfo::BT_NoBranch)) { 902249423Sdim HasMultipleSuccs = true; 903249423Sdim RegDU.addLiveOut(Pred, Succ); 904249423Sdim } 905249423Sdim 906249423Sdim BrMap[&Pred] = P.second; 907249423Sdim return true; 908249423Sdim} 909249423Sdim 910341825Sdimbool MipsDelaySlotFiller::delayHasHazard(const MachineInstr &Candidate, 911341825Sdim RegDefsUses &RegDU, 912341825Sdim InspectMemInstr &IM) const { 913288943Sdim assert(!Candidate.isKill() && 914288943Sdim "KILL instructions should have been eliminated at this point."); 915249423Sdim 916288943Sdim bool HasHazard = Candidate.isImplicitDef(); 917288943Sdim 918249423Sdim HasHazard |= IM.hasHazard(Candidate); 919249423Sdim HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands()); 920249423Sdim 921249423Sdim return HasHazard; 922249423Sdim} 923249423Sdim 924341825Sdimbool MipsDelaySlotFiller::terminateSearch(const MachineInstr &Candidate) const { 925249423Sdim return (Candidate.isTerminator() || Candidate.isCall() || 926276479Sdim Candidate.isPosition() || Candidate.isInlineAsm() || 927249423Sdim Candidate.hasUnmodeledSideEffects()); 928249423Sdim} 929321369Sdim 930321369Sdim/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay 931321369Sdim/// slots in Mips MachineFunctions 932341825SdimFunctionPass *llvm::createMipsDelaySlotFillerPass() { return new MipsDelaySlotFiller(); } 933