1234353Sdim//===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===// 2193323Sed// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6193323Sed// 7193323Sed//===----------------------------------------------------------------------===// 8193323Sed 9193323Sed//===----------------------------------------------------------------------===// 10193323Sed// Declarations that describe the MSP430 register file 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13344779Sdimclass MSP430Reg<bits<4> num, string n, list<string> alt = []> : Register<n> { 14193323Sed field bits<4> Num = num; 15193323Sed let Namespace = "MSP430"; 16344779Sdim let HWEncoding{3-0} = num; 17344779Sdim let AltNames = alt; 18193323Sed} 19193323Sed 20344779Sdimclass MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs, 21344779Sdim list<string> alt = []> 22193323Sed : RegisterWithSubRegs<n, subregs> { 23193323Sed field bits<4> Num = num; 24193323Sed let Namespace = "MSP430"; 25344779Sdim let HWEncoding{3-0} = num; 26344779Sdim let AltNames = alt; 27193323Sed} 28193323Sed 29193323Sed//===----------------------------------------------------------------------===// 30193323Sed// Registers 31193323Sed//===----------------------------------------------------------------------===// 32193323Sed 33344779Sdimdef PCB : MSP430Reg<0, "r0", ["pc"]>; 34344779Sdimdef SPB : MSP430Reg<1, "r1", ["sp"]>; 35344779Sdimdef SRB : MSP430Reg<2, "r2", ["sr"]>; 36344779Sdimdef CGB : MSP430Reg<3, "r3", ["cg"]>; 37344779Sdimdef FPB : MSP430Reg<4, "r4", ["fp"]>; 38193323Seddef R5B : MSP430Reg<5, "r5">; 39193323Seddef R6B : MSP430Reg<6, "r6">; 40193323Seddef R7B : MSP430Reg<7, "r7">; 41193323Seddef R8B : MSP430Reg<8, "r8">; 42193323Seddef R9B : MSP430Reg<9, "r9">; 43193323Seddef R10B : MSP430Reg<10, "r10">; 44193323Seddef R11B : MSP430Reg<11, "r11">; 45193323Seddef R12B : MSP430Reg<12, "r12">; 46193323Seddef R13B : MSP430Reg<13, "r13">; 47193323Seddef R14B : MSP430Reg<14, "r14">; 48193323Seddef R15B : MSP430Reg<15, "r15">; 49193323Sed 50261991Sdimdef subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } 51208599Srdivacky 52208599Srdivackylet SubRegIndices = [subreg_8bit] in { 53344779Sdimdef PC : MSP430RegWithSubregs<0, "r0", [PCB], ["pc"]>; 54344779Sdimdef SP : MSP430RegWithSubregs<1, "r1", [SPB], ["sp"]>; 55344779Sdimdef SR : MSP430RegWithSubregs<2, "r2", [SRB], ["sr"]>; 56344779Sdimdef CG : MSP430RegWithSubregs<3, "r3", [CGB], ["cg"]>; 57344779Sdimdef FP : MSP430RegWithSubregs<4, "r4", [FPB], ["fp"]>; 58280031Sdimdef R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; 59280031Sdimdef R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; 60280031Sdimdef R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; 61280031Sdimdef R8 : MSP430RegWithSubregs<8, "r8", [R8B]>; 62280031Sdimdef R9 : MSP430RegWithSubregs<9, "r9", [R9B]>; 63280031Sdimdef R10 : MSP430RegWithSubregs<10, "r10", [R10B]>; 64280031Sdimdef R11 : MSP430RegWithSubregs<11, "r11", [R11B]>; 65280031Sdimdef R12 : MSP430RegWithSubregs<12, "r12", [R12B]>; 66280031Sdimdef R13 : MSP430RegWithSubregs<13, "r13", [R13B]>; 67280031Sdimdef R14 : MSP430RegWithSubregs<14, "r14", [R14B]>; 68280031Sdimdef R15 : MSP430RegWithSubregs<15, "r15", [R15B]>; 69208599Srdivacky} 70193323Sed 71193323Seddef GR8 : RegisterClass<"MSP430", [i8], 8, 72193323Sed // Volatile registers 73224145Sdim (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, 74193323Sed // Frame pointer, sometimes allocable 75193323Sed FPB, 76193323Sed // Volatile, but not allocable 77224145Sdim PCB, SPB, SRB, CGB)>; 78193323Sed 79193323Seddef GR16 : RegisterClass<"MSP430", [i16], 16, 80193323Sed // Volatile registers 81280031Sdim (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, 82193323Sed // Frame pointer, sometimes allocable 83280031Sdim FP, 84193323Sed // Volatile, but not allocable 85280031Sdim PC, SP, SR, CG)>; 86