MSP430ISelDAGToDAG.cpp revision 344779 
1//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MSP430 target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430.h"
15#include "MSP430TargetMachine.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/SelectionDAGISel.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/IR/Constants.h"
26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/Intrinsics.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32using namespace llvm;
33
34#define DEBUG_TYPE "msp430-isel"
35
36namespace {
37  struct MSP430ISelAddressMode {
38    enum {
39      RegBase,
40      FrameIndexBase
41    } BaseType;
42
43    struct {            // This is really a union, discriminated by BaseType!
44      SDValue Reg;
45      int FrameIndex;
46    } Base;
47
48    int16_t Disp;
49    const GlobalValue *GV;
50    const Constant *CP;
51    const BlockAddress *BlockAddr;
52    const char *ES;
53    int JT;
54    unsigned Align;    // CP alignment.
55
56    MSP430ISelAddressMode()
57      : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
58        BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
59    }
60
61    bool hasSymbolicDisplacement() const {
62      return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
63    }
64
65#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
66    LLVM_DUMP_METHOD void dump() {
67      errs() << "MSP430ISelAddressMode " << this << '\n';
68      if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
69        errs() << "Base.Reg ";
70        Base.Reg.getNode()->dump();
71      } else if (BaseType == FrameIndexBase) {
72        errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
73      }
74      errs() << " Disp " << Disp << '\n';
75      if (GV) {
76        errs() << "GV ";
77        GV->dump();
78      } else if (CP) {
79        errs() << " CP ";
80        CP->dump();
81        errs() << " Align" << Align << '\n';
82      } else if (ES) {
83        errs() << "ES ";
84        errs() << ES << '\n';
85      } else if (JT != -1)
86        errs() << " JT" << JT << " Align" << Align << '\n';
87    }
88#endif
89  };
90}
91
92/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
93/// instructions for SelectionDAG operations.
94///
95namespace {
96  class MSP430DAGToDAGISel : public SelectionDAGISel {
97  public:
98    MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
99        : SelectionDAGISel(TM, OptLevel) {}
100
101  private:
102    StringRef getPassName() const override {
103      return "MSP430 DAG->DAG Pattern Instruction Selection";
104    }
105
106    bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107    bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108    bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
109
110    bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
111                                      std::vector<SDValue> &OutOps) override;
112
113    // Include the pieces autogenerated from the target description.
114  #include "MSP430GenDAGISel.inc"
115
116    // Main method to transform nodes into machine nodes.
117    void Select(SDNode *N) override;
118
119    bool tryIndexedLoad(SDNode *Op);
120    bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
121                         unsigned Opc16);
122
123    bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
124  };
125}  // end anonymous namespace
126
127/// createMSP430ISelDag - This pass converts a legalized DAG into a
128/// MSP430-specific DAG, ready for instruction scheduling.
129///
130FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
131                                        CodeGenOpt::Level OptLevel) {
132  return new MSP430DAGToDAGISel(TM, OptLevel);
133}
134
135
136/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
137/// These wrap things that will resolve down into a symbol reference.  If no
138/// match is possible, this returns true, otherwise it returns false.
139bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
140  // If the addressing mode already has a symbol as the displacement, we can
141  // never match another symbol.
142  if (AM.hasSymbolicDisplacement())
143    return true;
144
145  SDValue N0 = N.getOperand(0);
146
147  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
148    AM.GV = G->getGlobal();
149    AM.Disp += G->getOffset();
150    //AM.SymbolFlags = G->getTargetFlags();
151  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
152    AM.CP = CP->getConstVal();
153    AM.Align = CP->getAlignment();
154    AM.Disp += CP->getOffset();
155    //AM.SymbolFlags = CP->getTargetFlags();
156  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
157    AM.ES = S->getSymbol();
158    //AM.SymbolFlags = S->getTargetFlags();
159  } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
160    AM.JT = J->getIndex();
161    //AM.SymbolFlags = J->getTargetFlags();
162  } else {
163    AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
164    //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
165  }
166  return false;
167}
168
169/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
170/// specified addressing mode without any further recursion.
171bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
172  // Is the base register already occupied?
173  if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
174    // If so, we cannot select it.
175    return true;
176  }
177
178  // Default, generate it as a register.
179  AM.BaseType = MSP430ISelAddressMode::RegBase;
180  AM.Base.Reg = N;
181  return false;
182}
183
184bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
185  LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump());
186
187  switch (N.getOpcode()) {
188  default: break;
189  case ISD::Constant: {
190    uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
191    AM.Disp += Val;
192    return false;
193  }
194
195  case MSP430ISD::Wrapper:
196    if (!MatchWrapper(N, AM))
197      return false;
198    break;
199
200  case ISD::FrameIndex:
201    if (AM.BaseType == MSP430ISelAddressMode::RegBase
202        && AM.Base.Reg.getNode() == nullptr) {
203      AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
204      AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
205      return false;
206    }
207    break;
208
209  case ISD::ADD: {
210    MSP430ISelAddressMode Backup = AM;
211    if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
212        !MatchAddress(N.getNode()->getOperand(1), AM))
213      return false;
214    AM = Backup;
215    if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
216        !MatchAddress(N.getNode()->getOperand(0), AM))
217      return false;
218    AM = Backup;
219
220    break;
221  }
222
223  case ISD::OR:
224    // Handle "X | C" as "X + C" iff X is known to have C bits clear.
225    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
226      MSP430ISelAddressMode Backup = AM;
227      uint64_t Offset = CN->getSExtValue();
228      // Start with the LHS as an addr mode.
229      if (!MatchAddress(N.getOperand(0), AM) &&
230          // Address could not have picked a GV address for the displacement.
231          AM.GV == nullptr &&
232          // Check to see if the LHS & C is zero.
233          CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
234        AM.Disp += Offset;
235        return false;
236      }
237      AM = Backup;
238    }
239    break;
240  }
241
242  return MatchAddressBase(N, AM);
243}
244
245/// SelectAddr - returns true if it is able pattern match an addressing mode.
246/// It returns the operands which make up the maximal addressing mode it can
247/// match by reference.
248bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
249                                    SDValue &Base, SDValue &Disp) {
250  MSP430ISelAddressMode AM;
251
252  if (MatchAddress(N, AM))
253    return false;
254
255  if (AM.BaseType == MSP430ISelAddressMode::RegBase)
256    if (!AM.Base.Reg.getNode())
257      AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16);
258
259  Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
260             ? CurDAG->getTargetFrameIndex(
261                   AM.Base.FrameIndex,
262                   getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
263             : AM.Base.Reg;
264
265  if (AM.GV)
266    Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
267                                          MVT::i16, AM.Disp,
268                                          0/*AM.SymbolFlags*/);
269  else if (AM.CP)
270    Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
271                                         AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
272  else if (AM.ES)
273    Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
274  else if (AM.JT != -1)
275    Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
276  else if (AM.BlockAddr)
277    Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
278                                         0/*AM.SymbolFlags*/);
279  else
280    Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
281
282  return true;
283}
284
285bool MSP430DAGToDAGISel::
286SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
287                             std::vector<SDValue> &OutOps) {
288  SDValue Op0, Op1;
289  switch (ConstraintID) {
290  default: return true;
291  case InlineAsm::Constraint_m: // memory
292    if (!SelectAddr(Op, Op0, Op1))
293      return true;
294    break;
295  }
296
297  OutOps.push_back(Op0);
298  OutOps.push_back(Op1);
299  return false;
300}
301
302static bool isValidIndexedLoad(const LoadSDNode *LD) {
303  ISD::MemIndexedMode AM = LD->getAddressingMode();
304  if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
305    return false;
306
307  EVT VT = LD->getMemoryVT();
308
309  switch (VT.getSimpleVT().SimpleTy) {
310  case MVT::i8:
311    // Sanity check
312    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
313      return false;
314
315    break;
316  case MVT::i16:
317    // Sanity check
318    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
319      return false;
320
321    break;
322  default:
323    return false;
324  }
325
326  return true;
327}
328
329bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
330  LoadSDNode *LD = cast<LoadSDNode>(N);
331  if (!isValidIndexedLoad(LD))
332    return false;
333
334  MVT VT = LD->getMemoryVT().getSimpleVT();
335
336  unsigned Opcode = 0;
337  switch (VT.SimpleTy) {
338  case MVT::i8:
339    Opcode = MSP430::MOV8rp;
340    break;
341  case MVT::i16:
342    Opcode = MSP430::MOV16rp;
343    break;
344  default:
345    return false;
346  }
347
348  ReplaceNode(N,
349              CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other,
350                                     LD->getBasePtr(), LD->getChain()));
351  return true;
352}
353
354bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
355                                         unsigned Opc8, unsigned Opc16) {
356  if (N1.getOpcode() == ISD::LOAD &&
357      N1.hasOneUse() &&
358      IsLegalToFold(N1, Op, Op, OptLevel)) {
359    LoadSDNode *LD = cast<LoadSDNode>(N1);
360    if (!isValidIndexedLoad(LD))
361      return false;
362
363    MVT VT = LD->getMemoryVT().getSimpleVT();
364    unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
365    MachineMemOperand *MemRef = cast<MemSDNode>(N1)->getMemOperand();
366    SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
367    SDNode *ResNode =
368      CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
369    CurDAG->setNodeMemRefs(cast<MachineSDNode>(ResNode), {MemRef});
370    // Transfer chain.
371    ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
372    // Transfer writeback.
373    ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
374    return true;
375  }
376
377  return false;
378}
379
380
381void MSP430DAGToDAGISel::Select(SDNode *Node) {
382  SDLoc dl(Node);
383
384  // If we have a custom node, we already have selected!
385  if (Node->isMachineOpcode()) {
386    LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
387    Node->setNodeId(-1);
388    return;
389  }
390
391  // Few custom selection stuff.
392  switch (Node->getOpcode()) {
393  default: break;
394  case ISD::FrameIndex: {
395    assert(Node->getValueType(0) == MVT::i16);
396    int FI = cast<FrameIndexSDNode>(Node)->getIndex();
397    SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
398    if (Node->hasOneUse()) {
399      CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI,
400                           CurDAG->getTargetConstant(0, dl, MVT::i16));
401      return;
402    }
403    ReplaceNode(Node, CurDAG->getMachineNode(
404                          MSP430::ADDframe, dl, MVT::i16, TFI,
405                          CurDAG->getTargetConstant(0, dl, MVT::i16)));
406    return;
407  }
408  case ISD::LOAD:
409    if (tryIndexedLoad(Node))
410      return;
411    // Other cases are autogenerated.
412    break;
413  case ISD::ADD:
414    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
415                        MSP430::ADD8rp, MSP430::ADD16rp))
416      return;
417    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
418                             MSP430::ADD8rp, MSP430::ADD16rp))
419      return;
420
421    // Other cases are autogenerated.
422    break;
423  case ISD::SUB:
424    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
425                        MSP430::SUB8rp, MSP430::SUB16rp))
426      return;
427
428    // Other cases are autogenerated.
429    break;
430  case ISD::AND:
431    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
432                        MSP430::AND8rp, MSP430::AND16rp))
433      return;
434    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
435                             MSP430::AND8rp, MSP430::AND16rp))
436      return;
437
438    // Other cases are autogenerated.
439    break;
440  case ISD::OR:
441    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
442                        MSP430::BIS8rp, MSP430::BIS16rp))
443      return;
444    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
445                             MSP430::BIS8rp, MSP430::BIS16rp))
446      return;
447
448    // Other cases are autogenerated.
449    break;
450  case ISD::XOR:
451    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
452                        MSP430::XOR8rp, MSP430::XOR16rp))
453      return;
454    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
455                             MSP430::XOR8rp, MSP430::XOR16rp))
456      return;
457
458    // Other cases are autogenerated.
459    break;
460  }
461
462  // Select the default instruction
463  SelectCode(Node);
464}
465