MSP430ISelDAGToDAG.cpp revision 341825 
1//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the MSP430 target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430.h"
15#include "MSP430TargetMachine.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/SelectionDAGISel.h"
22#include "llvm/CodeGen/TargetLowering.h"
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/IR/Constants.h"
26#include "llvm/IR/DerivedTypes.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/Intrinsics.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32using namespace llvm;
33
34#define DEBUG_TYPE "msp430-isel"
35
36namespace {
37  struct MSP430ISelAddressMode {
38    enum {
39      RegBase,
40      FrameIndexBase
41    } BaseType;
42
43    struct {            // This is really a union, discriminated by BaseType!
44      SDValue Reg;
45      int FrameIndex;
46    } Base;
47
48    int16_t Disp;
49    const GlobalValue *GV;
50    const Constant *CP;
51    const BlockAddress *BlockAddr;
52    const char *ES;
53    int JT;
54    unsigned Align;    // CP alignment.
55
56    MSP430ISelAddressMode()
57      : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
58        BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
59    }
60
61    bool hasSymbolicDisplacement() const {
62      return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
63    }
64
65#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
66    LLVM_DUMP_METHOD void dump() {
67      errs() << "MSP430ISelAddressMode " << this << '\n';
68      if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
69        errs() << "Base.Reg ";
70        Base.Reg.getNode()->dump();
71      } else if (BaseType == FrameIndexBase) {
72        errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
73      }
74      errs() << " Disp " << Disp << '\n';
75      if (GV) {
76        errs() << "GV ";
77        GV->dump();
78      } else if (CP) {
79        errs() << " CP ";
80        CP->dump();
81        errs() << " Align" << Align << '\n';
82      } else if (ES) {
83        errs() << "ES ";
84        errs() << ES << '\n';
85      } else if (JT != -1)
86        errs() << " JT" << JT << " Align" << Align << '\n';
87    }
88#endif
89  };
90}
91
92/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
93/// instructions for SelectionDAG operations.
94///
95namespace {
96  class MSP430DAGToDAGISel : public SelectionDAGISel {
97  public:
98    MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
99        : SelectionDAGISel(TM, OptLevel) {}
100
101    StringRef getPassName() const override {
102      return "MSP430 DAG->DAG Pattern Instruction Selection";
103    }
104
105    bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
106    bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
107    bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
108
109    bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
110                                      std::vector<SDValue> &OutOps) override;
111
112    // Include the pieces autogenerated from the target description.
113  #include "MSP430GenDAGISel.inc"
114
115  private:
116    void Select(SDNode *N) override;
117    bool tryIndexedLoad(SDNode *Op);
118    bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
119                         unsigned Opc16);
120
121    bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
122  };
123}  // end anonymous namespace
124
125/// createMSP430ISelDag - This pass converts a legalized DAG into a
126/// MSP430-specific DAG, ready for instruction scheduling.
127///
128FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
129                                        CodeGenOpt::Level OptLevel) {
130  return new MSP430DAGToDAGISel(TM, OptLevel);
131}
132
133
134/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
135/// These wrap things that will resolve down into a symbol reference.  If no
136/// match is possible, this returns true, otherwise it returns false.
137bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
138  // If the addressing mode already has a symbol as the displacement, we can
139  // never match another symbol.
140  if (AM.hasSymbolicDisplacement())
141    return true;
142
143  SDValue N0 = N.getOperand(0);
144
145  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
146    AM.GV = G->getGlobal();
147    AM.Disp += G->getOffset();
148    //AM.SymbolFlags = G->getTargetFlags();
149  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
150    AM.CP = CP->getConstVal();
151    AM.Align = CP->getAlignment();
152    AM.Disp += CP->getOffset();
153    //AM.SymbolFlags = CP->getTargetFlags();
154  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
155    AM.ES = S->getSymbol();
156    //AM.SymbolFlags = S->getTargetFlags();
157  } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
158    AM.JT = J->getIndex();
159    //AM.SymbolFlags = J->getTargetFlags();
160  } else {
161    AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
162    //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
163  }
164  return false;
165}
166
167/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
168/// specified addressing mode without any further recursion.
169bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
170  // Is the base register already occupied?
171  if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
172    // If so, we cannot select it.
173    return true;
174  }
175
176  // Default, generate it as a register.
177  AM.BaseType = MSP430ISelAddressMode::RegBase;
178  AM.Base.Reg = N;
179  return false;
180}
181
182bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
183  LLVM_DEBUG(errs() << "MatchAddress: "; AM.dump());
184
185  switch (N.getOpcode()) {
186  default: break;
187  case ISD::Constant: {
188    uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
189    AM.Disp += Val;
190    return false;
191  }
192
193  case MSP430ISD::Wrapper:
194    if (!MatchWrapper(N, AM))
195      return false;
196    break;
197
198  case ISD::FrameIndex:
199    if (AM.BaseType == MSP430ISelAddressMode::RegBase
200        && AM.Base.Reg.getNode() == nullptr) {
201      AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
202      AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
203      return false;
204    }
205    break;
206
207  case ISD::ADD: {
208    MSP430ISelAddressMode Backup = AM;
209    if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
210        !MatchAddress(N.getNode()->getOperand(1), AM))
211      return false;
212    AM = Backup;
213    if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
214        !MatchAddress(N.getNode()->getOperand(0), AM))
215      return false;
216    AM = Backup;
217
218    break;
219  }
220
221  case ISD::OR:
222    // Handle "X | C" as "X + C" iff X is known to have C bits clear.
223    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
224      MSP430ISelAddressMode Backup = AM;
225      uint64_t Offset = CN->getSExtValue();
226      // Start with the LHS as an addr mode.
227      if (!MatchAddress(N.getOperand(0), AM) &&
228          // Address could not have picked a GV address for the displacement.
229          AM.GV == nullptr &&
230          // Check to see if the LHS & C is zero.
231          CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
232        AM.Disp += Offset;
233        return false;
234      }
235      AM = Backup;
236    }
237    break;
238  }
239
240  return MatchAddressBase(N, AM);
241}
242
243/// SelectAddr - returns true if it is able pattern match an addressing mode.
244/// It returns the operands which make up the maximal addressing mode it can
245/// match by reference.
246bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
247                                    SDValue &Base, SDValue &Disp) {
248  MSP430ISelAddressMode AM;
249
250  if (MatchAddress(N, AM))
251    return false;
252
253  EVT VT = N.getValueType();
254  if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
255    if (!AM.Base.Reg.getNode())
256      AM.Base.Reg = CurDAG->getRegister(0, VT);
257  }
258
259  Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
260             ? CurDAG->getTargetFrameIndex(
261                   AM.Base.FrameIndex,
262                   getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
263             : AM.Base.Reg;
264
265  if (AM.GV)
266    Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
267                                          MVT::i16, AM.Disp,
268                                          0/*AM.SymbolFlags*/);
269  else if (AM.CP)
270    Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
271                                         AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
272  else if (AM.ES)
273    Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
274  else if (AM.JT != -1)
275    Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
276  else if (AM.BlockAddr)
277    Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
278                                         0/*AM.SymbolFlags*/);
279  else
280    Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
281
282  return true;
283}
284
285bool MSP430DAGToDAGISel::
286SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
287                             std::vector<SDValue> &OutOps) {
288  SDValue Op0, Op1;
289  switch (ConstraintID) {
290  default: return true;
291  case InlineAsm::Constraint_m: // memory
292    if (!SelectAddr(Op, Op0, Op1))
293      return true;
294    break;
295  }
296
297  OutOps.push_back(Op0);
298  OutOps.push_back(Op1);
299  return false;
300}
301
302static bool isValidIndexedLoad(const LoadSDNode *LD) {
303  ISD::MemIndexedMode AM = LD->getAddressingMode();
304  if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
305    return false;
306
307  EVT VT = LD->getMemoryVT();
308
309  switch (VT.getSimpleVT().SimpleTy) {
310  case MVT::i8:
311    // Sanity check
312    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
313      return false;
314
315    break;
316  case MVT::i16:
317    // Sanity check
318    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
319      return false;
320
321    break;
322  default:
323    return false;
324  }
325
326  return true;
327}
328
329bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) {
330  LoadSDNode *LD = cast<LoadSDNode>(N);
331  if (!isValidIndexedLoad(LD))
332    return false;
333
334  MVT VT = LD->getMemoryVT().getSimpleVT();
335
336  unsigned Opcode = 0;
337  switch (VT.SimpleTy) {
338  case MVT::i8:
339    Opcode = MSP430::MOV8rm_POST;
340    break;
341  case MVT::i16:
342    Opcode = MSP430::MOV16rm_POST;
343    break;
344  default:
345    return false;
346  }
347
348  ReplaceNode(N,
349              CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other,
350                                     LD->getBasePtr(), LD->getChain()));
351  return true;
352}
353
354bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
355                                         unsigned Opc8, unsigned Opc16) {
356  if (N1.getOpcode() == ISD::LOAD &&
357      N1.hasOneUse() &&
358      IsLegalToFold(N1, Op, Op, OptLevel)) {
359    LoadSDNode *LD = cast<LoadSDNode>(N1);
360    if (!isValidIndexedLoad(LD))
361      return false;
362
363    MVT VT = LD->getMemoryVT().getSimpleVT();
364    unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
365    MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
366    MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
367    SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
368    SDNode *ResNode =
369      CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
370    cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
371    // Transfer chain.
372    ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
373    // Transfer writeback.
374    ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
375    return true;
376  }
377
378  return false;
379}
380
381
382void MSP430DAGToDAGISel::Select(SDNode *Node) {
383  SDLoc dl(Node);
384
385  // If we have a custom node, we already have selected!
386  if (Node->isMachineOpcode()) {
387    LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
388    Node->setNodeId(-1);
389    return;
390  }
391
392  // Few custom selection stuff.
393  switch (Node->getOpcode()) {
394  default: break;
395  case ISD::FrameIndex: {
396    assert(Node->getValueType(0) == MVT::i16);
397    int FI = cast<FrameIndexSDNode>(Node)->getIndex();
398    SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
399    if (Node->hasOneUse()) {
400      CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI,
401                           CurDAG->getTargetConstant(0, dl, MVT::i16));
402      return;
403    }
404    ReplaceNode(Node, CurDAG->getMachineNode(
405                          MSP430::ADDframe, dl, MVT::i16, TFI,
406                          CurDAG->getTargetConstant(0, dl, MVT::i16)));
407    return;
408  }
409  case ISD::LOAD:
410    if (tryIndexedLoad(Node))
411      return;
412    // Other cases are autogenerated.
413    break;
414  case ISD::ADD:
415    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
416                        MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
417      return;
418    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
419                             MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
420      return;
421
422    // Other cases are autogenerated.
423    break;
424  case ISD::SUB:
425    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
426                        MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
427      return;
428
429    // Other cases are autogenerated.
430    break;
431  case ISD::AND:
432    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
433                        MSP430::AND8rm_POST, MSP430::AND16rm_POST))
434      return;
435    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
436                             MSP430::AND8rm_POST, MSP430::AND16rm_POST))
437      return;
438
439    // Other cases are autogenerated.
440    break;
441  case ISD::OR:
442    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
443                        MSP430::OR8rm_POST, MSP430::OR16rm_POST))
444      return;
445    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
446                             MSP430::OR8rm_POST, MSP430::OR16rm_POST))
447      return;
448
449    // Other cases are autogenerated.
450    break;
451  case ISD::XOR:
452    if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1),
453                        MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
454      return;
455    else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
456                             MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
457      return;
458
459    // Other cases are autogenerated.
460    break;
461  }
462
463  // Select the default instruction
464  SelectCode(Node);
465}
466