HexagonMCInstrInfo.cpp revision 309124 
1//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonMCInstrInfo.h"
15
16#include "Hexagon.h"
17#include "HexagonBaseInfo.h"
18#include "HexagonMCChecker.h"
19
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24
25namespace llvm {
26void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
27                                     MCContext &Context) {
28  MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
29}
30
31void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
32                                          MCInstrInfo const &MCII, MCInst &MCB,
33                                          MCInst const &MCI) {
34  assert(HexagonMCInstrInfo::isBundle(MCB));
35  MCOperand const &exOp =
36      MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
37
38  // Create the extender.
39  MCInst *XMCI =
40      new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
41
42  MCB.addOperand(MCOperand::createInst(XMCI));
43}
44
45iterator_range<MCInst::const_iterator>
46HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
47  assert(isBundle(MCI));
48  return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
49}
50
51size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
52  if (HexagonMCInstrInfo::isBundle(MCI))
53    return (MCI.size() - bundleInstructionsOffset);
54  else
55    return (1);
56}
57
58bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
59                                            MCSubtargetInfo const &STI,
60                                            MCContext &Context, MCInst &MCB,
61                                            HexagonMCChecker *Check) {
62  // Examine the packet and convert pairs of instructions to compound
63  // instructions when possible.
64  if (!HexagonDisableCompound)
65    HexagonMCInstrInfo::tryCompound(MCII, Context, MCB);
66  // Check the bundle for errors.
67  bool CheckOk = Check ? Check->check() : true;
68  if (!CheckOk)
69    return false;
70  HexagonMCShuffle(MCII, STI, MCB);
71  // Examine the packet and convert pairs of instructions to duplex
72  // instructions when possible.
73  MCInst InstBundlePreDuplex = MCInst(MCB);
74  if (!HexagonDisableDuplex) {
75    SmallVector<DuplexCandidate, 8> possibleDuplexes;
76    possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB);
77    HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes);
78  }
79  // Examines packet and pad the packet, if needed, when an
80  // end-loop is in the bundle.
81  HexagonMCInstrInfo::padEndloop(Context, MCB);
82  // If compounding and duplexing didn't reduce the size below
83  // 4 or less we have a packet that is too big.
84  if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)
85    return false;
86  HexagonMCShuffle(MCII, STI, MCB);
87  return true;
88}
89
90void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
91                                       MCContext &Context, MCInst &MCI) {
92  assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
93         HexagonMCInstrInfo::isExtended(MCII, MCI));
94  MCOperand &exOp =
95      MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
96  // If the extended value is a constant, then use it for the extended and
97  // for the extender instructions, masking off the lower 6 bits and
98  // including the assumed bits.
99  int64_t Value;
100  if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
101    unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
102    exOp.setExpr(HexagonMCExpr::create(
103        MCConstantExpr::create((Value & 0x3f) << Shift, Context), Context));
104  }
105}
106
107MCInst HexagonMCInstrInfo::createBundle() {
108  MCInst Result;
109  Result.setOpcode(Hexagon::BUNDLE);
110  Result.addOperand(MCOperand::createImm(0));
111  return Result;
112}
113
114MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
115                                         MCInst const &inst0,
116                                         MCInst const &inst1) {
117  assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
118  MCInst *duplexInst = new (Context) MCInst;
119  duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
120
121  MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
122  MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
123  duplexInst->addOperand(MCOperand::createInst(SubInst0));
124  duplexInst->addOperand(MCOperand::createInst(SubInst1));
125  return duplexInst;
126}
127
128MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
129                                          MCInst const &Inst,
130                                          MCOperand const &MO) {
131  assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
132         HexagonMCInstrInfo::isExtended(MCII, Inst));
133
134  MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
135  MCInst XMI;
136  XMI.setOpcode((Desc.isBranch() || Desc.isCall() ||
137                 HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR)
138                    ? Hexagon::A4_ext_b
139                    : Hexagon::A4_ext);
140  if (MO.isImm())
141    XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
142  else if (MO.isExpr())
143    XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
144  else
145    llvm_unreachable("invalid extendable operand");
146  return XMI;
147}
148
149MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
150                                                   size_t Index) {
151  assert(Index <= bundleSize(MCB));
152  if (Index == 0)
153    return nullptr;
154  MCInst const *Inst =
155      MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
156  if (isImmext(*Inst))
157    return Inst;
158  return nullptr;
159}
160
161void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
162                                        MCInstrInfo const &MCII, MCInst &MCB,
163                                        MCInst const &MCI) {
164  if (isConstExtended(MCII, MCI))
165    addConstExtender(Context, MCII, MCB, MCI);
166}
167
168HexagonII::MemAccessSize
169HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
170  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
171
172  return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
173                                   HexagonII::MemAccesSizeMask));
174}
175
176unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII,
177                                         MCInst const &MCI) {
178  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
179  return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
180}
181
182// Return constant extended operand number.
183unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII,
184                                                MCInst const &MCI) {
185  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
186  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
187}
188
189MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
190                                               MCInst const &MCI) {
191  return (MCII.get(MCI.getOpcode()));
192}
193
194unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
195  using namespace Hexagon;
196  switch (Reg) {
197  default:
198    llvm_unreachable("unknown duplex register");
199  // Rs       Rss
200  case R0:
201  case D0:
202    return 0;
203  case R1:
204  case D1:
205    return 1;
206  case R2:
207  case D2:
208    return 2;
209  case R3:
210  case D3:
211    return 3;
212  case R4:
213  case D8:
214    return 4;
215  case R5:
216  case D9:
217    return 5;
218  case R6:
219  case D10:
220    return 6;
221  case R7:
222  case D11:
223    return 7;
224  case R16:
225    return 8;
226  case R17:
227    return 9;
228  case R18:
229    return 10;
230  case R19:
231    return 11;
232  case R20:
233    return 12;
234  case R21:
235    return 13;
236  case R22:
237    return 14;
238  case R23:
239    return 15;
240  }
241}
242
243MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
244  const auto &HExpr = cast<HexagonMCExpr>(Expr);
245  assert(HExpr.getExpr());
246  return *HExpr.getExpr();
247}
248
249unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
250                                                   MCInst const &MCI) {
251  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
252  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
253}
254
255MCOperand const &
256HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
257                                         MCInst const &MCI) {
258  unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
259  MCOperand const &MO = MCI.getOperand(O);
260
261  assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
262          HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
263         (MO.isImm() || MO.isExpr()));
264  return (MO);
265}
266
267unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
268                                                MCInst const &MCI) {
269  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
270  return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
271}
272
273unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
274                                           MCInst const &MCI) {
275  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
276  return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
277}
278
279// Return the max value that a constant extendable operand can have
280// without being extended.
281int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
282                                    MCInst const &MCI) {
283  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
284  unsigned isSigned =
285      (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
286  unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
287
288  if (isSigned) // if value is signed
289    return ~(-1U << (bits - 1));
290  else
291    return ~(-1U << bits);
292}
293
294// Return the min value that a constant extendable operand can have
295// without being extended.
296int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
297                                    MCInst const &MCI) {
298  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
299  unsigned isSigned =
300      (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
301  unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
302
303  if (isSigned) // if value is signed
304    return -1U << (bits - 1);
305  else
306    return 0;
307}
308
309char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
310                                        MCInst const &MCI) {
311  return MCII.getName(MCI.getOpcode());
312}
313
314unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
315                                                 MCInst const &MCI) {
316  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
317  return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
318}
319
320MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
321                                                        MCInst const &MCI) {
322  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
323  unsigned const O =
324      (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
325  MCOperand const &MCO = MCI.getOperand(O);
326
327  assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
328          HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
329         MCO.isReg());
330  return (MCO);
331}
332
333/// Return the new value or the newly produced value.
334unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
335                                                  MCInst const &MCI) {
336  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
337  return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
338}
339
340MCOperand const &
341HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
342                                        MCInst const &MCI) {
343  unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
344  MCOperand const &MCO = MCI.getOperand(O);
345
346  assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
347          HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
348         MCO.isReg());
349  return (MCO);
350}
351
352int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII,
353                                     MCInst const &MCI) {
354  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
355
356  HexagonII::SubTarget Target = static_cast<HexagonII::SubTarget>(
357      (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask);
358
359  switch (Target) {
360  default:
361    return Hexagon::ArchV4;
362  case HexagonII::HasV5SubT:
363    return Hexagon::ArchV5;
364  }
365}
366
367// Return the Hexagon ISA class for the insn.
368unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
369                                     MCInst const &MCI) {
370  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
371
372  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
373}
374
375unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
376                                      MCSubtargetInfo const &STI,
377                                      MCInst const &MCI) {
378
379  const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
380  int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
381  return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
382}
383
384bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
385  if (!HexagonMCInstrInfo::isBundle(MCI))
386    return false;
387
388  for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
389    auto MI = I.getInst();
390    if (isImmext(*MI))
391      return true;
392  }
393
394  return false;
395}
396
397bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
398  return extenderForIndex(MCB, Index) != nullptr;
399}
400
401// Return whether the instruction is a legal new-value producer.
402bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
403                                     MCInst const &MCI) {
404  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
405  return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
406}
407
408/// Return whether the insn produces a second value.
409bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
410                                      MCInst const &MCI) {
411  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
412  return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
413}
414
415MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
416  assert(isBundle(MCB));
417  assert(Index < HEXAGON_PACKET_SIZE);
418  return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
419}
420
421bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
422  auto Result = Hexagon::BUNDLE == MCI.getOpcode();
423  assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
424  return Result;
425}
426
427// Return whether the insn is an actual insn.
428bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
429  return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
430          !HexagonMCInstrInfo::isPrefix(MCII, MCI) &&
431          HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP);
432}
433
434bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
435                                    MCInst const &MCI) {
436  return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
437}
438
439bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
440  return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
441          (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
442}
443
444bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
445  return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
446}
447
448// Return whether the instruction needs to be constant extended.
449// 1) Always return true if the instruction has 'isExtended' flag set.
450//
451// isExtendable:
452// 2) For immediate extended operands, return true only if the value is
453//    out-of-range.
454// 3) For global address, always return true.
455
456bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
457                                         MCInst const &MCI) {
458  if (HexagonMCInstrInfo::isExtended(MCII, MCI))
459    return true;
460  if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
461    return false;
462  MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
463  if (isa<HexagonMCExpr>(MO.getExpr()) &&
464      HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
465    return true;
466  // Branch insns are handled as necessary by relaxation.
467  if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
468      (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
469       HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
470      (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
471       HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
472    return false;
473  // Otherwise loop instructions and other CR insts are handled by relaxation
474  else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
475           (MCI.getOpcode() != Hexagon::C4_addipc))
476    return false;
477
478  assert(!MO.isImm());
479  if (isa<HexagonMCExpr>(MO.getExpr()) &&
480      HexagonMCInstrInfo::mustNotExtend(*MO.getExpr()))
481    return false;
482  int64_t Value;
483  if (!MO.getExpr()->evaluateAsAbsolute(Value))
484    return true;
485  int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
486  int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
487  return (MinValue > Value || Value > MaxValue);
488}
489
490bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
491                                      MCInst const &MCI) {
492  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
493  return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
494}
495
496bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
497                                    MCInst const &MCI) {
498  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
499  return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
500}
501
502bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
503  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
504  return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
505}
506
507bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
508  auto Op = MCI.getOpcode();
509  return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
510          Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
511}
512
513bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
514  assert(isBundle(MCI));
515  int64_t Flags = MCI.getOperand(0).getImm();
516  return (Flags & innerLoopMask) != 0;
517}
518
519bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
520  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
521}
522
523bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
524  return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
525          (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
526}
527
528// Return whether the insn is a new-value consumer.
529bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
530                                    MCInst const &MCI) {
531  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
532  return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
533}
534
535// Return whether the operand can be constant extended.
536bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII,
537                                           MCInst const &MCI,
538                                           unsigned short OperandNum) {
539  uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
540  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
541         OperandNum;
542}
543
544bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
545  assert(isBundle(MCI));
546  int64_t Flags = MCI.getOperand(0).getImm();
547  return (Flags & outerLoopMask) != 0;
548}
549
550bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
551                                      MCInst const &MCI) {
552  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
553  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
554}
555
556bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
557                                         MCInst const &MCI) {
558  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
559  return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
560}
561
562/// Return whether the insn is newly predicated.
563bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
564                                         MCInst const &MCI) {
565  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
566  return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
567}
568
569bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
570                                          MCInst const &MCI) {
571  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
572  return (
573      !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
574}
575
576bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
577  return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
578}
579
580bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
581  return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
582}
583
584bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
585  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
586  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
587}
588
589bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
590  assert(isBundle(MCI));
591  auto Flags = MCI.getOperand(0).getImm();
592  return (Flags & memReorderDisabledMask) != 0;
593}
594
595bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {
596  assert(isBundle(MCI));
597  auto Flags = MCI.getOperand(0).getImm();
598  return (Flags & memStoreReorderEnabledMask) != 0;
599}
600
601bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
602  switch (MCI.getOpcode()) {
603  default:
604    return false;
605  case Hexagon::V4_SA1_addi:
606  case Hexagon::V4_SA1_addrx:
607  case Hexagon::V4_SA1_addsp:
608  case Hexagon::V4_SA1_and1:
609  case Hexagon::V4_SA1_clrf:
610  case Hexagon::V4_SA1_clrfnew:
611  case Hexagon::V4_SA1_clrt:
612  case Hexagon::V4_SA1_clrtnew:
613  case Hexagon::V4_SA1_cmpeqi:
614  case Hexagon::V4_SA1_combine0i:
615  case Hexagon::V4_SA1_combine1i:
616  case Hexagon::V4_SA1_combine2i:
617  case Hexagon::V4_SA1_combine3i:
618  case Hexagon::V4_SA1_combinerz:
619  case Hexagon::V4_SA1_combinezr:
620  case Hexagon::V4_SA1_dec:
621  case Hexagon::V4_SA1_inc:
622  case Hexagon::V4_SA1_seti:
623  case Hexagon::V4_SA1_setin1:
624  case Hexagon::V4_SA1_sxtb:
625  case Hexagon::V4_SA1_sxth:
626  case Hexagon::V4_SA1_tfr:
627  case Hexagon::V4_SA1_zxtb:
628  case Hexagon::V4_SA1_zxth:
629  case Hexagon::V4_SL1_loadri_io:
630  case Hexagon::V4_SL1_loadrub_io:
631  case Hexagon::V4_SL2_deallocframe:
632  case Hexagon::V4_SL2_jumpr31:
633  case Hexagon::V4_SL2_jumpr31_f:
634  case Hexagon::V4_SL2_jumpr31_fnew:
635  case Hexagon::V4_SL2_jumpr31_t:
636  case Hexagon::V4_SL2_jumpr31_tnew:
637  case Hexagon::V4_SL2_loadrb_io:
638  case Hexagon::V4_SL2_loadrd_sp:
639  case Hexagon::V4_SL2_loadrh_io:
640  case Hexagon::V4_SL2_loadri_sp:
641  case Hexagon::V4_SL2_loadruh_io:
642  case Hexagon::V4_SL2_return:
643  case Hexagon::V4_SL2_return_f:
644  case Hexagon::V4_SL2_return_fnew:
645  case Hexagon::V4_SL2_return_t:
646  case Hexagon::V4_SL2_return_tnew:
647  case Hexagon::V4_SS1_storeb_io:
648  case Hexagon::V4_SS1_storew_io:
649  case Hexagon::V4_SS2_allocframe:
650  case Hexagon::V4_SS2_storebi0:
651  case Hexagon::V4_SS2_storebi1:
652  case Hexagon::V4_SS2_stored_sp:
653  case Hexagon::V4_SS2_storeh_io:
654  case Hexagon::V4_SS2_storew_sp:
655  case Hexagon::V4_SS2_storewi0:
656  case Hexagon::V4_SS2_storewi1:
657    return true;
658  }
659}
660
661bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
662  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
663  return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
664}
665
666bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII,
667                                    MCInst const &MCI) {
668  const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
669  return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);
670}
671
672bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
673  if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
674      (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
675    return true;
676  return false;
677}
678
679int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
680  auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
681                  << 8;
682  if (MCI.size() <= Index)
683    return Sentinal;
684  MCOperand const &MCO = MCI.getOperand(Index);
685  if (!MCO.isExpr())
686    return Sentinal;
687  int64_t Value;
688  if (!MCO.getExpr()->evaluateAsAbsolute(Value))
689    return Sentinal;
690  return Value;
691}
692
693void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
694  HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
695  HExpr.setMustExtend(Val);
696}
697
698bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
699  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
700  return HExpr.mustExtend();
701}
702void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
703  HexagonMCExpr &HExpr =
704      const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
705  HExpr.setMustNotExtend(Val);
706}
707bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
708  HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
709  return HExpr.mustNotExtend();
710}
711
712void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) {
713  MCInst Nop;
714  Nop.setOpcode(Hexagon::A2_nop);
715  assert(isBundle(MCB));
716  while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
717          (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
718         ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
719           (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))))
720    MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
721}
722
723bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
724                                      MCInst const &MCI) {
725  if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR)
726    return false;
727
728  unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
729  switch (SchedClass) {
730  case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
731  case Hexagon::Sched::ALU64_tc_2_SLOT23:
732  case Hexagon::Sched::ALU64_tc_3x_SLOT23:
733  case Hexagon::Sched::M_tc_2_SLOT23:
734  case Hexagon::Sched::M_tc_3x_SLOT23:
735  case Hexagon::Sched::S_2op_tc_2_SLOT23:
736  case Hexagon::Sched::S_3op_tc_2_SLOT23:
737  case Hexagon::Sched::S_3op_tc_3x_SLOT23:
738    return true;
739  }
740  return false;
741}
742
743void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
744                                       DuplexCandidate Candidate) {
745  assert(Candidate.packetIndexI < MCB.size());
746  assert(Candidate.packetIndexJ < MCB.size());
747  assert(isBundle(MCB));
748  MCInst *Duplex =
749      deriveDuplex(Context, Candidate.iClass,
750                   *MCB.getOperand(Candidate.packetIndexJ).getInst(),
751                   *MCB.getOperand(Candidate.packetIndexI).getInst());
752  assert(Duplex != nullptr);
753  MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
754  MCB.erase(MCB.begin() + Candidate.packetIndexJ);
755}
756
757void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
758  assert(isBundle(MCI));
759  MCOperand &Operand = MCI.getOperand(0);
760  Operand.setImm(Operand.getImm() | innerLoopMask);
761}
762
763void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
764  assert(isBundle(MCI));
765  MCOperand &Operand = MCI.getOperand(0);
766  Operand.setImm(Operand.getImm() | memReorderDisabledMask);
767  assert(isMemReorderDisabled(MCI));
768}
769
770void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
771  assert(isBundle(MCI));
772  MCOperand &Operand = MCI.getOperand(0);
773  Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
774  assert(isMemStoreReorderEnabled(MCI));
775}
776void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) {
777  HexagonMCExpr &HExpr =
778      const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
779  HExpr.setS23_2_reloc(Val);
780}
781bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) {
782  HexagonMCExpr const &HExpr = *llvm::cast<HexagonMCExpr>(&Expr);
783  return HExpr.s23_2_reloc();
784}
785
786void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
787  assert(isBundle(MCI));
788  MCOperand &Operand = MCI.getOperand(0);
789  Operand.setImm(Operand.getImm() | outerLoopMask);
790}
791
792unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
793                                            unsigned Producer,
794                                            unsigned Producer2) {
795  // If we're a single vector consumer of a double producer, set subreg bit
796  // based on if we're accessing the lower or upper register component
797  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
798    if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
799      return (Consumer - Hexagon::V0) & 0x1;
800  if (Consumer == Producer2)
801    return 0x1;
802  return 0;
803}
804}
805