HexagonVLIWPacketizer.h revision 344779
1327952Sdim//===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===// 2327952Sdim// 3327952Sdim// The LLVM Compiler Infrastructure 4327952Sdim// 5327952Sdim// This file is distributed under the University of Illinois Open Source 6327952Sdim// License. See LICENSE.TXT for details. 7327952Sdim// 8327952Sdim//===----------------------------------------------------------------------===// 9292915Sdim 10327952Sdim#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H 11327952Sdim#define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H 12327952Sdim 13292915Sdim#include "llvm/CodeGen/DFAPacketizer.h" 14327952Sdim#include "llvm/CodeGen/MachineBasicBlock.h" 15292915Sdim#include "llvm/CodeGen/ScheduleDAG.h" 16327952Sdim#include <vector> 17292915Sdim 18292915Sdimnamespace llvm { 19327952Sdim 20321369Sdimclass HexagonInstrInfo; 21321369Sdimclass HexagonRegisterInfo; 22327952Sdimclass MachineBranchProbabilityInfo; 23327952Sdimclass MachineFunction; 24327952Sdimclass MachineInstr; 25327952Sdimclass MachineLoopInfo; 26327952Sdimclass TargetRegisterClass; 27321369Sdim 28292915Sdimclass HexagonPacketizerList : public VLIWPacketizerList { 29292915Sdim // Vector of instructions assigned to the packet that has just been created. 30327952Sdim std::vector<MachineInstr *> OldPacketMIs; 31292915Sdim 32292915Sdim // Has the instruction been promoted to a dot-new instruction. 33292915Sdim bool PromotedToDotNew; 34292915Sdim 35292915Sdim // Has the instruction been glued to allocframe. 36292915Sdim bool GlueAllocframeStore; 37292915Sdim 38292915Sdim // Has the feeder instruction been glued to new value jump. 39292915Sdim bool GlueToNewValueJump; 40292915Sdim 41327952Sdim // This holds the offset value, when pruning the dependences. 42327952Sdim int64_t ChangedOffset; 43327952Sdim 44292915Sdim // Check if there is a dependence between some instruction already in this 45292915Sdim // packet and this instruction. 46292915Sdim bool Dependence; 47292915Sdim 48292915Sdim // Only check for dependence if there are resources available to 49292915Sdim // schedule this instruction. 50292915Sdim bool FoundSequentialDependence; 51292915Sdim 52327952Sdim bool MemShufDisabled = false; 53327952Sdim 54292915Sdim // Track MIs with ignored dependence. 55292915Sdim std::vector<MachineInstr*> IgnoreDepMIs; 56292915Sdim 57321369Sdim // Set to true if the packet contains an instruction that stalls with an 58321369Sdim // instruction from the previous packet. 59321369Sdim bool PacketStalls = false; 60321369Sdim 61292915Sdimprotected: 62341825Sdim /// A handle to the branch probability pass. 63292915Sdim const MachineBranchProbabilityInfo *MBPI; 64292915Sdim const MachineLoopInfo *MLI; 65292915Sdim 66292915Sdimprivate: 67292915Sdim const HexagonInstrInfo *HII; 68292915Sdim const HexagonRegisterInfo *HRI; 69344779Sdim const bool Minimal; 70292915Sdim 71292915Sdimpublic: 72292915Sdim HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, 73292915Sdim AliasAnalysis *AA, 74344779Sdim const MachineBranchProbabilityInfo *MBPI, 75344779Sdim bool Minimal); 76292915Sdim 77292915Sdim // initPacketizerState - initialize some internal flags. 78292915Sdim void initPacketizerState() override; 79292915Sdim 80292915Sdim // ignorePseudoInstruction - Ignore bundling of pseudo instructions. 81309124Sdim bool ignorePseudoInstruction(const MachineInstr &MI, 82292915Sdim const MachineBasicBlock *MBB) override; 83292915Sdim 84292915Sdim // isSoloInstruction - return true if instruction MI can not be packetized 85292915Sdim // with any other instruction, which means that MI itself is a packet. 86309124Sdim bool isSoloInstruction(const MachineInstr &MI) override; 87292915Sdim 88292915Sdim // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ 89292915Sdim // together. 90292915Sdim bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override; 91292915Sdim 92292915Sdim // isLegalToPruneDependencies - Is it legal to prune dependece between SUI 93292915Sdim // and SUJ. 94292915Sdim bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override; 95292915Sdim 96327952Sdim bool foundLSInPacket(); 97309124Sdim MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override; 98309124Sdim void endPacket(MachineBasicBlock *MBB, 99309124Sdim MachineBasicBlock::iterator MI) override; 100309124Sdim bool shouldAddToPacket(const MachineInstr &MI) override; 101292915Sdim 102292915Sdim void unpacketizeSoloInstrs(MachineFunction &MF); 103292915Sdim 104292915Sdimprotected: 105327952Sdim bool getmemShufDisabled() { 106327952Sdim return MemShufDisabled; 107327952Sdim }; 108327952Sdim void setmemShufDisabled(bool val) { 109327952Sdim MemShufDisabled = val; 110327952Sdim }; 111314564Sdim bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, 112292915Sdim unsigned DepReg); 113314564Sdim bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, 114292915Sdim MachineBasicBlock::iterator &MII, 115314564Sdim const TargetRegisterClass *RC); 116314564Sdim bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, 117292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII, 118314564Sdim const TargetRegisterClass *RC); 119292915Sdim void cleanUpDotCur(); 120292915Sdim 121314564Sdim bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, 122292915Sdim MachineBasicBlock::iterator &MII, 123314564Sdim const TargetRegisterClass *RC); 124314564Sdim bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, 125292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII, 126314564Sdim const TargetRegisterClass *RC); 127314564Sdim bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, 128292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII); 129314564Sdim bool canPromoteToNewValueStore(const MachineInstr &MI, 130314564Sdim const MachineInstr &PacketMI, unsigned DepReg); 131314564Sdim bool demoteToDotOld(MachineInstr &MI); 132314564Sdim bool useCallersSP(MachineInstr &MI); 133314564Sdim void useCalleesSP(MachineInstr &MI); 134327952Sdim bool updateOffset(SUnit *SUI, SUnit *SUJ); 135327952Sdim void undoChangedOffset(MachineInstr &MI); 136309124Sdim bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2); 137314564Sdim bool restrictingDepExistInPacket(MachineInstr&, unsigned); 138314564Sdim bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC); 139314564Sdim bool isCurifiable(MachineInstr &MI); 140314564Sdim bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ); 141327952Sdim 142327952Sdim bool isPromotedToDotNew() const { 143292915Sdim return PromotedToDotNew; 144292915Sdim } 145327952Sdim 146292915Sdim bool tryAllocateResourcesForConstExt(bool Reserve); 147292915Sdim bool canReserveResourcesForConstExt(); 148292915Sdim void reserveResourcesForConstExt(); 149314564Sdim bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J); 150314564Sdim bool hasControlDependence(const MachineInstr &I, const MachineInstr &J); 151321369Sdim bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J); 152344779Sdim bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J); 153314564Sdim bool producesStall(const MachineInstr &MI); 154292915Sdim}; 155292915Sdim 156327952Sdim} // end namespace llvm 157327952Sdim 158327952Sdim#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H 159