HexagonVLIWPacketizer.h revision 314564
1292915Sdim#ifndef HEXAGONVLIWPACKETIZER_H 2292915Sdim#define HEXAGONVLIWPACKETIZER_H 3292915Sdim 4292915Sdim#include "llvm/CodeGen/DFAPacketizer.h" 5292915Sdim#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 6292915Sdim#include "llvm/CodeGen/ScheduleDAG.h" 7292915Sdim#include "llvm/CodeGen/ScheduleDAGInstrs.h" 8292915Sdim 9292915Sdimnamespace llvm { 10292915Sdimclass HexagonPacketizerList : public VLIWPacketizerList { 11292915Sdim // Vector of instructions assigned to the packet that has just been created. 12292915Sdim std::vector<MachineInstr*> OldPacketMIs; 13292915Sdim 14292915Sdim // Has the instruction been promoted to a dot-new instruction. 15292915Sdim bool PromotedToDotNew; 16292915Sdim 17292915Sdim // Has the instruction been glued to allocframe. 18292915Sdim bool GlueAllocframeStore; 19292915Sdim 20292915Sdim // Has the feeder instruction been glued to new value jump. 21292915Sdim bool GlueToNewValueJump; 22292915Sdim 23292915Sdim // Check if there is a dependence between some instruction already in this 24292915Sdim // packet and this instruction. 25292915Sdim bool Dependence; 26292915Sdim 27292915Sdim // Only check for dependence if there are resources available to 28292915Sdim // schedule this instruction. 29292915Sdim bool FoundSequentialDependence; 30292915Sdim 31292915Sdim // Track MIs with ignored dependence. 32292915Sdim std::vector<MachineInstr*> IgnoreDepMIs; 33292915Sdim 34292915Sdimprotected: 35292915Sdim /// \brief A handle to the branch probability pass. 36292915Sdim const MachineBranchProbabilityInfo *MBPI; 37292915Sdim const MachineLoopInfo *MLI; 38292915Sdim 39292915Sdimprivate: 40292915Sdim const HexagonInstrInfo *HII; 41292915Sdim const HexagonRegisterInfo *HRI; 42292915Sdim 43292915Sdimpublic: 44292915Sdim // Ctor. 45292915Sdim HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, 46292915Sdim AliasAnalysis *AA, 47292915Sdim const MachineBranchProbabilityInfo *MBPI); 48292915Sdim 49292915Sdim // initPacketizerState - initialize some internal flags. 50292915Sdim void initPacketizerState() override; 51292915Sdim 52292915Sdim // ignorePseudoInstruction - Ignore bundling of pseudo instructions. 53309124Sdim bool ignorePseudoInstruction(const MachineInstr &MI, 54292915Sdim const MachineBasicBlock *MBB) override; 55292915Sdim 56292915Sdim // isSoloInstruction - return true if instruction MI can not be packetized 57292915Sdim // with any other instruction, which means that MI itself is a packet. 58309124Sdim bool isSoloInstruction(const MachineInstr &MI) override; 59292915Sdim 60292915Sdim // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ 61292915Sdim // together. 62292915Sdim bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override; 63292915Sdim 64292915Sdim // isLegalToPruneDependencies - Is it legal to prune dependece between SUI 65292915Sdim // and SUJ. 66292915Sdim bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override; 67292915Sdim 68309124Sdim MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override; 69309124Sdim void endPacket(MachineBasicBlock *MBB, 70309124Sdim MachineBasicBlock::iterator MI) override; 71309124Sdim bool shouldAddToPacket(const MachineInstr &MI) override; 72292915Sdim 73292915Sdim void unpacketizeSoloInstrs(MachineFunction &MF); 74292915Sdim 75292915Sdimprotected: 76314564Sdim bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, 77292915Sdim unsigned DepReg); 78314564Sdim bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, 79292915Sdim MachineBasicBlock::iterator &MII, 80314564Sdim const TargetRegisterClass *RC); 81314564Sdim bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, 82292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII, 83314564Sdim const TargetRegisterClass *RC); 84292915Sdim void cleanUpDotCur(); 85292915Sdim 86314564Sdim bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, 87292915Sdim MachineBasicBlock::iterator &MII, 88314564Sdim const TargetRegisterClass *RC); 89314564Sdim bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, 90292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII, 91314564Sdim const TargetRegisterClass *RC); 92314564Sdim bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, 93292915Sdim unsigned DepReg, MachineBasicBlock::iterator &MII); 94314564Sdim bool canPromoteToNewValueStore(const MachineInstr &MI, 95314564Sdim const MachineInstr &PacketMI, unsigned DepReg); 96314564Sdim bool demoteToDotOld(MachineInstr &MI); 97314564Sdim bool useCallersSP(MachineInstr &MI); 98314564Sdim void useCalleesSP(MachineInstr &MI); 99309124Sdim bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2); 100314564Sdim bool restrictingDepExistInPacket(MachineInstr&, unsigned); 101314564Sdim bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC); 102314564Sdim bool isCurifiable(MachineInstr &MI); 103314564Sdim bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ); 104292915Sdim inline bool isPromotedToDotNew() const { 105292915Sdim return PromotedToDotNew; 106292915Sdim } 107292915Sdim bool tryAllocateResourcesForConstExt(bool Reserve); 108292915Sdim bool canReserveResourcesForConstExt(); 109292915Sdim void reserveResourcesForConstExt(); 110314564Sdim bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J); 111314564Sdim bool hasControlDependence(const MachineInstr &I, const MachineInstr &J); 112314564Sdim bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J); 113314564Sdim bool producesStall(const MachineInstr &MI); 114292915Sdim}; 115292915Sdim} // namespace llvm 116292915Sdim#endif // HEXAGONVLIWPACKETIZER_H 117292915Sdim 118